AD AD8341ACPZ-WP1 1.5 ghz to 2.4 ghz rf vector modulator Datasheet

1.5 GHz to 2.4 GHz
RF Vector Modulator
AD8341
FUNCTIONAL BLOCK DIAGRAM
FEATURES
VPRF
QBBP QBBM
VPS2
90°
RFOP
RFIP
RFIM
RFOM
0°
CMOP
IBBP IBBM
DSOP
04700-001
Cartesian amplitude and phase modulation
1.5 GHz to 2.4 GHz frequency range
Continuous magnitude control of −4.5 dB to −34.5 dB
Continuous phase control of 0° to 360°
Output third-order intercept 17.5 dBm
Output 1 dB compression point 8.5 dBm
Output noise floor −150.5 dBm/Hz @ full gain
Adjustable modulation bandwidth up to 230 MHz
Fast output power disable
4.75 V to 5.25 V single-supply voltage
Figure 1.
APPLICATIONS
RF PA linearization/RF predistortion
Amplitude and phase modulation
Variable attenuators and phase shifters
CDMA2000, WCDMA, GSM/EDGE linear power amplifiers
Smart antennas
GENERAL DESCRIPTION
The AD8341 vector modulator performs arbitrary amplitude
and phase modulation of an RF signal. Since the RF signal path
is linear, the original modulation is preserved. This part can be
used as a general-purpose RF modulator, a variable attenuator/phase shifter, or a remodulator. The amplitude can be
controlled from a maximum of −4.5 dB to less than −34.5 dB,
and the phase can be shifted continuously over the entire 360°
range. For maximum gain, the AD8341 delivers an OP1dB of
8.5 dBm, an OIP3 of 17.5 dBm, and an output noise floor of
−150.5 dBm/Hz, independent of phase. It operates over a
frequency range of 1.5 GHz to 2.4 GHz.
The baseband inputs in Cartesian I and Q format control the
amplitude and phase modulation imposed on the RF input
signal. Both I and Q inputs are dc-coupled with a ±500 mV
differential full-scale range. The maximum modulation bandwidth is 230 MHz, which can be reduced by adding external
capacitors to limit the noise bandwidth on the control lines.
Both the RF inputs and outputs can be used differentially or
single-ended and must be ac-coupled. The RF input and output
impedances are nominally 50 Ω over the operating frequency
range. The DSOP pin allows the output stage to be disabled
quickly in order to protect subsequent stages from overdrive.
The AD8341 operates off supply voltages from 4.75 V to 5.25 V
while consuming approximately 125 mA.
The AD8341 is fabricated on Analog Devices’ proprietary, high
performance 25 GHz SOI complementary bipolar IC process. It
is available in a 24-lead, Pb-free LFCSP package and operates
over a −40°C to +85°C temperature range. Evaluation boards
are available.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD8341
TABLE OF CONTENTS
Specifications..................................................................................... 3
Applications..................................................................................... 12
Absolute Maximum Ratings............................................................ 4
Using the AD8341 ...................................................................... 12
ESD Caution.................................................................................. 4
RF Input and Matching ............................................................. 12
Pin Configuration and Function Descriptions............................. 5
RF Output and Matching .......................................................... 13
Typical Performance Characteristics ............................................. 6
Driving the I-Q Baseband Controls......................................... 13
Theory of Operation ...................................................................... 10
Interfacing to High Speed DACs.............................................. 14
RF Quadrature Generator ......................................................... 10
CDMA2000 Application............................................................ 14
I-Q Attenuators and Baseband Amplifiers.............................. 11
WCDMA Application ................................................................ 15
Output Amplifier ........................................................................ 11
Evaluation Board ............................................................................ 17
Noise and Distortion.................................................................. 11
Outline Dimensions ....................................................................... 20
Gain and Phase Accuracy.......................................................... 11
Ordering Guide .......................................................................... 20
RF Frequency Range .................................................................. 11
REVISION HISTORY
7/04—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD8341
SPECIFICATIONS
VS = 5 V, TA = 25°C, ZO = 50 Ω, f = 1.9 GHz, single-ended, ac-coupled source drive to RFIP through 1.2 nH series inductor, RFIM
ac-coupled through 1.2 nH series inductor to common, differential-to-single-ended conversion at output using 1:1 balun.
Table 1.
Parameter
OVERALL FUNCTION
Frequency Range
Maximum Gain
Minimum Gain
Gain Control Range
Phase Control Range
Gain Flatness
Group Delay Flatness
RF INPUT STAGE
Input Return Loss
CARTESIAN CONTROL INTERFACE (I AND Q)
Gain Scaling
Modulation Bandwidth
Second Harmonic Distortion
Third Harmonic Distortion
Step Response
Recommended Common-Mode Level
RF OUTPUT STAGE
Output Return Loss
f = 1.9 GHz
Gain
Output Noise Floor
Output IP3
Adjacent Channel Power
Output 1 dB Compression Point
POWER SUPPLY
Positive Supply Voltage
Total Supply Current
OUTPUT DISABLE
Disable Threshold
Attenuation
Enable Response Time
Disable Response Time
Conditions
Min
Typ
Max
Unit
2.4
−4.5
−34.5
GHz
dB
dB
30
360
0.5
50
dB
Degrees
dB
ps
12
dB
2
230
41
47
45
1/V
MHz
dBc
dBc
ns
45
ns
0.5
V
7.5
dB
−4.5
−150.5
−149
17.5
−76
dB
dBm/Hz
dBm/Hz
dBm
dBm
8.5
dBm
1.5
Maximum gain setpoint for all phase setpoints
VBBI = VBBQ = 0 V differential
(at recommended common-mode level)
Relative to maximum gain
Over 30 dB control range
Over any 60 MHz bandwidth
Over any 60 MHz bandwidth
RFIM, RFIP (Pins 21 and 22)
From RFIP to CMRF (with 1.2 nH series inductors)
IBBP, IBBM, QBBP, QBBM (Pins 16, 15, 3, 4)
500 mV p-p, sinusoidal baseband input single-ended
500 mV p-p, 1 MHz, sinusoidal baseband input differential
500 mV p-p, 1 MHz, sinusoidal baseband input differential
For gain setpoint from 0.1 to 0.9
(VBBP = 0.5 V, VBBM = 0.55 V to 0.95 V)
For gain setpoint from 0.9 to 0.1
(VBBP = 0.5 V, VBBM = 0.95 V to 0.55 V)
RFOP, RFOM (Pins 9, 10)
Measured through balun
Maximum gain setpoint
Maximum gain setpoint, no input
PIN = 0 dBm, frequency offset = 20 MHz
f1 = 1900 MHz, f2 = 1897.5 MHz, maximum gain setpoint
CDMA2000, single carrier, POUT = -4 dBm,
maximum gain, phase setpoint = 45° (See Figure 35)
Maximum gain
VPS2 (Pins 5, 6, and 14), VPRF (Pins 19 and 24),
RFOP, RFOM (Pins 9 and 10)
Includes load current
DSOP (Pin 13)
(See Figure 24)
DSOP = 5 V
Delay following high-to-low transition until
RF output amplitude is within 10% of final value.
Delay following low-to-high transition until
device produces full attenuation
Rev. 0 | Page 3 of 20
4.75
105
5
125
5.25
145
V
mA
Vs/2
33
30
V
dB
ns
15
ns
AD8341
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameters
Supply Voltage VPRF, VPS2
DSOP
IBBP, IBBM, QBBP, QBBM
RFOP, RFOM
RF Input Power at Maximum Gain
(RFIP or RFIM, Single-Ended Drive)
Equivalent Voltage
Internal Power Dissipation
θJA (With Pad Soldered to Board)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature Range (Soldering 60 sec)
Rating
5.5 V
5.5 V
2.5 V
5.5V
13 dBm, re: 50 Ω
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
2.8 V p-p
825 mW
59 °C/W
125°C
−40°C to +85°C
−65°C to +150°C
300°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
Rev. 0 | Page 4 of 20
AD8341
24 VPRF
23 CMRF
22 RFIP
21 RFIM
20 CMRF
19 VPRF
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
AD8341
TOP VIEW
(Not to Scale)
18 IFLP
17 IFLM
16 IBBP
15 IBBM
14 VPS2
13 DSOP
04700-002
1
2
3
4
5
6
CMOP 7
CMOP 8
RFOP 9
RFOM 10
CMOP 11
CMOP 12
QFLP
QFLM
QBBP
QBBM
VPS2
VPS2
Figure 2. 24-Lead Lead Frame Chip Scale Package (LFCSP)
Table 3. Pin Function Descriptions
Pin No.
1, 2
Mnemonic
QFLP, QFLM
3, 4
5, 6, 14, 19, 24
7, 8, 11, 12, 20, 23
9, 10
13
15, 16
17, 18
QBBP, QBBM
VPS2, VPRF
CMOP, CMRF
RFOP, RFOM
DSOP
IBBM, IBBP
IFLM, IFLP
21, 22
RFIM, RFIP
Function
Q Baseband Input Filter Pins. Connect optional capacitor to reduce Q baseband channel low-pass
corner frequency.
Q Channel Differential Baseband Inputs.
Positive Supply Voltage. 4.75 V − 5.25 V.
Device Common. Connect via lowest possible impedance to external circuit common.
Differential RF Outputs. Must be ac-coupled. Differential impedance 50 Ω nominal.
Output disable. Pull high to disable output stage.
I Channel Differential Baseband Inputs.
I Baseband Input Filter Pins. Connect optional capacitor to reduce I baseband channel low-pass
corner frequency.
Differential RF Inputs. Must be ac-coupled. Differential impedance 50 Ω nominal.
Rev. 0 | Page 5 of 20
AD8341
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0
GAIN SETPOINT = 1.0
PHASE SETPOINT = 0°
0.5
PHASE SETPOINT = 270°
–15
PHASE SETPOINT = 180°
–20
PHASE SETPOINT = 90°
–25
–30
04700-003
–35
–40
0
0.1
0.2
0.3
0.4
0.5
0.6
GAIN SETPOINT
0.7
0.8
0.9
0
–0.5
–1.0
–1.5
–2.0
GAIN SETPOINT = 0.25
–2.5
–3.0
–3.5
GAIN SETPOINT = 0.1
–4.0
–4.5
1.0
0
6
180
225
270
315
360
360
315
4
PHASE SETPOINT = 270°
3
GAIN SETPOINT = 0.25
270
PHASE SETPOINT = 0°
2
GAIN SETPOINT = 0.5
PHASE (Degrees)
PHASE SETPOINT = 45°
1
0
–1
PHASE SETPOINT = 225°
–2
–3
PHASE SETPOINT = 90°
–4
PHASE SETPOINT = 180°
–5
–6
PHASE SETPOINT = 135°
–8
0
0.1
0.2
0.3
225
GAIN SETPOINT = 0.1
GAIN SETPOINT = 1.0
180
135
90
45
04700-004
GAIN CONFORMANCE ERROR (dB)
135
Figure 6. Gain Conformance Error vs. Phase Setpoint at
Different Gain Setpoints, RF Frequency = 1900 MHz
PHASE SETPOINT = 315°
–7
0.4
0.5 0.6
GAIN SETPOINT
0.7
0.8
0.9
0
0
1.0
Figure 4. Gain Conformance Error vs. Gain Setpoint at
Different Phase Setpoints, RF Frequency = 1900 MHz
45
90
135
180
225
270
PHASE SETPOINT (Degrees)
315
360
Figure 7. Phase vs. Phase Setpoint at
Different Gain Setpoints, RF Frequency = 1900 MHz
25
–2
GAIN SETPOINT = 0.1
GAIN SETPOINT = 1.0
–4
20
–6
PHASE ERROR (Degrees)
–8
GAIN SETPOINT = 0.5
–12
–14
GAIN SETPOINT = 0.25
–16
–18
–20
–22
GAIN SETPOINT = 0.1
–26
–28
0
45
90
135
180
225
270
315
GAIN SETPOINT = 0.25
10
5
0
GAIN SETPOINT = 0.5
GAIN SETPOINT = 1.0
–5
–10
04700-005
–24
15
04700-008
–10
GAIN (dB)
90
PHASE SETPOINT (Degrees)
Figure 3. Gain Magnitude vs. Gain Setpoint at Different
Phase Setpoints, RF Frequency = 1900 MHz
5
45
04700-007
GAIN (dB)
–10
GAIN SETPOINT = 0.5
04700-006
GAIN CONFORMANCE ERROR (dB)
–5
–15
0
360
PHASE SETPOINT (Degrees)
45
90
135
180
225
270
PHASE SETPOINT (Degrees)
315
360
Figure 8. Phase Error vs. Phase Setpoint at Different Gain Setpoints,
RF Frequency = 1900 MHz
Figure 5. Gain Magnitude vs. Phase Setpoint at Different
Gain Setpoints, RF Frequency = 1900 MHz
Rev. 0 | Page 6 of 20
AD8341
–147
0
–1
–148
–40°C
–2
RF PIN = +5dBm
+25°C
–3
RF PIN = 0dBm
GAIN (dB)
–150
–151
04700-009
0.2
0.3
0.4
0.5
0.6
GAIN SETPOINT
0.7
0.8
0.9
–9
–10
1500
1.0
Figure 9. Output Noise Floor vs. Gain Setpoint, Noise in dBm/Hz, No Carrier,
and With 1900 MHz Carrier (Measured at 20 MHz Offset)
Pin = −5, 0, and +5 dBm
–8
GAIN (dB)
2200
2300
2400
FUNDAMENTAL POWER, 1899MHz, 1900MHz
GAIN SETPOINT = 0.5
GAIN SETPOINT = 0.25
–14
–16
–18
–20
1800 1900 2000 2100
FREQUENCY (MHz)
0
–10
–12
1700
GAIN SETPOINT = 1.0
–4
–6
1600
Figure 12. Gain Magnitude vs. Frequency and Temperature,
Maximum Gain, Phase Setpoint = 0°
RF OUTPUT AM SIDEBAND POWER (dBm)
0
–2
04700-012
–8
–154
0.1
–6
–7
NO RF INPUT
–153
0
–5
+85°C
RF PIN = –5dBm
–152
–4
GAIN SETPOINT = 0.1
–22
04700-010
–24
–26
–28
1500
1600
1700
1800
1900
2000
2100
2200
2300
–10
–20
–30
–40
–50
–60
–70
–80
THIRD BASEBAND HARMONIC PRODUCT,
1897MHz, 1903MHz
–90
–100
100
2400
SECOND BASEBAND HARMONIC PRODUCT,
1898MHz, 1902MHz
200
300
400
500
600
700
800
900
04700-013
NOISE (dBm/Hz)
–149
1000
DIFFERENTIAL BB LEVEL (mV p-p)
FREQUENCY (MHz)
Figure 13. Baseband Harmonic Distortion (I and Q Channel,
RF Input = 0 dBm, Output Balun and Cable Losses of Approximately
2 dB Not Accounted for in Plot)
Figure 10. Gain vs. Frequency at Different Gain Setpoints,
Phase Setpoint = 0°
12
–146
–40°C
–147
10
+25°C
8
OP1dB (dBm)
–149
–150
–151
6
+85°C
4
–152
–154
1500
1600
1700
1800 1900 2000 2100
FREQUENCY (MHz)
2200
2300
0
1500
2400
04700-014
2
–153
04700-011
NOISE (dBm/Hz)
–148
1600
1700
1800 1900 2000 2100
FREQUENCY (MHz)
2200
2300
2400
Figure 14. Output 1 dB Compression Point vs. Frequency and
Temperature, Maximum Gain, Phase Setpoint = 0°
Figure 11. Output Noise Floor vs. Frequency, Maximum Gain,
No RF Carrier, Phase Setpoint = 0°
Rev. 0 | Page 7 of 20
AD8341
20
25
GAIN SETPOINT = 1.0
–40°C
15
20
GAIN SETPOINT = 0.5
+25°C
OIP3 (dBm)
OIP3 (dBm)
10
15
+85°C
10
GAIN SETPOINT = 0.25
5
0
GAIN SETPOINT = 0.1
5
1600
1700
1800 1900 2000 2100
FREQUENCY (MHz)
2200
2300
04700-018
0
1500
04700-015
–5
–10
2400
0
45
90
135
180
Figure 15. Output IP3 vs. Frequency and Temperature,
Maximum Gain, Phase Setpoint = 0°, 2.5 MHz Carrier Spacing
270
315
360
Figure 18. Output IP3 vs. Gain and Phase Setpoints,
RF Frequency = 1900 MHz, 2.5 MHz Carrier Spacing
–10
1V p-p BB INPUT
0
RBW 30kHz
VBW 30kHz
SWT 100ms
REF LVL
0dBm
RF ATT
20dB
UNIT
dBm
A
–15
–30
60
110
160
210
260
FREQUENCY (MHz)
310
360
–60
–70
–80
410
1SA
04700-019
–35
10
–50
SECOND BASEBAND HARMONIC
250mV p-p BB INPUT
–40
UNDESIRED SIDEBAND
OUTPUT POWER (dBm)
–25
–30
RF FEEDTHROUGH
–20
–20
DESIRED SIDEBAND
500mV p-p BB INPUT
SECOND BASEBAND HARMONIC
–10
04700-016
RF OUTPUT AM SIDEBAND POWER (dBm)
225
PHASE SETPOINT (Degrees)
–90
–100
CENTER 1.9GHz
500kHz/
SPAN 5MHz
FREQUENCY (MHz)
Figure 16. I/Q Modulation Bandwidth vs. Baseband Magnitude
10
Figure 19. Single-Sideband Performance, RF Frequency = 1900 MHz,
RF Input = −10 dBm; 1 MHz, 500 mV p-p Differential BB Drive
90
GAIN SETPOINT = 1.0
60
120
5
30
150
0
GAIN SETPOINT = 0.25
–5
0
180
1500MHz
–10
210
GAIN SETPOINT = 0.1
45
90
135
180
330
225
270
315
360
240
PHASE SETPOINT (Degrees)
300
270
Figure 17. Output 1 dB Compression Point vs. Gain and
Phase Setpoints, RF Frequency = 1900 MHz
S11 RF PORT WITH 1.2nH INDUCTORS
S11 RF PORT WITHOUT INDUCTORS
Figure 20. Input Impedance Smith Chart
Rev. 0 | Page 8 of 20
04700-020
–15
0
2400MHz
04700-017
OP1dB (dBm)
GAIN SETPOINT = 0.5
AD8341
90
0
–5
60
120
RF OUTPUT POWER (dBm)
–10
30
0
180
1500MHz
2400MHz
210
–20
–25
–30
–35
–40
–45
330
04700-024
150
–15
–50
–55
0
240
300
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
DSOP VOLTAGE (V)
04700-021
270
SDD22 PORT DIFFERENTIAL
S22 WITH 1 TO 1 TRANSFORMER
Figure 24. Output Disable Attenuation,
RF Frequency = 1900 MHz, RF Input = −5 dBm
Figure 21. Output Impedance Smith Chart
0
2V/DIV
DSOP
–20
3
PHASE SETPOINT = 0°
VOLTS
–30
–40
RF OUTPUT
PHASE SETPOINT = 45°
–50
4
100mV/DIV
04700-022
–60
PHASE SETPOINT = 90°
–70
0
0.1
0.2
0.3
0.4
0.5
0.6
GAIN SETPOINT
0.7
0.8
0.9
CH3 2.0V Ω CH4 100mV Ω M10.0ns 5.0GS/s A CH3
TIME (10ns/DIV)
1.0
Figure 25. Output Disable Response Time,
RF Frequency = 1900 MHz, RF Input = 0 dBm
Figure 22. Phase Error vs. Gain Setpoint by Phase Setpoint,
RF Frequency = 1900 MHz
127
VPOS = 5.00V
125
VPOS = 5.25V
124
123
VPOS = 4.75V
122
121
–40 –30 –20 –10
04700-023
SUPPLY CURRENT (mA)
126
0
10 20 30 40
TEMPERATURE (°C)
50
60
70
80
Figure 23. Supply Current vs. Temperature
Rev. 0 | Page 9 of 20
04700-025
PHASE ERROR (Degrees)
–10
1.84V
AD8341
THEORY OF OPERATION
By controlling the relative amounts of I and Q components that
are summed, continuous magnitude and phase control of the
gain is possible. Consider the vector gain representation of the
AD8341 expressed in polar form in Figure 27. The attenuation
factors for the I and Q signal components are represented on
the x- and y-axis, respectively, by the baseband inputs, VBBI and
VBBQ. The resultant of their vector sum represents the vector
gain, which can also be expressed as a magnitude and phase. By
applying different combinations of baseband inputs, any vector
gain within the unit circle can be programmed.
Pure amplitude modulation is represented by radial movement
of the gain vector tip at a fixed angle, while pure phase modulation is represented by rotation of the tip around the circle at a
fixed radius. Unlike traditional I-Q modulators, the AD8341 is
designed to have a linear RF signal path from input to output.
Traditional I-Q modulators provide a limited LO carrier path
through which any amplitude information is removed.
VBBI
I CHANNEL INPUT
LINEAR
ATTENUATOR
V-I
SINGLE-ENDED OR
DIFFERENTIAL
50Ω INPUT Z
0°/90°
SINGLE-ENDED OR
DIFFERENTIAL
50Ω OUTPUT
I-V
V-I
OUTPUT
DISABLE
LINEAR
ATTENUATOR
04700-026
The AD8341 is a linear RF vector modulator with Cartesian
baseband controls. In the simplified block diagram given in
Figure 26, the RF signal propagates from the left to the right
while baseband controls are placed above and below. The RF
input is first split into in-phase (I) and quadrature (Q) components. The variable attenuators independently scale the I and Q
components of the RF input. The attenuator outputs are then
summed and buffered to the output.
Q CHANNEL INPUT
VBBQ
Figure 26. Simplified Architecture of the AD8341
A change in sign of VBBI or VBBQ can be viewed as a change in
sign of the gain or as a 180° phase change. The outermost
circle represents the maximum gain magnitude of unity. The
circle origin implies, in theory, a gain of 0. In practice, circuit
mismatches and unavoidable signal feedthrough limit the
minimum gain to approximately −34.5 dB. The phase angle
between the resultant gain vector and the positive x-axis is defined as the phase shift. Note that there is a nominal, systematic
insertion phase through the AD8341 to which the phase shift is
added. In the following discussions, the systematic insertion
phase is normalized to 0°.
Vq
MAX GAIN
+0.5
A
|A|
+0.5
MIN GAIN
–0.5
The correspondence between the desired gain and phase setpoints, GainSP and PhaseSP, and the Cartesian inputs, VBBI and
VBBQ, is given by simple trigonometric identities
GainSP =
[(VBBI /VO )2 + (VBBQ /VO )2 ]
PhaseSP = arctan(VBBQ /VBBI )
where:
VO is the baseband scaling constant (500 mV).
VBBI and VBBQ are the differential I and Q baseband voltages,
respectively.
Note that when evaluating the arctangent function, the proper
phase quadrant must be selected. For example, if the principal
value of the arctangent (known as the Arctangent(x)) is used,
quadrants 2 and 3 could be interpreted mistakenly as quadrants
4 and 1, respectively. In general, both VBBI and VBBQ are needed
in concert to modulate the gain and the phase.
Vi
04700-027
θ
–0.5
Figure 27. Vector Gain Representation
RF QUADRATURE GENERATOR
The RF input is directly coupled differentially or single-ended
to the quadrature generator, which consists of a multistage RC
polyphase network tuned over the operating frequency range of
1.5 GHz to 2.4 GHz. The recycling nature of the polyphase network generates two replicas of the input signal, which are in
precise quadrature, i.e., 90°, to each other. Since the passive
network is perfectly linear, the amplitude and phase information
contained in the RF input is transmitted faithfully to both channels. The quadrature outputs are then separately buffered to
drive the respective attenuators. The characteristic impedance
of the polyphase network is used to set the input impedance of
the AD8341.
Rev. 0 | Page 10 of 20
AD8341
I-Q ATTENUATORS AND BASEBAND AMPLIFIERS
GAIN AND PHASE ACCURACY
The proprietary linear-responding attenuator structure is an
active solution with differential inputs and outputs that offer
excellent linearity, low noise, and greater immunity from mismatches than other variable attenuator methods. The gain, in
linear terms, of the I and Q channels is proportional to its control
voltage with a scaling factor designed to be 2/V, i.e., a full-scale
gain setpoint of 1.0 (−4.5 dB) for a VBBI (or a VBBQ) of 500 mV. The
control voltages can be driven differentially or single-ended. The
combination of the baseband amplifiers and attenuators allows
for maximum modulation bandwidths in excess of 200 MHz.
There are numerous ways to express the accuracy of the
AD8341. Ideally, the gain and phase should precisely follow the
setpoints. Figure 4 illustrates the gain error in dB from a best fit
line, normalized to the gain measured at the gain setpoint = 1.0,
for the different phase setpoints. Figure 6 shows the gain error
in a different form, normalized to the gain measured at phase
setpoint = 0°; the phase setpoint is swept from 0° to 360° for
different gain setpoints. Figure 8 and Figure 22 show analogous
errors for the phase error as a function of gain and phase
setpoints. The accuracy clearly depends on the region of operation within the vector gain unit circle. Operation very close to
the origin generally results in larger errors as the relative
accuracy of the I and Q vectors degrades.
OUTPUT AMPLIFIER
The output amplifier accepts the sum of the attenuator outputs
and delivers a differential output signal into the external load.
The output pins must be pulled up to an external supply,
preferably through RF chokes. When the 50 Ω load is taken
differentially, an output P1dB and IP3 of 8.5 dBm and 17.5 dBm
is achieved, respectively, at 1.9 GHz. The output can be taken in
single-ended fashion, albeit at lower performance levels.
NOISE AND DISTORTION
The output noise floor and distortion levels vary with the gain
magnitude but do not vary significantly with the phase. At the
higher gain magnitude setpoints, the OIP3 and the noise floor
vary in direct proportion with the gain. At lower gain magnitude setpoints, the noise floor levels off while the OIP3
continues to vary with the gain.
RF FREQUENCY RANGE
The frequency range on the RF input is limited by the internal
polyphase quadrature phase-splitter. The phase-splitter splits
the incoming RF input into two signals, 90° out of phase, as
previously described in the RF Quadrature Generator section.
This polyphase network has been designed to ensure robust
quadrature accuracy over standard fabrication process
parameter variations for the 1.5 GHz to 2.4 GHz specified RF
frequency range. Using the AD8341 as a single-sideband modulator and measuring the resulting sideband suppression is a
good gauge of how well the quadrature accuracy is maintained
over RF frequency. A typical plot of sideband suppression from
1.1 GHz to 2.7 GHz is shown in Figure 28. The level of sideband
suppression degradation outside the 1.5 GHz to 2.4 GHz specified range will be subject to manufacturing process variations.
–20
–25
–30
–35
–40
–45
0.7
04700-028
SIDEBAND SUPPRESSION (dBc)
–15
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
FREQUENCY (GHz)
Figure 28. Sideband Suppression vs. Frequency
Rev. 0 | Page 11 of 20
2.5
2.7
AD8341
APPLICATIONS
loss of >10 dB over the operating frequency range. Different
matching inductors can improve matching over a narrower
frequency range. The single-ended and differential input
impedances are exactly the same.
USING THE AD8341
The AD8341 is designed to operate in a 50 Ω impedance
system. Figure 30 illustrates an example where the RF input is
driven in a single-ended fashion while the differential RF output is converted to a single-ended output with an RF balun. The
baseband controls for the I and Q channels are typically driven
from differential DAC outputs. The power supplies, VPRF and
VPS2, should be bypassed appropriately with 0.1 µF and 100 pF
capacitors. Low inductance grounding of the CMOP and CMRF
common pins is essential to prevent unintentional peaking of
the gain.
100pF 1.2nH
RFIM
~1VDC
RC
PHASE
RF
04700-029
100pF 1.2nH
RFIP
50Ω
Figure 29. RF Input Interface to the AD8341 Showing
Coupling Capacitors and Matching Inductors
RF INPUT AND MATCHING
The RFIP and RFIM should be ac-coupled through low loss
series capacitors as shown in Figure 29. The internal dc levels
are at approximately 1 V. For single-ended operation, one input
is driven by the RF signal while the other input is ac grounded.
The input impedance of the AD8341 is defined by the characteristics of the polyphase network. The capacitive component of
the network causes its impedance to roll-off with frequency
albeit at a rate slower than 6 dB/octave. By using matching
inductors on the order of 1.2 nH in series with each of the RF
inputs, RFIP and RFIM, a 50 Ω match is achieved with a return
VP
C2
100pF
C1
0.1µF
IBBM
VP
IBBP
C12
(SEE TEXT)
C6
100pF
VPS2
OUTPUT
DISABLE
DSOP
CMOP
CMRF
CMOP
RFIM
RFOM
C17
100pF
AD8341
RFOP
CMRF
CMOP
VPRF
C3
0.1µF
C4
100pF
QFLP
VPS2
VP
RFIP
QBBM
L4
1.2nH
QBBP
C5
100pF
QFLM
RF
INPUT
L3
1.2nH
IFLP
VPRF
IBBM
VP
IBBP
C7
100pF
B
IFLM
C8
0.1µF
A
L1
120nH
ETC1-1-13
RF
OUTPUT
C18
L2
100pF
120nH
CMOP
VPS2
C14
0.1µF
VP
C10
0.1µF
QBBP
QBBM
C9
100pF
Figure 30. Basic Connections
Rev. 0 | Page 12 of 20
04700-030
C11
(SEE TEXT)
AD8341
–2.5
RF OUTPUT AND MATCHING
RL2 = SHORT
–3.0
The RF outputs of the AD8341, RFOP, and RFOM, are open
collectors of a transimpedance amplifier which need to be
pulled up to the positive supply, preferably with RF chokes as
shown in Figure 31. The nominal output impedance looking
into each individual output pin is 25 Ω. Consequently, the
differential output impedance is 50 Ω.
–3.5
–4.0
GAIN (dB)
–4.5
–5.0
RL2 = 50Ω
–5.5
–6.0
–6.5
VP
–7.0
GM
100pF
1.0
1:1
100pF
RF
OUTPUT
04700-031
50Ω
DIFFERENTIAL
1.2
1.4
1.6
1.8
2.0
2.2
2.4
FREQUENCY (GHz)
2.6
2.8
3.0
Figure 32. Gain of the AD8341 Using a Single-Ended Output with Different
Dummy Loads, RL2 , on the Unused Output
RFOP
RT
RL = 50Ω
–8.5
RFOM
±ISIG
–8.0
120nH
RT
04700-032
RL2 = OPEN
–7.5
Figure 31. RF Output Interface to the AD8341 Showing
Coupling Capacitors, Pull-Up RF Chokes, and Balun
Since the output dc levels are at the positive supply, ac coupling
capacitors will usually be needed between the AD8341 outputs
and the next stage in the system.
A 1:1 RF broadband output balun, such as the ETC1-1-13
(M/A-COM), converts the differential output of the AD8341
into a single-ended signal. Note that the loss and balance of the
balun directly impact the apparent output power, noise floor,
and gain/phase errors of the AD8341. In critical applications,
narrow-band baluns with low loss and superior balance are
recommended.
If the output is taken in a single-ended fashion directly into a
50 Ω load through a coupling capacitor, there will be an impedance mismatch. This can be resolved with a 1:2 balun to convert
the single-ended 25 Ω output impedance to 50 Ω. If loss of
signal swing is not critical, a 25 Ω back termination in series
with the output pin can also be used. The unused output pin
must still be pulled up to the positive supply. The user may load
it through a coupling capacitor with a dummy load to preserve
balance. The gain of the AD8341 when the output is singleended varies slightly with dummy load value as shown in Figure 32.
The RF output signal can be disabled by raising the DSOP pin
to the positive supply. The output disable function provides
>30 dB attenuation of the input signal even at full gain. The
interface to DSOP is high impedance and the shutdown and
turn-on response times are <100 ns. If the disable function is
not needed, the DSOP pin should be tied to ground.
DRIVING THE I-Q BASEBAND CONTROLS
The I and Q inputs to the AD8341 set the gain and phase between input and output. These inputs are differential and should
normally have a common-mode level of 0.5 V. However, when
differentially driven, the common mode can vary from 250 mV
to 750 mV while still allowing full gain control. Each input pair
has a nominal input swing of ±0.5 V differential around the
common-mode level. The maximum gain of unity is achieved if
the differential voltage is equal to +500 mV or −500 mV. So
with a common-mode level of 500 mV, IBBP and IBBM will
each swing between 250 mV and 750 mV.
The I and Q inputs can also be driven with a single-ended
signal. In this case, one side of each input should be tied to a
low noise 0.5 V voltage source (a 0.1 µF decoupling capacitor
located close to the pin is recommended), while the other input
swings from 0 V to 1 V. Differential drive generally offers superior
even-order distortion and lower noise than single-ended drive.
The bandwidth of the baseband controls exceeds 200 MHz even
at full-scale baseband drive. This allows for very fast gain and
phase modulation of the RF input signal. In cases where lower
modulation bandwidths are acceptable or desired, external filter
capacitors can be connected across Pins IFLP to IFLM and
QFLP to QFLM to reduce the ingress of baseband noise and
spurious signal into the control path.
Rev. 0 | Page 13 of 20
f3dB ≈
45 kHz × 10 nF
C FLT + 0.5 pF
This equation has been verified for values of CFLT from 10 pF to
0.1 µF (bandwidth settings of approximately 4.5 kHz to 43 MHz).
INTERFACING TO HIGH SPEED DACs
The AD977x family of dual DACs is well suited to driving the I
and Q vector controls of the AD8341. While these inputs can in
general be driven by any DAC, the differential outputs and bias
level of the ADI TxDAC® family allows for a direct connection
between DAC and modulator.
The AD977x family of dual DACs has differential current outputs. The full-scale current is user programmable and is usually
set to 20 mA, that is, each output swings from 0 mA to 20 mA.
The basic interface between the AD9777 DAC outputs and the
AD8341 I and Q inputs is shown in Figure 33. The Resistors R1
and R2 set the dc bias level according to the equation:
Bias Level = Average Output Current × R1
For example, if the full-scale current from each output is 20 mA,
each output will have an average current of 10 mA. Therefore to
set the bias level to the recommended 0.5 V, R1 and R2 should
be set to 50 Ω each. R1 and R2 should always be equal.
If R3 is omitted, this will result in an available swing from
the DAC of 2 V p-p differential, which is twice the maximum
voltage range required by the AD8341. DAC resolution can be
maximized by adding R3, which scales down this voltage
according to the following equation:
Full Scale Swing =
Figure 34. Peak-to-Peak DAC Output Swing vs.
Swing Scaling Resistor R3 (R1 = R2 = 50 Ω)
Figure 34 shows the relationship between the value of R3 and
the peak baseband voltage with R1 and R2 equal to 50 Ω.
From Figure 34, it can be seen that a value of 100 Ω for R3 will
provide a peak-to-peak swing of 1 V p-p differential into the
AD8341’s I and Q inputs.
When using a DAC, low-pass image reject filters are typically
used to eliminate the Nyquist images produced by the DAC.
They also provide the added benefit of eliminating broadband
noise that might feed into the modulator from the DAC.
CDMA2000 APPLICATION
To test the compliance to the CDMA2000 base station standard,
a single-carrier CDMA2000 test model signal (forward pilot,
sync, paging, and six traffic as per 3GPP2 C.S0010-B, Table
6.5.2.1) was applied to the AD8341 at 1960 MHz. A cavity tuned
filter was used to reduce noise from the signal source being
applied to the device. The 6.8 MHz pass band of this filter is
apparent in the subsequent spectral plots.
Figure 35 shows a plot of the spectrum of the output signal
under nominal conditions. POUT is equal to −4 dBm and VBBI =
VBBQ = 0.353 V, i.e., VIBBP − VIBBM = VQBBP − VQBBM = 0.353 V.
Noise and distortion is measured in a 1 MHz bandwidth at
±2.25 MHz carrier offset (30 kHz measurement bandwidth).
R2 ⎤
⎡
2 × I MAX (R1 || (R2 + R3)) × ⎢1 −
R2
+ R3 ⎥⎦
⎣
AD9777
AD8341
IBBP
IOUTA1
R1
R2
OPTIONAL
LOW-PASS
FILTER
R3
IOUTB1
IBBM
IOUTA2
QBBP
R1
R2
OPTIONAL
LOW-PASS
FILTER
R3
IOUTB2
1.15
1.13
1.10
1.08
1.05
1.02
1.00
0.97
0.95
0.92
0.90
0.88
0.85
0.82
0.80
0.77
0.75
0.72
0.70
50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130
(Ω)
04700-034
The 3 dB bandwidth is set by choosing CFLT according to the
following equation:
DIFFERENTIAL PEAK-TO-PEAK SWING (V)
AD8341
04700-033
QBBM
Figure 33. Basic AD9777 to AD8341 Interface
Rev. 0 | Page 14 of 20
RBW 30kHz
VBW 100kHz
SWT 500ms
1
0.3dB OFFSET
1 [T1]
–20
CH PWR
ACP UP
ACP LOW
–30
RF ATT 0dB
0
–60
–5
–65
–10
–70
–15
–75
–20
–80
–25
–85
UNIT dBm
–18.47dBm
1.95999900GHz
–4.06dBm
–77.64dBm
–76.66dBm
A
–40
1AVG
1RM
–50
–60
–70
–80
C0
C0
–90
C11
CU1
–112
CU1
04700-035
–100
CENTER 1.96Hz
1MHz/
–30
Holding the differential I and Q control voltages steady at
0.353 V, input power was swept. Figure 36 shows variation in
spurious content, again measured at ±2.25 MHz carrier offset in
a 1 MHz bandwidth, as defined by the 3GPP2 specification.
–70
–72
–74
–76
–78
–80
0.2
0.3
0.4
IQ CONTROL VOLTAGE
Figure 37 shows that for a fixed input power, the ACP (measured in
dBm) tracks the output power as the gain is changed.
WCDMA APPLICATION
Figure 38 shows a plot of the output spectrum of the AD8341
transmitting a single-carrier WCDMA signal (Test Model 1-64
at 2140 MHz). The carrier power is approximately −9 dBm. The
differential I and Q control voltages are both equal to 0.353 V,
that is, the vector is sitting on the unit circle at 45°. At this
power level, an adjacent channel power ratio of −61 dBc is
achieved. The alternate channel power ratio of −72 dBc is
dominated by the noise floor of the AD8341.
MARKER 1 [T1 ]
–28.39dBm
2.14050000GHz
REF LVL
–24
–30
–84
–86
–24dBm
RBW 30kHz
VBW 300kHz
SWT 1s
1
OFFSET 1dB
04700-036
–88
–16
–14 –12 –10
–8
–6
OUTPUT POWER (dBm)
–4
–2
RF ATT 0dB
UNIT dBm
1 [T1]
–28.39dBm
2.14050000GHz
CH PWR
–8.95dBm
ACP UP
–60.78dB
ACP LOW
–60.82dB
ALT1 UP
–72.67dB
ALT1 LOW
–72.66dB
–40
–18
0.5
Figure 37. Output Power and ACP vs. I and Q Control Voltages,
CDMA2000 Test Model, VBBI = VBBQ, ACP Measured at
±2.25 MHz Carrier Offset in 1 MHz BW
–82
–90
–20
0.1
SPAN 10MHz
Figure 35. Output Spectrum, 1960 MHz, Single-Carrier CDMA2000
Test Model at −4 dBm, VBBI = VBBQ = 0.353 V, Adjacent Channel Power
Measured at ±2.25 MHz Carrier Offset in 1 MHz BW Input Signal Filtered
Using a Cavity Tuned Filter (Pass Band = 6.8 MHz)
ACP @ 2.25MHz OFFSET (dBm, 1MHz, BW)
–90
0
–50
1RM
–60
0
A
–70
Figure 36. Adjacent Channel Power vs. Output Power,
CDMA2000 Single Carrier @ 1960 MHz; ACP Measured at
±2.25 MHz Carrier Offset (1 MHz BW); VBBI = VBBQ = 0.353 V
–80
–90
C0
–100
With a fixed input power of 2.4 dBm, the output power was
again swept by exercising the I and Q inputs. VBBI and VBBQ were
kept equal and were swept from 100 mV to 500 mV. The resulting output power and ACP are shown in Figure 37.
C12
C12
C0
CU2
C11
–110
CU1
C11
–120
–124
04700-038
C11
ACP dBm (1MHz BW) @ 2.25MHz OFFSET
–12
–12dBm
OUTPUT POWER (dBm)
MARKER 1 [T1 ]
–18.47dBm
1.95999900GHz
REF LVL
04700-037
AD8341
CU1
CENTER 2.14GHz
2.5MHz/
SPAN 25MHz
Figure 38. AD8341 Single-Carrier WCDMA Spectrum at 2140 MHz
Figure 39 shows how ACPR and noise vary with varying input
power (differential I and Q control voltages are held at 0.353 V).
At high power levels, both adjacent and alternate channel power
ratios increase sharply. As output power drops, adjacent and
alternate channel power ratios both reach minimums before the
measurement becomes dominated by the noise floor of the
AD8341. At this point, adjacent and alternate channel power
ratios become approximately equal.
Rev. 0 | Page 15 of 20
AD8341
0
–40
–60
–45
–65
ACPR 10MHz OFFSET
–50
–70
–55
–75
–60
–80
–65
–85
–70
–90
–95
–75
NOISE –50MHz OFFSET
–80
–30
–100
–25
–20
–15
–10
–5
OUTPUT POWER (dBm)
0
5
–10
–50
–15
–60
–25
–65
–70
–30
ACPR 10MHz OFFSET
–35
–75
–40
–80
–45
–50
Figure 39. AD8341 ACPR and Noise vs. Output Power;
Single-Carrier WCDMA (Test Model 1-64 at 2140 MHz)
Figure 40 shows how output power, ACPR, and noise vary with
the differential I and Q control voltages. VBBI and VBBQ are tied
together and are varied from 0.5 V to 50 mV.
–55
ACPR 5MHz OFFSET
–20
–85
NOISE –50MHz OFFSET
–90
0
0.1
0.2
0.3
0.4
IQ CONTROL VOLTAGE
04700-040
–55
ACPR 5MHz OFFSET
–45
ACPR (dBc)
NOISE dBm @ 50MHz OFFSET (1MHz BW)
–35
OUTPUT POWER (dBm)
–50
–40
OUTPUT POWER dBm
–5
04700-039
–30
NOISE dBm @ 50MHz CARRIER OFFSET (1MHz BW)
ADJACENT/ALTERNATE CHANNEL POWER RATIO (dBc)
As the output power drops, the noise floor, measured in dBm in
1 MHz BW at 50 MHz carrier offset, drops slightly.
0.5
Figure 40. AD8341 Output Power, ACPR and Noise vs. VIQ.
Single-Carrier WCDMA (Test Model 1-64 at 2140 MHz)
In this case, adjacent channel power ratio remains constant as
the (noise dominated) alternate channel power degrades
roughly 1-for-1 with output power. As the I and Q control voltage drops, the noise floor again drops slowly.
Rev. 0 | Page 16 of 20
AD8341
EVALUATION BOARD
The evaluation board circuit schematic for the AD8341 is
shown in Figure 41.
The evaluation board is configured to be driven from a
single-ended 50 Ω source. Although the input of the AD8341 is
differential, it may be driven single-ended, with no loss of performance.
The low-pass corner frequency of the baseband I and Q channels can be reduced by installing capacitors in the C11 and C12
positions. The low-pass corner frequency for either channel is
approximated by
f3dB
45 kHz × 10 nF
≈
C FLT + 0.5 pF
On this evaluation board, the I and Q baseband circuits are
identical to each other, so the following description applies
equally to each. The connections and circuit configuration for
the Q baseband inputs are described in Table 4.
The baseband input of the AD8341 requires a differential voltage drive. The evaluation board is set up to allow such a drive by
connecting the differential voltage source to QBBP and QBBM.
The common-mode voltage should be maintained at approximately 0.5 V. For this configuration, Jumpers W1 through W4
should be removed.
The baseband input of the evaluation board may also be driven
with a single-ended voltage. In this case, a bias level is provided
to the unused input from Potentiometer R10 by installing either
W1 or W2.
Setting SW1 in Position B disables the AD8341 output amplifier.
With SW1 set to Position A, the output amplifier is enabled.
With SW1 set to Position A, an external voltage signal, such as a
pulse, can be applied to the DSOP SMA connector to exercise
the output amplifier enable/disable function.
Table 4. Evaluation Board Configuration Options
Components
R7, R9, R11,
R14, R15, R19,
R20, R21, C15,
C19, W3, W4
Function
I Channel Baseband Interface. Resistors R7 and R9 may be installed to accommodate a
baseband source that requires a specific terminating impedance. Capacitors C15 and C19
are bypass capacitors.
For single-ended baseband drive, the Potentiometer R11 can be used to provide a bias level
to the unused input (install either W3 or W4).
R1, R3, R10,
R12, R13, R16,
R17, R18, C16,
C20, W1, W2
Q Channel Baseband Interface. See the I Channel Baseband Interface section.
C11, C12
Baseband Low-Pass Filtering. By adding Capacitor C11 between QFLP and QFLM, and C12
between IFLP and IFLM, the 3 dB low-pass corner frequency of the baseband interface can
be reduced from 230 MHz (nominal). See equation in text.
Output Interface. The 1:1 balun transformer, T1, converts the 50 Ω differential output to 50
Ω single-ended. C17 and C18 are dc blocks. L1 and L2 provide dc bias for the output.
T1, C17, C18,
L1, L2
L3, L4, C5, C6
Input Interface. The input impedance of the AD8341 requires 1.2 nH inductors in series
with RFIP and RFIM for optimum return loss when driven by a single-ended 50 Ω line. C5
and C6 are dc blocks.
Rev. 0 | Page 17 of 20
Default Conditions
R7, R9 = Not Installed
R11 = Potentiometer, 2 kΩ,
10 Turn (Bourns)
R14 = 4 kΩ (Size 0603)
R15 = 44 kΩ (Size 0603)
R19, R20, R21 = 0 Ω
(Size 0603)
C15, C19 = 0.1 µF
(Size 0603)
W3 = Jumper (Installed)
W4 = Jumper (Open)
R1, R3 = Not Installed
R10 = Potentiometer, 2 kΩ,
10 Turn (Bourns)
R12 = 4 kΩ (Size 0603)
R13 = 44 kΩ (Size 0603)
R16, R17, R18 = 0 Ω
(Size 0603)
C16, C20 = 0.1 µF
(Size 0603)
W1 = Jumper (Installed)
W2 = Jumper (Open)
C11, C12 = Not Installed
C17, C18 = 100 pF
(Size 0603)
T1 = ETC1-1-13 (M/A-COM)
L1, L2 = 120 nH
(Size 0603)
L3, L4 = 1.2 nH (Size 0402)
C5, C6 = 100 pF (Size 0603)
AD8341
Components
C2, C4, C7,
C9, C14, C1,
C3, C8, C10,
R2, R4, R5, R6
Function
Supply Decoupling.
R8, SW1
Output Disable Interface. The output stage of the AD8341 is disabled by applying a high
voltage to the DSOP pin by moving SW1 to Position B. The output stage is enabled moving
SW1 to Position A. The output disable function can also be exercised by applying an external high or low voltage to the DSOP SMA connector with SW1 in Position A.
IBBP
Default Conditions
C2, C4, C7, C9, C14 = 0.1 µF
(Size 0603)
C1, C3, C8, C10 = 100 pF
(Size 0603)
R2, R4, R5, R6 = 0 Ω
(Size 0603)
R8 = 10 kΩ (Size 0603)
SW1 = SPDT (Position A,
Output Enabled)
IBBM
C19
R7
0.1µF (OPEN)
R9
(OPEN)
W4
R21
0Ω
VP
TEST POINT
C2
0.1µF
R20
0Ω
C15
0.1µF
R2
0Ω
VS
R14
4kΩ
GND
TEST POINT
R19
0Ω
W3
R11
2kΩ
R15
44kΩ
C1
100pF
C12
(OPEN)
C6
100pF
VPS2
IBBM
IFLP
VPRF
IBBP
VS
C8
100pF
R5
0Ω
IFLM
C7
0.1µF
SW1
CMRF
L3
1.2nH
R8
10kΩ
DSOP
CMOP
CMOP
RFIN
B
A
DSOP
C18
100pF
T1
ETC1-1-13
M/A-COM
RFOM
AD8341
RFIP
L4
1.2nH
C3
100pF
QFLP
C17
L1
100pF
120nH
CMOP
C14
0.1µF
VPS2
VP
C11
(OPEN)
C10
100pF
R12
4kΩ
R10
2kΩ
R6
0Ω
C9
0.1µF
R13
44kΩ
VS
C16
0.1µF
W2
R17
0Ω
R1
(OPEN)
W1
R16
0Ω
R18
0Ω
R3
C20 (OPEN)
0.1µF
QBBP
QBBM
Figure 41. Evaluation Board Schematic
Rev. 0 | Page 18 of 20
04700-041
R4
0Ω
VPS2
VPRF
C4
0.1µF
L2
120nH
CMOP
QBBM
CMRF
VP
RFOP
RFOP
QBBP
C5
100pF
QFLM
RFIN
Figure 42. Component Side Layout
04700-043
04700-042
AD8341
Figure 43. Component Side Silkscreen
Rev. 0 | Page 19 of 20
AD8341
OUTLINE DIMENSIONS
0.60 MAX
4.00
BSC SQ
PIN 1
INDICATOR
0.60 MAX
0.50
BSC
3.75
BSC SQ
TOP
VIEW
0.50
0.40
0.30
1.00
0.85
0.80
12° MAX
SEATING
PLANE
0.80 MAX
0.65 TYP
0.30
0.23
0.18
PIN 1
INDICATOR
24 1
19
18
2.25
2.10 SQ
1.95
EXPOSED
PAD
(BOTTOM VIEW)
13
12
7
6
0.25 MIN
2.50 REF
0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
Figure 44. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body (CP-24-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8341ACPZ-WP1, 2
AD8341ACPZ-REEL72
AD8341-EVAL
1
2
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
24-Lead Lead Frame Chip Scale Package (LFCSP)
24-Lead Lead Frame Chip Scale Package (LFCSP)
Evaluation Board
WP = Waffle pack.
Z = Pb-free part.
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
D04700–0–7/04(0)
Rev. 0 | Page 20 of 20
Package Option
CP-24-1
CP-24-1
Order Multiple
64
1,500
1