DCP01B SERIES SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004 Miniature, 1W Isolated UNREGULATED DC/DC CONVERTERS FEATURES D Up To 85% Efficiency D Thermal Protection D Device-to-Device Synchronization D Short-Circuit Protection D EN55022 Class B EMC Performance D UL1950 Recognized Component D JEDEC DIP-14 and SOP-14 Packages DESCRIPTION The DCP01B series is a family of 1W, unregulated, isolated DC/DC converters. Requiring a minimum of external components and including on-chip device protection, the DCP01B series provides extra features such as output disable and synchronization of switching frequencies. The use of a highly-integrated package design results in highly reliable products with a power density of 40W/in3 (2.4W/cm3). This combination of features and small sizes makes the DCP01B suitable for a wide range of applications. APPLICATIONS D Point-of-Use Power Conversion D Ground Loop Elimination D Data Acquisition D Industrial Control and Instrumentation D Test Equipment SYNCOUT 800kHz Oscillator ÷ 2 Reset VOUT Power Stage SYNCIN 0V Watch−dog/ start−up PSU T herm al Shutdown IBIAS VS Power Controller IC 0V Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright 2000−2004, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com DCP01B SERIES www.ti.com SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. SUPPLEMENTAL ORDERING INFORMATION ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) Input voltage DCP01B SERIES UNIT 5V models 7 V 15V models 18 V 24V models 29 V −40 to +125 °C +270 °C Storage temperature Lead temperature (soldering, 10s) (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. DCP01 05 05 (D) (B) ( ) Basic Model Number: 1W Product Voltage Input: 5V In Voltage Output: 5V Out Dual Output: Model Revision: Package Code: P = DIP−14 P−U = SOP−14 (Gullwing) ORDERING INFORMATION(1) PRODUCT PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE DIP-14 NVA −40°C to +100°C DCP010505BP DCP010505BP Rails SOP-14(4) DUA −40°C to +100°C DCP010505BP−U DCP010505BP−U/700 Tape and Reel DIP-14 NVA −40°C to +100°C DCP010512BP DCP010512BP Rails SOP-14(4) DUA −40°C to +100°C DCP010512BP−U DCP010512BP−U/700 Tape and Reel DIP-14 NVA −40°C to +100°C DCP010515BP DCP010515BP Rails SOP-14(4) DUA −40°C to +100°C DCP010515BP−U DCP010515BP−U/700 Tape and Reel DIP-14 NVA −40°C to +100°C DCP012405BP DCP012405BP Rails SOP-14(4) DUA −40°C to +100°C DCP012405BP−U DCP012405BP−U/700 Tape and Reel DIP-14 NVA −40°C to +100°C DCP010505DBP DCP010505DBP Rails SOP-14(4) DUA −40°C to +100°C DCP010505DBP−U DCP010505DBP−U/700 Tape and Reel PACKAGE-LEAD PACKAGE MARKING ORDERING NUMBER(2) TRANSPORT MEDIA SINGLE VOLTAGE(3) DCP010505 DCP010512 DCP010515 DCP012405 DUAL VOLTAGE(3) DCP010505 DCP010512 DCP010515 DCP011512 DCP011515 DCP012415 (1) DIP-14 NVA −40°C to +100°C DCP010512DBP DCP010512DBP Rails SOP-14(4) DUA −40°C to +100°C DCP010512DBP−U DCP010512DBP−U/700 Tape and Reel DIP-14 NVA −40°C to +100°C DCP010515DBP DCP010515DBP Rails SOP-14(4) DUA −40°C to +100°C DCP010515DBP−U DCP010515DBP−U/700 Tape and Reel DIP-14 NVA −40°C to +100°C DCP011512DBP DCP011512DBP Rails SOP-14(4) DUA −40°C to +100°C DCP011512DBP−U DCP011512DBP−U/700 Tape and Reel DIP-14 NVA −40°C to +100°C DCP011515DBP DCP011515DBP Rails SOP-14(4) DUA −40°C to +100°C DCP011515DBP−U DCP011515DBP−U/700 Tape and Reel DIP-14 NVA −40°C to +100°C DCP012415DBP DCP012415DBP Rails SOP-14(4) DUA −40°C to +100°C DCP012415DBP−U DCP012415DBP−U/700 Tape and Reel All devices also available in tray quatities. For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or refer to our web site at www.ti.com. (2) Models with a (/) are available only in Tape and Reel in the quantities indicated (for example, /700 indicates 700 devices per reel). Ordering 700 pieces of “DCP010505BP−U/700” will get a single 700-piece Tape and Reel. (3) Single voltage versions have six active pins; dual voltage versions have seven active pins. (4) SOP package is gullwing surface-mount. 2 DCP01B SERIES www.ti.com SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS At TA = +25°C, VS = nominal, CIN = 2.2µF, and COUT = 0.1µF, unless otherwise noted. DCP01B SERIES PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Output Power 100% full load Ripple O/P capacitor = 1µF, 50% load Voltage vs Temperature 0.97 W 20 mVPP Room to cold 0.046 %/°C Room to hot 0.016 %/°C Input Voltage range on VS −10 +10 % Isolation Voltage 1s flash test 1 kVrms 60s test, UL1950(1) 1 kVrms Line Regulation Minimum VS ≤ IO constant ≤ typical VS Typical VS ≤ IO constant ≤ maximum VS Voltage Source (VS) 1 15(2) % change of VS Switching/Synchronization Oscillator frequency (fOSC) Switcing frequency = fOSC/2 800 Sync input low kHz 0.4 Sync input current VSYNC = +2V V µA 75 Disable time µs 2 Capacitance loading on SYNCIN pin External 3 pF +70 °C Reliability Demonstrated MSL 3−(U) versions TA = +55°C −40 Thermal Shutdown IC temperature at shutdown +150 °C 3 mA Shutdown current Temperature Range Operating −40 °C +100 (1) During UL1950 recognition tests only. (2) Line regulation is measured at constant load current. Line regulation = (V OUT at IOUT fixed)/VS. Variation % = VS min to VS typ, VS typ to VS max. ELECTRICAL CHARACTERISTICS PER DEVICE At TA = +25°C, VS = nominal, CIN = 2.2µF, and COUT = 0.1µF, unless otherwise noted. INPUT VOLTAGE (V) OUTPUT VOLTAGE (V) VS VNOM = VS Typical 75% LOAD(3) LOAD REGULATION (%) NO LOAD CURRENT (mA) EFFICIENCY (%) BARRIER CAPACITANCE (pF) 10% TO 100% LOAD(4) 0% LOAD 100% LOAD VISO = 750VRMS IQ CISO PRODUCT MIN TYP MAX MIN TYP MAX TYP MAX TYP TYP TYP DCP010505B 4.5 5 5.5 4.75 5 5.25 19 31 20 80 3.6 DCP010505DB 4.5 5 5.5 ±4.25 ±5 ±5.75 18 32 22 81 3.8 DCP010512B 4.5 5 5.5 11.4 12 12.6 21 38 29 85 5.1 DCP010512DB 4.5 5 5.5 ±11.4 ±12 ±12.6 19 37 40 82 4.0 DCP010515B 4.5 5 5.5 14.25 15 15.75 26 42 34 82 3.8 DCP010515DB 4.5 5 5.5 ±14.25 ±15 ±15.75 19 41 42 85 4.7 DCP011512DB 13.5 15 16.5 ±11.4 ±12 ±12.6 11 39 19 78 2.5 DCP011515DB 13.5 15 16.5 ±14.25 ±15 ±15.75 12 39 20 80 2.5 DCP012405B 21.6 24 26.4 4.75 5 5.25 13 23 14 77 2.5 DCP012415DB 21.6 24 26.4 ±14.25 ±15 ±15.75 10 35 17 76 3.8 (3) (4) 100% load current = 1W/VS typical. Load regulation = (VOUT at 10% load − VOUT at 100% load)/VOUT at 75% load. 3 DCP01B SERIES www.ti.com SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004 PIN ASSIGNMENTS (Single Voltage Version) PIN ASSIGNMENTS (Dual Voltage Version) NVA and DUA PACKAGES (TOP VIEW) VS 1 0V 2 NVA and DUA PACKAGES (TOP VIEW) 14 SYNCIN VS 1 0V 2 14 SYNCIN DCP01B DCP01DB 0V 5 0V 5 +VOUT 6 +VOUT 6 NC 7 −VOUT 7 8 SYNCOUT Terminal Functions (Single Voltage) SYNCOUT Terminal Functions (Dual Voltage) TERMINAL NAME 8 TERMINAL NO. I/O NO. I/O VS 1 I Voltage input DESCRIPTION VS 1 I Voltage input 0V 2 I Input side common 0V 2 I Input side common 0V 5 O Output side common 0V 5 O Output side common +VOUT 6 O +Voltage out +VOUT 6 O +Voltage out NC 7 Not connected −VOUT 7 O −Voltage out SYNCOUT 8 O Unrectified transformer output SYNCOUT 8 O Unrectified transformer output SYNCIN 14 I Synchronization pin SYNCIN 14 I Synchronization pin NOTE: I = input and O = output. 4 NAME DESCRIPTION NOTE: I = input and O = output. DCP01B SERIES www.ti.com SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS At TA = 25°C, unless otherwise noted. DCP010505B OUTPUT RIPPLE vs LOAD (20MHz BW) DCP010505B VOUT vs VS 5.5 50 1µF Ceramic 4.7µF Ceramic 10µF Ceramic 45 40 5.4 5.3 5.2 5.1 30 VOUT (V) Ripple (mVPP) 35 25 20 5.0 4.9 4.8 15 4.7 10 4.6 5 4.5 4.4 0 10 20 30 40 50 60 70 80 90 4.5 100 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 90 100 90 100 VS (V) Load (%) DCP010505B VOUT vs LOAD DCP010505B EFFICIENCY vs LOAD 5.8 85 5.7 80 5.6 Efficiency (%) 5.5 VOUT (V) 5.4 5.3 5.2 5.1 75 70 65 5.0 4.9 60 4.8 4.7 55 10 20 30 40 50 60 70 80 90 100 10 20 30 40 Load (%) 50 60 70 80 Load (%) DCP010505DB VOUT vs LOAD DCP010505DB EFFICIENCY vs LOAD 5.8 85 +VOUT 5.7 −VOUT 5.6 80 Efficiency (%) 5.5 VOUT (V) 5.4 5.3 5.2 5.1 75 70 65 5.0 4.9 60 4.8 4.7 55 10 20 30 40 50 60 Load (%) 70 80 90 100 10 20 30 40 50 60 70 80 Load (%) 5 DCP01B SERIES www.ti.com SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS (continued) At TA = 25°C, unless otherwise noted. DCP010512B VOUT vs LOAD DCP010512B EFFICIENCY vs LOAD 14.5 90 14.0 85 80 Efficiency (%) VOUT (V) 13.5 13.0 12.5 12.0 75 70 65 60 11.5 55 11.0 50 10 20 30 40 50 60 70 80 90 10 100 20 30 40 Load (%) 50 60 70 80 90 100 90 100 90 100 Load (%) DCP010512DB VOUT vs LOAD DCP010512DB EFFICIENCY vs LOAD 14.5 85 14.0 80 13.5 75 Efficiency (%) VOUT (V) 13.0 12.5 12.0 11.5 70 65 60 11.0 +VOUT −VOUT 10.5 55 50 10.0 10 20 30 40 50 60 70 80 90 10 100 20 30 40 Load (%) DCP010515B VOUT vs LOAD 85 17.5 80 70 80 75 Efficiency (%) VOUT (V) 60 DCP010515B EFFICIENCY vs LOAD 18.0 17.0 16.5 16.0 15.5 70 65 60 15.0 55 14.5 50 14.0 10 20 30 40 50 60 Load (%) 6 50 Load (%) 70 80 90 100 10 20 30 40 50 60 Load (%) 70 80 DCP01B SERIES www.ti.com SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS (continued) At TA = 25°C, unless otherwise noted. DCP010515DB VOUT vs LOAD DCP010515DB EFFICIENCY vs LOAD 18 90 85 80 Efficiency (%) VOUT (V) 17 16 15 75 70 65 60 +VOUT −VOUT 55 14 50 10 20 30 40 50 60 70 80 90 100 10 20 30 40 50 Load (%) DCP012405B VOUT vs LOAD 90 5.50 80 80 90 100 90 100 70 Efficiency (%) 5.40 5.30 5.20 5.10 60 50 40 30 5.00 20 4.90 10 0 4.80 10 20 30 40 50 60 70 80 100 10 30 40 50 60 70 80 Load (%) DCP010505B CONDUCTED EMISSIONS (125% Load) DCP010505B CONDUCTED EMISSIONS (8% Load) 60 60 50 50 40 30 20 10 0 −10 −20 0.15 20 Load (%) Emission Level, Peak (dBµA) VOUT (V) 70 DCP012405B EFFICIENCY vs LOAD 5.60 Emission Level, Peak (dBµA) 60 Load (%) 1 Frequency (MHz) 10 30 40 30 20 10 0 −10 −20 0.15 1 10 30 Frequency (MHz) 7 DCP01B SERIES www.ti.com SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS (continued) At TA = 25°C, unless otherwise noted. DCP011512DBP EFFICIENCY vs LOAD DCP011512DBP VOUT vs LOAD 13.50 80 +VOUT −VOUT 13.00 75 70 65 Efficiency (%) VOUT (V) 12.50 12.00 11.50 60 55 50 45 40 11.00 35 30 10.50 10 20 30 40 50 60 70 80 90 100 10 20 30 40 Load (%) 50 60 70 80 90 100 Load (%) DCP011515DBP EFFICIENCY vs LOAD DCP011515DBP VOUT vs LOAD 90 17.00 +VOUT −VOUT 16.50 80 Efficiency (%) Efficiency (%) 16.00 70 60 50 15.50 15.00 14.50 14.00 40 13.50 30 13.00 10 20 30 40 50 60 70 80 90 100 10 20 30 40 Load (%) DCP012415DBP EFFICIENCY vs LOAD 16.50 80 16.00 70 80 90 100 +VOUT −VOUT 15.50 VOUT (V) Efficiency (%) 60 DCP012415DBP VOUT vs LOAD 90 70 60 50 15.00 14.50 40 14.00 30 20 13.50 10 20 30 40 50 60 Load (%) 8 50 Load (%) 70 80 90 100 10 20 30 40 50 60 Load (%) 70 80 90 100 DCP01B SERIES www.ti.com SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004 FUNCTIONAL DESCRIPTION OVERVIEW The DCP01B offers up to 1W of unregulated output power with a typical efficiency of up to 85%. This is achieved through highly integrated packaging technology and the implementation of a custom power stage and control IC. The circuit design uses an advanced BiCMOS/DMOS process. For additional information, refer to the application notes located in the DCP01B product folder at www.ti.com. POWER STAGE This uses a push-pull, center-tapped topology switching at 400kHz (divide-by-2 from 800kHz oscillator). OSCILLATOR AND WATCHDOG The onboard 800kHz oscillator generates the switching frequency via a divide-by-2 circuit. The oscillator can be synchronized to other DCP01B circuits or an external source, and is used to minimize system noise. A watchdog circuit checks the operation of the oscillator circuit. The oscillator can be stopped by pulling the SYNC pin low. The output pins will be tri-stated. This will occur in 2µs. THERMAL SHUTDOWN The DCP01B is protected by a thermal shutdown circuit. If the on-chip temperature exceeds 150°C, the device will shut down. Once the temperature falls below 150°C, normal operation will resume. If the thermal condition continues, operation will randomly cycle on and off. This will continue until the temperature is reduced. SYNCHRONIZATION In the event that more than one DC/DC converter is needed onboard, beat frequencies and other electrical interference can be generated. This is due to the small variations in switching frequencies between the DC/DC converters. The DCP01B overcomes this by allowing devices to be synchronized to one another. Up to eight devices can be synchronized by connecting the SYNCIN pins together, taking care to minimize the stray capacitance. Stray capacitance (> 3pF) will have the effect of reducing the switching frequency, or even stopping the oscillator circuit. If synchronized devices are used, it should be noted that at startup, all devices will draw maximum current simultaneously. This can cause the input voltage to dip. If it dips below the minimum input voltage (4.5V), the devices may not start up. A 2.2µF capacitor should be connected close to the input pins. If more than eight devices are to be synchronized, it is recommended that the SYNCIN pins are driven by an external device. Details are contained in Application Report SBAA035, External Synchronization of the DCP01/02 Series of DC/DC Converters, available for download at www.ti.com. CONSTRUCTION The DCP01B basic construction is the same as standard ICs. There is no substrate within the molded package. The DCP01B is constructed using an IC, rectifier diodes, and a wound magnetic toroid on a leadframe. Since there is no solder within the package, the DCP01B does not require any special PCB assembly processing. This results in an isolated DC/DC converter with inherently high reliability. ADDITIONAL FUNCTIONS DISABLE/ENABLE The DCP01B can be disabled or enabled by driving the SYNC pin using an open drain CMOS gate. If the SYNCIN pin is pulled low, the DCP01B will be disabled. The disable time depends upon the external loading; the internal disable function is implemented in 2µs. Removal of the pull-down will cause the DCP01B to be enabled. Capacitive loading on the SYNCIN pin should be minimized in order to prevent a reduction in the oscillator frequency. DECOUPLING Ripple Reduction A high switching frequency of 400kHz allows simple filtering. To reduce ripple, it is recommended that at least a 1µF capacitor is used on VOUT. Dual outputs should have both the positive and negative buses decoupled to VOUT ground (pin 5). The required 2.2µF low equivalent series resistance (ESR) ceramic capacitor on the input of the 5V to 15V versions, and the ≥ 0.47µF low-ESR ceramic capacitor on the 24V versions help reduce ripple and noise. See Application Bulletin SBVA012, DC-to-DC Converter Noise Reduction, available for download at www.ti.com. 9 DCP01B SERIES www.ti.com SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004 The outputs on dual output DCP01B versions can also be connected in series to provide two times the magnitude of VOUT, as shown in Figure 2. For example, a dual 15V DCP01B could be connected to provide a 30V rail. Connecting the DCP01B in Series Multiple DCP01B isolated 1W DC/DC converters can be connected in series to provide nonstandard voltage rails. This is possible by using the floating outputs provided by the DCP01B galvanic isolation. Connecting the DCP01B in Parallel Connect the positive VOUT from one DCP01B to the negative VOUT (0V) of another, as shown in Figure 1. If the SYNC IN pins are tied together, the self-synchronization feature of the DCP01B will prevent beat frequencies on the voltage rails. The SYNCIN feature of the DCP01B allows easy connection in series, which reduces separate filtering components. VSUPPLY If the output power from one DCP01B is not sufficient, it is possible to parallel the outputs of multiple DCP01B converters (see Figure 3). Again, the SYNCIN feature allows easy synchronization to prevent power-rail beat frequencies at no additional filtering cost. VOUT 1 VS CIN(1) SYNCIN DCP C OUT 01B 0V 0V VS VOUT 2 VOUT1 + VOUT2 CIN(1) SYNCIN DCP COUT 01B 0V COM 0V NOTE: (1) CIN requires a low−ESR ceramic capacitor: 5V to 15V version is 2.2µF; 24V version is minimum 0.47µF. COUT = 1.0µF. Figure 1. Connecting the DCP01B in Series VSUPPLY VS CIN(1) +VOUT DCP 01B 0V −VOUT +VOUT COUT(1) COUT(1) 0V −VOUT NOTE: (1) CIN requires a low−ESR ceramic capacitor: 5V to 15V version is 2.2µF; 24V version is minimum 0.47µF. COUT = 1.0µF. COM Figure 2. Connecting Dual Outputs in Series VSUPPLY VOUT VS CIN(1) SYNCIN DCP COUT(1) 01B 0V 0V VS VOUT 2 x Power Out CIN(1) SYNCIN 0V COM DCP COUT(1) 01B 0V NOTE: (1) CIN requires a low−ESR ceramic capacitor: 5V to 15V version is 2.2µF; 24V version is minimum 0.47µF. COUT = 1.0µF. Figure 3. Connecting Multiple DCP01Bs in Parallel 10 DCP01B SERIES www.ti.com SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004 APPLICATION INFORMATION The DCP01B, DCV01, and DCP02 are three families of miniature DC/DC converters providing an isolated unregulated voltage output. All are fabricated using a CMOS/DMOS process with the DCP01B replacing the familiar DCP01 family that was fabricated from a bipolar process. The DCP02 is essentially an extension of the DCP01B family providing a higher power output with a significantly improved load regulation, and the DCV01 is tested to a higher isolation voltage. TRANSFORMER DRIVE CIRCUIT Transformer drive transistors have a characteristically low value of transistor on resistance (RDS); thus, more power is transferred to the transformer. The transformer drive circuit is limited by the base current available to switch on the power transistors driving the transformer and their characteristic current gain (beta), resulting in a slower turn-on time. Consequently, more power is dissipated within the transistor. This results in a lower overall efficiency, particularly at higher output load currents. SELF-SYNCHRONIZATION The input synchronizations facility (SYNCIN), allows for easy synchronizing of multiple devices. If two to eight devices (maximum) have their respective SYNCIN pins connected together, then all devices will be synchronized. Each device has its own onboard oscillator. This is generated by charging a capacitor from a constant current and producing a ramp. When this ramp passes a threshold, an internal switch is activated that discharges the capacitor to a second threshold before the cycle is repeated. When several devices are connected together, all the internal capacitors are charged simultaneously. cycle so that all devices discharge together. A subsequent charge cycle is only restarted when the last device has finished its discharge cycle. OPTIMIZING PERFORMANCE Optimum performance can only be achieved if the device is correctly supported. By the very nature of a switching converter, it requires power to be instantly available when it switches on. If the converter has DMOS switching transistors, the fast edges will create a high current demand on the input supply. This transient load placed on the input is supplied by the external input decoupling capacitor, thus maintaining the input voltage. Therefore, the input supply does not see this transient (this is an analogy to high-speed digital circuits). The positioning of the capacitor is critical and must be placed as close as possible to the input pins and connected via a low-impedance path. The optimum performance is primarily dependent on two factors: 1. Connection of the input and output circuits for minimal loss. 2. The ability of the decoupling capacitors to maintain the input and output voltages at a constant level. PCB Design The copper losses (resistance and inductance) can be minimized by the use of mutual ground and power planes (tracks) where possible. If that is not possible, use wide tracks to reduce the losses. If several devices are being powered from a common power source, a star-connected system for the track must be deployed; devices must not be connected in series, as this will cascade the resistive losses. The position of the decoupling capacitors is important. They must be as close to the devices as possible in order to reduce losses. See the PCB Layout section for more details. When one device passes its threshold during the charge cycle, it starts the discharge cycle. All the other devices sense this falling voltage and, likewise, initiate a discharge 11 DCP01B SERIES www.ti.com SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004 Decoupling Ceramic Capacitors Input Capacitor and the effects of ESR All capacitors have losses due to their internal equivalent series resistance (ESR), and to a lesser degree their equivalent series inductance (ESL). Values for ESL are not always easy to obtain. However, some manufacturers provide graphs of Frequency versus Capacitor Impedance. These will show the capacitors’ impedance falling as frequency is increased (see Figure 4). As the frequency is increased, the impedance will stop decreasing and begin to rise. The point of minimum impedance indicates the capacitors’ resonant frequency. This frequency is where the components of capacitance and inductance reactance are of equal magnitude. Beyond this point, the capacitor is not effective as a capacitor. If the input decoupling capacitor is not ceramic with < 20mΩ ESR, then at the instant the power transistors switch on, the voltage at the input pins will fall momentarily. Should the voltage fall below approximately 4V, the DCP will detect an under-voltage condition and switch the DCP drive circuits to the off state. This is carried out as a precaution against a genuine low input voltage condition that could slow down or even stop the internal circuits from operating correctly. This would result in the drive transistors being turned on too long, causing saturation of the transformer and destruction of the device. Z XL 0 fO Normal startup should occur in approximately 1ms from power being applied to the device. If a considerably longer startup duration time is encountered, it is likely that either (or both) the input supply or the capacitors are not performing adequately. Frequency Where: XC is the reactance due to the capacitance, XL is the reactance due to the ESL fO the resonant frequency Z = √ (XC − XL)2 + (ESR)2 Figure 4. Capacitor Impedance vs Frequency At fO, XC = XL; however, there is a 180° phase difference resulting in cancellation of the imaginary component. The resulting effect is that the impedance at the resonant point is the real part of the complex impedance; namely, the value of the ESR. The resonant frequency must be well above the 800kHz switching frequency of the DCP and DCVs. The effect of the ESR is to cause a voltage drop within the capacitor. The value of this voltage drop is simply the product of the ESR and the transient load current, as shown in Equation (1): V IN + VPK * (ESR I TR) (1) Where: VIN is the voltage at the device input. For 5V to 15V input devices, a 2.2µF low-ESR ceramic capacitor will ensure a good startup performance, and for the remaining input voltage ranges, 0.47µF ceramic capacitors are good. Tantalum capacitors are not recommended, since most do not have low-ESR values and will degrade performance. If tantalum capacitors must be used, close attention must be paid to both the ESR and voltage as derated by the vendor. Output Ripple Calculation Example DCP020505: Output voltage 5V, Output current 0.4A. At full output power, the load resistor is 12.5Ω. Output capacitor of 1µF, ESR of 0.1Ω. Capacitor discharge time 1% of 800kHz (ripple frequency): tDIS = 0.0125µs t = C × RLOAD t = 1 × 10−6 × 12.5 = 12.5µs VDIS = VO(1 − EXP(−tDIS/τ)) VDIS = 5mV By contrast the voltage dropped due to the ESR: VPK is the maximum value of the voltage on the capacitor during charge. VESR = ILOAD × ESR ITR is the transient load current. Ripple voltage = 45mV The other factor that affects the performance is the value of the capacitance. However, for the input and the full wave outputs (single-output voltage devices), the ESR is the dominant factor. 12 Following detection of a low input voltage condition, the device switches off the internal drive circuits until the input voltage returns to a safe value. Then the device tries to restart. If the input capacitor is still unable to maintain the input voltage, shutdown recurs. This process is repeated until the capacitor is charged sufficiently to start the device correctly. Otherwise, the device will be caught up in a loop. VESR = 40mV Clearly, increasing the capacitance will have a much smaller effect on the output ripple voltage than reducing the value of the ESR for the filter capacitor. DCP01B SERIES www.ti.com SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004 DUAL OUTPUT VOLTAGE DCP AND DCVs The voltage output for the dual DCPs is half wave rectified; therefore, the discharge time is 1.25µs. Repeating the above calculations using the 100% load resistance of 25Ω (0.2A per output), the results are shown below: τ = 25µs TDIS = 1.25µs. VDIS = 244mV The Sync pin, when not being used, is best left as a floating pad. A ground ring or annulus connected around the pin will prevent noise being conducted onto the pin. If the Sync pin is being connected to one or more Sync pins, then the linking trace should be narrow and must be kept short in length. In addition, no other trace should be in close proximity to this trace because that will increase the stray capacitance on this pin, and that will effect the performance of the oscillator. VESR = 20mV Ripple and Noise Ripple Voltage = 266mV Careful consideration should be given to the layout of the PCB, in order that the best results can be obtained. This time, it is the capacitor discharging that is contributing to the largest component of ripple. Changing the output filter to 10µF, and repeating the calculations: Ripple Voltage = 45mV. This value is composed of almost equal components. The above calculations are given only as a guide. Capacitor parameters usually have large tolerances and can be susceptible to environmental conditions. PCB LAYOUT Figure 5 and Figure 6 illustrate a printed circuit board (PCB) layout for the two conventional (DCP01/02, DCV01), and two SO-28 surface-mount packages (DCP02U). Figure 7 shows the schematic. Input power and ground planes have been used, providing a low-impedance path for the input power. For the output, the common or 0V has been connected via a ground plane, while the connections for the positive and negative voltage outputs are conducted via wide traces in order to minimize losses. The location of the decoupling capacitors in close proximity to their respective pins ensures low losses due to the effects of stray inductance; thus, improving the ripple performance. This is of particular importance to the input decoupling capacitor as this supplies the transient current associated with the fast switching waveforms of the power drive circuits. The DCP01B is a switching power supply and as such can place high peak current demands on the input supply. In order to avoid the supply falling momentarily during the fast switching pulses, ground and power planes should be used to connect the power to the input of DCP01B. If this is not possible, then the supplies must be connected in a star formation with the traces made as wide as possible. If the SYNCIN pin is being used, then the trace connection between device SYNCIN pins should be short to avoid stray capacitance. If the SYNCIN pin is not being used, it is advisable to place a guard ring (connected to input ground) around this pin to avoid any noise pick up. The output should be taken from the device using ground and power planes; this ensures minimum losses. A good quality low-ESR ceramic capacitor placed as close as practical across the input will reduce reflected ripple and ensure a smooth startup. A good quality low-ESR capacitor (ceramic preferred) placed as close as practical across the rectifier output terminal and output ground gives the best ripple and noise performance. See SBVA012 for more information on noise rejection. THERMAL MANAGEMENT Due to the high power density of this device, it is advisable to provide ground planes on the input and output. 13 DCP01B SERIES www.ti.com SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004 Figure 5. Example of PCB Layout, Component-Side View Figure 6. Example of PCB Layout, Non-component-Side View 14 DCP01B SERIES www.ti.com SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004 CON3 CON1 1 VS1 C1 2 0V1 SYNC 14 VS3 JP1 6 +V1 R1 C3 C2−1 C2 R2 C5 C4−1 C11 0S3 2 3 +V3 13 DCP02xP C14 C15 −V3 SYNC 14 C6 2 0V2 R3 C8 C7−1 COM2 R4 −V2 C10 C9−1 NC CON4 VS4 JP2 C16 R7 5 COM4 7 −V4 SYNC 28 27 C17 JP2 26 NC DCP02xU C 18 12 R8 C9 2 3 13 +V4 DCP02xP C7 26 1 0S4 6 +V2 JP1 14 CON2 1 VS2 28 27 12 R6 7 SYNC DCP02xU C12 COM3 C4 −V1 C13 R5 5 COM1 1 C20 C19 14 (1) Capacitors C2−1, C4−1, C7−1, and C9−1 are through-hole plated components connected in parallel with C2, C4, C7 and C9 (1206 SMD), respectively. For optimum low-noise performance, use low-ESR capacitors. (3) Do not connect the SYNC pin jumper (JP1−JP4) if the SYNC function is not being used. (4) Connections to the power input should be made with a minimum wire of 16/0.2 twisted pair, with the length kept short. (5) VSx and 0Vx are input supply and ground respecively (x represents the channel). (6) +Vx and −Vx are the positive and negative outputs, referenced to a common ground COMx. (7) JPx are the links used for self-synchronization; if this facility is not being used, the links should be unconnected. (8) R1−R8 are the power output loads; do not fit these if an external load is connected. (9) CON1 and CON2 are DIL-14; CON3 and CON4 are SO-28 packages. (10) NC = not connected. (2) Figure 7. Example of PCB Layout, Schematic Diagram 15 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) DCP010505BP ACTIVE PDIP NVA 7 25 TBD CU SNPB Level-NA-NA-NA DCP010505BP-U ACTIVE SOP DUA 7 25 TBD CU SNPB Level-3-240C-168 HR DCP010505BP-U/700 ACTIVE SOP DUA 7 700 TBD CU SNPB Level-3-240C-168 HR DCP010505DBP ACTIVE PDIP NVA 7 25 TBD CU SNPB Level-NA-NA-NA DCP010505DBP-U ACTIVE SOP DUA 7 25 TBD CU SNPB Level-3-240C-168 HR DCP010505DBP-U/700 ACTIVE SOP DUA 7 700 TBD CU SNPB Level-3-240C-168 HR DCP010512BP ACTIVE PDIP NVA 7 25 TBD CU SNPB Level-NA-NA-NA DCP010512BP-U ACTIVE SOP DUA 7 25 TBD CU SNPB Level-3-240C-168 HR DCP010512BP-U/700 ACTIVE SOP DUA 7 700 TBD CU SNPB Level-3-240C-168 HR DCP010512DBP ACTIVE PDIP NVA 7 25 TBD CU SNPB Level-NA-NA-NA DCP010512DBP-U ACTIVE SOP DUA 7 25 TBD CU SNPB Level-3-240C-168 HR DCP010512DBP-U/700 ACTIVE SOP DUA 7 700 TBD CU SNPB Level-3-240C-168 HR DCP010515BP ACTIVE PDIP NVA 7 25 TBD CU SNPB Level-NA-NA-NA DCP010515BP-U ACTIVE SOP DUA 7 25 TBD CU SNPB Level-3-240C-168 HR DCP010515BP-U/700 ACTIVE SOP DUA 7 700 TBD CU SNPB Level-3-240C-168 HR DCP010515DBP ACTIVE PDIP NVA 7 25 TBD CU SNPB Level-NA-NA-NA DCP010515DBP-U ACTIVE SOP DUA 7 25 TBD CU SNPB Level-3-240C-168 HR DCP010515DBP-U/700 ACTIVE SOP DUA 7 700 TBD CU SNPB Level-3-240C-168 HR DCP011512DBP ACTIVE PDIP NVA 7 25 TBD CU SNPB Level-NA-NA-NA DCP011512DBP-U ACTIVE SOP DUA 7 25 TBD CU SNPB Level-3-240C-168 HR DCP011512DBP-U/700 ACTIVE SOP DUA 7 700 TBD CU SNPB Level-3-240C-168 HR DCP011515DBP ACTIVE PDIP NVA 7 25 TBD CU SNPB Level-NA-NA-NA DCP011515DBP-U ACTIVE SOP DUA 7 25 TBD CU SNPB Level-3-240C-168 HR DCP011515DBP-U/700 ACTIVE SOP DUA 7 700 TBD CU SNPB Level-3-240C-168 HR DCP012415DBP ACTIVE PDIP NVA 7 25 TBD CU SNPB Level-NA-NA-NA DCP012415DBP-U ACTIVE SOP DUA 7 25 TBD CU SNPB Level-3-240C-168 HR DCP012415DBP-U/700 ACTIVE SOP DUA 7 700 TBD CU SNPB Level-3-240C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 MECHANICAL DATA MPDI058 – APRIL 2001 NVA (R-PDIP-T7/14) PLASTIC DUAL-IN-LINE D 0.775 (19,69) 0.735 (18,67) 14 8 0.280 (7,11) 0.240 (6,10) D 1 7 Index Area E H Base Plane 0.070 (1,78) 0.045 (1,14) 0.015 (0,38) MIN C 0.005 (0,13) D MIN Full Lead 4 PL 0.195 (4,95) 0.115 (2,92) –C– 0.100 (2,54) Seating Plane 0.022 (0,56) 0.014 (0,36) 0.210 (5,33) MAX 0.325 (8,26) 0.300 (7,62) C 0.150 (3,81) 0.115 (2,92) 0.300 (7,63) E C 0.430 (10,92) MAX F 0.010 (0,25) M C 0.014 (0,36) 0.008 (0,20) 0.060 (1,52) 0.000 (0,00) F 4202489/A 03/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Dimensions are measured with the package seated in JEDEC seating plane gauge GS-3. D. Dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 (0,25). E. Dimensions measured with the leads constrained to be perpendicular to Datum C. F. Dimensions are measured at the lead tips with the leads unconstrained. G. Pointed or rounded lead tips are preferred to ease insertion. H. Lead shoulder maximum dimension does not include dambar protrusions. Dambar protrusions shall not exceed 0.010 (0,25). POST OFFICE BOX 655303 I. Distance between leads including dambar protrusions to be 0.005 (0,13) minumum. J. A visual index feature must be located within the cross–hatched area. K. For automatic insertion, any raised irregularity on the top surface (step, mesa, etc.) shall be symmetrical about the lateral and longitudinal package centerlines. L. Falls within JEDEC MS-001-AA. • DALLAS, TEXAS 75265 1 MECHANICAL DATA MPDS097 – APRIL 2001 DUA (R-PDSO-G7/14) PLASTIC SMALL-OUTLINE C 0.775 (19,69) 14 0.735 (18,67) 8 0.280 (7,11) 0.240 (6,10) Index Area 1 C 7 0.022 (0,56) 0.014 (0,36) 0.420 (10,70) 0.405 (10,30) 0.070 (1,78) 0.045 (1,14) D 0.210 (5,33) MAX 0.325 (8,26) 0.300 (7,62) Base Plane 0.014 (0,36) 0.008 (0,20) Seating Plane 0.100 (2,54) 0.043 (1,10) 0.015 (0,38) MIN 0 " 5° 0.025 (0,65) 0.057 (1,45) 0.005 (0,13) MIN Full Lead 4 PL C 0.045 (1,15) 4202490/A 03/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 (0,25). D. Lead shoulder maximum dimension does not include dambar protrusions. Dambar protrusions shall not exceed 0.010 (0,25). E. Distance between leads including dambar protrusions to be 0.005 (0,13) minimum. F. A visual index feature must be located within the cross–hatched area. G. For automatic insertion, any raised irregularity on the top surface (step, mesa, etc.) shall be symmetrical about the lateral and longitudinal package centerlines. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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