Maxim MAX189AEWE 5v, low-power, 12-bit serial adc Datasheet

19-0196; Rev 0; 10/93
NUAL
KIT MA
ATION
SHEET
A
EVALU
T
A
D
WS
FOLLO
+5V, Low-Power, 12-Bit Serial ADCs
________________________________Features
♦
♦
♦
♦
♦
___________________________Applications
Portable Data Logging
12-Bit Resolution
±1⁄2 LSB Integral Nonlinearity (MAX187A/MAX189A)
Internal Track/Hold, 75kHz Sampling Rate
Single +5V Operation
Low Power: 2µA Shutdown Current
1.5mA Operating Current
♦ Internal 4.096V Buffered Reference (MAX187)
♦ 3-Wire Serial Interface, Compatible with SPI,
QSPI, and Microwire
♦ Small-Footprint 8-Pin DIP and 16-Pin SO
_________________Ordering Information
TEMP. RANGE PIN-PACKAGE ERROR
(LSB)
PART
MAX187ACPA
0°C to +70°C
8 Plastic DIP
±1⁄2
MAX187BCPA
0°C to +70°C
8 Plastic DIP
±1
MAX187CCPA
0°C to +70°C
8 Plastic DIP
±2
MAX187ACWE
0°C to +70°C
16 Wide SO
±1⁄2
MAX187BCWE
0°C to +70°C
16 Wide SO
±1
MAX187CCWE
0°C to +70°C
16 Wide SO
±2
MAX187BC/D
0°C to +70°C
Dice*
±1
Ordering Information continued on last page.
* Dice are specified at TA = +25°C, DC parameters only.
** Contact factory for availability and processing to MIL-STD-883.
Remote Digital Signal Processing
Isolated Data Acquisition
High-Accuracy Process Control
________________Functional Diagram
GND
5
REFDAC
AV = 1.638
REF
AIN
4
2
+2.5V
BANDGAP
REFERENCE
(MAX187 ONLY)
10k
(4.096V)
OUTPUT
SHIFT
REGISTER
6
DOUT
8
SCLK
REF+
12-BIT
SAR
_________________Pin Configurations
TOP VIEW
V DD
1
8
SCLK
AIN
2
7
CS
6
DOUT
5
GND
SHDN 3
MAX187
MAX189
REF 4
T/H
COMPARATOR
MAX187
MAX189
VDD
1
7
BUFFER ENABLE/DISABLE CONTROL
AND
TIMING
NOTE: PIN NUMBERS SHOWN ARE FOR 8-PIN DIPs ONLY.
3
DIP
CS
SHDN
Pin Configurations continued on last page.
™ SPI and QSPI are trademarks of Motorola. Microwire is a trademark of National Semiconductor.
________________________________________________________________ Maxim Integrated Products
Call toll free 1-800-998-8800 for free samples or literature.
1
MAX187/MAX189
__________________General Description
The MAX187/MAX189 serial 12-bit analog-to-digital
converters (ADCs) operate from a single +5V supply
and accept a 0V to 5V analog input. Both parts feature
an 8.5µs successive-approximation ADC, a fast
track/hold (1.5µs), an on-chip clock, and a high-speed
3-wire serial interface.
The MAX187/MAX189 digitize signals at a 75ksps
throughput rate. An external clock accesses data from
the interface, which communicates without external
hardware to most digital signal processors and microcontrollers. The interface is compatible with SPI™,
QSPI™, and Microwire™.
The MAX187 has an on-chip buffered reference, and
the MAX189 requires an external reference. Both the
MAX187 and MAX189 save space with 8-pin DIP and
16-pin SO packages. Power consumption is 7.5mW
and reduces to only 10µW in shutdown.
Excellent AC characteristics and very low power consumption combined with ease of use and small package size make these converters ideal for remote DSP
and sensor applications, or for circuits where power
consumption and space are crucial.
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
ABSOLUTE MAXIMUM RATINGS
VDD to GND .............................................................-0.3V to +6V
AIN to GND................................................-0.3V to (VDD + 0.3V)
REF to GND ...............................................-0.3V to (VDD + 0.3V)
Digital Inputs to GND.................................-0.3V to (VDD + 0.3V)
Digital Outputs to GND..............................-0.3V to (VDD + 0.3V)
SHDN to GND.............................................-0.3V to (VDD + 0.3V)
REF Load Current (MAX187) .........................4.0mA Continuous
REF Short-Circuit Duration (MAX187)................................20sec
DOUT Current ..................................................................±20mA
Continuous Power Dissipation (TA = +70°C)
8-Pin Plastic DIP (derate 9.09mW/°C above +70°C) ..500mW
16-Pin Wide SO (derate 8.70mW/°C above +70°C) ...478mW
8-Pin CERDIP (derate 8.00mW/°C above +70°C) ......440mW
Operating Temperature Ranges:
MAX187_C_ _/MAX189_C_ _.............................0°C to +70°C
MAX187_E_ _/MAX189_E_ _ ..........................-40°C to +85°C
MAX187_MJA/MAX189_MJA .......................-55°C to +125°C
Storage Temperature Range............................-60°C to +150°C
Lead Temperature (soldering, 10sec) ............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +5V ±5%; GND = 0V; unipolar input mode; 75ksps, fCLK = 4.0MHz, external clock (50% duty cycle); MAX187—internal
reference: VREF = 4.096V, 4.7µF capacitor at REF pin, or MAX189—external reference: VREF = 4.096V applied to REF pin, 4.7µF
capacitor at REF pin; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
12
Bits
DC ACCURACY (Note 1)
Resolution
±1⁄2
MAX18_A
Relative Accuracy (Note 2)
Differential Nonlinearity
DNL
MAX18_B
±1
MAX18_C
±2
No missing codes over temperature
±1
±1
MAX18_B/C
Gain Error (Note 3)
Gain Temperature Coefficient
LSB
1
MAX18_A
Offset Error
⁄2
LSB
LSB
±3
MAX187
±3
MAX189A
±1
MAX189B/C
±3
External reference, 4.096V
±0.8
LSB
ppm/°C
DYNAMIC SPECIFICATIONS (10kHz sine wave input, 0V to 4.096Vp-p, 75ksps)
Signal-to-Noise plus
Distortion Ratio
SINAD
Total Harmonic Distortion
(up to the 5th harmonic)
THD
Spurious-Free Dynamic Range
SFDR
Small-Signal Bandwidth
Full-Power Bandwidth
2
70
dB
-80
80
Rolloff -3dB
dB
dB
4.5
MHz
0.8
MHz
_______________________________________________________________________________________
+5V, Low-Power, 12-Bit Serial ADCs
(VDD = +5V ±5%; GND = 0V; unipolar input mode; 75ksps, fCLK = 4.0MHz, external clock (50% duty cycle); MAX187—internal
reference: VREF = 4.096V, 4.7µF capacitor at REF pin, or MAX189—external reference: VREF = 4.096V applied to REF pin, 4.7µF
capacitor at REF pin; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CONVERSION RATE
Conversion Time
tCONV
Track/Hold Acquisition Time
tACQ
Throughput Rate
5.5
µs
75
ksps
1.5
µs
External clock, 4MHz, 13 clocks
Aperture Delay
8.5
tAPR
Aperture Jitter
10
ns
<50
ps
ANALOG INPUT
Input Voltage Range
0 to VREF
Input Capacitance (Note 4)
16
V
pF
INTERNAL REFERENCE (MAX187 only, reference buffer enabled)
TA = +25°C
REF Output Voltage
VREF
TA = TMIN to TMAX
4.076
4.096
4.060
4.132
MAX187_E
4.050
4.140
MAX187_M
4.040
4.150
REF Short-Circuit Current
30
MAX187AC/BC
REF Tempco
Load Regulation (Note 5)
4.116
MAX187_C
±30
mA
±50
MAX187AE/BE
±30
±60
MAX187AM/BM
±30
±80
MAX187C
±30
0mA to 0.6mA output load
V
1
ppm/°C
mV
EXTERNAL REFERENCE AT REF (Buffer disabled, VREF = 4.096V)
Input Voltage Range
2.50
Input Current
200
Input Resistance
12
Shutdown REF Input Current
VDD + 50mV
V
350
µA
20
1.5
kΩ
10
µA
_______________________________________________________________________________________
3
MAX187/MAX189
ELECTRICAL CHARACTERISTICS (continued)
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V ±5%; GND = 0V; unipolar input mode; 75ksps, fCLK = 4.0MHz, external clock (50% duty cycle); MAX187—internal
reference: VREF = 4.096V, 4.7µF capacitor at REF pin, or MAX189—external reference: VREF = 4.096V applied to REF pin, 4.7µF
capacitor at REF pin; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (SCLK, CS, SHDN)
SCLK, CS Input High Voltage
VINH
SCLK, CS Input Low Voltage
VINL
SCLK, CS Input Hysteresis
2.4
VHYST
V
0.8
V
0.15
V
SCLK, CS Input Leakage
IIN
VIN = 0V or VDD
±1
µA
SCLK, CS Input Capacitance
CIN
(Note 4)
15
pF
0.5
V
±4.0
µA
VDD -1.5
V
SHDN Input High Voltage
VINSH
SHDN Input Low Voltage
VINSL
SHDN Input Current
IINS
SHDN Input Mid Voltage
VIM
SHDN Voltage, Floating
VFLT
SHDN Maximum Allowed
Leakage, Mid Input
VDD - 0.5
V
SHDN = VDD or 0V
1.5
SHDN = open
2.75
SHDN = open
-100
V
100
nA
DIGITAL OUTPUT (DOUT)
Output Voltage Low
Output Voltage High
Three-State Leakage Current
Three-State Output
Capacitance
VOL
VOH
IL
COUT
ISINK = 5mA
0.4
ISINK = 16mA
V
0.3
ISOURCE = 1mA
4
V
CS = 5V
CS = 5V (Note 4)
±10
µA
15
pF
5.25
V
POWER REQUIREMENTS
Supply Voltage
VDD
4.75
Operating mode
Supply Current
IDD
MAX187
1.5
2.5
MAX189
1.0
2.0
2
10
µA
±0.06
±0.5
mV
Power-down mode
Power-Supply Rejection
4
PSR
VDD = +5V, ±5%; external reference, 4.096V;
full-scale input (Note 6)
_______________________________________________________________________________________
mA
+5V, Low-Power, 12-Bit Serial ADCs
(VDD = +5.0V ±5%, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
Track/Hold Acquisition Time
tACQ
SCLK Fall to Output Data Valid
CONDITIONS
CS = high (Note 7)
MIN
TYP
MAX
1.5
UNITS
µs
MAX18_ _C/E
20
150
MAX18_ _M
20
200
tDO
CLOAD = 100pF
ns
CS Fall to Output Enable
tDV
CLOAD = 100pF
100
CS Rise to Output Disable
tTR
CLOAD = 100pF
100
ns
5
MHz
ns
SCLK Clock Frequency
fSCLK
SCLK Pulse Width High
tCH
100
ns
SCLK Pulse Width Low
tCL
100
ns
tCSO
50
ns
tCS
500
ns
SCLK Low to CS Fall
Setup Time
CS Pulse Width
Note 1: Tested at VDD = +5V.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: MAX187—internal reference, offset nulled; MAX189–external +4.096V reference, offset nulled. Excludes reference errors.
Note 4: Guaranteed by design. Not subject to production testing.
Note 5: External load should not change during conversion for specified ADC accuracy.
Note 6: DC test, measured at 4.75V and 5.25V only.
Note 7: To guarantee acquisition time, tACQ is the maximum time the device takes to acquire the signal, and is also the minimum
time needed for the signal to be acquired.
_______________________________________________________________________________________
5
MAX187/MAX189
TIMING CHARACTERISTICS
________________________________________________Typical Operating Characteristics
POWER-SUPPLY REJECTION vs.
TEMPERATURE
VREF vs. TEMPERATURE
4.090
0.16
0.14
INTERNAL REFERENCE VOLTAGE (V)
POWER-SUPPLY REJECTION (mV)
4.089
0.12
0.10
0.08
0.06
0.04
0.02
4.088
4.087
4.086
4.085
4.084
4.083
4.082
4.081
4.080
0
-60
-20
20
60
100
-60
140
-20
20
60
100
140
TEMPERATURE (°C)
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT vs.
TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
7
SHUTDOWN SUPPLY CURRENT (µA)
2.2
SUPPLY CURRENT (mA)
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
1.8
MAX187
1.4
MAX189
1.0
0.6
6
5
4
3
2
1
0.2
0
-60
-20
20
60
TEMPERATURE (°C)
6
100
140
-60
-20
20
60
100
TEMPERATURE (°C)
_______________________________________________________________________________________
140
+5V, Low-Power, 12-Bit Serial ADCs
PIN
NAME
DIP
WIDE SO
1
1
VDD
2
3
AIN
3
6
SHDN
FUNCTION
Supply voltage, +5V ±5%
Sampling analog input, 0V to VREF range
Three-level shutdown input. Pulling SHDN low shuts the MAX187/MAX189
down to 10µA (max) supply current. Both MAX187 and MAX189 are fully operational with either SHDN high or floating. For the MAX187, pulling SHDN high
enables the internal reference, and letting SHDN float disables the internal
reference and allows for the use of an external reference.
4
8
REF
Reference voltage—sets analog voltage range and functions as a 4.096V output
for the MAX187 with enabled internal reference. REF also serves as a +2.5V to
VDD input for a precision reference for both MAX187 (disabled internal reference)
and MAX189. Bypass with 4.7µF if internal reference is used, and with 0.1µF if an
external reference is applied.
5
—
GND
Analog and digital ground
—
10
AGND
Analog ground
—
11
DGND
Digital ground
6
12
DOUT
Serial data output. Data changes state at SCLK’s falling edge.
Active-low chip select initiates conversions on the falling edge. When CS is high,
DOUT is high impedance.
15
CS
8
16
SCLK
Serial clock input. Clocks data out with rates up to 5MHz.
—
2,4,5,7,9,13,14
N.C.
Not internally connected. Connect to AGND for best noise performance.
7
_______________Detailed Description
Converter Operation
The MAX187/MAX189 use input track/hold (T/H) and
successive approximation register (SAR) circuitry to
convert an analog input signal to a digital 12-bit output.
No external hold capacitor is needed for the T/H.
Figures 3a and 3b show the MAX187/MAX189 in their
simplest configuration. The MAX187/MAX189 convert
input signals in the 0V to VREF range in 10µs, including
T/H acquisition time. The MAX187’s internal reference
is trimmed to 4.096V, while the MAX189 requires an
external reference. Both devices accept external reference voltages from +2.5V to VDD. The serial interface
requires only three digital lines, SCLK, CS, and DOUT,
and provides easy interface to microprocessors (µPs).
Both converters have two modes: normal and shutdown. Pulling SHDN low shuts the device down and
reduces supply current to below 10µA, while pulling
SHDN high or leaving it floating puts the device into the
operational mode. A conversion is initiated by CS
falling. The conversion result is available at DOUT in
unipolar serial format. A high bit, signaling the end of
conversion (EOC), followed by the data bits (MSB first),
make up the serial data stream.
The MAX187 operates in one of two states: (1) internal
reference and (2) external reference. Select internal
reference operation by forcing SHDN high, and external
reference operation by floating SHDN.
Analog Input
Figure 4 illustrates the sampling architecture of the
ADC’s analog comparator. The full-scale input voltage
depends on the voltage at REF.
ZERO
SCALE
FULL
SCALE
Internal Reference
(MAX187 only)
0V
+4.096V
External Reference
0V
VREF
REFERENCE
For specified accuracy, the external reference voltage
range spans from +2.5V to VDD.
_______________________________________________________________________________________
7
MAX187/MAX189
_______________________________________________________________________Pin Description
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
+5V
3k
DOUT
DOUT
3k
CLOAD = 100pF
CLOAD = 100pF
DGND
DGND
a. High-Z to VOH and VOL to VOH
b. High-Z to VOL and VOH to VOL
Figure 1. Load Circuits for DOUT Enable Time
+5V
3k
DOUT
DOUT
3k
CLOAD = 100pF
DGND
a. VOH to High-Z
CLOAD = 100pF
DGND
b. VOLto High-Z
Figure 2. Load Circuits for DOUT Disable Time
8
_______________________________________________________________________________________
+5V, Low-Power, 12-Bit Serial ADCs
2
ANALOG INPUT
0V TO +5V
SHUTDOWN
INPUT
1
3
4.7µF
0.1µF
0.1µF
SCLK
VDD
AIN MAX187 CS
DOUT
SHDN
8
+5V
7
SERIAL
INTERFACE
6
4
OFF
GND
REF
OFF
REFERENCE
INPUT
5
4.7µF
2
ANALOG INPUT
0V TO +5V
SHUTDOWN
INPUT
ON
1
3
VDD
SCLK
AIN MAX189 CS
SHDN
DOUT
MAX187/MAX189
+5V
4.7µF
8
7
SERIAL
INTERFACE
6
ON
4
REF
GND
5
0.1µF
Figure 3b. MAX189 Operational Diagram
Figure 3a. MAX187 Operational Diagram
12-BIT CAPACITIVE DAC
REF
AIN
HOLD
CPACKAGE
COMPARATOR
TRACK INPUT CHOLD
ZERO
- +
16pF
CSWITCH
5k
RIN
HOLD
TRACK
AT THE SAMPLING INSTANT,
THE INPUT SWITCHES FROM
AIN TO GND.
GND
Figure 4. Equivalent Input Circuit
Track/Hold
In track mode, the analog signal is acquired and stored
in the internal hold capacitor. In hold mode, the T/H
switch opens and maintains a constant input to the
ADC’s SAR section.
During acquisition, the analog input AIN charges
capacitor CHOLD. Bringing CS low ends the acquisition
interval. At this instant, the T/H switches the input side
of CHOLD to GND. The retained charge on CHOLD represents a sample of the input, unbalancing the node
ZERO at the comparator’s input.
In hold mode, the capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to 0V within the limits of a 12-bit resolution. This
action is equivalent to transferring a charge from
CHOLD to the binary-weighted capacitive DAC, which in
turn forms a digital representation of the analog input
signal. At the conversion’s end, the input side of CHOLD
switches back to AIN, and CHOLD charges to the input
signal again.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is
high, the acquisition time lengthens and more time
must be allowed between conversions. Acquisition time
is calculated by:
tACQ = 9 (RS + RIN) 16pF,
where RIN = 5kΩ, RS = the source impedance of the
input signal, and tACQ is never less than 1.5µs. Source
impedances below 5kΩ do not significantly affect the
AC performance of the ADC.
_______________________________________________________________________________________
9
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
Input Bandwidth
The ADCs’ input tracking circuitry has a 4.5MHz smallsignal bandwidth, and an 8V/µs slew rate. It is possible
to digitize high-speed transient events and measure
periodic signals with bandwidths exceeding the ADC's
sampling rate by using undersampling techniques. To
avoid aliasing of unwanted high-frequency signals into
the frequency band of interest, an anti-alias filter is recommended. See the MAX274/MAX275 continuous-time
filters data sheet.
ed by the 75ksps sample rate of the MAX187/MAX189.
Therefore, the maximum sinusoidal input frequency
allowed is 37.5kHz. Higher-frequency signals cause
aliasing problems unless undersampling techniques
are used.
Reference
The MAX187 can be used with an internal or external reference, while the MAX189 requires an external reference.
Input Protection
Internal protection diodes that clamp the analog input
allow the input to swing from GND - 0.3V to VDD + 0.3V
without damage. However, for accurate conversions
near full scale, the input must not exceed VDD by more
than 50mV, or be lower than GND by 50mV.
If the analog input exceeds the supplies by more than
50mV beyond the supplies, limit the input current to
2mA, since larger currents degrade conversion
accuracy.
Internal Reference
The MAX187 has an on-chip reference with a buffered
temperature-compensated bandgap diode, lasertrimmed to +4.096V ±0.5%. Its output is connected to
REF and also drives the internal DAC. The output can
be used as a reference voltage source for other components and can source up to 0.6mA. Decouple REF
with a 4.7µF capacitor. The internal reference is
enabled by pulling the SHDN pin high. Letting SHDN
float disables the internal reference, which allows the
use of an external reference, as described in the
External Reference section.
Driving the Analog Input
The input lines to AIN and GND should be kept as short
as possible to minimize noise pickup. Shield longer
leads. Also see the Input Protection section.
Because the MAX187/MAX189 incorporate a T/H, the
drive requirements of the op amp driving AIN are less
stringent than those for a successive-approximation
ADC without a T/H. The typical input capacitance is
16pF. The amplifier bandwidth should be sufficient to
handle the frequency of the input signal. The MAX400
and OP07 work well at lower frequencies. For higherfrequency operation, the MAX427 and OP27 are practical choices. The allowed input frequency range is limit-
External Reference
The MAX189 operates with an external reference at the
REF pin. To use the MAX187 with an external reference,
disable the internal reference by letting SHDN float. Stay
within the voltage range +2.5V to VDD to achieve specified accuracy. The minimum input impedance is 12kΩ
for DC currents. During conversion, the external reference must be able to deliver up to 350µA DC load current and have an output impedance of 10Ω or less. The
recommended minimum value for the bypass capacitor
is 0.1µF. If the reference has higher output impedance
or is noisy, bypass it close to the REF pin with a 4.7µF
capacitor.
COMPLETE CONVERSION SEQUENCE
CS
tWAKE
SHDN
DOUT
CONVERSION 0
POWERED UP
CONVERSION 1
POWERED DOWN
POWERED UP
Figure 5. MAX187/MAX189 Shutdown Sequence
10
______________________________________________________________________________________
+5V, Low-Power, 12-Bit Serial ADCs
MAX187/MAX189
10000
3.0
2.5
2.0
MAX187
tWAKE (ms)
SUPPLY CURRENT (µA)
1000
100
MAX189*
1.5
1.0
10
0.5
*REF CONNECTED TO VDD
1
0.1
1
10
100
1000
10000 100000
CONVERSIONS PER SECOND
Figure 6. Average Supply Current vs. Conversion Rate
____________________Serial Interface
Initialization After Power-Up and
Starting a Conversion
When power is first applied, it takes the fully discharged 4.7µF reference bypass capacitor up to 20ms
to provide adequate charge for specified accuracy.
With SHDN not pulled low, the MAX187/MAX189 are
now ready to convert.
To start a conversion, pull CS low. At CS’s falling edge,
the T/H enters its hold mode and a conversion is initiated. After an internally timed 8.5µs conversion period,
the end of conversion is signaled by DOUT pulling
high. Data can then be shifted out serially with the
external clock.
Using
SHDN to Reduce Supply Current
Power consumption can be reduced significantly by
shutting down the MAX187/MAX189 between conversions. This is shown in Figure 6, a plot of average supply current vs. conversion rate. Because the MAX189
uses an external reference voltage (assumed to be present continuously), it "wakes up" from shutdown more
quickly, and therefore provides lower average supply
currents. The wakeup-time, tWAKE, is the time from
SHDN deasserted to the time when a conversion may
be initiated. For the MAX187, this time is 2µs. For the
MAX189, this time depends on the time in shutdown
(see Figure 7) because the external 4.7µF reference
bypass capacitor loses charge slowly during shutdown
(see the specifications for shutdown, REF Input Current
= 10µA max).
0
0.0001
0.001
0.01
0.1
1
10
TIME IN SHUTDOWN (sec)
Figure 7. tWAKE vs. Time in Shutdown (MAX187 only)
External Clock
The actual conversion does not require the external
clock. This frees the µP from the burden of running the
SAR conversion clock, and allows the conversion result
to be read back at the µP’s convenience at any clock
rate from 0MHz to 5MHz. The clock duty cycle is unrestricted if each clock phase is at least 100ns. Do not
run the clock while a conversion is in progress.
Timing and Control
Conversion-start and data-read operations are controlled by the CS and SCLK digital inputs. The timing
diagrams of Figures 8 and 9 outline the operation of the
serial interface.
A CS falling edge initiates a conversion sequence: The
T/H stage holds input voltage, the ADC begins to convert, and DOUT changes from high impedance to logic
low. SCLK must be kept inactive during the conversion.
An internal register stores the data when the conversion
is in progress.
End of conversion (EOC) is signaled by DOUT going
high. DOUT’s rising edge can be used as a framing
signal. SCLK shifts the data out of this register any time
after the conversion is complete. DOUT transitions on
SCLK’s falling edge. The next falling clock edge produces the MSB of the conversion at DOUT, followed by
the remaining bits. Since there are 12 data bits and one
leading high bit, at least 13 falling clock edges are
needed to shift out these bits. Extra clock pulses occurring after the conversion result has been clocked out,
and prior to a rising edge of CS, produce trailing 0s at
DOUT and have no effect on converter operation.
______________________________________________________________________________________
11
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
CS
1
4
8
12
SCLK
B11 B10 B9
DOUT
CONVERSION
IN PROGRESS
INTERFACE IDLE
A/D
STATE
EOC
EOC
B8
B7
B6
8.5µs (tCONV)
MINIMUM
CYCLE TIME
B4
B3
B2
B1
B0
TRAILING
ZEROS
CLOCK OUTPUT DATA
CONVERSION
0
TRACK
B5
IDLE
TRACK
0µs
CONV. 1
12 × 0.250µs = 3.25µs
0.5µs
(tCS)
0µs
TOTAL = 12.25µs
Figure 8. MAX187/MAX189 Interface Timing Sequence
tCS
CS
…
tCS0
tCH
…
SCLK
tDO
tDV
tCL
tTR
tCONV
…
DOUT
B2
B1
B0
tAPR
INTERNAL
T/H
(TRACK)
(HOLD)
…
(TRACK)
Figure 9. MAX187/MAX189 Detailed Serial-Interface Timing
12
______________________________________________________________________________________
+5V, Low-Power, 12-Bit Serial ADCs
MAX187/MAX189
20
OUTPUT CODE
11…111
fS = 75ksps
fT = 10kHz
TA = +25°C
0
FULL-SCALE
TRANSITION
-20
11…110
FS = +4.096V
1LSB = FS
4096
AMPLITUDE (dB)
11…101
-40
-60
-80
00…011
-100
00…010
00…001
-120
00…000
0
1
2
FS
3
INPUT VOLTAGE (LSBs)
FS - 3/2LSB
-140
0
18.75
37.5
FREQUENCY (kHz)
Figure 10. MAX187/MAX189 Unipolar Transfer Function,
4.096V = Full Scale
Figure 11. MAX187/MAX189 FFT plot
Minimum cycle time is accomplished by using DOUT’s
rising edge as the EOC signal. Clock out the data with
13 clock cycles at full speed. Raise CS after the conversion’s LSB has been read. After the specified minimum
time, tACQ, CS can be pulled low again to initiate the
next conversion.
input frequency. ADCs have traditionally been evaluated by specifications such as Zero and Full-Scale Error,
Integral Nonlinearity (INL), and Differential Nonlinearity
(DNL). Such parameters are widely accepted for specifying performance with DC and slowly varying signals,
but are less useful in signal-processing applications,
where the ADC’s impact on the system transfer function
is the main concern. The significance of various DC
errors does not translate well to the dynamic case, so
different tests are required.
Output Coding and Transfer Function
The data output from the MAX187/MAX189 is binary,
and Figure 10 depicts the nominal transfer function.
Code transitions occur halfway between successive
integer LSB values. If V REF = +4.096V, then
1 LSB = 1.00mV or 4.096V/4096.
_____________Dynamic Performance
High-speed sampling capability and a 75ksps throughput make the MAX187/MAX189 ideal for wideband signal processing. To support these and other related
applications, Fast Fourier Transform (FFT) test techniques are used to guarantee the ADC’s dynamic frequency response, distortion, and noise at the rated
throughput. Specifically, this involves applying a lowdistortion sine wave to the ADC input and recording the
digital conversion results for a specified time. The data
is then analyzed using an FFT algorithm that determines its spectral content. Conversion errors are then
seen as spectral elements outside of the fundamental
Signal-to-Noise Ratio and
Effective Number of Bits
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS amplitude of all other ADC output signals. The
input bandwidth is limited to frequencies above DC and
below one-half the ADC sample (conversion) rate.
The theoretical minimum ADC noise is caused by quantization error and is a direct result of the ADC’s resolution: SINAD = (6.02N + 1.76)dB, where N is the number
of bits of resolution. An ideal 12-bit ADC can, therefore,
do no better than 74dB. An FFT plot of the output
shows the output level in various spectral bands. Figure
11 shows the result of sampling a pure 10kHz sine
wave at a 75ksps rate with the MAX187/MAX189.
______________________________________________________________________________________
13
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
12.2
12.0
I/O
11.8
11.6
SCK
11.4
EFFECTIVE BITS
CS
SCLK
MISO
11.2
DOUT
+5V
11.0
MAX187
MAX189
10.8
10.6
SS
10.4
(UNDERSAMPLED)
10.2
a. SPI
1
10
100
1000
INPUT FREQUENCY (kHz)
CS
CS
SCK
Figure 12. Effective Bits vs. Input Frequency
SCLK
MISO
DOUT
+5V
The effective resolution (effective number of bits) the
ADC provides can be determined by transposing the
above equation and substituting in the measured
SINAD: N = (SINAD - 1.76)/6.02. Figure 12 shows the
effective number of bits as a function of the input frequency for the MAX187/MAX189.
MAX187
MAX189
SS
b. QSPI
Total Harmonic Distortion
If a pure sine wave is sampled by an ADC at greater
than the Nyquist frequency, the nonlinearities in the
ADC’s transfer function create harmonics of the input
frequency present in the sampled output data.
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all the harmonics (in the frequency band above
DC and below one-half the sample rate, but not including the DC component) to the RMS amplitude of the
fundamental frequency. This is expressed as follows:
THD = 20log
√ V22 + V32 + V42 + … VN2
V1
where V1 is the fundamental RMS amplitude, and V2
through VN are the amplitudes of the 2nd through Nth
harmonics. The THD specification in the Electrical
Characteristics includes the 2nd through 5th
harmonics.
14
I/O
CS
SK
SCLK
SI
DOUT
MAX187
MAX189
c. MICROWIRE
Figure 13. Common Serial-Interface Connections to the
MAX187/MAX189
______________________________________________________________________________________
+5V, Low-Power, 12-Bit Serial ADCs
SCLK’s falling edge and is available in MSB-first format. Observe the SCLK to DOUT valid timing characteristic. Data can be clocked into the µP on SCLK’s
rising edge.
4. Pull CS high at or after the 13th falling clock edge. If
CS remains low, trailing zeros are clocked out after
the LSB.
5. With CS = high, wait the minimum specified time, tCS,
before launching a new conversion by pulling CS
low. If a conversion is aborted by pulling CS high
before the conversions end, wait for the minimum
acquisition time, t ACQ , before starting a new
conversion.
Connection to Standard Interfaces
The MAX187/MAX189 serial interface is fully compatible
with SPI, QSPI, and Microwire standard serial
interfaces.
If a serial interface is available, set the CPU’s serial
interface in master mode so the CPU generates the serial clock. Choose a clock frequency up to 2.5MHz.
1. Use a general-purpose I/O line on the CPU to pull CS
low. Keep SCLK low.
2. Wait the for the maximum conversion time specified
before activating SCLK. Alternatively, look for a
DOUT rising edge to determine the end of
conversion.
3. Activate SCLK for a minimum of 13 clock cycles. The
first falling clock edge will produce the MSB of the
DOUT conversion. DOUT output data transitions on
Data can be output in 1-byte chunks or continuously, as
shown in Figure 8. The bytes will contain the result of
the conversion padded with one leading 1, and trailing
0s if SCLK is still active with CS kept low.
1ST BYTE READ
2ND BYTE READ
SCLK
CS
HI-Z
DOUT
tCONV
HI-Z
MSB
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
EOC
Figure 14. SPI/Microwire Serial Interface Timing (CPOL = CPHA = 0)
SCLK
CS
HI-Z
DOUT
tCONV
HI-Z
MSB
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
EOC
Figure 15. QSPI Serial Interface Timing (CPOL = CPHA = 0)
______________________________________________________________________________________
15
MAX187/MAX189
____________Applications Information
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
SPI and Microwire
When using SPI or QSPI, set CPOL = 0 and CPHA = 0.
Conversion begins with a CS falling edge. DOUT goes
low, indicating a conversion in progress. Wait until
DOUT goes high or the maximum specified 8.5µs conversion time. Two consecutive 1-byte reads are
required to get the full 12 bits from the ADC. DOUT output data transitions on SCLK’s falling edge and is
clocked into the µP on SCLK’s rising edge.
The first byte contains a leading 1 and 7 bits of conversion result. The second byte contains the remaining 5
bits and 3 trailing 0s. See Figure 13 for connections
and Figure 14 for timing.
QSPI
Set CPOL = CPHA = 0. Unlike SPI, which requires two
1-byte reads to acquire the 12 bits of data from the
ADC, QSPI allows the minimum number of clock cycles
necessary to clock in the data. The MAX187/MAX189
require 13 clock cycles from the µP to clock out the
12 bits of data with no trailing 0s (Figure 15). The maximum clock frequency to ensure compatibility with QSPI
is 2.77MHz.
Opto-Isolated Interface,
Serial-to-Parallel Conversion
Many industrial applications require electrical isolation
to separate the control electronics from hazardous
electrical conditions, provide noise immunity, or prevent excessive current flow where ground disparities
exist between the ADC and the rest of the system.
Isolation amplifiers typically used to accomplish these
tasks are expensive. In cases where the signal is eventually converted to a digital form, it is cost effective to
isolate the input using opto-couplers in a serial link.
The MAX187 is ideal in this application because it
includes both T/H amplifier and voltage reference,
operates from a single supply, and consumes very little
power (Figure 16).
CS/START
+5V ON THIS SIDE OF
BARRIER MUST BE ISOLATED POWER
6N136
+5V
3k
10µF
8
1
7
2
6
3
5
4
MAX187
0.1µF
1
2
4
ANALOG
INPUT
4.7µF 5
VDD
AIN
REF
GND
200Ω
CS
SCLK
DOUT
8
1
7
2
8
6
3
6
5
4
3
7
3k
200Ω
74HC04
SER
13
470Ω
8
2
7
3
6
4
5
D11 (MSB)
D10
D9
D8
+5V
8
9
QH′
1
7
6
5
4
3
2
1
15
16
0.1µF
6N136
SIGNAL
GROUND
QH
QG
74HC595 QF
11
QE
SCK
QD
12
QC
RCK
QB
10
QA
SCLR
14
74HC04
6N136
SHDN
SCLK/INPUT CLOCK
+5V
QH
QG
74HC595 QF
11
QE
SCK
QD
12
QC
RCK
QB
10
QA
+5V
SCLR
14 SER
8.2k
13
7
6
5
4
3
2
1
15
16
D7
D6
D5
D4
D3
D2
D1
D0(LSB)
+5V
8
0.1µF
Figure 16. 12-Bit Isolated ADC
16
______________________________________________________________________________________
+5V, Low-Power, 12-Bit Serial ADCs
+5V
Layout, Grounding, Bypassing
VDD
For best performance, use printed circuit boards. Wirewrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.
Figure 17 shows the recommended system ground
connections. A single-point analog ground (“star”
ground point) should be established at GND, separate
from the logic ground. All other analog grounds should
be connected to this ground. The 16-pin versions also
have a dedicated DGND pin available. Connect DGND
to this star ground point for further noise reduction. No
other digital system ground should be connected to
this single-point analog ground. The ground return to
the power supply for this ground should be low impedance and as short as possible for noise-free operation.
High-frequency noise in the V DD power supply may
affect the ADC’s high-speed comparator. Bypass this
supply to the single-point analog ground with 0.01µF
and 4.7µF bypass capacitors. Minimize capacitor lead
lengths for best supply-noise rejection. If the +5V
power supply is very noisy, a 10Ω resistor can be connected as a lowpass filter to attenuate supply noise
(Figure 17).
MAX187/MAX189
The ADC results are transmitted across a 1500V isolation barrier provided by three 6N136 opto-isolators.
Isolated power must be supplied to the converter and
the isolated side of the opto-couplers. 74HC595 threestate shift registers are used to construct a 12-bit parallel data output. The timing sequence is identical to the
timing shown in Figure 8. Conversion speed is limited
by the delay through the opto-isolators. With a 140kHz
clock, conversion time is 100µs.
The universal 12-bit parallel data output can also be
used without the isolation stage when a parallel interface is required. Clock frequencies up to 2.9MHz are
possible without violating the 20ns shift-register setup
time. Delay or invert the clock signal to the shift registers beyond 2.9MHz.
SUPPLIES
GND
R* = 10Ω
4.7µF
0.01µF
AGND
DGND
MAX187
MAX189
+5V
DGND
DIGITAL
CIRCUITRY
*OPTIONAL
Figure 17. Power-Supply Grounding Condition
______________________________________________________________________________________
17
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
__Ordering Information (continued)
PART
____Pin Configurations (continued)
TEMP. RANGE PIN-PACKAGE ERROR
(LSB)
MAX187AEPA
-40°C to +85°C
8 Plastic DIP
±1⁄2
MAX187BEPA
-40°C to +85°C
8 Plastic DIP
±1
V DD 1
16 SCLK
MAX187CEPA
-40°C to +85°C
8 Plastic DIP
±2
N.C. 2
-40°C to +85°C
16 Wide SO
±1⁄2
15 CS
MAX187AEWE
AIN 3
MAX187BEWE
-40°C to +85°C
16 Wide SO
±1
MAX187CEWE -40°C to +85°C
16 Wide SO
±2
MAX187AMJA
-55°C to +125°C
8 CERDIP**
±1⁄2
MAX187BMJA
-55°C to +125°C
8 CERDIP**
±1
MAX189ACPA
0°C to +70°C
8 Plastic DIP
±1⁄2
MAX189BCPA
0°C to +70°C
8 Plastic DIP
±1
MAX189CCPA
0°C to +70°C
8 Plastic DIP
±2
MAX189ACWE
0°C to +70°C
16 Wide SO
±1⁄2
MAX189BCWE
0°C to +70°C
16 Wide SO
±1
MAX189CCWE
0°C to +70°C
16 Wide SO
±2
MAX189BC/D
0°C to +70°C
Dice*
±1
MAX189AEPA
-40°C to +85°C
8 Plastic DIP
±1⁄2
MAX189BEPA
-40°C to +85°C
8 Plastic DIP
±1
MAX189CEPA
-40°C to +85°C
8 Plastic DIP
±2
MAX189AEWE
-40°C to +85°C
16 Wide SO
±1⁄2
MAX189BEWE
-40°C to +85°C
16 Wide SO
±1
MAX189CEWE -40°C to +85°C
16 Wide SO
±2
MAX189AMJA
-55°C to +125°C
8 CERDIP**
±1⁄2
MAX189BMJA
-55°C to +125°C
8 CERDIP**
±1
N.C. 4
N.C. 5
14 N.C.
MAX187
MAX189
13 N.C.
12 DOUT
SHDN 6
11 DGND
N.C. 7
10 AGND
REF 8
9
Wide SO
* Dice are specified at TA = +25°C, DC parameters only.
**Contact factory for availability and processing to MIL-STD-883.
18
______________________________________________________________________________________
N.C.
+5V, Low-Power, 12-Bit Serial ADCs
MAX187/MAX189
___________________Chip Topography
MAX187/MAX189
V DD
SCLK
CS
AIN
0.151"
(3.84mm)
DOUT
DGND
SHDN
REF
0.117"
(2.97mm)
AGND
AGND
TRANSISTOR COUNT: 2278;
SUBSTRATE CONNECTED TO VDD.
______________________________________________________________________________________
19
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
________________________________________________________________Package Information
DIM
E
A2
A3
D
A
E1
0°-15°
A1
C
e
L
eA
B1
eB
B
D1
P PACKAGE
PLASTIC
DUAL-IN-LINE
A
A1
A2
A3
B
B1
C
D1
E
E1
e
eA
eB
L
DIM PINS
D
D
D
DIM
D
0°- 8°
A
e
B
0.101mm
0.005in.
A1
C
L
INCHES
MAX
MIN
0.200
–
–
0.015
0.175
0.125
0.080
0.055
0.020
0.016
0.065
0.045
0.012
0.008
0.090
0.050
0.625
0.600
0.575
0.525
–
0.100
–
0.600
0.700
–
0.150
0.120
A
A1
B
C
E
e
H
L
24
28
40
INCHES
MAX
MIN
0.104
0.093
0.012
0.004
0.019
0.014
0.013
0.009
0.299
0.291
0.050
0.419
0.394
0.050
0.016
DIM PINS
E
W PACKAGE
SMALL
OUTLINE
H
D
D
D
D
D
INCHES
MIN
MAX
1.230 1.270
1.430 1.470
2.025 2.075
16
18
20
24
28
INCHES
MIN MAX
0.398 0.413
0.447 0.463
0.496 0.512
0.598 0.614
0.697 0.713
MILLIMETERS
MIN
MAX
–
5.08
0.38
–
3.18
4.45
1.40
2.03
0.41
0.51
1.14
1.65
0.20
0.30
1.27
2.29
15.24
15.88
13.34
14.61
2.54
–
15.24
–
–
17.78
3.05
3.81
MILLIMETERS
MIN
MAX
31.24 32.26
36.32 37.34
51.44 52.71
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.30
0.35
0.49
0.23
0.32
7.40
7.60
1.27
10.00
10.65
0.40
1.27
MILLIMETERS
MIN
MAX
10.10 10.50
11.35 11.75
12.60 13.00
15.20 15.60
17.70 18.10
21-0042A
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1993 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.