HC55180, HC55181, HC55182, HC55183, HC55184 Data Sheet October 1998 File Number 4519.4 Extended Reach Ringing SLIC Family Features The RSLIC18 family of ringing subscriber line interface circuits (RSLIC) supports analog Plain Old Telephone Service (POTS) in short and medium loop length, wireless and wireline applications. Ideally suited for remote subscriber units, this family of products offers flexibility to designers with high ringing voltage and low power consumption system requirements. • Battery Operation to 100V The RSLIC18 family operates to 100V which translates directly to the amount of ringing voltage supplied to the end subscriber. With the high operating voltage, subscriber loop lengths can be extended to 500Ω (i.e., 5,000 feet) and beyond. • Thermal Shutdown with Alarm Indicator Other key features across the product family include: low power consumption, ringing using sinusoidal or trapezoidal waveforms, robust auto-detection mechanisms for when subscribers go on or off hook, and minimal external discrete application components. Integrated test access features are also offered on selected products to support loopback testing as well as line measurement tests. There are five product offerings in the RSLIC18 family: HC55180, HC55181, HC55182, HC55183 and HC55184. The architecture for this family is based on a voltage feed amplifier design using low fixed loop gains to achieve high analog performance with low susceptibility to system induced noise. Block Diagram POL ILIM CDC DC CONTROL VBL VBH BATTERY SWITCH RINGING PORT VRS 4-WIRE PORT VRX VTX -IN VFB • Low Standby Power Consumption of 50mW • Peak Ringing Amplitude 95V, 5 REN • Sinusoidal or Trapezoidal Ringing Capability • Integrated CODEC Ringing Interface • Integrated MTU DC Characteristics • Low External Component Count • Pulse Metering and On Hook Transmission • Tip Open Ground Start Operation • 28 Lead Surface Mount Packaging • Dielectric Isolated (DI) High Voltage Design • HC55180 - Silent Polarity Reversal - 53dB Longitudinal Balance - Loopback Test Capability • HC55181 - Integrated Battery Switch - Silent Polarity Reversal - 58/53dB Longitudinal Balance - Loopback and Test Access Capability • HC55182 - Integrated Battery Switch - 58/53dB Longitudinal Balance - Loopback and Test Access Capability • HC55183 - Integrated Battery Switch - 45dB Longitudinal Balance • HC55184 - Integrated Battery Switch - Silent Polarity Reversal - 45dB Longitudinal Balance Applications • Wireless Local Loop (WLL) TIP RING 2-WIRE PORT TRANSMIT SENSING • Digital Added Main Line (DAML)/Pairgain • Integrated Services Digital Network (ISDN) • Small Office Home Office (SOHO) PBX • Cable/Computer Telephony SW+ SW- TEST ACCESS DETECTOR LOGIC RTD RD E0 DET ALM 28 CONTROL LOGIC BSEL SWC F2 F1 F0 Related Literature • AN9814, User’s Guide for Development Board • AN9824, Modeling of the AC Loop • AN TBD, Interfacing to DSP CODECs CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. RSLIC18™ is a trademark of Intersil Corporation. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 HC55180, HC55181, HC55182, HC55183, HC55184 Ordering Information (PLCC Package Only) PART NUMBER 100V BAT SW 85V • HC55180CIM • HC55180DIM • HC55181AIM • HC55181BIM • HC55181CIM • HC55181DIM • HC55182AIM • HC55182BIM • HC55182CIM LB = 53dB • • • • FULL TEST TEMP. RANGE oC PACKAGE PACKAGE NO. • -40 to 85 28 Ld PLCC N28.45 • -40 to 85 28 Ld PLCC N28.45 LB = 58dB • • • • -40 to 85 28 Ld PLCC N28.45 • • • • -40 to 85 28 Ld PLCC N28.45 • • • • -40 to 85 28 Ld PLCC N28.45 • • • • -40 to 85 28 Ld PLCC N28.45 • • • -40 to 85 28 Ld PLCC N28.45 • • • -40 to 85 28 Ld PLCC N28.45 • • • -40 to 85 28 Ld PLCC N28.45 • • -40 to 85 28 Ld PLCC N28.45 45dB 0 to 70 28 Ld PLCC N28.45 45dB 0 to 70 28 Ld PLCC N28.45 HC55182DIM • • HC55183ECM 75V • HC55184ECM 75V • HC5518XEVAL1 LOOP BACK ONLY POL REV • Evaluation board platform, including CODEC. Device Operating Modes OPERATING MODE F2 F1 F0 HC55180 HC55181 HC55182 HC55183 HC55184 Low Power Standby 0 0 0 SHD GKD MTU compliant standby mode with active loop detector. • • • • • Forward Active 0 0 1 SHD GKD Forward battery loop feed. • • • • • Unused 0 1 0 n/a n/a This is a reserved internal test mode. Reverse Active 0 1 1 SHD GKD Reverse battery loop feed. • • Ringing 1 0 0 RTD RTD Balanced ringing mode supporting both sinusoidal, trapezoidal and ringing waveforms with DC offset. • • • Forward Loop Back 1 0 1 SHD GKD Internal device test mode. • • • Tip Open 1 1 0 SHD GKD Tip amplifier disabled and ring amplifier enabled. Intended for PBX type applications. • • • Power Denial 1 1 1 n/a n/a Device shutdown. • • • 29 E0 = 1 E0 = 0 DESCRIPTION • • • • • HC55180, HC55181, HC55182, HC55183, HC55184 Pinouts TIP 2 1 ILIM BGND 3 RD VBL 4 RING VBH HC55180 (PLCC) TOP VIEW 28 27 26 NC 5 25 RTD NC 6 24 CDC NC 7 23 VCC F2 8 22 -IN F1 9 21 VFB F0 10 20 VTX E0 11 18 VRS AGND 17 NC ALM 16 POL 14 15 NC 13 DET 19 VRX 12 3 2 1 ILIM TIP 4 RD BGND 28 27 26 RING VBL 1 VBH TIP 2 ILIM BGND 3 RD VBL 4 HC55182 (PLCC) TOP VIEW RING VBH HC55181 (PLCC) TOP VIEW 28 27 26 5 25 RTD SW+ 5 25 RTD 6 24 CDC SW- 6 24 CDC SWC 7 23 VCC SWC 7 23 VCC F2 8 22 -IN F2 8 22 -IN 9 21 VFB F1 9 21 VFB SW+ SW- F1 13 18 3 2 1 ILIM TIP 4 RD BGND 28 27 26 RING VBL 1 VBH TIP 2 ILIM BGND 3 17 16 HC55184 (PLCC) TOP VIEW RD VBL 4 RING VBH HC55183 (PLCC) TOP VIEW 14 15 VRS VRS 12 NC 18 NC 17 BSEL 16 AGND 14 15 DET 13 ALM 12 NC 20 VTX 19 VRX POL 10 11 BSEL F0 E0 AGND 20 VTX 19 VRX ALM 10 11 DET F0 E0 28 27 26 NC 5 25 RTD NC 5 25 RTD NC 23 VCC F2 8 22 -IN F2 8 22 -IN F1 9 21 VFB F1 9 21 VFB F0 10 20 VTX F0 10 20 VTX E0 11 19 VRX E0 11 30 13 14 15 16 17 18 VRS 19 VRX 12 POL 18 NC 17 BSEL 16 AGND 14 15 DET 13 ALM 12 VRS 7 NC 7 NC 24 CDC BSEL 6 NC AGND NC 23 VCC ALM 24 CDC DET 6 NC HC55180, HC55181, HC55182, HC55183, HC55184 Absolute Maximum Ratings TA = 25oC Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (PLCC - Lead Tips Only) Maximum Supply Voltages VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V VCC - VBAT (180, 181, 182) . . . . . . . . . . . . . . . . . . . . . . . . . 110V VCC - VBAT (183, 184) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85V Uncommitted Switch Voltage . . . . . . . . . . . . . . . . . . . . . . . -110V ESD (Human Body Model). . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V Operating Conditions Die Characteristics Temperature Range Industrial (I suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC Commercial (C suffix). . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC Positive Power Supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . +5V ±5% Negative Power Supply (VBH, VBL) (180, 181, 182) . -16V to -100V Negative Power Supply (VBH, VBL) (183, 184) . . . . . . -24V to -75V Uncommitted Switch (loop back or relay driver). . . . . . +5V to -100V Substrate Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VBAT Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Unless Otherwise Specified, TA = 0oC to 70oC for the HC55183, 184 only, all others -40oC to 85oC, VBL = -24V, VBH = -100V, -85V or -75V, VCC = +5V, AGND = BGND = 0V, loop current limit = 25mA. All AC Parameters are specified at 600Ω 2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz. Protection resistors = 0Ω. These parameters apply generically to each product offering. Electrical Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 480 - - kΩ 78 80 82 V/V RINGING PARAMETERS (Note 2) VRS Input Impedance (Note 3) Differential Ringing Gain VRS to 2-wire, RLOAD = ∞ (Note 4) 4-Wire to 2-Wire Ringing Off Isolation Active mode, referenced to VRS input. - 60 - dB 2-Wire to 4-Wire Transmit Isolation Ringing mode referenced to the differential ringing amplitude. - 60 - dB 160 - - kΩ - - 1 Ω THD = 1% 3.1 3.5 - VPK 2-Wire Port Overload Level THD = 1% 3.1 3.5 - VPK 2-Wire Return Loss 300Hz ≤ f < 1kHz 30 45 - dB 1kHz ≤ f ≤ 3.4kHz 35 45 - dB Test for False Detect 20 - - mARMS Test for False Detect, Low Power Standby 10 - - mARMS 4-Wire to 2-Wire Insertion Loss -0.20 0.0 +0.30 dB 2-Wire to 4-Wire Insertion Loss -6.22 -6.02 -5.82 dB 4-Wire to 4-Wire Insertion Loss -6.22 -6.02 -5.82 dB C-Message - 16 19 dBrnC Psophometric - -73.5 -71 dBmp C-Message - 10 13 dBrnC Psophometric - -79.5 -77 dBmp AC TRANSMISSION PARAMETERS (Notes 5, 6) Receive Input Impedance (Note 3) Transmit Output Impedance (Note 3) 4-Wire Port Overload Level Longitudinal Current Capability (Per Wire) (Note 3) Idle Channel Noise 2-Wire Idle Channel Noise 4-Wire DC PARAMETERS (Note 6) Loop Current Limit Programming Range (Note 5) Max Low Battery = -52V 15 - 45 mA Loop Current During Low Power Standby Forward polarity only. 18 - 26 mA 31 HC55180, HC55181, HC55182, HC55183, HC55184 Unless Otherwise Specified, TA = 0oC to 70oC for the HC55183, 184 only, all others -40oC to 85oC, VBL = -24V, VBH = -100V, -85V or -75V, VCC = +5V, AGND = BGND = 0V, loop current limit = 25mA. All AC Parameters are specified at 600Ω 2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz. Protection resistors = 0Ω. These parameters apply generically to each product offering. (Continued) Electrical Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 5 - 15 mA LOOP DETECTORS AND SUPERVISORY FUNCTIONS Switch Hook Programming Range Switch Hook Programming Accuracy Assumes 1% external programming resistor Dial Pulse Distortion - 2 10 % - - 1 % 2.3 2.6 2.9 V - - 10 % 10 12 13.5 mA - 175 - oC Input Low Voltage - - 0.8 V Input High Voltage 2.0 - - V Ring Trip Comparator Threshold Ring Trip Programming Current Accuracy Ground Key Threshold Thermal Alarm Output IC junction temperature LOGIC INPUTS (F0, F1, F2, E0, SWC) Input Low Current VIL = 0.4V -20 - - µA Input High Current VIH = 2.4V - - 5 µA Output Low Voltage IOL = 5mA - - 0.4 V Output High Voltage IOH = 100 µA 2.4 - - V f = 300Hz - 40 - dB f = 1kHz - 35 - dB f = 3.4kHz - 28 - dB f = 300Hz - 45 - dB f = 1kHz - 43 - dB f = 3.4kHz - 33 - dB VBL to 2-Wire 300Hz ≤ f ≤ 3.4kHz - 30 - dB VBL to 4-Wire 300Hz ≤ f ≤ 3.4kHz - 35 - dB VBH to 2-Wire 300Hz ≤ f ≤ 3.4kHz - 33 - dB VBH to 4-Wire 300Hz ≤ f ≤ 1kHz - 40 - dB 1kHz < f ≤ 3.4kHz - 45 - dB LOGIC OUTPUTS (DET, ALM) POWER SUPPLY REJECTION RATIO VCC to 2-Wire VCC to 4-Wire NOTES: 2. These parameters are specified at high battery operation. For the HC55180 the external supply is set to high battery voltage, for the HC55181, HC55182, HC55183 and HC55184, BSEL = 1. 3. These parameters are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics. 4. Differential Ringing Gain is measured with VRS = 0.795 VRMS for -100V devices, VRS = 0.663 VRMS for -85V devices and VRS = 0.575 VRMS for -75V devices. 5. These parameters are specified at low battery operation. For the HC55180, the external supply is set to low battery voltage, for the HC55181, HC55182, HC55183 and HC55184, BSEL = 0. 6. Forward Active and Reverse Active performance is guaranteed for the HC55180, HC55181 and HC55184 devices only. The HC55182 and HC55183 are specified for Forward Active operation only. 32 Electrical Specifications Unless Otherwise Specified, TA = 0oC to 70oC for the HC55183, 184 only, all others -40oC to 85oC, VBL = -24V, VCC = +5V, AGND = BGND = 0V, loop current limit = 25mA. All AC Parameters are specified at 600W 2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz. Protection resistors = 0W. HC55180 (Note 7) PARAMETER TEST CONDITIONS HC55181, HC55182 MIN TYP MAX TEST CONDITIONS HC55183, HC55184 MIN TYP MAX TEST CONDITIONS MIN TYP MAX UNITS 70 - - VPEAK - - - VPEAK 70 - - VPEAK - - - VPEAK RINGING PARAMETERS (Note 2) THD ≤ 0.5% VB = -85V - 80 - THD ≤ 0.5% VBH = -85V 80 - - THD ≤ 0.5% VBH = -75V THD ≤ 0.5% VB = -100V - 95 - THD ≤ 0.5% VBH = -100V 95 - - (Note 9) Ringing Voltage Load = 1.3K (Notes 8, 10) THD ≤ 2.5% VB = -85V - 80 - THD ≤ 2.5% VBH = -85V 80 - - THD ≤ 3.0% VBH = -75V THD ≤ 2.0% VB = -100V - 95 - THD ≤ 2.0% VBH = -100V 95 - - (Note 9) Tip Centering Voltage Ring Centering Voltage VB = -85V, RL = ∞ - 2.5 - VBH = -85V, RL = ∞ - - 2.5 VBH = -75V, RL = ∞ - - 3 V VB = -100V, RL = ∞ - 2.0 - VBH = -100V, RL = ∞ - - 2.0 (Note 9) - - - V VB = -85V, RL = ∞ - 2.5 - VBH = -85V, RL = ∞ - - 2.5 VBH = -75V, RL = ∞ - - 3 V VB = -100V, RL = ∞ - 2.0 - VBH = -100V, RL = ∞ - - 2.0 (Note 9) - - - V AC TRANSMISSION PARAMETERS (Notes 5, 6) 2-Wire Longitudinal Balance (Notes 12, 13) 4-Wire Longitudinal Balance (Note 11) - - - Grade A, B 58 62 - Grade E 45 53 - dB Grade C, D - 59 - Grade C, D 53 59 - (Note 11) - - - dB (Note 11) - - - Grade A, B - 67 - Grade E - 58 - dB Grade C, D - 64 - Grade C, D - 64 - (Note 11) - - - dB - 0.025 - +3 to -40dBm, 1kHz - 0.025 - +3 to -40dBm, 1kHz - 0.025 - dB - 0.050 - -40 to -50dBm, 1kHz - 0.050 - -40 to -50dBm, 1kHz - 0.050 - dB - 0.100 - -50 to -55dBm, 1kHz - 0.100 - -50 to -55dBm, 1kHz - 0.100 - dB - 7 - IL = 25mA - - IL = 25mA - - 10 % 2-Wire to 4-Wire Level Linearity +3 to -40dBm, 1kHz 4-Wire to 2-Wire Level -40 to -50dBm, 1kHz Linearity -50 to -55dBm, 1kHz Referenced to -10dBm DC PARAMETERS Loop Current Accuracy (Notes 5, 6) IL = 25mA Open Circuit Voltage (|Tip - Ring|, Note 6) VB = -16V - 7.5 - VBL = -16V 6.5 7.5 9.5 VBL = -16V - 7.5 - V VB = -24V 14 15.5 17 VBL = -24V 14 15.5 17 VBL = -24V 14 15.5 17 V VB = -85V - 50 - BSEL = 1, VBH = -85V - 50 - BSEL = 1, VBH = -75V - 50 - V BSEL = 1, VBH = -100V (Note 9) Low Power Standby Open Circuit Voltage (Tip - Ring, Note 2) 7 VB = -100V - 50 - - 50 - - - - V VB = -48V 43 45 47 VBH = -48V 43 45 47 VBH = -48V 43 45 47 V VB = -85V 46 49 52 VBH = -85V 46 49 52 VBH = -75V 46 49 52 V VB = -100V 46 49 52 VBH = -100V 46 49 52 (Note 9) - - - V - - - IOL = 45mA - 0.30 0.60 (Note 14) - - - V - - 52 - - 52 (Note 15) - - 52 V TEST ACCESS FUNCTIONS Switch On Voltage Loopback Max Battery (Note 14) HC55180, HC55181, HC55182, HC55183, HC55184 33 Ringing Voltage Open Circuit (Note 8) Electrical Specifications Unless Otherwise Specified, TA = 0oC to 70oC for the HC55183, 184 only, all others -40oC to 85oC, VBL = -24V, VCC = +5V, AGND = BGND = 0V, loop current limit = 25mA. All AC Parameters are specified at 600W 2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz. Protection resistors = 0W. (Continued) HC55180 (Note 7) PARAMETER TEST CONDITIONS MIN HC55181, HC55182 TYP MAX TEST CONDITIONS MIN HC55183, HC55184 TYP MAX TEST CONDITIONS MIN TYP MAX UNITS SUPPLY CURRENTS (Supply currents not listed are considered negligible and do not contribute significantly to total power dissipation. All measurements made under open circuit load conditions.) ICC Forward or Reverse (Note 5) ICC Forward (Note 2) ICC Ringing (Note 2) Forward Loopback (Note 5) IB , VB = -100V, -85V IB , VB = -24V 2.0 3.7 - 0.375 2.5 4.0 5.0 ICC 0.600 IBH , VBH = -100V, -85V 5.0 ICC 2.0 3.7 5.0 ICC - 0.375 2.5 4.0 0.600 IBH, VBH = -75V 5.0 ICC - 3.7 6.0 mA - 0.375 - mA 2.0 4.0 6.0 mA - 1.0 2.5 IBL - 1.0 2.5 IBL - 1.0 2.5 mA 3.5 5.5 7.0 ICC 3.5 5.5 7.0 ICC 2.0 5.5 8.0 mA mA (Note 7) - - - IBL - 1.3 2.0 IBL - 1.3 2.5 IB , VB = -100V, -85V - 3.2 4.5 IBH , VBH = -100V, -85V - 1.7 2.5 IBH, VBH = -75V - 1.4 3.0 mA 4.5 7.5 11 ICC 4.5 7.5 11 ICC - 7.5 11 mA (Note 7) - - - IBL - 0.4 7.5 IBL - 0.4 1.5 mA IB , VB = -100V, -85V - 2.3 5.0 IBH , VBH = -100V, -85V - 1.3 2.5 IBH, VBH = -75V - 1.3 2.5 mA ICC - 8.5 10.0 ICC - 8.5 10.0 (Note 15) - - - mA - - - mA (Note 16) - - - mA ICC IB , VB = -24V - 19 23.5 IBL - 19 23.5 Tip Open (Note 5) ICC - - 5.5 ICC - - 5.5 Power Denial (Note 5) ICC IB , VB = -24V IB , VB = -24V - - 1.0 IBL - - 1.0 - - - mA 0.5 3.0 5.0 ICC 0.5 3.0 4.5 ICC - 3.0 5.0 mA - 0.2 0.5 IBL - 0.2 0.5 IBL - 0.2 0.5 mA ON HOOK POWER DISSIPATION (Note 17) Forward or Reverse (Notes 5, 6) VB = -24V - 44 60 VBL = -24V - 44 60 VBL = -24V - 44 60 mW Low Power Standby (Note 2) VB = -85V - 52 - VBH = -85V - 52 65 VBH = -75V - 46 65 mW VB = -100V - 59 - VBH = -100V - 59 75 (Note 9) Ringing (Note 2) VB = -85V - 190 - VBH = -85V - 190 275 VBH = -75V - 170 250 mW VB = -100V - 220 - VBH = -100V - 220 300 (Note 9) - 290 - VBL = -24V - 290 310 VBL = -24V - 280 310 mW OFF HOOK POWER DISSIPATION (Notes 5, 17) Forward or Reverse VB = -24V NOTES: 7. The HC55180 does not provide battery switch operation. Therefore all battery voltage references will be made to VB. VB is the voltage applied to the common connection of the device VBL and VBH pins. See the HC55180 Basic Application Circuit. 8. Ringing Voltage is measured with VRS = 0.839 VRMS for -100V devices, VRS = 0.707 VRMS for -85V devices and VRS = 0.619 VRMS for -75V devices. 9. The HC55183 and HC55184 devices are specified with a single high battery voltage grade. 10. The device represents a low output impedance during ringing. Therefore the voltage across the ringing load is determined by the voltage divider formed by the protection resistance, loop resistance and ringing load impedance. 11. The HC55180, HC55183 and HC55184 are specified with a single longitudinal balance grade. 12. Longitudinal Balance is tested per IEEE455-1985, with 368Ω per Tip and Ring Terminal. 13. These parameters are tested 100% at room temperature. These parameters are guaranteed not tested across temperature via statistical characterization. 14. The HC55180, HC55183 and HC55184 do not support uncommitted switch operation. 15. The HC55183 and HC55184 do not support the Forward Loopback operating mode. 16. The HC55183 and HC55184 do not support the Tip Open operating mode. 17. The power dissipation numbers are actual device measurements and will be less than worse case calculations based on data sheet supply current limits. HC55180, HC55181, HC55182, HC55183, HC55184 34 Low Power Standby (Note 2) HC55180, HC55181, HC55182, HC55183, HC55184 Design Equations 4-WIRE TO 2-WIRE GAIN Loop Supervision Thresholds SWITCH HOOK DETECT The switch hook detect threshold is set by a single external resistor, RSH . Equation 1 is used to calculate the value of RSH. (EQ. 1) R SH = 600 ⁄ I SH The 4-wire to 2-wire gain is defined as the receive gain. It is a function of the terminating impedance, synthesized impedance and protection resistors. Equation 6 calculates the receive gain, G42. ZL G 42 = – 2 ------------------------------------------ Z + 2R O P + Z L (EQ. 6) The term ISH is the desired DC loop current threshold. The loop current threshold programming range is from 5mA to 15mA. When the device source impedance and protection resistors equals the terminating impedance, the receive gain equals unity. GROUND KEY DETECT 2-WIRE TO 4-WIRE GAIN The ground key detector senses a DC current imbalance between the Tip and Ring terminals when the ring terminal is connected to ground. The ground key detect threshold is not externally programmable and is internally fixed to 12mA regardless of the switch hook threshold. The 2-wire to 4-wire gain (G24) is the gain from tip and ring to the VTX output. The transmit gain is calculated in Equation 7. ZO G 24 = – ------------------------------------------ Z O + 2R P + Z L (EQ. 7) RING TRIP DETECT When the protection resistors are set to zero, the transmit gain is -6dB. The ring trip detect threshold is set by a single external resistor, RRT. IRT should be set between the peak ringing current and the peak off hook current while still ringing. TRANSHYBRID GAIN (EQ. 2) R RT = 1800 ⁄ I RT The capacitor CRT, in parallel with RRT, will set the ring trip response time. The transhybrid gain is defined as the 4-wire to 4-wire gain (G44). ZO G 44 = – --------------------------------------- Z + 2R O P + Z L (EQ. 8) Loop Current Limit When the protection resistors are set to zero, the transhybrid gain is -6dB. The loop current limit of the device is programmed by the external resistor RIL. The value of RIL can be calculated using Equation 3. COMPLEX IMPEDANCE SYNTHESIS 1760 R IL = ------------I LIM (EQ. 3) Substituting the impedance programming resistor, RS, with a complex programming network provides complex impedance synthesis. The term ILIM is the desired loop current limit. The loop current limit programming range is from 15mA to 45mA. Impedance Matching 2-WIRE NETWORK C2 R1 The impedance of the device is programmed with the external component RS . RS is the gain setting resistor for the feedback amplifier that provides impedance matching. If complex impedance matching is required, then a complex network can be substituted for RS . RESISTIVE IMPEDANCE SYNTHESIS The source impedance of the device, ZO , can be calculated in Equation 4. (EQ. 4) R S = 400 ( Z O ) RS R2 (EQ. 5) Z O = Z L – 2R P 35 RP FIGURE 1. COMPLEX PROGRAMMING NETWORK The reference designators in the programming network match the evaluation board. The component RS has a different design equation than the RS used for resistive impedance synthesis. The design equations for each component are provided below. R S = 400 × ( R 1 – 2 ( R P ) ) The required impedance is defined by the terminating impedance and protection resistors as shown in Equation 5. PROGRAMMING NETWORK CP (EQ. 9) R P = 400 × R 2 (EQ. 10) C P = C 2 ⁄ 400 (EQ. 11) HC55180, HC55181, HC55182, HC55183, HC55184 Low Power Standby Overview The low power standby mode (LPS, 000) should be used during idle line conditions. The device is designed to operate from the high battery during this mode. Most of the internal circuitry is powered down, resulting in low power dissipation. If the 2-wire (tip/ring) DC voltage requirements are not critical during idle line conditions, the device may be operated from the low battery. Operation from the low battery will decrease the standby power dissipation. TABLE 1. DEVICE INTERFACES DURING LPS INTERFACE ON OFF NOTES Receive x Ringing x AC transmission, impedance matching and ringing are disabled during this mode. Transmit x 2-Wire x Amplifiers disabled. Loop Detect x Switch hook or ground key. 2-Wire Interface During LPS, the 2-wire interface is maintained with internal switches and voltage references. The Tip and Ring amplifiers are turned off to conserve power. The device will provide MTU compliance, loop current and loop supervision. Figure 2 represents the internal circuitry providing the 2-wire interface during low power standby. Ring terminal will be clamped by the internal reference. The same Ring relationships apply when operating from the low battery voltage. For high battery voltages (VBH) less than or equal to the internal MTU reference threshold: V RING = V BH + 4 Loop Current During LPS, the device will provide current to a load. The current path is through resistors and switches, and will be function of the off hook loop resistance (RLOOP). This includes the off hook phone resistance and copper loop resistance. The current available during LPS is determined by Equation 13. I LOOP = ( – 1 – ( – 49 ) ) ⁄ ( 600 + 600 + R LOOP ) 600Ω TIP AMP TIP RING RING AMP 600Ω MTU REF FIGURE 2. LPS 2-WIRE INTERFACE CIRCUIT DIAGRAM Another loop current related parameter is longitudinal current capability. The longitudinal current capability is reduced to 10mARMS per pin. The reduction in longitudinal current capability is a result of turning off the Tip and Ring amplifiers. On Hook Power Dissipation The on hook power dissipation of the device during LPS is determined by the operating voltages and quiescent currents and is calculated using Equation 14. (EQ. 14) The quiescent current terms are specified in the electrical tables for each operating mode. Load power dissipation is not a factor since this is an on hook mode. Some applications may specify a standby current. The standby current may be a charging current required for modern telephone electronics. Standby Current Power dissipation Any standby line current, ISLC , introduces an additional power dissipation term PSLC . Equation 15 illustrates the power contribution is zero when the standby line current is zero. P SLC = I SLC × ( V BH – 49 + 1 + I SLC x1200 ) MTU Compliance (EQ. 13) Internal current limiting of the standby switches will limit the maximum current to 20mA. P LPS = V BH × I BHQ + V BL × I BLQ + V CC × I CCQ GND (EQ. 12) (EQ. 15) Maintenance Termination Unit or MTU compliance places DC voltage requirements on the 2-wire terminals during idle line conditions. The minimum idle voltage is 42.75V. The high side of the MTU range is 56V. The voltage is expressed as the difference between Tip and Ring. If the battery voltage is less than -49V (the MTU clamp is off), the standby line current power contribution reduces to Equation 16. The Tip voltage is held near ground through a 600Ω resistor and switch. The Ring voltage is limited to a maximum of -49V (by MTU REF) when operating from either the high or low battery. A switch and 600Ω resistor connect the MTU reference to the Ring terminal. When the high battery voltage exceeds the MTU reference of -49V (typically), the Most applications do not specify charging current requirements during standby. When specified, the typical charging current may be as high as 5mA. 36 P SLC = I SLC × ( V BH + 1 + I SLC x1200 ) (EQ. 16) HC55180, HC55181, HC55182, HC55183, HC55184 Overview The forward active mode (FA, 001) is the primary AC transmission mode of the device. On hook transmission, DC loop feed and voice transmission are supported during forward active. Loop supervision is provided by either the switch hook detector (E0 = 1) or the ground key detector (E0 = 0). The device may be operated from either high or low battery for onhook transmission and low battery for loop feed. On-Hook Transmission The primary purpose of on hook transmission will be to support caller ID and other advanced signalling features. The transmission over load level while on hook is 3.5VPEAK . When operating from the high battery, the DC voltages at Tip and Ring are MTU compliant. The typical Tip voltage is -4V and the Ring voltage is a function of the battery voltage for battery voltages less than -60V as shown in Equation 17. (EQ. 17) V RING = V BH + 4 Loop supervision is provided by the switch hook detector at the DET output. When DET goes low, the low battery should be selected for DC loop feed and voice transmission. Feed Architecture Most applications will operate the device from low battery while off hook. The DC feed characteristic of the device will drive Tip and Ring towards half battery to regulate the DC loop current. For light loads, Tip will be near -4V and Ring will be near VVBL + 4V. The following diagram shows the DC feed characteristic. VTR(OC) ILOOP (mA) The point on the y-axis labeled VTR(OC) is the open circuit Tip to Ring voltage and is defined by the feed battery voltage. The curve of Figure 5 determines the actual loop current for a given set of loop conditions. The loop conditions are determined by the low battery voltage and the DC loop impedance. The DC loop impedance is the sum of the protection resistance, copper resistance (ohms/foot) and the telephone off hook DC resistance. - IB ILOOP (mA) ILIM 2RP RLOOP (Ω) RKNEE FIGURE 5. ILOOP VERSUS RLOOP LOAD CHARACTERISTIC + RL RC - + KS FIGURE 3. VOLTAGE FEED CURRENT SENSE DIAGRAM By monitoring the current at the amplifier output, a negative feedback mechanism sets the output voltage for a defined load. The amplifier gains are set by resistor ratios (RA , RB , RC) providing all the performance benefits of matched resistors. The internal sense resistor, RCS , is much smaller than the gain resistors and is typically 20Ω for this device. The feedback mechanism, KS , represents the amplifier configuration providing the negative feedback. DC Loop Feed The feedback mechanism for monitoring the DC portion of the loop current is the loop detector. A low pass filter is used in the feedback to block voice band signals from interfering with the loop current limit function. The pole of the low pass filter is set by the external capacitor CDC . The value of the external capacitor should be 4.7µF. 37 IA ISC VIN VOUT (EQ. 18) V TR ( OC ) = V BL – 8 RA RCS ILIM FIGURE 4. DC FEED CHARACTERISTIC The design implements a voltage feed current sense architecture. The device controls the voltage across Tip and Ring based on the sensing of load current. Resistors are placed in series with Tip and Ring outputs to provide the current sensing. The diagram below illustrates the concept. RB m = (∆VTR/∆IL) = 10kΩ VTR , DC (V) Forward Active The slope of the feed characteristic and the battery voltage define the maximum loop current on the shortest possible loop as the short circuit current ISC. V TR ( OC ) – 2R P I LIM I SC = I LIM + -----------------------------------------------------10e3 (EQ. 19) The term ILIM is the programmed current limit, 1760/RIL. The line segment IA represents the constant current region of the loop current limit function. V TR ( OC ) – R LOOP I LIM I A = I LIM + -------------------------------------------------------------10e3 (EQ. 20) The maximum loop impedance for a programmed loop current is defined as RKNEE . V TR ( OC ) R KNEE = -----------------------I LIM (EQ. 21) When RKNEE is exceeded, the device will transition from constant current feed to constant voltage, resistive feed. The line segment IB represents the resistive feed portion of the load characteristic. V TR ( OC ) I B = -----------------------R LOOP (EQ. 22) HC55180, HC55181, HC55182, HC55183, HC55184 Voice Transmission The feedback mechanism for monitoring the AC portion of the loop current consists of two amplifiers, the sense amplifier (SA) and the transmit amplifier (TA). The AC feedback signal is used for impedance synthesis. A detailed model of the AC feed back loop is provided below. R VRX R RA RX OUT RF 1:1 VTX RB - + TA TX IN - + RS R R +2.4V VRX 20 TIP - -IN R + HC5518x CODEC 1:1 20 RING FIGURE 7. TRANSHYBRID BALANCE INTERFACE VTX + - TA - + RS R -IN 0.75R 3R 3R 3R + 3R CFB 8K - VFB VSA R/2 The resistor ratio, RF /RB , provides the final adjustment for the transmit gain, GTX . The transmit gain is calculated using Equation 25. R F G TX = – G 24 -------- R B (EQ. 25) Most applications set RF = RB , hence the device 2-wire to 4-wire equals the transmit gain. Typically RB is greater than 20kΩ to prevent loading of the device transmit output. FIGURE 6. AC SIGNAL TRANSMISSION MODEL The gain of the transmit amplifier, set by RS , determines the programmed impedance of the device. The capacitor CFB blocks the DC component of the loop current. The ground symbols in the model represent AC grounds, not actual DC potentials. The resistor ratio, RF /RA , is determined by the transhybrid gain of the device, G44 . RF is previously defined by the transmit gain requirement and RA is calculated using Equation 26. RB R A = ---------G 44 (EQ. 26) The sense amp output voltage, VSA , as a function of Tip and Ring voltage and load is calculated using Equation 23. Power Dissipation 10 V SA = – ( V T – V R ) -----ZL The power dissipated by the device during on hook transmission is strictly a function of the quiescent currents for each supply voltage during Forward Active operation. (EQ. 23) The transmit amplifier provides the programmable gain required for impedance synthesis. In addition, the output of this amplifier interfaces to the CODEC transmit input. The output voltage is calculated using Equation 24. RS V VTX = – V SA ---------- 8e3 (EQ. 24) Once the impedance matching components have been selected using the design equations, the above equations provide additional insight as to the expected AC node voltages for a specific Tip and Ring load. Transhybrid Balance The final step in completing the impedance synthesis design is calculating the necessary gains for transhybrid balance. The AC feed back loop produces an echo at the VTX output of the signal injected at VRX . The echo must be cancelled to maintain voice quality. Most applications will use a summing amplifier in the CODEC front end as shown below to cancel the echo signal. 38 + V BL × I BLQ + V CC × I CCQ P FAQ = V BH × I BHQ (EQ. 27) Off hook power dissipation is increased above the quiescent power dissipation by the DC load. If the loop length is less than or equal to RKNEE , the device is providing constant current, IA , and the power dissipation is calculated using Equation 28. P FA ( IA ) = P FA ( Q ) + ( V BL xI A ) – ( R LOOP xI 2 A ) (EQ. 28) If the loop length is greater than RKNEE , the device is operating in the constant voltage, resistive feed region. The power dissipated in this region is calculated using Equation 29. P FA ( IB ) = P FA ( Q ) + ( V BL xI B ) – ( R LOOP xI 2 B ) (EQ. 29) Since the current relationships are different for constant current versus constant voltage, the region of device operation is critical to valid power dissipation calculations. HC55180, HC55181, HC55182, HC55183, HC55184 Reverse Active Ringing Overview Overview The reverse active mode (RA, 011) provides the same functionality as the forward active mode. On hook transmission, DC loop feed and voice transmission are supported. Loop supervision is provided by either the switch hook detector (E0 = 1) or the ground key detector (E0 = 0). The device may be operated from either high or low battery. The ringing mode (RNG, 100) provides linear amplification to support a variety of ringing waveforms. A programmable ring trip function provides loop supervision and auto disconnect upon ring trip. The device is designed to operate from the high battery during this mode. During reverse active the Tip and Ring DC voltage characteristics exchange roles. That is, Ring is typically 4V below ground and Tip is typically 4V more positive than battery. Otherwise, all feed and voice transmission characteristics are identical to forward active. Architecture The device provides linear amplification to the signal applied to the ringing input, VRS . The differential ringing gain of the device is 80V/V. The circuit model for the ringing path is shown in the following figure. R Silent Polarity Reversal R/8 Changing from forward active to reverse active or vice versa is referred to as polarity reversal. Many applications require slew rate control of the polarity reversal event. Requirements range from minimizing cross talk to protocol signalling. The device uses an external low voltage capacitor, CPOL , to set the reversal time. Once programmed, the reversal time will remain nearly constant over various load conditions. In addition, the reversal timing capacitor is isolated from the AC loop, therefore loop stability is not impacted. The internal circuitry used to set the polarity reversal time is shown below. I1 POL 75kΩ CPOL I2 FIGURE 8. REVERSAL TIMING CONTROL During forward active, the current from source I1 charges the external timing capacitor CPOL and the switch is open. The internal resistor provides a clamping function for voltages on the POL node. During reverse active, the switch closes and I2 (roughly twice I1) pulls current from I1 and the timing capacitor. The current at the POL node provides the drive to a differential pair which controls the reversal time of the Tip and Ring DC voltages. ∆time C POL = ---------------75000 (EQ. 30) Where ∆time is the required reversal time. Polarized capacitors may be used for CPOL . The low voltage at the POL pin and minimal voltage excursion ±0.75V, are well suited to polarized capacitors. Power Dissipation The power dissipation equations for forward active operation also apply to the reverse active mode. 39 20 TIP - + - + 5:1 20 + RING - VRS 800K + VBH 2 R FIGURE 9. LINEAR RINGING MODEL The voltage gain from the VRS input to the Tip output is 40V/V. The resistor ratio provides a gain of 8 and the current mirror provides a gain of 5. The voltage gain from the VRS input to the Ring output is -40V/V. The equations for the Tip and Ring outputs during ringing are provided below. V BH V T = ----------- + ( 40 × VRS ) 2 (EQ. 31) V BH V R = ----------- – ( 40 × VRS ) 2 (EQ. 32) When the input signal at VRS is zero, the Tip and Ring amplifier outputs are centered at half battery. The device provides auto centering for easy implementation of sinusoidal ringing waveforms. Both AC and DC control of the Tip and Ring outputs is available during ringing. This feature allows for DC offsets as part of the ringing waveform. Ringing Input The ringing input, VRS , is a high impedance input. The high impedance allows the use of low value capacitors for AC coupling the ring signal. The VRS input is enabled only during the ringing mode, therefore a free running oscillator may be connected to VRS at all times. When operating from a battery of -100V, each amplifier, Tip and Ring, will swing a maximum of 95VP-P. Hence, the maximum signal swing at VRS to achieve full scale ringing is approximately 2.4VP-P. The low signal levels are compatible with the output voltage range of the CODEC. The digital nature of the CODEC ideally suits it for the function of programmable ringing generator. See Applications. HC55180, HC55181, HC55182, HC55183, HC55184 Forward Loop Back Logic Control Ringing patterns consist of silent intervals. The ringing to silent pattern is called the ringing cadence. During the silent portion of ringing, the device can be programmed to any other operating mode. The most likely candidates are low power standby or forward active. Depending on system requirements, the low or high battery may be selected. Loop supervision is provided with the ring trip detector. The ring trip detector senses the change in loop current when the phone is taken off hook. The loop detector full wave rectifies the ringing current, which is then filtered with external components RRT and CRT. The resistor RRT sets the trip threshold and the capacitor CRT sets the trip response time. Most applications will require a trip response time less than 150ms. Three very distinct actions occur when the devices detects a ring trip. First, the DET output is latched low. The latching mechanism eliminates the need for software filtering of the detector output. The latch is cleared when the operating mode is changed externally. Second, the VRS input is disabled, removing the ring signal from the line. Third, the device is internally forced to the forward active mode. Overview The forward loop back mode (FLB, 101) provides test capability for the device. An internal signal path is enabled allowing for both DC and AC verification. The internal 600Ω terminating resistor has a tolerance of ±20%. The device is intended to operate from only the low battery during this mode. Architecture When the forward loop back mode is initiated internal switches connect a 600Ω load across the outputs of the Tip and Ring amplifiers. TIP TIP AMP 600Ω RING AMP RING FIGURE 10. FORWARD LOOP BACK INTERNAL TERMINATION Power Dissipation The power dissipation during ringing is dictated by the load driving requirements and the ringing waveform. The key to valid power calculations is the correct definition of average and RMS currents. The average current defines the high battery supply current. The RMS current defines the load current. The cadence provides a time averaging reduction in the peak power. The total power dissipation consists of ringing power, Pr , and the silent interval power, Ps . tr ts P RNG = P r × -------------- + P s × -------------t +t t +t r s r (EQ. 33) s The terms tR and tS represent the cadence. The ringing interval is tR and the silent interval is tS . The typical cadence ratio tR :tS is 1:2. The quiescent power of the device in the ringing mode is defined in Equation 34. P r ( Q ) = V BH × I BHQ + V BL × I BLQ + V CC × I CCQ (EQ. 34) The total power during the ringing interval is the sum of the quiescent power and loading power: 2 V RMS P r = P r ( Q ) + V BH × I AVG – -----------------------------------------Z +R REN (EQ. 35) LOOP For sinusoidal waveforms, the average current, IAVG , is defined in Equation 36. V RMS × 2 2 I AVG = --- ----------------------------------------- π Z +R REN (EQ. 36) LOOP The silent interval power dissipation will be determined by the quiescent power of the selected operating mode. 40 DC Verification When the internal signal path is provided, DC current will flow from Tip to Ring. The DC current will force DET low, indicating the presence of loop current. In addition, the ALM output will also go low. This does not indicate a thermal alarm condition. Rather, proper logic operation is verified in the event of a thermal shutdown. In addition to verifying device functionality, toggling the logic outputs verifies the interface to the system controller. AC Verification The entire AC loop of the device is active during the forward loop back mode. Therefore a 4-wire to 4-wire level test capability is provided. Depending on the transhybrid balance implementation, test coverage is provided by a one or two step process. System architectures which cannot disable the transhybrid function would require a two step process. The first step would be to send a test tone to the device while on hook and not in forward loop back mode. The return signal would be the test level times the gain RF /RA of the transhybrid amplifier. Since the device would not be terminated, cancellation would not occur. The second step would be to program the device to FLB and resend the test tone. The return signal would be much lower in amplitude than the first step, indicating the device was active and the internal termination attenuated the return signal. System architectures which disable the transhybrid function would achieve test coverage with a signal step. Once the transhybrid function is disable, program the device for FLB and send the test tone. The return signal level is determined by the 4-wire to 4-wire gain of the device. HC55180, HC55181, HC55182, HC55183, HC55184 Tip Open Battery Switching Overview Overview The tip open mode (110) is intended for compatibility for PBX type interfaces. Used during idle line conditions, the device does not provide transmission. Loop supervision is provided by either the switch hook detector (E0 = 1) or the ground key detector (E0 = 0). The ground key detector will be used in most applications. The device may be operated from either high or low battery. The integrated battery switch selects between the high battery and low battery. The battery switch is controlled with the logic input BSEL. When BSEL is a logic high, the high battery is selected and when a logic low, the low battery is selected. All operating modes of the device will operate from high or low battery except forward loop back. Functionality The logic control is independent of the operating mode decode. Independent logic control provides the most flexibility and will support all application configurations. During tip open operation, the Tip amplifier is disabled and the Ring amplifier is enabled. The minimum Tip impedance is 30kΩ. The only active path through the device will be the Ring amplifier. In keeping with the MTU characteristics of the device, Ring will not exceed -56.5V when operating from the high battery. Though MTU does not apply to tip open, safety requirements are satisfied. On Hook Power Dissipation The on hook power dissipation of the device during tip open is determined by the operating voltages and quiescent currents and is calculated using Equation 37. P TO = V BH × I BHQ + V BL × I BLQ + V CC × I CCQ (EQ. 37) The quiescent current terms are specified in the electrical tables for each operating mode. Load power dissipation is not a factor since this is an on hook mode. Functionality When changing device operating states, battery switching should occur simultaneously with or prior to changing the operating mode. In most cases, this will minimize overall power dissipation and prevent glitches on the DET output. The only external component required to support the battery switch is a diode in series with the VBH supply lead. In the event that high battery is removed, the diode allows the device to transition to low battery operation. Low Battery Operation All off hook operating conditions should use the low battery. The prime benefit will be reduced power dissipation. The typical low battery for the device is -24V. However this may be increased to support longer loop lengths or high loop current requirements. Standby conditions may also operate from the low battery if MTU compliance is not required, further reducing standby power dissipation. Power Denial High Battery Operation Overview Other than ringing, the high battery should be used for standby conditions which must provide MTU compliance. During standby operation the power consumption is typically 50mW with -100V battery. If ringing requirements do not require full 100V operation, then a lower battery will result in lower standby power. The power denial mode (111) will shutdown the entire device except for the logic interface. Loop supervision is not provided. This mode may be used as a sleep mode or to shut down in the presence of a persistent thermal alarm. Switching between high and low battery will have no effect during power denial. Functionality During power denial, both the Tip and Ring amplifiers are disabled, representing high impedances. The voltages at both outputs are near ground. Thermal Shutdown In the event the safe die temperature is exceeded, the ALM output will go low and DET will go high and the part will automatically shut down. When the device cools, ALM will go high and DET will reflect the loop status. If the thermal fault persists, ALM will go low again and the part will shut down. Programming power denial will permanently shutdown the device and stop the self cooling cycling. High Voltage Decoupling The 100V rating of the device will require a capacitor of higher voltage rating for decoupling. Suggested decoupling values for all device pins are 0.1µF. Standard surface mount ceramic capacitors are rated at 100V. For applications driven at low cost and small size, the decoupling scheme shown below could be implemented. 0.22µ 0.22µ VBL VBH HC5518X FIGURE 11. ALTERNATE DECOUPLING SCHEME As with all decoupling schemes, the capacitors should be as close to the device pins as physically possible. 41 HC55180, HC55181, HC55182, HC55183, HC55184 Uncommitted Switch Test Load Overview The uncommitted switch is a three terminal device designed for flexibility. The independent logic control input, SWC, allows switch operation regardless of device operating mode. The switch is activated by a logic low. The positive and negative terminals of the device are labeled SW+ and SW- respectively. Relay Driver The switch may be used to connect test loads across Tip and Ring. The test loads can provide external test termination for the device. Proper connection of the uncommitted switch to Tip and Ring is shown below. TIP RING The uncommitted switch may be used as a relay driver by connecting SW+ to the relay coil and SW- to ground. The switch is designed to have a maximum on voltage of 0.6V with a load current of 45mA. TEST LOAD SW+ +5V SW- RELAY SWC FIGURE 13. TEST LOAD SWITCHING SW+ SW- SWC FIGURE 12. EXTERNAL RELAY SWITCHING Since the device provides the ringing waveform, the relay functions which may be supported include subscriber disconnect, test access or line interface bypass. An external snubber diode is not required when using the uncommitted switch as a relay driver. 42 The diode in series with the test load blocks current from flowing through the uncommitted switch when the polarity of the Tip and Ring terminals are reversed. In addition to the reverse active state, the polarity of Tip and Ring are reversed for half of the ringing cycle. With independent logic control and the blocking diode, the uncommitted switch may be continuously connected to the Tip and Ring terminals. HC55180, HC55181, HC55182, HC55183, HC55184 Basic Application Circuits CPS1 CPS3 VCC VBL VBH CRX VRX RP1 U1 TIP VRS CRS HC55180 RP2 RING CTX VTX CRT RRT RS RTD -IN CFB VFB RSH RD E0 RIL ILIM F1 CDC VCC F0 CDC CPOL POL F2 DET ALM AGND BGND FIGURE 14. HC55180 BASIC APPLICATION CIRCUIT TABLE 2. BASIC APPLICATION CIRCUIT COMPONENT LIST COMPONENT VALUE TOLERANCE RATING U1 - Ringing SLIC HC5518x N/A N/A RRT 20kΩ 1% 0.1W RSH 49.9kΩ 1% 0.1W RIL 71.5kΩ 1% 0.1W RS 210kΩ 1% 0.1W CRX , CRS , CTX , CRT , CPOL , CFB 0.47µF 20% 10V CDC 4.7µF 20% 10V CPS1 0.1µF 20% >100V CPS2 , CPS3 0.1µF 20% 100V D1 1N400X type with breakdown > 100V. RP1 , RP2 Protection resistor values are application dependent and will be determined by protection requirements. Standard applications will use ≥ 35Ω per side. Design Parameters: Ring Trip Threshold = 90mAPEAK , Switch Hook Threshold = 12mA, Loop Current Limit = 24.6mA, Synthesize Device Impedance = 210kΩ/400 = 525Ω, with 39Ω protection resistors, impedance across Tip and Ring terminals = 603Ω. Where applicable, these component values apply to the Basic Application Circuits for the HC55180, HC55181, HC55182, HC55183 and HC55184. Pins not shown in the Basic Application Circuit are no connect (NC) pins. 43 HC55180, HC55181, HC55182, HC55183, HC55184 CPS1 CPS1 CPS2 CPS2 D1 CPS3 VCC D1 CPS3 VBL VBH VCC VBL VBH CRX CRX VRX RP1 U1 TIP HC55181 CRS RS VTX RS SW+ -IN CFB -IN SW- CRT CFB VFB RRT RTD RSH SWC RD BSEL E0 RIL ILIM E0 ILIM F0 CDC CDC POL AGND F0 F1 CDC VCC F2 CPOL BSEL RIL F1 VCC RTD RSH SWC RD CDC DET ALM ALM BGND AGND BGND FIGURE 17. HC55182 BASIC APPLICATION CIRCUIT CPS1 CPS1 CPS2 CPS2 D1 CPS3 VCC VBL VBH U1 TIP HC55183 RP2 RING VCC CRX CRS U1 TIP HC55184 RP2 CTX RING VTX RS CRS CTX VTX RS -IN RRT CFB VFB RSH CRX VRS CRT -IN RTD VBL VBH VRX RP1 VRS CRT D1 CPS3 VRX RP1 RTD CFB VFB RSH RD RD BSEL RIL BSEL RIL E0 ILIM CDC F1 CDC F2 DET E0 ILIM F0 CDC VCC F2 DET FIGURE 15. HC55181 BASIC APPLICATION CIRCUIT RRT CRS CTX RING VFB RRT VRS RP2 VTX SW- CRT HC55182 CTX SW+ U1 TIP VRS RP2 RING VRX RP1 VCC F1 CDC CPOL POL ALM AGND BGND FIGURE 16. HC55183 BASIC APPLICATION CIRCUIT 44 F0 F2 DET ALM AGND BGND FIGURE 18. HC55184 BASIC APPLICATION CIRCUIT HC55180, HC55181, HC55182, HC55183, HC55184 Additional Application Diagrams Reducing Overhead Voltages The transmission overhead voltage of the device is internally set to 4V per side. The overhead voltage may be reduced by injecting a negative DC voltage on the receive input using a voltage divider (Fig. 19). Accordingly, the 2-wire port overload level will decrease the same amount as the injected offset. R2 CRX 160 kΩ VD VRX FROM CODEC R1 1:1 HC5518X VBL will not match the 200Ω teletax impedance. The gain set by RT cancels the impedance matching feedback with respect to the teletax injection point. Therefore the device appears as a low impedance source for teletax. The resistor RT is calculated using the following equation. 200 R T = ------------------------------------------------------------------- × R S 200 + 2 × R P + ( R S ⁄ 400 ) The signal level across a 200Ω load will be twice the injected teletax signal level. As the teletax level at VTX will equal the injection level, set RC = RB for cancellation. The value of RB is based on the voice band transhybrid balance requirements. The connection of the teletax source to the transhybrid amplifier should be AC coupled to allow proper biasing of the transhybrid amplifier input FIGURE 19. EXTERNAL OVERHEAD CONTROL TA + - The divider shunt resistance is the parallel combination of the internal 160kΩ resistor and the external R2 . The sum of R1 and R2 should be greater than 500kΩ to minimize the additional power dissipation of the divider. The DC gain relationship from the divider voltage, VD, to the Tip and Ring outputs is shown below. CFB VFB -IN + VTX TX IN RC RT +2.4V CODEC TELETAX SOURCE FIGURE 21. TELETAX SIGNALLING With a low battery voltage -24V and a divider voltage of -0.5V, the Tip to Ring voltage is 17V. As a result, the overhead voltage is reduced from 8V to 7V and the overload level will decrease from 3.5VPEAK to 3.0VPEAK. CODEC Ringing Generation Maximum ringing amplitudes of the device are achieved with signal levels approximately 2.4VP-P. Therefore the low pass receive output of the CODEC may serve as the low level ring generator. The ringing input impedance of 480kΩ minimum should not interfere with CODEC drive capability. A single external capacitor is required to AC coupled the ringing signal from the CODEC. The circuit diagram for CODEC ringing is shown below. Ringing With DC Offsets The balanced ringing waveform consists of zero DC offset between the Tip and Ring terminals. However, the linear amplifier architecture provides control of the DC offset during ringing. The DC gain is the same as the AC gain, 40V/V per amplifier. Positive DC offsets applied directly to the ringing input will shift both Tip and Ring away from half battery towards ground and battery respectively. A voltage divider on the ringing input may be used to generate the offset (Figure 22). The reference voltage, VREF, can be either the CODEC 2.4V reference voltage or the 5V supply. R2 - + 160 kΩ VRS VRX 480K RX OUT VD CRS FROM RING GEN. R1 HC5518X - + 480K RF RB RS (EQ. 38) V T – R = V BL – 8 – ( 2 × V D ) 1:1 (EQ. 39) VREF VRS FIGURE 22. EXTERNAL OVERHEAD CONTROL CODEC HC5518X FIGURE 20. CODEC RINGING INTERFACE Implementing Teletax Signalling A resistor, RT, is required at the -IN input of the device for injecting the teletax signal (Figure 20). For most applications the synthesized device impedance (i.e., 600Ω) 45 An offset during ringing of 30V, would require a DC shift of 15V at Tip and 15V at Ring. The DC offset would be created by a +0.375V (VD) at the VRS input. The divider resistors should be selected to minimize the value of the AC coupling capacitor CRS and the loading of the ring generator and voltage reference. The ringing input impedance should also be accounted for in divider resistor calculations. HC55180, HC55181, HC55182, HC55183, HC55184 Pin Descriptions PLCC SYMBOL DESCRIPTION 1 TIP 2 BGND 3 VBL Low battery supply connection. 4 VBH High battery supply connection for the most negative battery. 5 SW+ Uncommitted switch positive terminal. This pin is a no connect (NC) on the HC55180, HC55183 and HC55184. 6 SW- Uncommitted switch negative terminal. This pin is a no connect (NC) on the HC55180, HC55183 and HC55184. 7 SWC Switch control input. This TTL compatible input controls the uncommitted switch, with a logic “0” enabling the switch and logic “1” disabling the switch. This pin is a no connect (NC) on the HC55180, HC55183 and HC55184. 8 F2 Mode control input - MSB. F2-F0 for the TTL compatible parallel control interface for controlling the various modes of operation of the device. 9 F1 Mode control input. 10 F0 Mode control input. 11 E0 Detector Output Selection Input. This TTL input controls the multiplexing of the SHD (E0 = 1) and GKD (E0 = 0) comparator outputs to the DET output based upon the state at the F2-F0 pins (see the Device Operating Modes table shown on page 2). 12 DET Detector Output - This TTL output provides on-hook/off-hook status of the loop based upon the selected operating mode. The detected output will either be switch hook, ground key or ring trip (see the Device Operating Modes table shown on page 2). 13 ALM Thermal Shutdown Alarm. This pin signals the internal die temperature has exceeded safe operating temperature (approximately 175oC) and the device has been powered down automatically. 14 AGND Analog ground reference. This pin should be externally connected to BGND. 15 BSEL Selects between high and low battery, with a logic “1” selecting the high battery and logic “0” the low battery. This pin is a no connect (NC) on the HC55180. 16 NC This pin is a no connect (NC) for all the devices. 17 POL External capacitor on this pin sets the polarity reversal time. This pin is a no connect on the HC55182 and HC55183. 18 VRS Ringing Signal Input - Analog input for driving 2-wire interface while in Ring Mode. 19 VRX Analog Receive Voltage - 4-wire analog audio input voltage. AC couples to CODEC. 20 VTX Transmit output voltage - Output of impedance matching amplifier, AC couples to CODEC. 21 VFB Feedback voltage for impedance matching. This voltage is scaled to accomplish impedance matching. 22 -IN 23 VCC Positive voltage power supply, usually +5V. 24 CDC DC Biasing Filter Capacitor - Connects between this pin and VCC. 25 RTD Ring trip filter network. 26 ILIM Loop Current Limit programming resistor. 27 RD Switch hook detection threshold programming resistor. 28 RING TIP power amplifier output. Battery Ground - To be connected to zero potential. All loop current and longitudinal current flow from this ground. Internally separate from AGND but it is recommended that it is connected to the same potential as AGND. Impedance matching amplifier summing node. RING power amplifier output. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 46