NB100EP223 3.3V1:22 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Output Enable http://onsemi.com Description The NB100EP223 is a low skew 1−to−22 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low voltage applications which require a large number of outputs to drive precisely aligned low skew signals to their destination. The two clock inputs are differential HSTL or LVPECL and they are selected by the CLK_SEL pin which is LVTTL. To avoid generation of a runt clock pulse when the device is enabled/disabled, the Output Enable (OE), which is LVTTL, is synchronous ensuring the outputs will only be enabled/disabled when they are already in LOW state (See Figure 7). The NB100EP223 guarantees low output−to−output skew. The optimal design, layout, and processing minimize skew within a device and from lot to lot. In any differential output pair, the same bias and termination scheme is required. Unused output pairs should be left unterminated (open) to “reduce power and switching noise as much as possible.” Any unused single line of a differential pair should be terminated the same as the used line to maintain balanced loads on the differential driver outputs. The output structure uses an open emitter architecture and will be terminated with 50 W to ground instead of a standard HSTL configuration (See Figure 6). The wide VIHCMR specification allows both pair of CLOCK inputs to accept LVDS levels. MARKING DIAGRAM* LQFP−64 FA SUFFIX CASE 848G A WL YY WW G NB100 EP223 AWLYYWWG 64 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. Features • 100 ps Typical Device−to−Device Skew • 25 ps Typical Within Device Skew • HSTL Compatible Outputs Drive 50 W to Ground With No • • • • • • • Offset Voltage Maximum Frequency >500 MHz 1 ns Typical Propagation Delay LVPECL and HSTL Mode Operating Range: VCC = 3 V to 3.6 V with GND = 0 V, VCCO = 1.6 V to 2.0 V Q Output will Default Low with Inputs Open Thermally Enhanced 64−Lead LQFP CLOCK Inputs are LVDS−Compatible; Requires External 100 W LVDS Termination Resistor Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev. 7 1 Publication Order Number: NB100EP223/D Q7 Q8 Q8 Q9 Q9 Q10 Q10 Q11 Q11 Q12 Q12 Q13 Q13 VCCO VCC0 Q7 VCCO NB100EP223 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 48 49 32 VCC0 Q6 50 31 Q14 Q6 51 30 Q14 Q5 52 29 Q15 Q5 53 28 Q15 Q4 54 27 Q16 Q4 55 26 Q16 Q3 56 25 Q17 Q3 57 24 Q17 Q2 58 23 Q18 Q2 59 22 Q18 Q1 60 21 Q19 Q1 61 20 Q19 Q0 62 19 Q20 Q0 63 18 Q20 VCC0 64 17 VCC0 12 13 14 15 16 Q21 VCC0 11 Q21 10 NC 9 NC 8 OE VCC 7 GND NC 6 LVPECL_CLK NC 5 LVPECL_CLK 4 CLK_SEL 3 HSTL_CLK 2 HSTL_CLK 1 VCC0 NB100EP223 All VCC, VCCO, and GND pins must be externally connected to appropriate Power Supply to guarantee proper operation (VCC 0 VCCO). The thermally conductive exposed pad on package bottom (see package case drawing) is electrically connected to GND internally. Figure 1. 64−Lead LQFP Pinout (Top View) Table 1. PIN DESCRIPTION PIN HSTL_CLK*, HSTL_CLK** LVPECL_CLK*, LVPECL_CLK** CLK_SEL** OE** Q0−Q21, Q0−Q21 VCC VCCO GND*** Table 2. FUNCTION TABLE FUNCTION OE* CLK_SEL Q0−Q21 Q0−Q21 HSTL, LVPECL or LVDS Differential Inputs L H L L LVPECL Differential Inputs L H L H LVCMOS/LVTTL Input CLK Select H L HSTL_CLK HSTL_CLK LVCMOS/LVTTL Output Enable H H LVPECL_CLK LVPECL_CLK HSTL Differential Outputs Positive Supply_Core (3.0 V − 3.6 V) * The OE (Output Enable) signal is synchronized with the Positive Supply_HSTL Outputs(1.6V−2.0V) rising edge of the HSTL_CLK and LVPECL_CLK signal. Ground * Pins will default LOW when left open. ** Pins will default HIGH when left open. *** The thermally conductive exposed pad on the bottom of the package is electrically connected to GND internally. http://onsemi.com 2 NB100EP223 CLK_SEL HSTL_CLK 0 22 HSTL_CLK 22 LVPECL_CLK Q0−Q21 (HSTL) 1 LVPECL_CLK VCC GND Q0−Q21 (HSTL) Q VCCO D OE Figure 2. Logic Diagram Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor ESD Protection 37.5 kW Human Body Model Machine Model Charged Device Model > 2 kV > 150 V > 2 kV Moisture Sensitivity (Note 1) LQFP−64 Flammability Rating Oxygen Index: 28 to 34 Pb Pkg Pb−Free Pkg Level 2 Level 3 UL 94 V−0 @ 0.125 in Transistor Count 693 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, refer to Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC Core Power Supply GND = 0 V VCCO = 1.8 V 4 V VCCO HSTL Output Power Supply GND = 0 V VCC = 3.3 V 4 V VI PECL Mode Input Voltage GND = 0 V VI ≤ VCC 4 V Iout Output Current Continuous Surge 50 100 mA mA TA Operating Temperature Range 0 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) (See Application Information) 0 lfpm 500 lfpm 64 LQFP 64 LQFP 35.6 30 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) (See Application Information) 0 lfpm 500 lfpm 64 LQFP 64 LQFP 3.2 6.4 °C/W °C/W Tsol Wave Solder 265 265 °C Pb Pb−Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 3 NB100EP223 Table 5. LVPECL DC CHARACTERISTICS VCC = 3.3 V; VCCO = 1.8 V; GND = 0 V 0°C Symbol Characteristic 85°C Typ Max Min Typ Max Min Typ Max Unit 82 100 130 82 100 130 82 100 130 mA ICC Power Supply Current VIH Input HIGH Voltage (Single−Ended) 2135 2420 2135 2420 2135 2420 mV VIL Input LOW Voltage (Single−Ended) 1490 1675 1490 1675 1490 1675 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 2) (Figure 4) LVPECL_CLK/LVPECL_CLK HSTL_CLK/HSTL_CLK 1.2 0.3 3.3 1.6 1.2 0.3 3.3 1.6 1.2 0.3 3.3 1.6 V V 150 mA IIH Input HIGH Current IIL Input LOW Current VCC 25°C Min 150 CLK CLK 150 0.5 −150 0.5 −150 0.5 −150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. VIHCMR min varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 6. LVTTL/LVCMOS DC CHARACTERISTICS VCC = 3.3 V; VCCO = 1.8 V; GND = 0 V 0°C Symbol Min Characteristic 25°C Typ Max Min 2.0 Typ 85°C Max VIH Input HIGH Voltage 2.0 VIL Input LOW Voltage IIH Input HIGH Current −150 150 −150 150 IIL Input LOW Current −300 300 −300 300 Min Typ Max 2.0 0.8 Unit V 0.8 0.8 V −150 150 mA −300 300 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. Table 7. HSTL DC CHARACTERISTICS VCC = 3.3 V; VCCO = 1.6−2.0 V; GND = 0 V 0°C Symbol Characteristic Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit VOH Output HIGH Voltage (Note 3) 1000 1200 1000 1200 1000 1200 mV VOL Output LOW Voltage (Note 3) 0 400 0 400 0 400 mV VIH Input HIGH Voltage (Differential) HSTL_CLK/HSTL_CLK VX+100 1600 VX+100 1600 VX+100 1600 mV VIL Input LOW Voltage (Differential) HSTL_CLK/HSTL_CLK −300 VX−100 −300 VX−100 −300 VX−100 mV VX Differential Cross Point Voltage 680 900 680 900 680 900 mV IIH Input HIGH Current −150 150 −150 150 −150 150 mA IIL Input LOW Current −300 300 −300 300 −300 300 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. All outputs loaded with 50 W to GND (See Figure 6). http://onsemi.com 4 NB100EP223 Table 8. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V; GND = 0 V (Note 4) 0°C Symbol Characteristic Min Typ 25°C Max 85°C Min Typ Max 600 750 750 850 900 950 1100 1200 Min Typ Max 600 700 800 850 1000 1050 1300 1350 ps ps Unit VOpp Differential Output Voltage (Figure 3) fout < 500 MHz 600 750 tPLH tPHL Propagation Delay (Differential) LVPECL_CLK to Q HSTL_CLK to Q 700 800 900 900 1000 1100 tskew Within−Device Skew (Note 5) Device−to−Device Skew (Note 6) 25 100 50 250 30 200 65 450 50 250 115 450 ps ps tJITTER Random Clock Jitter (Figure 3) (RMS) 0.5 2 0.5 2 0.5 2 ps VPP Input Swing (Differential Mode) (Note 8) (Figure 4) LVPECL, HSTL 150 800 1200 800 1200 800 1200 tS OE Set Up Time (Note 7) 1.0 1.0 1.0 ns tH OE Hold Time 0.5 0.5 0.5 ns tr/tf Output Rise/Fall Time (20%−80%) 300 450 700 150 275 450 700 150 350 500 mV 750 mV ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Measured with 750 mV (LVPECL) source or 1 V (HSTL) source, 50% duty cycle clock source. All outputs loaded with 50 W to ground (See Figure 6). 5. Skew is measured between outputs under identical transitions and conditions on any one device. 6. Device−to−Device skew for identical transitions at identical VCC levels. 7. OE Set Up Time is defined with respect to the rising edge of the clock. OE High−to−Low transition ensures outputs remain disabled during the next clock cycle. OE Low−to−High transition enables normal operation of the next input clock (See Figure 7). 8. VPP is the differential input voltage swing required to maintain AC characteristics including tPD and device−to−device skew. 10 9.0 800 8.0 700 7.0 Q AMP (mV) 600 6.0 5.0 500 4.0 3.0 400 2.0 300 200 RMS JITTER (ps) OUTPUT AMPLITUDE (mV) 900 RMS JITTER (ps) 0.5 0.6 0.7 0.8 0.9 1.0 1.0 0 FREQUENCY (GHz) Figure 3. Output Frequency (FOUT) versus Output Voltage (VOPP) and Random Clock Jitter (tJITTER) http://onsemi.com 5 NB100EP223 VPP VIHCMR VCC(LVPECL) VCCO(HSTL) VIH(DIFF) VIH(DIFF) VX VPP VIL(DIFF) GND Figure 4. LVPECL Differential Input Levels Q VIL(DIFF) GND Figure 5. HSTL Differential Input Levels Z = 50 W HSTL OUTPUT Q 50 W 50 W GROUND Figure 6. HSTL Output Termination and AC Test Reference CLK CLK OE Q Q Figure 7. Output Enable (OE) Timing Diagram http://onsemi.com 6 NB100EP223 APPLICATIONS INFORMATION Using the thermally enhanced package of the NB100EP223 supply enough solder paste to fill those vias and not starve the solder joints. The attachment process for the exposed pad package is equivalent to standard surface mount packages. Figure 9, “Recommended solder mask openings”, shows a recommended solder mask opening with respect to a 4 X 4 thermal via array. Because a large solder mask opening may result in a poor rework release, the opening should be subdivided as shown in Figure 9. For the nominal package standoff of 0.1 mm, a stencil thickness of 5 to 8 mils should be considered. The NB100EP223 uses a thermally enhanced 64−lead LQFP package. The package is molded so that a portion of the leadframe is exposed at the surface of the package bottom side. This exposed metal pad will provide the low thermal impedance that supports the power consumption of the NB100EP223 high−speed bipolar integrated circuit and will ease the power management task for the system design. In multilayer board designs, a thermal land pattern on the printed circuit board and thermal vias are recommended to maximize both the removal of heat from the package and electrical performance of the NB100EP223. The size of the land pattern can be larger, smaller, or even take on a different shape than the exposed pad on the package. However, the solderable area should be at least the same size and shape as the exposed pad on the package. Direct soldering of the exposed pad to the thermal land will provide an efficient thermal conduit. The thermal vias will connect the exposed pad of the package to internal copper planes of the board. The number of vias, spacing, via diameters and land pattern design depend on the application and the amount of heat to be removed from the package. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. The recommended thermal land design for NB100EP223 applications on multi−layer boards comprises a 4 X 4 thermal via array using a 1.2 mm pitch as shown in Figure 8 providing an efficient heat removal path. All Units mm 0.2 4.6 1.0 1.0 0.2 4.6 Thermal Via Array (4 X 4) 1.2 mm Pitch 0.3 mm Diameter Exposed Pad Land Pattern Figure 9. Recommended Solder Mask Openings All Units mm Proper thermal management is critical for reliable system operation. This is especially true for high−fanout and high output drive capability products. For thermal system analysis and junction temperature calculation the thermal resistance parameters of the package is provided: 4.6 Table 9. Thermal Resistance * 4.6 Thermal Via Array (4 X 4) 1.2 mm Pitch 0.3 mm Diameter lfpm qJA 5C/W qJC 5C/W 0 35.6 3.2 100 32.8 4.9 500 30.0 6.4 * Junction to ambient and Junction to board, four−conductor layer test board (2S2P) per JESD 51−8 These recommendations are to be used as a guideline, only. It is therefore recommended that users employ sufficient thermal modeling analysis to assist in applying the general recommendations to their particular application to assure adequate thermal performance. The exposed pad of the NB100EP223 package is electrically shorted to the substrate of the integrated circuit and GND. The thermal land should be electrically connected to GND. Exposed Pad Land Pattern Figure 8. Recommended Thermal Land Pattern The via diameter should be approximately 0.3 mm with 1 oz. copper via barrel plating. Solder wicking inside the via may result in voiding during the solder process and must be avoided. If the copper plating does not plug the vias, stencil print solder paste onto the printed circuit pad. This will http://onsemi.com 7 NB100EP223 ORDERING INFORMATION Package Shipping † NB100EP223FA LQFP−64 160 Units / Tray NB100EP223FAG LQFP−64 (Pb−Free) 160 Units / Tray NB100EP223FAR2 LQFP−64 1500 / Tape & Reel NB100EP223FAR2G LQFP−64 (Pb−Free) 1500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 8 NB100EP223 PACKAGE DIMENSIONS LQFP 64 LEAD EXPOSED PAD 848G−02 ISSUE A 4 PL M M/2 −Z− 0.20 (0.008) T X−Y Z AJ AJ 64 49 1 48 ÇÇÇÇ ÉÉÉÉ ÉÉÉÉ ÇÇÇÇ ÉÉÉÉ ÇÇÇÇ PLATING −X− AA −Y− L B B/2 L/2 16 D REF 33 0.08 (0.003) 32 17 J AB M Y T−U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MM. 3. DATUM PLANE E" IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING PLANE. 4. DATUM X", Y" AND Z" TO BE DETERMINED AT DATUM PLANE DATUM E". 5. DIMENSIONS M AND L TO BE DETERMINED AT SEATING PLANE DATUM T". 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE BASE DETERMINED AT DATUM PLAND E". METAL 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM D DIMENSION BY MORE THAN 0.08 (0.003). DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). 8. EXACT SHAPE OF EACH CORNER IS OPTIONAL. Z DIM A B C D F G H J K L M N P R S V W AA AB AC AD AE AF DETAIL AJ−AJ A/2 0.20 (0.008) E X−Y Z A DETAIL AH −E− −T− AG AG G/2 SEATING PLANE G 0.08 (0.003) T 4 PL 60 PL D 0.08 (0.003) 64 PL M T X−Y V Z 0.05 (0.002) R S AC AD AE EXPOSED PAD 17 32 33 16 S C W N K P F AF H DETAIL AH 1 48 64 49 VIEW AG−AG http://onsemi.com 9 0.25 GAGE PLANE MILLIMETERS MIN MAX 10.00 BSC 10.00 BSC 1.35 1.45 0.17 0.27 0.45 0.75 0.50 BSC 1.00 REF 0.09 0.20 0.05 0.15 12.00 BSC 12.00 BSC 0.20 −−− 0_ 7_ 0_ −−− −−− 1.60 11 _ 13 _ 11 _ 13 _ 0.17 0.23 0.09 0.16 0.08 −−− 0.08 −−− 4.50 4.78 4.50 4.78 INCHES MIN MAX 0.394 BSC 0.394 BSC 0.053 0.057 0.007 0.011 0.018 0.030 0.020 BSC 0.039 BSC 0.004 0.008 0.002 0.006 0.472 BSC 0.472 BSC 0.008 −−− 0_ 7_ 0_ −−− −−− 0.063 11 _ 13 _ 11 _ 13 _ 0.007 0.009 0.004 0.006 0.003 −−− 0.003 −−− 0.180 0.188 0.180 0.188 NB100EP223 ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 10 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB100EP223/D