ALSC AS6C8016A-55BIN Process technology Datasheet

AUGUST 2010
AS6C8016A
512K X 16 BIT LOW POWER CMOS SRAM
FEATURES
GENERAL DESCRIPTION
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The AS6C8016A is fabricated by Alliance ' s
advanced full CMOS process technology. The families
support industrial temperature range and Chip Scale
Package for user flexibility of system design. The families
also support low data retention voltage for battery backup operation with low data retention current.
Process Technology : 0.15μm Full CMOS
Organization : 512K x 16 bit
Power Supply Voltage : 2.7V ~ 3.6V
Low Data Retention Voltage : 1.5V(Min.)
Three state output and TTL Compatible
Package Type : 48-FPBGA, 44-TSOP2
PRODUCT FAMILY
Power Dissipation
Product
Family
Operating
Temperature
Vcc
Range
Speed
Standby
(ISB1, Typ.)
Operating
(ICC1.Max.)
AS6C8016A
KGD
Industrial
(-40 ~ 85oC)
AS6C8016A-55BIN
2.7 ~ 3.6 V
2 μA1)
55 ns
4 mA
48-FPBGA
44-TSOP2
AS6C8016A-55ZIN
1. Typical values are measured at Vcc=3.3V, TA=25oC and not 100% tested.
FUNCTIONAL BLOCK DIAGRAM
Pre-charge Circuit
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
Row Select
VCC
DQ0 ~ DQ7
Data
Cont
Data
Cont
DQ8 ~ DQ15
VSS
Memory Array
2048 x 4096
I/O Circuit
Column Select
A11 A12 A13 A14 A15 A16 A17 A18
WE
OE
UB
LB
CS
PKG
Type
Control Logic
1
AUGUST 2010
AS6C8016A
512K X 16 BIT LOW POWER CMOS SRAM
Low Power, 512Kx16 SRAM
EM681FV16B Family
PIN CONFIGURATIONS
FPBGA-48 : Top view(ball down)
A
44 - TSOP2 : Top view
1
2
3
4
5
6
LB
OE
A0
A1
A2
NC
B
DQ8
UB
A3
A4
CS
DQ0
C
DQ9
DQ10
A5
A6
DQ1
DQ2
D
VSS
DQ11
A17
A7
DQ3
VCC
E
VCC
DQ12
NC
A16
DQ4
VSS
F
DQ14
DQ13
A14
A15
DQ5
DQ6
G
DQ15
NC
A12
A13
WE
DQ7
H
A18
A8
A9
A10
A11
NC
A4
A3
1
2
44
43
A2
A1
A0
3
4
5
6
7
8
9
10
11
12
42
41
40
39
38
37
36
35
34
33
UB
LB
DQ15
DQ14
DQ13
DQ12
VSS
VCC
WE
A18
13
14
15
16
17
18
32
31
30
29
28
27
DQ11
DQ10
DQ9
DQ8
A8
A9
A17
A16
A15
A14
19
20
21
22
26
25
24
23
A10
A11
A12
A13
CS
DQ0
DQ1
DQ2
DQ3
VCC
VSS
DQ4
DQ5
DQ6
DQ7
44 - TSOP2
A5
A6
A7
OE
PIN DESCRIPTION
Name
Function
Name
Function
CS
Chip Select input
VCC
Power Supply
OE
Output Enable input
VSS
Ground
WE
Write Enable input
UB
Upper Byte (DQ8~DQ15)
Address inputs
LB
Lower Byte (DQ0~DQ7)
Data inputs/outputs
NC
No Connection
A0~A18
DQ0~DQ15
2
AUGUST 2010
AS6C8016A
512K X 16 BIT LOW POWER CMOS SRAM
Low Power, 512Kx16 SRAM
EM681FV16B Family
ABSOLUTE MAXIMUM RATINGS1)
Parameter
Symbol
Ratings
VIN, VOUT
-0.2 to 4.0
V
Voltage on Vcc supply relative to Vss
VCC
-0.2 to 4.0
V
Power Dissipation
PD
1.0
W
Operating Temperature
TA
-40 to 85
Voltage on Any Pin Relative to Vss
Unit
o
C
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
FUNCTIONAL DESCRIPTION
CS
OE
WE
LB
UB
DQ0~7
DQ8~15
Mode
Power
H
X
X
X
X
High-Z
High-Z
Deselected
Stand by
X
X
X
H
H
High-Z
High-Z
Deselected
Stand by
L
H
H
L
X
High-Z
High-Z
Output Disabled
Active
L
H
H
X
L
High-Z
High-Z
Output Disabled
Active
L
L
H
L
H
Data Out
High-Z
Lower Byte Read
Active
L
L
H
H
L
High-Z
Data Out
Upper Byte Read
Active
L
L
H
L
L
Data Out
Data Out
Word Read
Active
L
X
L
L
H
Data In
High-Z
Lower Byte Write
Active
L
X
L
H
L
High-Z
Data In
Upper Byte Write
Active
L
X
L
L
L
Data In
Data In
Word Write
Active
NOTE : X means don’t care. (Must be low or high state)
3
AUGUST 2010
AS6C8016A
512K X 16 BIT LOW POWER CMOS SRAM
Low Power, 512Kx16 SRAM
EM681FV16B Family
RECOMMENDED DC OPERATING CONDITIONS 1)
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VCC
2.7
3.3
3.6
V
Ground
VSS
0
0
0
V
Input high voltage
VIH
2.2
-
VCC + 0.22)
V
Input low voltage
VIL
-0.23)
-
0.6
V
1.
2.
3.
4.
TA= -40 to 85oC, otherwise specified
Overshoot: VCC +2.0 V in case of pulse width < 20ns
Undershoot: -2.0 V in case of pulse width < 20ns
Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f =1MHz, TA=25oC)
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
CIN
VIN=0V
-
8
pF
Input/Ouput capacitance
CIO
VIO=0V
-
10
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Input leakage current
ILI
VIN=VSS to VCC
-1
-
1
μA
Output leakage current
ILO
CS=VIH or OE=VIH or WE=VIL or LB=UB=VIH
VIO=VSS to VCC
-1
-
1
μA
Operating power supply
ICC
IIO=0mA, CS=VIL, WE=VIH, VIN=VIH or VIL
-
-
2
mA
ICC1
Cycle time=1μs, 100% duty, IIO=0mA,
CS<0.2V, LB<0.2V or/and UB<0.2V,
VIN<0.2V or VIN>VCC-0.2V
-
-
4
mA
ICC2
Cycle time =Min, IIO=0mA, 100% duty,
CS=VIL, LB=VIL or/and UB=VIL ,
VIN=VIL or VIH
-
-
35
mA
Output low voltage
VOL
IOL = 2.1mA
-
-
0.4
V
Output high voltage
VOH
IOH = -1.0mA
2.4
-
-
V
Standby Current (TTL)
ISB
CS=VIH, Other inputs=VIH or VIL
-
-
0.5
mA
-
2 1)
15
μA
Average operating
current
55ns
CS>VCC-0.2V, Other inputs = 0~VCC
Standby Current (CMOS)
ISB1
(Typ. condition : VCC=3.3V @ 25oC)
(Max. condition : VCC=3.6V @ 85oC)
1. Typical values are measured at Vcc=3.3V, TA=25oC and not 100% tested.
4
LF
AUGUST 2010
AS6C8016A
512K X 16 BIT LOW POWER CMOS SRAM
Low Power, 512Kx16 SRAM
EM681FV16B Family
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
Input Pulse Level : 0.4 to 2.4V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V
Output Load (See right) : CL1) = 100pF+ 1 TTL(70nsec)
CL1) = 30pF + 1 TTL(45ns/55ns)
1. Including scope and Jig capacitance
2. R1=3070Ω,
R2=3150Ω
3. VTM=2.8V
4. CL = 5pF + 1 TTL (measurement with tLZ, tHZ, tOLZ, tOHZ, tWHZ)
READ CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC)
Parameter
Symbol
55ns
Min
Max
Unit
Read cycle time
tRC
55
-
ns
Address access time
tAA
-
55
ns
Chip select to output
tCO
-
55
ns
Output enable to valid output
tOE
-
35
ns
UB, LB access time
tBA
45
ns
Chip select to low-Z output
tLZ
5
-
ns
UB, LB enable to low-Z output
tBLZ
5
-
ns
Output enable to low-Z output
tOLZ
5
-
ns
Chip disable to high-Z output
tHZ
0
20
ns
UB, LB disable to how-Z output
tBHZ
0
20
ns
Output disable to high-Z output
tOHZ
0
20
ns
tOH
10
-
ns
Output hold from address change
WRITE CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC)
Parameter
Symbol
55ns
Min
Max
Unit
Write cycle time
tWC
55
-
ns
Chip select to end of write
tCW
45
-
ns
Address setup time
tAS
0
-
ns
Address valid to end of write
tAW
45
-
ns
UB, LB valid to end of write
tBW
45
-
ns
Write pulse width
tWP
45
-
ns
Write recovery time
tWR
0
-
ns
Write to ouput high-Z
tWHZ
0
20
ns
Data to write time overlap
tDW
25
Data hold from write time
tDH
0
-
End write to output low-Z
tOW
5
-
ns
ns
ns
55ns
Min
55
45
0
45
45
45
70ns
Max
-
0
-
0
20
40
0
5
5
Min
70
60
0
60
60
55
Max
-
Unit
ns
ns
ns
ns
ns
ns
0
-
ns
0
25
ns
40
-
ns
0
-
ns
5
-
ns
VTM3)
R12)
CL1)
R22)
AUGUST 2010
AS6C8016A
512K X 16 BIT LOW POWER CMOS SRAM
EM681FV16B Family
Low Power, 512Kx16 SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Out
Data Valid
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH)
tRC
Address
tAA
tOH
tCO
CS
tHZ
tBA
UB,LB
tBHZ
tOE
OE
tOHZ
tOLZ
Data Out
High-Z
Data Valid
tBLZ
tLZ
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
AUGUST 2010
AS6C8016A
512K X 16 BIT LOW POWER CMOS SRAM
Low Power, 512Kx16 SRAM
EM681FV16B Family
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tCW(2)
tWR(4)
CS
tAW
tBW
UB,LB
tWP(1)
WE
tAS(3)
Data in
tDH
tDW
High-Z
High-Z
Data Valid
tWHZ
Data out
tOW
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS
tAW
tBW
UB,LB
tWP(1)
WE
tDW
Data in
Data out
Data Valid
High-Z
High-Z
7
tDH
AUGUST 2010
AS6C8016A
512K X 16 BIT LOW POWER CMOS SRAM
Low Power, 512Kx16 SRAM
EM681FV16B Family
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
tWC
Address
tCW(2)
tWR(4)
CS
tAW
tBW
UB,LB
tWP(1)
tAS(3)
WE
tDW
Data in
Data out
tDH
Data Valid
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest
transition when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high.
8
AUGUST 2010
AS6C8016A
512K X 16 BIT LOW POWER CMOS SRAM
EM681FV16B Family
Low Power, 512Kx16 SRAM
DATA RETENTION CHARACTERISTICS
Parameter
Symbol
VCC for Data Retention
VDR
Data Retention Current
IDR
Chip Deselect to Data Retention Time
tSDR
Operation Recovery Time
Test Condition
ISB1 Test Condition
(Chip Disabled)1)
VCC=1.5V, ISB1 Test Condition
(Chip Disabled)1)
See data retention wave form
tRDR
Min
Typ
1.5
-
3.6
V
-
-
4
μA
0
-
-
tRC
-
-
NOTES
1. See the ISB1 measurement condition of datasheet page 4.
DATA RETENTION WAVE FORM
tSDR
Data Retention Mode
Vcc
2.7V
2.2V
VDR
CS, LB / UB
GND
CS > Vcc-0.2V
9
tRDR
Max
Max Unit
ns
AUGUST 2010
AS6C8016A
512K X 16 BIT LOW POWER CMOS SRAM
Low Power, 512Kx16 SRAM
EM681FV16B Family
PACKAGE DIMENSION
44 - TSOP2 (0.8mm pin pitch)
Unit : millimeters / inches
10
AUGUST 2010
AS6C8016A
512K X 16 BIT LOW POWER CMOS SRAM
Low Power, 512Kx16 SRAM
EM681FV16B Family
48 Ball Fine Pitch BGA (0.75mm ball pitch)
Unit: millimeters
Bottom View
A1 index Mark
B
B1
B
6
5
4
3
0.5
2
0.5
Top View
1
A
B
#A1
C
C1
C
C
D
C1/2
E
F
G
H
B/2
Detail A
D
E2
0.26
Side View
0.25 Typ.
E
E1
A
Min
Typ
Max
A
-
0.75
-
B
7.95
8.00
8.05
B1
-
3.75
-
C
9.95
10.00
10.05
C1
-
5.25
-
D
0.30
0.35
0.40
E
-
-
1.00
E1
-
-
0.70
E2
0.20
0.25
0.30
Y
-
-
0.08
Y
0.79Typ.
C
NOTES.
1. Bump counts : 48(8row x 6column)
2. Bump pitch : (x,y)=(0.75x0.75) (typ.)
3. All tolerence are +/-0.050 unless
otherwise specified.
4. Typ : Typical
5. Y is coplanarity : 0.08(Max)
11
AUGUST 2010
AS6C8016A
512K X 16 BIT LOW POWER CMOS SRAM
Low Power, 512Kx16 SRAM
EM681FV16B Family
ORDERING INFORMATION
Organization
VCC
Range
Package
Operating Temp
AS6C8016A -55ZIN
512K x 16
2.7 - 3.6V
44pin TSOP II
Industrial ~ -40 C - 85 C
55
AS6C8016A -55BIN
512K x 16
2.7 - 3.6V
48ball FBGA
Industrial ~ -40 C - 85 C
55
Alliance
Speed
ns
PART NUMBERING SYSTEM
1. EMLSI Memory
2. Device Type
3. Density
4. Function
5. Technology
6. Operating Voltage
AS6C
8016
Device Number
/ow power
SRAM prefix
80 = 8M
16 = x16
-55
X
Package Option
X
Temperature Range
Access
Time
Z - 44pin TSOP
I = Industrial
B = 48ball FBGA
(-40 to + 85 C)
11. Power
10. Speed
9. Package
8. Version
7. Organization
N
N = Lead Free
RoHS
compliant part
ORDERING INFORMATION
Alliance
VCC
Range
Organization
AS6C8016A -55ZIN
512K x 16
AS6C8016A -55BIN
Package
2.7 - 5.5V
512K x 16
2.7 - 5.5V
Speed
ns
Operating Temp
44pin TSOP II
Industrial ~ -40 C - 85 C
55
48ball FBGA
Industrial ~ -40 C - 85 C
55
PART NUMBERING SYSTEM
AS6C
8016
-55
Device Number
low power
SRAM prefix
80 = 8M
16 = x16
Access
Time
X
X
Package Option
Temperature Range
Z - 44pin TSOP
I = Industrial
B = 48ball TFBGA
(-40 to + 85 C)
N
N = Lead Free
RoHS
compliant part
®
Alliance Memory, Inc
51 Taylor Way,
San Carlos, CA 94070, USA
Phone: 650-610-6800
Fax: 650-620-9211
Copyright © Alliance Memory
All Rights Reserved
www.alliancememory.com
7. Organization
8
--------------- X8 bit
16
--------------- X16 bit
32
--------------- X32 bit
11. Power
LL
--------------- Low Low Power
LF
--------------- Low Low Power(Pb-free & Green)
L
--------------- Low Power
S
--------------- Standard Power
6. Operating Voltage
T
--------------- 5.0V
V
--------------- 3.3V
U
--------------- 3.0V
S
--------------- 2.5V
R
--------------- 2.0V
P
--------------- 1.8V
4. Option
0
--------------- Dual CS
1
--------------- Single CS
3. Density
1
--------------1M
2
--------------2M
4
--------------4M
8
--------------8M
16
--------------- 16M
32
--------------- 32M
64
--------------- 64M
28
--------------- 128M
10. Speed
45
--------------- 45ns
55
--------------- 55ns
60
--------------- 60ns
70
--------------- 70ns
85
--------------- 85ns
90
--------------- 90ns
10
--------------- 100ns
12
--------------- 120ns
9. Package
Blank--------------- KGD, FBGA
S
--------------- 32 sTSOP1
T
--------------- 32 TSOP1
U
--------------- 44 TSOP2
V
--------------- 32 SOP
2. Device Type
6
--------------- Low Power SRAM
7
--------------- STRAM
C
--------------- CellularRAM
1. Memory Component
8. Version
Blank--------------- Mother die
A
--------------- 2 nd generation
B
--------------- 3 rd generation
C
--------------- 4 th generation
D
--------------- 5 th generation
E
--------------- 6 th generation
F
--------------- 7 th generation
G
--------------- 8 th generation
EM
X XX X X X XX X X - XX XX
MEMORY FUNCTION GUIDE
12
5. Technology
F
--------------- Full CMOS
© Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks ofAlliance.
All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to thisdocument and its
products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The datacontained herein represents
Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at anytime, without notice. If the product
described herein is under development, significant changes to these specifications are possible. The information inthis product data sheet is intended to be
general descriptive information for potential customers and users, and is not intended to operate as, or provide,any guarantee or warrantee to any user or
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express or implied warranties related to the sale and/or use of Alliance products including liability orwarranties related to fitness for a particular purpose,
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