AD ADA4625-1 Low noise, fast settling single supply, rro, jfet op amp Datasheet

PIN CONFIGURATION
Wide gain bandwidth product: 18 MHz typical
High slew rate: 48 V/μs typical
Low voltage noise density: 3.3 nV/√Hz typical at 1 kHz
Low peak-to-peak noise: 0.15 μV p-p, 0.1 Hz to 10 Hz
Low input bias current: ±15 pA typical at TA = 25°C
Low offset voltage: ±80 μV maximum at TA = 25°C
Offset voltage drift: ±1.2 μV/°C maximum at TA = −40°C to 85°C
Fast settling: 0.01% in 700 ns typical
Wide range of operating voltages
Dual-supply operation: ±2.5 V to ±18 V
Single-supply operation: 5 V to 36 V
Input voltage range includes V−
Rail-to-rail output
High capacitive load drive capability
Output short-circuit current: ±46 mA
No phase reversal
Unity-gain stable
APPLICATIONS
PLL filter amplifiers
Transimpedance amplifiers
Photodiode sensor interfaces
Low noise charge amplifiers
ADA4625-1
–IN 2
+IN 3
V– 4
TOP VIEW
(Not to Scale)
The ADA4625-1 provides optimal performance in high voltage,
high gain, and low noise applications. The input common-mode
voltage range includes the negative supply, and the output
swings rail to rail. This enables the user to maximize dynamic
input range in low voltage, single supply applications without
the need for a separate negative voltage power supply for
ground sense.
The combination of wide bandwidth, low noise, and low input
bias current makes the ADA4625-1 especially suitable for
phase-locked loop (PLL), active filter amplifiers and for high
tuning voltage (VTUNE), voltage controlled oscillators (VCOs)
and preamplifiers where low level signals require an amplifier
that provides both high amplification and wide bandwidth.
NC
7
V+
6
OUT
5
NC
Figure 1.
The ADA4625-1 is unity-gain stable, and there is no phase
reversal when input range exceeds either supply rail by 200 mV.
The output is capable of driving loads up to 1000 pF and/or
600 Ω loads.
The ADA4625-1 is specified for operation over the extended
industrial temperature range of −40°C to +125°C and operates
from +5 V to +36 V (±2.5 V to ±18 V) with specifications at +5 V
and ±18 V. The ADA4625-1 is available in 8-lead SOIC package
with an exposed pad (EPAD).
VOLTAGE NOISE DENSITY (nV/√Hz)
The ADA4625-1 builds upon Analog Devices, Inc., industry
leading high voltage, single-supply, rail-to-rail output (RRO),
precision junction field effect transistor (JFET) input op amps,
taking that product type to a level of speed and low noise that
has not been made available to the market previously.
8
NOTES
1. NC = NO CONNECTION. DO NOT CONNECT TO THIS PIN.
2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO GND,
V+ OR V– PLANE, OR LEAVE IT FLOATING.
100
GENERAL DESCRIPTION
Rev. 0
NC 1
15893-001
FEATURES
VSY = 5V
VSY = ±18V
10
1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
15893-157
Data Sheet
36 V, 18 MHz, Low Noise, Fast Settling
Single Supply, RRO, JFET Op Amp
ADA4625-1
Figure 2. Voltage Noise Density vs. Frequency
Table 1. Related Precision JFET Operational Amplifiers
Single
Not applicable
AD8510
AD8610
ADA4610-1
ADA4622-1
ADA4627-1/ADA4637-1
Dual
AD823A
AD8512
AD8620
ADA4610-2
ADA4622-2
Not applicable
Quad
Not applicable
AD8513
Not applicable
ADA4610-4
ADA4622-4
Not applicable
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADA4625-1
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Output Stage................................................................................ 20
Applications ....................................................................................... 1
No Phase Inversion .................................................................... 21
General Description ......................................................................... 1
Supply Current............................................................................ 21
Pin Configuration ............................................................................. 1
Applications Information .............................................................. 22
Revision History ............................................................................... 2
Active Loop Filter for Phase-Locked Loops (PLLs) .............. 22
Specifications..................................................................................... 3
ADA4625-1 Advantages and Design Example ....................... 23
Electrical Characteristics—±18 V Operation ........................... 3
Transimpedance Amplifier ....................................................... 24
Electrical Characteristics—5 V Operation................................ 5
Recommended Power Solution ................................................ 28
Absolute Maximum Ratings............................................................ 7
Input Overvoltage Protection ................................................... 28
Thermal Resistance ...................................................................... 7
Driving Capacitive Loads .......................................................... 28
ESD Caution .................................................................................. 7
Thermal Management ............................................................... 29
Pin Configuration and Function Descriptions ............................. 8
Outline Dimensions ....................................................................... 30
Typical Performance Characteristics ............................................. 9
Ordering Guide .......................................................................... 30
Theory of Operation ...................................................................... 20
Input and Gain Stages ................................................................ 20
REVISION HISTORY
10/2017—Revision 0: Initial Version
Rev. 0 | Page 2 of 30
Data Sheet
ADA4625-1
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—±18 V OPERATION
Supply voltage (VSY) = ±18 V, common-mode voltage (VCM) = output voltage (VOUT) = 0 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Symbol
Test Conditions/Comments
Min
VOS
Offset Voltage Drift
ΔVOS/ΔT
Input Bias Current
IB
Input Offset Current
IOS
−40°C < TA < +125°C
−40°C < TA < +85°C
−40°C < TA < +125°C
Typ
Max
Unit
±15
±80
±250
±1.2
±2.1
±75
±5.5
±50
±0.4
+14.5
μV
μV
μV/°C
μV/°C
pA
nA
pA
nA
V
dB
dB
dB
dB
dB
±0.2
±0.5
±15
−40°C < TA < +125°C
±2
−40°C < TA < +125°C
Input Voltage Range
Common-Mode Rejection Ratio
Large Signal Voltage Gain
Input Capacitance
Input Resistance
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
IVR
CMRR
AVO
CDM
CCM
RDM
RCM
VOH
VOL
Output Current
Short-Circuit Current
Closed-Loop Output Impedance
IOUT
ISC
ZOUT
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
Supply Current per Amplifier
ISY
VCM = −18.2 V to +14.5 V
−40°C < TA < +125°C
VCM = −18.2 V to +12 V
−40°C < TA < +125°C
Load resistance (RL) = 2 kΩ, VOUT = −17.5 V
to +17.5 V
−40°C < TA < +125°C
RL = 600 Ω, VOUT = −15 V to +15 V
−40°C < TA < +125°C
Differential mode
Common mode
Differential mode
Common mode, VCM from −18 V to +12 V
RL = 2 kΩ
−40°C < TA < +125°C
RL = 600 Ω
−40°C < TA < +125°C
RL = 2 kΩ
−40°C < TA < +125°C
RL = 600 Ω
−40°C < TA < +125°C
Dropout voltage (VDROPOUT) < 1 V
−18.2
97
94
115
110
140
135
130
115
Rev. 0 | Page 3 of 30
130
150
dB
dB
dB
pF
pF
Ω
Ω
135
8.6
11.3
1012
1012
17.65
17.5
17.0
16.75
17.72
17.28
−17.74
−17.4
−17.70
−17.5
−17.0
−16.85
±33
±46
2
18
29
f = 1 MHz, closed-loop gain (AV) = +1
AV = +10
AV = +100
VSY = ±5 V to ±18 V
−40°C < TA < +125°C
VOUT = 0 V
−40°C < TA < +125°C
115
105
102
120
4.0
4.5
5
V
V
V
V
V
V
V
V
mA
mA
Ω
Ω
Ω
dB
dB
mA
mA
ADA4625-1
Parameter
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Unity-Gain Crossover
−3 dB Bandwidth
Phase Margin
Settling Time
ELECTROMAGNETIC INTERFERENCE (EMI)
REJECTION RATIO
f = 1000 MHz
f = 2400 MHz
NOISE PERFORMANCE
Peak-to-Peak Noise
Voltage Noise Density
Current Noise Density
Total Harmonic Distortion + Noise
Data Sheet
Symbol
Test Conditions/Comments
SR
VOUT = ±10 V, RL = 2 kΩ, AV = −1
VOUT = ±10 V, RL = 2 kΩ, AV = −5
AV = 100
AV = 1
AV = 1
GBP
UGC
−3 dB
ΦΜ
tS
To 0.1%, input voltage (VIN) = 10V step,
RL = 2 kΩ, load capacitance (CL) = 15 pF,
AV = −1
To 0.01%, VIN = 10 V step, RL = 2 kΩ,
CL = 15 pF, AV = −1
Min
Typ
Max
Unit
48
44
18
12.4
16
88
500
V/μs
V/μs
MHz
MHz
MHz
Degrees
ns
700
ns
56
93
dB
dB
0.15
5.5
3.6
3.3
4.5
μV p-p
nV/√Hz
nV/√Hz
nV/√Hz
fA/√Hz
0.0003
−109
0.0007
−103
%
dB
%
dB
EMIRR
eN p-p
eN
iN
THD + N
0.1 Hz to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 1 kHz
AV = 1, f = 10 Hz to 20 kHz, RL = 2 kΩ,
VIN = 6 VRMS at 1 kHz
Bandwidth = 80 kHz
Bandwidth = 500 kHz
Rev. 0 | Page 4 of 30
Data Sheet
ADA4625-1
ELECTRICAL CHARACTERISTICS—5 V OPERATION
VSY = 5 V, VCM = 1.5 V, VOUT = VSY/2, TA = 25°C, unless otherwise noted.
Table 3.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Symbol
Test Conditions/Comments
Min
VOS
Offset Voltage Drift
ΔVOS/ΔT
Input Bias Current
IB
Input Offset Current
IOS
−40°C < TA < +125°C
−40°C < TA < +85°C
−40°C < TA < +125°C
Typ
Max
Unit
±0.1
±0.6
±1.0
±2.6
±3.6
±50
±3.5
±50
±150
+1.5
mV
mV
μV/°C
μV/°C
pA
nA
pA
pA
V
dB
dB
dB
dB
dB
dB
pF
pF
Ω
Ω
±0.4
±0.7
±15
−40°C < TA < +125°C
±2
−40°C < TA < +125°C
Input Voltage Range
Common-Mode Rejection Ratio
IVR
CMRR
Large Signal Voltage Gain
AVO
Input Capacitance
Input Resistance
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Output Current
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current per Amplifier
CDM
CCM
RDM
RCM
VOH
VOL
IOUT
ISC
ZOUT
PSRR
ISY
VCM = 0 V to 1.5 V
−40°C < TA < +125°C
RL = 2 kΩ to V−, VOUT = 0.35 V to 4.65 V
−40°C < TA < +125°C
RL = 600 Ω to V−, VOUT = 0.5 V to 4.5 V
−40°C < TA < +125°C
Differential mode
Common mode
Differential mode
Common mode, VCM from 0 V to 1.5 V
RL = 2 kΩ to V−
−40°C < TA < +125°C
RL = 600 Ω to V−
−40°C < TA < +125°C
RL = 2 kΩ to V+
−40°C < TA < +125°C
RL = 600 Ω to V+
−40°C < TA < +125°C
VDROPOUT < 1 V
−0.2
74
70
130
120
120
110
Rev. 0 | Page 5 of 30
145
130
12.1
16.3
1012
1012
4.75
4.7
4.65
4.55
4.82
4.74
0.17
0.25
0.22
0.3
0.3
0.45
±33
±46
2
18
29
f = 1 MHz, AV = +1
AV = +10
AV = +100
VSY = 4.5 V to 10 V
−40°C < TA < +125°C
VOUT = 0 V
−40°C < TA < +125°C
90
80
75
97
3.9
4.3
4.8
V
V
V
V
V
V
V
V
mA
mA
Ω
Ω
Ω
dB
dB
mA
mA
ADA4625-1
Parameter
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Unity-Gain Crossover
−3 dB Bandwidth
Phase Margin
Settling Time
EMI REJECTION RATIO
f = 1000 MHz
f = 2400 MHz
NOISE PERFORMANCE
Peak-to-Peak Noise
Voltage Noise Density
Current Noise Density
Total Harmonic Distortion + Noise
Data Sheet
Symbol
Test Conditions/Comments
SR
VOUT = 0.5 V to 4.5 V, RL = 2 kΩ, AV = −1
VOUT = 0.5 V to 4.5 V, RL = 2 kΩ, AV = −5
AV = 100
AV = 1
AV = 1
GBP
UGC
−3 dB
ΦM
tS
To 0.1%, VIN = 4 V step, RL = 2 kΩ, CL = 15 pF, AV = −1
To 0.01%, VIN = 4 V step, RL = 2 kΩ, CL = 15 pF,
AV = −1
Min
Typ
Max
Unit
32
27
16
11.2
16
86
600
950
V/μs
V/μs
MHz
MHz
MHz
Degrees
ns
ns
56
87
dB
dB
0.15
5.5
3.6
3.3
4.5
μV p-p
nV/√Hz
nV/√Hz
nV/√Hz
fA/√Hz
0.0003
−109
0.0007
−103
%
dB
%
dB
EMIRR
eN p-p
eN
iN
THD + N
0.1 Hz to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 1 kHz
AV = 1, f = 10 Hz to 20 kHz, RL = 2 kΩ,
VIN = 0.6 VRMS at 1 kHz
Bandwidth = 80 kHz
Bandwidth = 500 kHz
Rev. 0 | Page 6 of 30
Data Sheet
ADA4625-1
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
Parameter
Supply Voltage
Input Voltage
Differential Input Voltage
1
Input Current
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature, Soldering (10 sec)
Electrostatic Discharge (ESD)
Human Body Model (HBM)2
Field Induced Charge Device Model (FICDM)3
Rating
40 V
(V−) − 0.2 V to
(V+ ) + 0.2 V
(V−) − 0.2 V to
(V+) + 0.2 V
±20 mA
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
1.25 kV
1.25 kV
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Close attention to PCB
thermal design is required.
Table 5. Thermal Resistance
Package Type1, 2
RD-8-1
1
θJA3
52.8
θJC
5.7
Unit
°C/W
Values were obtained per JEDEC standard JESD-51.
Although the exposed pad can be left floating, it must be connected to the
GND, or the V+ or V− plane for proper thermal management.
3
Board layout impacts thermal characteristics such as θJA. When proper thermal
management techniques are used, a better θJA can be achieved. Refer to the
Thermal Management section for additional information.
2
ESD CAUTION
1
The input pins have clamp diodes connected to the power supply pins. Limit
the input current to 20 mA or less whenever input signals exceed the power
supply rail by 0.3 V.
2
ESDA/JEDEC JS-001-2011 applicable standard.
3
JESD22-C101 (ESD FICDM standard of JEDEC) applicable standard.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 7 of 30
ADA4625-1
Data Sheet
NC 1
ADA4625-1
–IN 2
+IN 3
V– 4
TOP VIEW
(Not to Scale)
8
NC
7
V+
6
OUT
5
NC
NOTES
1. NC = NO CONNECTION. DO NOT CONNECT TO THIS PIN.
2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO GND,
V+ OR V– PLANE, OR LEAVE IT FLOATING.
15893-002
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1, 5, 8
2
3
4
6
7
Mnemonic
NC
−IN
+IN
V−
OUT
V+
EPAD
Description
No Connect. Do not connect to these pins.
Inverting Input.
Noninverting Input.
Negative Supply Voltage.
Output.
Positive Supply Voltage.
Exposed Pad. Connect the exposed pad to GND, V+ or V− plane, or leave it floating.
Rev. 0 | Page 8 of 30
Data Sheet
ADA4625-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VCM = 0 V, unless otherwise noted.
25
VSY = ±18V
RL = ∞
20
NUMBER OF AMPLIFIERS
30
20
15
10
10
–75
–50
–25
0
25
50
75
100
VOS (µV)
0
–400
15893-003
0
–100
–300
45
VSY = ±18V
40
100
200
300
400
40
30
20
1.5
2.0
VSY = 5V
VCM = 1.5V
35
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
50
30
25
20
15
10
10
5
–1.5
–1.0
–0.5
0.0
0.5
1.0
1.5
2.0
TCVOS (µV/°C)
0
–2.0
15893-004
0
–2.0
–1.5
–1.0
–0.5
0.0
0.5
1.0
TCVOS (µV/°C)
Figure 5. TCVOS Distribution (−40°C to +125°C ), VSY = ±18 V
Figure 8. TCVOS Distribution (−40°C to +125°C ), VSY = 5 V
1000
VSY = ±18V
90 AMPLIFIERS
800
400
VSY = 5V
90 AMPLIFIERS
600
400
VOS (µV)
200
0
–200
200
0
–200
–400
–600
–400
–800
–600
–18.2
–13.2
–8.2
–3.2
1.8
6.8
11.8
16.8
VCM (V)
15893-005
VOS (µV)
0
Figure 7. VOS Distribution, VSY = 5 V
60
600
–100
VOS (µV)
Figure 4. Input Offset Voltage (VOS) Distribution, Supply Voltage (VSY) = ±18 V
70
–200
15893-006
5
–1000
–0.2
0.2
0.6
1.0
1.4
1.8
2.2
VCM (V)
Figure 9. VOS vs. VCM, VSY = 5 V
Figure 6. VOS vs. Common-Mode Voltage (VCM), VSY = ±18 V
Rev. 0 | Page 9 of 30
2.6
3.0
3.4
15893-008
NUMBER OF AMPLIFIERS
40
VSY = 5V
VCM = 1.5V
RL = ∞
15893-007
50
ADA4625-1
Data Sheet
25
200
VSY = 5V, VCM = 1.5V
VSY = ±18V
20
0
15
–200
–400
5
IB (pA)
0
–5
–600
–800
–1000
–10
–1200
–1400
–20
–25
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
–1600
–40
15893-009
–25
–40
VSY = 5V, VCM = 1.5V
VSY = ±18V
–25
–10
100
NUMBER OF AMPLIFIERS
65
80
95
110
125
40
VSY = 5V
VCM = 1.5V
RL = ∞
80
60
40
20
–50
–40
–30
–20
–10
0
10
IB (pA)
0
–60
15893-010
0
–60
–50
–40
–30
–20
–10
0
10
30
40
IB (pA)
15893-013
NUMBER OF AMPLIFIERS
60
20
Figure 14. IB Distribution, VSY = 5 V
Figure 11. Input Bias Current (IB) Distribution, VSY = ±18 V
90
VSY = ±18V
RL = ∞
80
NUMBER OF AMPLIFIERS
70
60
50
40
30
60
50
40
30
20
10
10
0
–40
–30
–20
–10
0
10
20
30
40
IOS (pA)
VSY = 5V
VCM = 1.5V
RL = ∞
70
20
15893-011
NUMBER OF AMPLIFIERS
50
120
VSY = ±18V
RL = ∞
80
80
35
Figure 13. IB vs. Temperature
100
90
20
TEMPERATURE (°C)
Figure 10. VOS vs. Temperature
120
5
15893-012
–15
0
–40
–30
–20
–10
0
10
20
IOS (pA)
Figure 15. IOS Distribution, VSY = 5 V
Figure 12. Input Offset Current (IOS) Distribution, VSY = ±18 V
Rev. 0 | Page 10 of 30
15893-014
VOS (µV)
10
Data Sheet
100
ADA4625-1
300
VSY = ±18V
VSY = 5V
250
80
200
60
150
40
100
IB (pA)
IB (pA)
20
0
–20
50
0
–50
–100
–40
–150
–60
–200
–80
–2.2
1.8
5.8
9.8
13.8
17.8
VCM (V)
–300
–0.2
15893-015
–6.2
0.3
0.8
1.3
1.8
2.3
2.8
3.3
15893-018
–250
–100
–18.2 –14.2 –10.2
3.8
VCM (V)
Figure 16. IB vs. VCM, VSY = ±18 V
Figure 19. IB vs. VCM, VSY = 5 V
10n
10n
TA = 125°C
ABSOLUTE VALUE OF IB (A)
TA = 85°C
100p
10p
1n
TA = 85°C
100p
10p
TA = 25°C
–2.2
1.8
5.8
9.8
13.8
17.8
VCM (V)
Figure 17. Absolute Value of IB vs. VCM for Various Temperatures, VSY = ±18 V
VCM (V)
Figure 20. Absolute Value of IB vs. VCM for Various Temperature, VSY = 5 V
10
VSY = ±18V
(V+) – VOUT (V)
10
1
0.1
0.001
VSY = 5V
VCM = 1.5V
1
+125°C
+85°C
+25°C
–40°C
0.01
0.1
1
IOUT SOURCE (mA)
TA = +125°C
TA = +85°C
TA = +25°C
TA = –40°C
10
100
0.1
0.001
15893-017
(V+) – VOUT (V)
100
1p
–0.2 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0
15893-019
–6.2
15893-016
1p
–18.2 –14.2 –10.2
TA = 25°C
Figure 18. Dropout Voltage ((V+) − VOUT) vs. Output Current (IOUT) Source
for Various Temperatures, VSY = ±18 V
0.01
0.1
1
IOUT SOURCE (mA)
10
100
15893-020
ABSOLUTE VALUE OF IB (A)
TA = 125°C
1n
Figure 21. ((V+) − VOUT) vs. IOUT Source for Various Temperatures, VSY = 5 V
Rev. 0 | Page 11 of 30
ADA4625-1
10
VSY = ±18V
VOUT – (V–) (V)
TA = +125°C
TA = +85°C
TA = +25°C
TA = –40°C
0.1
1
100
10
IOUT SINK (mA)
0.1
0.001
80
180
80
60
135
40
90
20
45
–40
100
1k
GAIN (dB)
PHASE (Degrees)
100
0
–45
10k
100k
1M
–90
100M
10M
FREQUENCY (Hz)
180
60
135
40
90
20
45
0
0
–45
1k
10k
100k
1M
–90
100M
10M
FREQUENCY (Hz)
60
VSY = ±18V
VSY = 5V
50
AV = 100
40
AV = 100
40
30
30
GAIN (dB)
GAIN (dB)
225
Figure 26. Open-Loop Gain and Phase vs. Frequency, VSY = 5 V
50
AV = 10
20
10
AV = 10
20
10
AV = 1
0
AV = 1
0
–10
–10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100M
–20
10
15893-023
–20
10
270
VSY = 5V
RL = 1kΩ
CL = 300pF
CL = 100pF
CL = 0pF
–40
100
Figure 23. Open-Loop Gain and Phase vs. Frequency, VSY = ±18 V
60
100
–20
15893-022
GAIN (dB)
225
–20
10
120
100
VSY = ±18V
RL = 1kΩ
CL = 300pF
CL = 100pF
CL = 0pF
1
Figure 25. (VOUT − (V−)) vs. IOUT Sink for Various Temperatures, VSY = 5 V
270
0
0.1
IOUT SINK (mA)
Figure 22. Dropout Voltage (VOUT − (V−)) vs. IOUT Sink for Various
Temperatures, VSY = ±18 V
120
0.01
15893-024
0.01
PHASE (Degrees)
0.1
0.001
TA = +125°C
TA = +85°C
TA = +25°C
TA = –40°C
15893-025
1
1
15893-021
VOUT – (V–) (V)
10
VSY = 5V
VCM = 1.5V
Figure 24. Gain vs. Frequency for Various Closed-Loop Gains, VSY = ±18 V
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 27. Gain vs. Frequency for Various Closed-Loop Gains, VSY = 5 V
Rev. 0 | Page 12 of 30
15893-026
100
Data Sheet
Data Sheet
1000
VSY = ±18V
100
OUTPUT IMPEDANCE (Ω)
10
AV = 100
AV = 10
AV = 1
1
0.1
10
AV = 100
1
0.1
0.01
0.01
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
0.001
100
15893-027
0.001
100
1k
100
100k
1M
10M
100M
Figure 31. ZOUT vs. Frequency, VSY = 5 V
100
VSY = ±18V
–PSRR
+PSRR
80
10k
FREQUENCY (Hz)
Figure 28. Output Impedance (ZOUT) vs. Frequency, VSY = ±18 V
VSY = 5V
VCM = 1.5V
–PSRR
+PSRR
80
60
PSRR (dB)
60
40
40
20
20
0
0
–20
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
–20
10
15893-028
PSRR (dB)
AV = 1
AV = 10
15893-030
OUTPUT IMPEDANCE (Ω)
100
VSY = 5V
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 29. Power Supply Rejection Ration (PSRR) vs. Frequency, VSY = ±18 V
15893-031
1000
ADA4625-1
Figure 32. PSRR vs. Frequency, VSY = 5 V
140
140
VSY = 5V
VSY = ±18V
130
120
120
PSRR (dB)
80
60
110
100
90
80
40
20
10M
100M
1G
FREQUENCY (Hz)
10G
Figure 30. EMI Rejection Ratio (EMIRR) vs. Frequency
60
–40
VSY = ±5V TO ±18V
VSY = +4.5V TO +10V
–25
–10
5
20
35
50
65
80
TEMPERATURE (°C)
Figure 33. PSRR vs.Temperature
Rev. 0 | Page 13 of 30
95
110
125
15893-032
70
15893-029
EMIRR (dB)
100
ADA4625-1
Data Sheet
120
140
VSY = 5V
VSY = ±18V
110
130
100
90
120
CMRR (dB)
70
60
50
40
110
100
90
80
20
VSY = ±18V, VCM = –18.2V TO +14.5V
VSY = ±18V, VCM = –18.2V TO +12.0V
VSY = 5V, VCM = 0V TO 1.5V
70
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
60
–40
15893-033
0
10
–25
–10
65
80
95
110
125
VSY = 5V
VCM = 1.5V
RL = 2kΩ
VIN = 100mV p-p
35
35
30
OS+
OS–
30
AV = +1
OVERSHOOT (%)
25
20
15
10
AV = +1
OS+
OS–
25
20
AV = –1
15
10
AV = –1
5
5
10
100
1k
LOAD CAPACITANCE (pF)
0
15893-034
1
1
100
1k
Figure 38. OS± vs. Load Capacitance, VSY = 5 V
Figure 35. Small Signal Overshoot (OS±) vs. Load Capacitance, VSY = ±18 V
4
20
VSY = ±18V
RL = 2kΩ
CL = 100pF
15
10
LOAD CAPACITANCE (pF)
VSY = 5V
RL = 2kΩ
CL = 100pF
3
OUTPUT VOLTAGE (V)
10
5
0
–5
–10
15893-037
OVERSHOOT (%)
50
40
VSY = ±18V
RL = 2kΩ
VIN = 100mV p-p
40
2
1
0
–1
–15
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
TIME (µs)
15893-035
VOLTAGE (V)
35
Figure 37. CMRR vs.Temperature
45
–20
20
TEMPERATURE (°C)
Figure 34. Common-Mode Rejection Ratio (CMRR) vs. Frequency
0
5
15893-036
30
Figure 36. Large Signal Transient Response, AV = +1, VSY = ±18 V
–2
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
TIME (µs)
Figure 39. Large Signal Transient Response, AV = +1, VSY = 5 V
Rev. 0 | Page 14 of 30
15893-038
CMRR (dB)
80
Data Sheet
ADA4625-1
20
5
VSY = ±18V
RL = 2kΩ
CL = 100pF
15
OUTPUT VOLTAGE (V)
5
0
–5
–10
1.0
1.5
2.0
2.5
3.0
3.5
–1
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Figure 43. Large Signal Transient Response, AV = -1, VSY = 5 V
0.10
1.60
VSY = ±18V
RL = 2kΩ
CL = 100pF
VIN = 0.1V p-p
VSY = 5V
VCM = 1.5V
RL = 2kΩ
CL = 100pF
VIN = 0.1V p-p
1.55
VOLTAGE (V)
0.05
0
–0.05
1.50
1.45
0.5
1.0
1.5
2.0
2.5
3.0
3.5
TIME (µs)
1.40
15893-040
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
TIME (µs)
Figure 41. Small Signal Transient Response, AV = 1, VSY = ±18 V
15893-043
VOLTAGE (V)
0
TIME (µs)
Figure 40. Large Signal Transient Response, AV = −1, VSY = ±18 V
Figure 44. Small Signal Transient Response, AV = 1, VSY = 5 V
0.10
1.60
VSY = ±18V
RL = 2kΩ
CL = 100pF
VIN = 0.1V p-p
VSY = 5V
VCM = 1.5V
RL = 2kΩ
CL = 100pF
VIN = 0.1V p-p
1.55
VOLTAGE (V)
0.05
0
–0.05
1.50
1.45
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
TIME (µs)
15893-041
VOLTAGE (V)
1
15893-042
0.5
15893-039
0
TIME (µs)
–0.10
2
0
–15
–0.10
3
Figure 42. Small Signal Transient Response, AV = −1, VSY = ±18 V
1.40
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
TIME (µs)
Figure 45. Small Signal Transient Response, AV = −1, VSY = 5 V
Rev. 0 | Page 15 of 30
15893-044
VOLTAGE (V)
10
–20
VSY = 5V
VCM = 1.5V
RL = 2kΩ
CL = 100pF
4
1.0
2.5
5
15
0.5
2.0
0
10
0
1.5
–5
5
–10
0
VIN
VOUT
–10
0.5
–1.5
0
–2.0
–0.5
–25
–15
–2.5
–1.0
–30
–20
–3.0
–1.5
TIME (200ns/DIV)
TIME (200ns/DIV)
0.5
14
0
30
0
12
25
–0.5
10
–10
20
VIN
VOUT
–15
15
INPUT VOLTAGE (V)
VSY = ±18V
VIN = 5.4V p-p
OUTPUT VOLTAGE (V)
35
VIN
VOUT
–1.0
(V+) = 3.5V, (V–) = –1.5V
VCM = 0V
VIN = 0.75V p-p
8
–1.5
6
–2.0
4
–2.5
2
10
–25
5
–30
0
–3.0
0
–35
–5
–3.5
–2
15893-046
–20
TIME (200ns/DIV)
TIME (200ns/DIV)
Figure 47. Positive Overload Recovery, AV = −10, VSY = ±18 V
Figure 50. Positive Overload Recovery, AV = −10, VSY = 5 V
10
5
VSY = ±18V
RL = 2kΩ
CL = 100pF
DUT AV = –1
INPUT
1
–5
–10
OUTPUT
–25
–30
TIME (400ns/DIV)
+100mV
–3
–5
0V
–7
–100mV
–9
15893-047
–20
ERROR BAND
POST GAIN = 20
–1
ERROR BAND
POST GAIN = 20
OUTPUT
TIME (400ns/DIV)
Figure 51. Negative Setting Time to 0.1%, VSY = 5 V
Rev. 0 | Page 16 of 30
0
–40mV
–11
Figure 48. Negative Setting Time to 0.1%, VSY = ±18 V
+40mV
15893-050
INPUT
0
VSY = 5V
VCM = 1.5V
RL = 2kΩ
CL = 100pF
DUT AV = –1
3
INPUT VOLTAGE (V)
5
–15
OUTPUT VOLTAGE (V)
Figure 49. Negative Overload Recovery, AV = −10, VSY = 5 V
5
–5
INPUT VOLTAGE (V)
1.0
–1.0
Figure 46. Negative Overload Recovery, AV = −10, VSY = ±18 V
INPUT VOLTAGE (V)
(V+) = 3.5V, (V–) = –1.5V
VCM = 0V
VIN = 0.75V p-p
15893-049
–20
–5
INPUT VOLTAGE (V)
VSY = ±18V
VIN = 5.4V p-p
–15
VIN
VOUT
–0.5
15893-048
20
OUTPUT VOLTAGE (V)
10
OUTPUT VOLTAGE (V)
Data Sheet
15893-045
INPUT VOLTAGE (V)
ADA4625-1
Data Sheet
ADA4625-1
10
1
–5
–10
ERROR BAND
POST GAIN = 20
–15
+10mV
OUTPUT
–20
INPUT
–1
–3
–5
0V
ERROR BAND
POST GAIN = 20
OUTPUT
+4mV
0
–4mV
–7
–10mV
–25
–30
TIME (400ns/DIV)
–11
TIME (400ns/DIV)
Figure 52. Negative Setting Time to 0.01%, VSY = ±18 V
Figure 55. Negative Setting Time to 0.01%, VSY = 5 V
10
5
5
–5
–10
–15
OUTPUT
+100mV
0V
TIME (400ns/DIV)
–3
0
–40mV
TIME (400ns/DIV)
5
INPUT
3
VSY = ±18V
RL = 2kΩ
CL = 100pF
DUT AV = –1
–5
–10
OUTPUT
ERROR BAND
POST GAIN = 20
+10mV
–20
INPUT
VSY = 5V
VCM = 1.5V
RL = 2kΩ
CL = 100pF
DUT AV = –1
1
INPUT VOLTAGE (V)
0
–1
–3
–5
0V
–10mV
ERROR BAND
POST GAIN = 20
OUTPUT
+4mV
0
–4mV
–7
–25
–9
–30
TIME (400ns/DIV)
15893-053
INPUT VOLTAGE (V)
+40mV
Figure 56. Positive Settling Time 0.1%, VSY = 5 V
10
–15
OUTPUT
–11
Figure 53. Positive Settling Time 0.1%, VSY = ±18 V
5
ERROR BAND
POST GAIN = 20
–5
–9
15893-052
–30
–1
–7
–100mV
–25
VSY = 5V
VCM = 1.5V
RL = 2kΩ
CL = 100pF
DUT AV = –1
15893-055
ERROR BAND
POST GAIN = 20
INPUT
1
INPUT VOLTAGE (V)
0
INPUT VOLTAGE (V)
3
VSY = ±18V
RL = 2kΩ
CL = 100pF
DUT AV = –1
INPUT
–20
15893-054
15893-051
–9
–11
Figure 54. Positive Settling Time 0.01%, VSY = ±18 V
TIME (400ns/DIV)
Figure 57. Positive Settling Time 0.01%, VSY = 5 V
Rev. 0 | Page 17 of 30
15893-056
INPUT VOLTAGE (V)
0
VSY = 5V
VCM = 1.5V
RL = 2kΩ
CL = 100pF
DUT AV = –1
3
INPUT VOLTAGE (V)
5
5
VSY = ±18V
RL = 2kΩ
CL = 100pF
DUT AV = –1
INPUT
ADA4625-1
Data Sheet
VSY = 5V
VSY = ±18V
VSY = 5V
VSY = ±18V
1
10
100
1k
10k
100k
FREQUENCY (Hz)
TIME (1s/DIV)
Figure 61. 0.1 Hz to 10 Hz Noise
Figure 58. Voltage Noise Density vs. Frequency
10
10
BW
BW
BW
BW
THD + N (%)
0.1
0.01
0.001
0.01
0.1
1
10
AMPLITUDE (V rms)
= 80kHz, AV = +1
= 80kHz, AV = –1
= 500kHz, AV = +1
= 500kHz, AV = –1
0.1
0.01
0.001
VSY = ±18V
RL = 2kΩ
FREQUENCY = 1kHz
0.0001
0.001
BW
BW
BW
BW
1
VSY = 5V
RL = 2kΩ
FREQUENCY = 1kHz
0.0001
0.001
15893-058
0.01
0.1
1
AMPLITUDE (V rms)
Figure 62. THD + N vs. Amplitude, VSY = 5 V
(BW Means Bandwidth)
Figure 59. Total Harmonic Distortion + Noise (THD + N) vs. Amplitude,
VSY = ±18 V (BW Means Bandwidth)
0.1
0.1
BW
BW
BW
BW
VSY = ±18V
RL = 2kΩ
VIN = 6V rms
= 80kHz, AV = +1
= 80kHz, AV = –1
= 500kHz, AV = +1
= 500kHz, AV = –1
BW
BW
BW
BW
VSY = 5V
RL = 2kΩ
VIN = 0.6V rms
= 80kHz, AV = +1
= 80kHz, AV = –1
= 500kHz, AV = +1
= 500kHz, AV = –1
0.01
THD + N (%)
THD + N (%)
0.01
0.001
0.0001
20
200
2k
FREQUENCY (Hz)
20k
15893-059
0.001
0.0001
20
200
2k
FREQUENCY (Hz)
Figure 63. THD + N vs. Frequency, VSY = 5 V
(BW Means Bandwidth)
Figure 60. THD + N vs. Frequency, VSY = ±18 V
(BW Means Bandwidth)
Rev. 0 | Page 18 of 30
20k
15893-062
THD + N (%)
1
= 80kHz, AV = +1
= 80kHz, AV = –1
= 500kHz, AV = +1
= 500kHz, AV = –1
15893-061
1
15893-057
10
15893-060
50nV/DIV
VOLTAGE NOISE DENSITY (nV/√Hz)
100
Data Sheet
5.0
ADA4625-1
400
TA = +125°C
4.5
TA = +85°C
4.0
TA = +25°C
3.5
200
TA = –40°C
100
3.0
VOS (µV)
ISY (mA)
5 AMPLIFIERS
TA = 25°C
300
2.5
2.0
0
–100
1.5
–200
VCM = VSY/2
VCM = VSY/2
–300
0.5
0
4
8
12
16
20
24
28
32
36
VSY (V)
–400
15893-063
0
VSY = ±18V
VSY = ±2.5V
OUTPUT VOLTAGE (V p-p)
30
MAXIMUM
OUTPUT
VOLTAGE
WITHOUT SID
20
15
10
100k
FREQUENCY (Hz)
1M
10M
15893-064
5
0
10k
12
16
20
24
Figure 66. VOS vs. VSY
40
25
8
VSY (V)
Figure 64. Supply Current (ISY) vs. VSY for Various Temperatures
35
4
Figure 65. Maximum Peak-to-Peak Output Voltage Without Slew Rate
Induced Distortion (SID) vs. Frequency
Rev. 0 | Page 19 of 30
28
32
36
15893-065
1.0
ADA4625-1
Data Sheet
THEORY OF OPERATION
of +IN and –IN steer ITAIL through M1 and M2 to R1 and R2,
generating a differential voltage. The first voltage to current gain
block (GM1) translates that differential voltage into differential
currents (I1 and I2) that drive the current mirror (Q1 and Q2),
which generates a differential voltage between the reference
node and gain node. JFET inputs of the second voltage to
current gain block (GM2) maximizes the gain node impedance,
giving the ADA4625-1 a high gain.
Figure 67 shows the simplified circuit diagram for the
ADA4625-1. The JFET input stage architecture offers the
advantages of low input bias current, high bandwidth, high
gain, low noise, and no phase reversal when the applied input
signal exceeds the common-mode voltage range. The output
stage is rail to rail with high drive characteristics and low
dropout voltage for both sinking and sourcing currents.
INPUT AND GAIN STAGES
OUTPUT STAGE
To achieve high input impedance, low noise, low offset, and low
offset drift, the ADA4625-1 uses large input N channel JFETs
(M1 and M2). These JFETs operate with the S source at about
1.2 V above the G gate. In the worst case, the source is only 0.9 V
above the gate. By design, the normal operation of the input tail
current (ITAIL) extends down to 0.6 V above V−, which gives the
ADA4625-1 an input common-mode range down to 0.2 V below
V− with margin. Resistive loads keep the noise low. The BUFF1
buffer drives the top of the input load resistors (R1 and R2),
keeping the voltage drop across M1 and M2 nearly constant,
making a virtual cascode. The differences of the input voltages
The GM2 gain block generates two pairs of differential currents.
One pair drives the bottom current mirror (Q3 and Q4) and the
NPN output transistor (Q7), and the second pair drives the top
current mirror (Q5 and Q6) and the output PNP transistor (Q8).
The common emitter output transistors (Q7 and Q8) source and
sink current rail to rail. GM2 also senses the base voltages of Q7
and Q8 and adjusts the I4 and I6 currents; with no output load,
Q7 and Q8 collector currents are 0.6 mA. In addition, GM2
clamps the base voltages of Q7 and Q8 so neither completely
turns off.
V+
BUFF1
G
+IN
INPUT LOAD
RESISTORS
AND V OS TRIM
R1
ITC1
5V
LEVEL SHIFT
TCVOS
TRIM
ITC2
BIAS
D
D
M4
S
Q10
G
D
M1
S
Q6
–IN
OUTPUT
PNP
Q8
R2
I5
DIFFERENTIAL
VOLTAGE
GM1
V/I GAIN
JFET
D
INPUT PAIR M2 G
S
I6
DIFFERENTIAL
CURRENTS
I1
–IN
Q5
G
M3
S
Q9
I2
CCOMP1
OUT
GAIN NODE
REF NODE
CCOMP2
GM2
V/I GAIN AND
OUTPUT
BIAS
OUTPUT
I4
NPN
Q7
I3
+IN
ITAIL
Q2
Q3
Q4
15893-066
V–
Q1
INPUT
TAIL CURRENT
Figure 67. Simplified Circuit Diagram
Rev. 0 | Page 20 of 30
Data Sheet
ADA4625-1
NO PHASE INVERSION
SUPPLY CURRENT
Rail-to-rail output (RRO) amplifiers without rail-to-rail input
(RRI) are prone to phase inversion because the output can drive
the input outside of the normal common-mode range, causing
the output to go in the wrong direction and latch up. To prevent
phase inversion control the input at all times. Even though the
RRO of the ADA4625-1 input stage (M1, M2, R1, and R2)
operates correctly down to 0.2 V below V−, it does not operate
correctly within 2.5 V of V+. The ADA4625-1 guarantees no
phase inversion by implementing an input pair (M3 and M4)
to extend the common-mode range to 0.2 V above V+, with
reduced performance. M3 and M4 are not active in the normal
common-mode range. Figure 68 shows that the input voltage
exceeds both supplies by 200 mV with no phase inversion at the
output.
The supply current (ISY) is the quiescent current drawn by the
op amp with no load. Figure 69 and Figure 70 show that the
quiescent current varies with the common-mode input voltage.
The shape of ISY vs. VCM at higher VCM shows saturation of
BUFF1 and the turn off of ITAIL.
4.5
TA = +85°C
TA = +25°C
ISY (mA)
4.0
TA = –40°C
3.5
3.0
VSY = ±18V
VIN = 36.4V p-p
AV = 1
2.5
2.0
–18.2
10
–12.2
5
–6.2
–0.2
VCM (V)
5.8
11.8
17.8
15893-068
15
TA = +125°C
4.3
5.2
15893-069
20
Figure 69. ISY vs VCM, VSY = ±18 V
0
5.0
–5
–10
4.5
VOUT
TA = +125°C
TA = +85°C
–15
–25
VIN
TIME (200µs/DIV)
Figure 68. No Phase Reversal If the Input Range Exceeds the Power Supply
by 200 mV
ISY (mA)
–20
15893-067
INPUT VOLTAGE AND OUTPUT VOLTAGE (V)
25
5.0
4.0
TA = +25°C
3.5
TA = –40°C
3.0
2.5
2.0
–0.2
0.7
1.6
2.5
VCM (V)
3.4
Figure 70. ISY vs VCM, VSY = 5 V
Rev. 0 | Page 21 of 30
ADA4625-1
Data Sheet
APPLICATIONS INFORMATION
ACTIVE LOOP FILTER FOR PHASE-LOCKED LOOPS
(PLLS)
PLL Basic
A PLL is a feedback system that combines a phase detector
(PD), a loop filter, and a voltage controlled oscillator (VCO)
that is so connected that the oscillator maintains a constant
frequency (or phase angle) relative to the reference signal. The
functional block diagram of a basic PLL is shown in Figure 71.
PHASE
DETECTOR
CHARGE
PUMP
LOOP
FILTER
VCO
fOUT
The loop filter, which smooths out the error signal, is a critical
part of the system. For applications that require low phase noise
and a wide tuning range, design the VCO with a low gain and a
large input voltage range to satisfy these requirements. When the
required VCO tuning voltage is higher than the maximum
voltage the charge pump can supply, implement an active loop
filter comprising of an op amp with gain to accommodate the
higher tuning voltages. Figure 73 and Figure 74 illustrate the typical
active loop filters in inverting and noninverting topologies,
respectively, with prefiltering.
15893-071
fREF
Loop Filter
N DIVIDER
CHARGE
PUMP
OUTPUT
Figure 72 shows the block diagram of the basic PLL model in
the Laplace transform format, where fREF is the frequency of the
input signal, and fOUT is the frequency of the VCO output signal.
Because the phase difference is the integral of the frequency
difference, there is a 1/s term in the PLL loop.
fREF
+
PD
–
1
s
CHARGE
PUMP
LOOP
FILTER
Kd
Z(s)
Figure 73. Typical Active Loop Filter—Inverting Topology
CHARGE
PUMP
OUTPUT
The inverting topology has the advantage of biasing the charge
pump output at a fixed voltage, typically one-half the charge
pump voltage (VP/2), which is optimal for spur performance.
When using the inverting topology, ensure that the PLL IC
allows the phase detector polarity to be inverted for the correct
polarity voltage at the output of the op amp for driving the VCO.
VCO
KV
fOUT
N DIVIDER
1
N
VCO
INPUT
Figure 74. Typical Active Loop Filter—Noninverting Topology
15893-072
PHASE
DETECTOR
VCO
INPUT
15893-074
The phase detector detects the phase difference between the
input reference signal and the feedback signal. The resulting
error signal is proportional to the relative phase of the input
and the feedback signals. The charge pump converts the PD
error signal into current pulses. A loop filter circuit is typically
required to integrate and smooth the source and sink current
pulses from the charge pump into a voltage, which in turn,
drives the VCO. The VCO outputs a range of frequencies
depending on the voltage level at its tuning port. By making
the frequency N divider programmable, the VCO frequency
can be tuned in either integer steps or fractional amounts
characterizing the PLL as either an integer-N PLL or a
fractional-N PLL. Because a PLL is a negative feedback loop,
the output of the VCO adjusts as necessary until the frequency
error signal is zero and the PLL is in lock. The output frequency
is given by fOUT = N × fREF.
15893-073
Figure 71. Basic PLL
Figure 72. Basic PLL Model
Rev. 0 | Page 22 of 30
Data Sheet
ADA4625-1
configuration. The VCO is set up to feedback the VCO/2 output
to the ADF4159. The loop filter has a 900 kHz loop bandwidth
(LBW) and a phase margin of 58° with 2.5 mA charge pump
current. Lowering the bandwidth further improves phase noise
at the expense of increased PLL lock time.
ADA4625-1 ADVANTAGES AND DESIGN EXAMPLE
The op amp choice for an active filter affects the key performance
parameters of the PLLs: frequency range, phase noise, spurious
frequencies, and lock time. The output of the filter directly
affects the generated frequency and phase. Low noise is
essential because any voltage noise applied to the tuning port
of the VCO is amplified by the VCO gain and translated into
phase noise. Low input bias current is also recommended
because the op amp bias current must be sourced from the PLL
phase detector/ charge pump, and any mismatch or leakage at
the output of the phase detector between the up and down
currents causes ripples and reference spurs.
Figure 75 shows the PLL loop filter transfer function. Capacitor C1
and Resistor R1 change the phase detector current pulses into a
continuous time voltage waveform. At frequencies lower than
the R2C2 zero, the amplifier and R1C2 form an integrator.
Between the R2C2 zero and the R2C3 pole, the gain is constant
at the value set by R2/R1. Above the R2C3 pole, the amplifier is
an integrator until R1C3 becomes a feedforward noninverting
zero path around the amplifier. Resistor R3 and Capacitor C4
add an additional pole in the loop filter signal path. Setting the
R3C4 pole below the R2C3 pole reduces the effect of the R1C3
feedforward zero.
R3C4 POLE
R2C2 ZERO
GAIN (dB)
With 18 MHz gain bandwidth product (GBP), low input bias
currents (±15 pA), low voltage noise density (3.3 nV/√Hz),
ultralow current noise density, and low 1/f corner frequency,
the ADA4625-1 is an ideal op amp for using in a PLL active
loop filter. The ADA4625-1 does not require a negative voltage
supply because of its ground sensing input. The rail-to-rail
output stage is beneficial in terms of increasing the flexibility
in biasing the op amp so that the output range of the PLL is
mapped efficiently onto the input range of the VCO. In
addition, the wide 5 V to 36 V operating supply range makes
the ADA4625-1 a versatile choice for the design of a wide
variety of active loop filters.
R2C3 POLE
R2/R1
AMP GAIN
R1C1 POLE
LOG FREQUENCY
Figure 76 shows the ADA4625-1 as the loop filter for the
ADF4159, a 13 GHz fractional-N synthesizer. The phase
detector polarity of the ADF4159 is programmed to negative
because the ADA4625-1 is used in an inverting active loop filter
Figure 75. PLL Loop Filter Transfer Function
C3
3.3V
1.8V
3.3V
33pF
R2
AVDD
DVDD
VP
ADF4159
RFINx
FRACTIONAL-N
SYNTHESIZER
15V
R1
100Ω
CP
C1
220pF
REFIN
3.3V
ADA4625-1
U4
47kΩ
AGND DGND CPGND SDGND
47kΩ
100pF
C2
3.3nF
R3
365Ω
C4
100pF
1µF
5V
VCC
6dB PAD
6GHz
11.4GHz TO 12.8GHz
VCO
RFOUT/2
5.7GHz TO 6.4GHz
VTUNE
52pF
RFOUT
11.4GHz TO 12.8GHz
GND
12GHz OUTPUT
Figure 76. Block Diagram of ADA4625-1 Active Loop Filter for ADF4159
Rev. 0 | Page 23 of 30
15893-075
100MHz
1kΩ
15893-076
0dB
ADA4625-1
Data Sheet
PLLs in which the loop gain passes through 0 dB above the R2C2
zero and below the R2C3 pole and R3C4 pole are stable. At low
charge pump currents, the loop gain passes through zero above
R2C2 zero. At high charge pump currents, the loop gain passes
through zero below the R2C3 pole and R3C4 pole (see Figure 77).
TRANSIMPEDANCE AMPLIFIER
The ADA4625-1 is an excellent choice for low noise
transimpedance amplifier (TIA) applications. While its low
voltage and current noise maximize signal-to-noise ratio (SNR),
its low voltage offset and input bias current minimize the dc
error at the amplifier output. Having a true ground sense
capability, the ADA4625-1 is ideal for single-supply operation.
In addition, its rail-to-rail output swing allows the detection
and amplification of a wide range of input current signals.
Figure 79 shows the ADA4625-1 as a current to voltage (I-V)
converter with an electrical model of a photodiode.
0dB FULL LOOP GAIN
HIGH CURRENT
GAIN (dB)
0dB FULL LOOP GAIN
LOW CURRENT
0
CF
RF
LOG FREQUENCY
–
CM
ID
CD
VOUT
CD
RSH = 1011Ω
+
CM
ADA4625-1
VB
Figure 77. Gain vs. Frequency of PLL and Loop Filter
Figure 78 shows the measured phase noise vs. frequency offset
from 12 GHz carrier for different charge pump currents (ICP).
Generally, most operations have a charge pump current of
2.5 mA and below. Refer to the UG-383 User Guide for details
on running these tests and setting up the software required.
–60
ICP = 4.7mA
–80
PHASE NOISE (dBc/Hz)
ICP = 2.5mA
–100
–120
Figure 79. Equivalent TIA Circuit
Photodiodes can operate in either photovoltaic mode (zero
bias) or photoconductive mode (with an applied reverse-bias
across the diode). Mode selection depends on the speed and
dark current requirements of the application and the choice of
photodiode. In photovoltaic mode, the dark current is at a
minimum and is preferred for low frequency and/or low light
level applications (that is, PN photodiodes). Photoconductive
mode is better for applications that required faster and linear
responses (that is, PIN photodiodes); however, the tradeoffs
include increases in dark and noise currents.
The following transfer function describes the transimpedance
gain of Figure 79:
ICP = 0.31mA
–140
VOUT 
–180
10k
100k
1M
10M
FREQUENCY OFFSET FROM 12GHz CARRIER (Hz)
100M
15893-078
–160
1k
15893-081
LOOP FILTER GAIN
15893-077
LOOP WITHOUT FILTER, HIGH CURRENT
LOOP WITHOUT FILTER, LOW CURRENT
LOOP FILTER
FULL LOOP, HIGH CURRENT
FULL LOOP, LOW CURRENT
Figure 78. Phase Noise vs. Frequency Offset from 12 GHz Carrier for Different
Charge Pump Currents (ICP)
The Analog Devices simulation tool, ADIsimPLL, allows the
design and simulation of PLL loop filter topologies and has a
library of Analog Devices op amps built in. The simulation tool
accurately predicts PLL closed-loop phase noise and is able to
model the effect of op amp noise along with the noise of the
other PLL loop components. For more information about the
ADIsimPLL design tools, refer to www.analog.com/ADIsimPLL.
I D RF
1  sC F RF
(1)
where:
VOUT is the desired output dc voltage of the op amp.
ID is the output current of the photodiode.
RF and CF are the feedback resistor and capacitor. The parallel
combination of RF and CF sets the signal bandwidth.
s is the s plane.
Set RF such that the maximum attainable output voltage
corresponds to the maximum diode output current. Because
signal levels increase directly with RF, while the noise due to RF
increases with the square root of the resistor value, employing
the full output swing maximizes the SNR.
Rev. 0 | Page 24 of 30
Data Sheet
ADA4625-1
It is important to distinguish between the signal gain and the
noise gain (NG) because the noise gain characteristics
determine the net circuit stability. The noise gain has the same
transfer function as the noninverting signal gain, which follows:

R
NG  1  F
 RSH
 1  s (RF // RSH )(C IN  C F )


1  sR F C F

(2)
1
CF 
1
2πRF (C IN  C F )
UNCOMPENSATED
(CF = 0pF)
GAIN
OPEN LOOP GAIN
SIGNAL BANDWIDTH
CIN
CF
fGBP
NOISE GAIN
fZ
fp
fP 
fx
fN
FREQUENCY
fN 
The instability caused by CIN can be compensated by adding CF to
introduce a pole at a frequency equal to or lower than fX. The pole
frequency is as follows:
1
2πRF C F
(8)
2RF f GBP
f GBP
2RF C IN
(9)
Because the input current noise of the FET input op amp is
negligible, and the shot noise of the photodiode is negligible
due to the filtering effect of the shunt capacitance, the dominant
sources of output noise in the wideband photodiode TIA circuit
are the input voltage noise of the amplifier eN and the thermal
noise generated by RF.
Figure 80. Generalized TIA Noise Gain and Transfer Function
fP 
C IN
Notice the attainable signal bandwidth is a function of the time
constant RFCIN and the fGBP of the amplifier. To maximize the
signal bandwidth, choose an op amp with high bandwidth and
low input capacitance, and operate the photodiode in reverse
bias to reduce its junction capacitance.
15893-082
R2
R1
(7)
4 RF f GBP
At low frequencies, the circuit noise gain is 1 + RF/RSH. At
frequencies equal to or greater than fZ, the noise gain begins to
increase and plateau when the gain is 1 + CIN/CF (see Figure 80).
In addition, the noise bandwidth frequency, fN (where the
compensated noise gain intersecting the open loop gain), can
be estimated by
COMPENSATED
1+
1  1  8RF C IN f GBP
Adding CF also sets the signal bandwidth at fP. Substitute
Equation 8 into Equation 5 and rearrange the equation for the
signal bandwidth in terms of fGBP, RF, and CIN:
(4)
Figure 80 shows the TIA noise gain superimposed upon the open
loop gain of the amplifier. For the system to be stable, the noise gain
curve must intersect with the open loop response with a net slope
of less than 20 dB/decade. In Figure 80, the dotted line shows an
uncompensated noise gain (CF = 0 pF) intersecting with the open
loop gain at the frequency (fX) with a slope of 20 dB/decade,
indicating an unstable condition.
1+
CF 
(3)
2 (RF // RSH )(C IN  C F )
(6)
If 8π × RF × CIN × fGBP >> 1, Equation 7 simplifies to
Because the photodiode shunt resistance RSH >> RF, the circuit
behavior is not impacted by the effect of the junction resistance,
and fZ simplifies to
fZ 
f X  f Z f GBP
Substituting Equation 4 and Equation 5 into Equation 6, the CF
value that produces fX is
where:
RSH is the diode shunt resistance.
CIN is the total input capacitance consisting of the sum of the
diode shunt capacitance (CD), the input capacitance of the
amplifier (CDM + CCM), and the external stray capacitance.
CIN and RF produce a zero in the noise gain transfer function
and the zero frequency (fZ) is as follows:
fZ 
Setting the pole at the fX frequency maximizes the signal bandwidth
with a 45° phase margin but is marginal for stability, as indicated by
the dashed line. Because fX is the geometric mean of fZ and the
gain bandwidth product frequency (fGBP) of the amplifier,
calculate fX by
(5)
Rev. 0 | Page 25 of 30
CF
fGBP
(CIN  CF )
(10)
ADA4625-1
Data Sheet
1M
100
49.9kΩ
+15V
60
1k
20
100
NOISE GAIN
0
VOUT
10k
OPEN-LOOP
GAIN
40
0.1µF
ADA4625-1
100k
I-V GAIN
–20
1k
10k
1kΩ
I-V GAIN (Ω)
2.2pF
80
GAIN (dB)
As a design example, Figure 81 shows the ADA4625-1 configured
as a TIA amplifier in a photodiode preamp application. Assuming
the photodiode has a CD of 5 pF and an ID of 200 μA, and the
desired full-scale VOUT is 10 V, and using Equation 1, RF is 50 kΩ.
10
100k
1M
10M
100M
1G
1
10G
15893-085
Design Example
15893-083
FREQUENCY (Hz)
Figure 83. Compensating the TIA, CF = 3.9 pF
150
Figure 81. Single-Supply TIA Circuit Using the ADA4625-1
1M
100
100k
80
10k
OPEN-LOOP
GAIN
40
1k
20
100
0
–20
1k
NOISE GAIN
10k
100k
10
1M
10M
100M
1G
FREQUENCY (Hz)
1
10G
15893-084
GAIN (dB)
60
I-V GAIN (Ω)
I-V GAIN
Figure 82. Compensating the TIA, CF = 2.2pF
Rev. 0 | Page 26 of 30
100
CF = 3.9pF
50
0
–50
TIME(1µS/DIV)
Figure 84. Pulse Response vs. CF
15893-086
Figure 82 and Figure 83 show the compensations of the TIA circuit.
The system has a bandwidth of 1.45 MHz when it is maximized
for a signal bandwidth with CF = 2.2 pF. Increasing CF to 3.9 pF
reduces the bandwidth to 0.82 MHz; however, it greatly reduces the
overshoot (see Figure 84). In practice, an optimum CF value is
determined experimentally by varying it slightly to optimize the
output pulse response.
OUTPUT VOLTAGE (%)
CF = 2.2pF
The ADA4625-1 input capacitance (CCM + CDM) is 19.9 pF;
therefore, the total input capacitance (CIN) is 24.9 pF. By
substituting CIN = 24.9 pF, RF = 50 kΩ, and fGBP = 18 MHz into
Equation 7 and Equation 9, the resulting feedback capacitor
value (CF) and the −3 dB signal bandwidth (fP) are 2.2 pF and
1.45 MHz, respectively.
Data Sheet
ADA4625-1
Table 7 shows the noise sources and estimated total output noise
for the photodiode amplifier with CF = 2.2 pF and CF =3.9 pF,
respectively.
Use the Analog Devices Analog Photodiode Wizard to design a
transimpedance amplifier circuit to interface with a photodiode.
Table 7. RMS Noise Contributions of the Photodiode Preamplifier
Noise Contributor
RF
Expression

4kTRF  fP 
2 
where:
k is Boltzmann’s constant (1.38 × 10−23 J/K).
T is the temperature in Kelvin (K).

fp
2
0.34
0.25
 C 
eN 1  IN  fGBP
CF  2

61.6
47.7
75.2
57.7
Current Noise, Vni, AMP
iN RF
Voltage Noise, Vnv, AMP
Total Noise
1
CF = 2.2 pF
43.2
RMS Noise (μV)1
CF = 3.9 pF
32.5
Vnv , AMP 2  Vnv , AMP 2  VRF 2
RMS noise with RF = 49.9 kΩ, CIN = CCM + CDM = 19.9 pF, CD = 5 pF, iN = 4.5 fA/√Hz, and eN =3.3 nV/√Hz.
Rev. 0 | Page 27 of 30
ADA4625-1
Data Sheet
RECOMMENDED POWER SOLUTION
INPUT OVERVOLTAGE PROTECTION
Analog Devices has a wide range of power management
products to meet the requirements of most high performance
signal chains.
The ADA4625-1 has internal protective circuitry that allows
voltages as high as 0.2 V beyond the supplies to be applied at the
input of either terminal without causing damage. For higher
input voltages, a series resistor is necessary to limit the input
current. Determine the resistor value by
+16V
+12V
ADP5070
–16V
ADP7118
+15V
ADP7182
–15V
15893-070
For a dual-supply application, the ADA4625-1 typically needs a
±15 V supply. Low dropout (LDO) linear regulators such as the
ADP7118 or the ADP7142 for the positive supply and the
ADP7182 for the negative supply help improve the PSRR at
high frequency and generate a low noise power rail. In addition,
if a negative supply is not available, the ADP5070 can generate
the negative supply from a positive supply. Figure 85 shows an
example of this power solution configuration for the ADA4625-1.
Figure 85. Power Solution Configuration for the ADA4625-1
Table 8. Recommended Power Management Devices
Product
ADP5070
ADP7118
ADP7142
ADP7182
Description
DC-to-dc switching regulator with independent
positive and negative outputs
20 V, 200 mA, low noise, CMOS LDO linear regulator
40 V, 200 mA, low noise, CMOS LDO linear regulator
−28 V, −200 mA, low noise, linear regulator
It is recommended to use a low ESR, 0.1 μF bypass capacitor close
to each power supply pins of the ADA4625-1 and ground to
reduce errors coupling in from the power supplies. For noisy
power supplies, place an additional 10 μF capacitor in parallel
with the 0.1 μF for better performance.
(VIN − VS)/RS ≤ 20 mA
where:
VIN is the input voltage.
VS is the voltage of either V+ or V−.
RS is the series resistor.
With a very low bias current of <5.5 nA up to 125°C, higher
resistor values can be used in series with the inputs. A 500 Ω
resistor protects the inputs from voltages as high as 10 V beyond
the supplies and adds less than 2.75 μV to the offset. However,
note that the added series resistor (RS) may increase the overall
noise and lower the bandwidth due to the addition of a pole
introduced by RS and the input capacitor of the amplifier.
DRIVING CAPACITIVE LOADS
The inherent output resistance of the op amp combined with a
capacitive load forms an additional pole in the transfer function
of the amplifier. Adding capacitance to the output of any op amp
results in additional phase lag. This lag reduces stability and
leads to overshoot or oscillation, which is a common situation
when an amplifier is used to drive the input of switched
capacitor analog-to-digital converters (ADCs).
The ADA4625-1 has a high phase margin and low output
impedance and is capable of directly driving a capacitive load
up to 1 nF with no external compensation at unity-gain without
oscillation.
For other considerations and various circuit solutions, see the
Ask the Applications Engineer-25, Op Amps Driving Capacitive
Loads Analog Dialogue article.
Rev. 0 | Page 28 of 30
Data Sheet
ADA4625-1
THERMAL MANAGEMENT
The ADA4625-1 can operate with up to a 36 V supply voltage
with a typical 4 mA quiescent current. Heavy loads increase
power dissipation and raise the chip junction temperature.
The maximum safe power dissipation for the ADA4625-1 is
limited by the associated rise in junction temperature (TJ) on
the die. Two conditions affect TJ: power dissipation (PD) of the
device and ambient temperature (TA) surrounding the package.
This relationship is shown in Equation 11.
TJ = PD × θJA + TA
(11)
where θJA is the thermal resistance between the die and the
ambient environment. The total power dissipation in the
amplifier is the sum of the power dissipated in the output stage
plus the quiescent power. Power dissipation for the sourcing
current is shown in Equation 12, where VSY is the total supply
voltage (V+) – (V−).
PD = VSY × ISY + ((V+) − VOUT)IOUT
(12)
Replace ((V+) − VOUT) in Equation 12 with ((V−) − VOUT) when
sinking current.
For symmetrical supplies with a ground referenced load, use the
following equation to calculate the average power for the amplifier
processing sine signal.
PAVG, SINE 

 


  2  RL 
VSY  I SY    2  (V )  VPEAK    VPEAK
π
RL
2
(13)
where VPEAK is the peak value of a sine wave output voltage.
The specified thermal resistance θJA of the ADA4625-1 is 52.8°C/W.
A good PCB layout and an external heat sink can improve thermal
performance by reducing junction to ambient temperature.
The ADA4625-1 features an exposed pad that floats internally
to provide the maximum flexibility and ease of use. Solder the
exposed pad to the PCB board GND, or the V+ or V− plane for
best thermal transfer. Where thermal heating is not an issue, the
exposed pad can be left floating.
Incorporate the use of thermal vias or heat pipes into the design
of the mounting pad for the exposed pad to lower the overall θJA.
Rev. 0 | Page 29 of 30
ADA4625-1
Data Sheet
OUTLINE DIMENSIONS
Figure 86. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP]
Narrow Body
(RD-8-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADA4625-1ARDZ
ADA4625-1ARDZ-R7
ADA4625-1ARDZ-RL
EVAL-ADA4625-1ARDZ
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP]
8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP]
8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP]
Evaluation Board
Z = RoHS Compliant Part.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15893-0-10/17(0)
Rev. 0 | Page 30 of 30
Package Option
RD-8-1
RD-8-1
RD-8-1