MITSUBISHI LSIs revision-P04, ' 98.12.16 M5M5V416BTP,RT PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM FEATURES DESCRIPTION The M5M5V416B is a f amily of low v oltage 4-Mbit static RAMs organized as 262,144-words by 16-bit, f abricated by Mitsubishi's high-perf ormance 0.25µm CMOS technology . The M5M5V416B is suitable f or memory applications where a simple interf acing , battery operating and battery backup are the important design objectiv es. M5M5V416BTP,RT are packaged in a 44-pin 400mil thin small outline package. M5M5V416BTP (normal lead bend ty pe package) , M5M5V416BRT (rev erse lead bend ty pe package) , both ty pes are v ery easy t o design a printed circuit board. From the point of operating temperature, the f amily is div ided into three v ersions; "Standard", "W-v ersion", and "I-v ersion". Those are summarized in the part name table below. Power Supply Part name Access time max. 70ns 85ns 100ns 70ns 85ns 100ns 70ns 85ns 100ns 70ns 85ns 100ns 70ns 85ns 100ns 70ns 85ns 100ns M5M5V416BTP , RT -70L M5M5V416BTP , RT -85L Standard M5M5V416BTP , RT -10L 0 ~ +70°C M5M5V416BTP , RT -70H M5M5V416BTP , RT -85H M5M5V416BTP , RT -10H 2.7 ~ 3.6V 2.7 ~ 3.6V M5M5V416BTP , RT -70LW M5M5V416BTP , RT -85LW W-v ersion M5M5V416BTP , RT -10LW -20 ~ +85°C M5M5V416BTP , RT -70HW M5M5V416BTP , RT -85HW 2.7 ~ 3.6V 2.7 ~ 3.6V M5M5V416BTP , RT -10HW M5M5V416BTP , RT -70LI M5M5V416BTP , RT -85LI I-v ersion M5M5V416BTP , -40 ~ +85°C M5M5V416BTP , 2.7 ~ 3.6V RT -10LI RT -70HI M5M5V416BTP , RT -85HI M5M5V416BTP , RT -10HI 2.7 ~ 3.6V ty pical * 25°C 40°C --- --- S1 DQ1 DQ2 DQ3 DQ4 Vcc GND DQ5 DQ6 DQ7 DQ8 WE A15 A14 A13 A12 A16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 25°C 40°C 70°C --- --- 0.3µA 1µA --- --- 0.3µA 1µA --- --- 20µA --- 1µA 3µA 10µA --- --- --- 20µA 40µA 1µA 3µA 10µA 20µA --- --- 20µA 40µA 1µA 3µA 10µA 20µA 40mA (10MHz) 5mA (1MHz) * "ty pical" parameter is sampled, not 100% tested. 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 44P3W-H Ratings (max.) 0.3µA 1µA PIN CONFIGURATION A4 A3 A2 A1 A0 Activ e current Icc1 85°C (3.0V, ty p.) Stand-by c urrent Icc (PD), Vcc=3.0V Version, Operating temperature Single +2.7~+3.6V power supply Small stand-by current: 0.3µA(3V,ty p.) No clocks, No ref resh Data retention supply v oltage=2.0V to 3.6V All inputs and outputs are TTL compatible. Easy memory expansion by S1, S2, BC1 and BC2 Common Data I/O Three-state outputs: OR-tie capability OE prev ents data contention in the I/O bus Process technology : 0.25µm CMOS Package: 44 pin 400mil TSOP (II) A5 A6 A7 OE BC2 BC1 DQ16 DQ15 DQ14 DQ13 GND Vcc DQ12 DQ11 DQ10 DQ9 S2 A8 A9 A10 A11 A17 A5 A6 A7 OE BC2 BC1 DQ16 DQ15 DQ14 DQ13 GND Vcc DQ12 DQ11 DQ10 DQ9 S2 A8 A9 A10 A11 A17 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A4 A3 A2 A1 A0 S1 DQ1 DQ2 DQ3 DQ4 Vcc GND DQ5 DQ6 DQ7 DQ8 WE A15 A14 A13 A12 A16 Pin Function A0 ~ A17 Address input DQ1 ~ DQ16 Data input / output 44P3W-J MITSUBISHI ELECTRIC S1 Chip select input 1 S2 Chip select input 2 W Write control input OE Output enable input BC1 Lower By te (DQ1 ~ 8) BC2 Vcc Upper By te (DQ9 ~ 16) GND Power supply Ground supply Outline: 44P3W-H/J NC: No Connection 1 MITSUBISHI LSIs revision-P04, ' 98.12.16 M5M5V416BTP,RT PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM FUNCTION The M5M5V416BTP,RT are organized as 262,144-words by 16-bit. These dev ices operate on a single +2.7~3.6V power supply , and are directly TTL compatible to both input and output. Its f ully static circuit needs no clocks and no ref resh, and makes it usef ul. The operation mode are determined by a combination of the dev ice control inputs BC1 , BC2 , S1, S2 , W and OE. Each mode is summarized in the f unction table. A write operation is executed whenev er the low lev el W ov erlaps with the low lev el BC1 and/or BC2 and the low lev el S1 and the high lev el S2. The address(A0~A17) must be set up bef ore the write cy cle and must be stable during the entire cycle. A read operation is executed by s etting W at a high lev el and OE at a low lev el while BC1 and/or BC2 and S1 and S2 are in an activ e state(S1=L,S2=H). When setting BC1 at the high lev el and other pins are in an activ e stage , upper-by t e are in a selectable mode in which both reading and writing are enabled, and lower-by t e are in a non-selectable mode. And when setting BC2 at a high lev el and other pins are in an activ e stage, lowerby t e are in a selectable mode and upper-by te are in a non-selectable mode. When setting BC1 and BC2 at a high lev el or S1 at a high lev el or S2 at a low lev el, the chips are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by BC1, BC2 and S1, S2. The power supply c urrent is reduced as low as 0.3µA(25°C, ty pical), and the memory data can be held at +2V power supply , enabling battery back-up operation during power f ailure or power-down operation in the non-selected mode. FUNCTION TABLE BLOCK DIAGRAM S1 H L H X L L L L L L L L L S2 BC1 BC2 W OE X X X L X L X X X X H X X X X X H H X X H L H L X H L H H L H L H H H H H L L X H H L H L H H L H H H L L L X H L L H L H L L H H A0 Mode Non selection Non selection Non selection Non selection Write Read Write Read Write Read DQ1~8 DQ9~16 High-Z High-Z High-Z High-Z Din Dout High-Z High-Z High-Z High-Z Din Dout High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Din Dout High-Z Din Dout High-Z Icc Standby Standby Standby Standby Activ e Activ e Activ e Activ e Activ e Activ e Activ e Activ e Activ e DQ 1 A1 MEMORY ARRAY DQ 8 262144 WORDS x 16 BITS A 16 - DQ 9 A 17 S1 CLOCK GENERATOR DQ 16 S2 BC1 Vcc BC2 W GND OE MITSUBISHI ELECTRIC 2 MITSUBISHI LSIs revision-P04, ' 98.12.16 M5M5V416BTP,RT PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Vcc VI VO Pd Parameter With respect to GND With respect to GND Output v oltage With respect to GND Operating temperature Ta=25°C Standard (-L, -H) W-v ersion (-LW, -HW) I-v ersion (-LI, -HI) Storage temperature T stg Units Ratings Supply v oltage Input v oltage Power dissipation Ta Conditions -0.5 * ~ +4.6 -0.5 * ~ Vcc + 0.5 0 ~ Vcc 700 0 ~ +70 - 20 ~ +85 - 40 ~ +85 - 65 ~ +150 V mW °C °C * -3.0V in case of AC (Pulse width < = 30ns) DC ELECTRICAL CHARACTERISTICS Symbol Parameter ( Vcc=2.7 ~ 3.6V, unless otherwise noted) Limits Conditions Min V IH V IL V OH1 V OH2 V OL II IO High-lev el input v oltage 2.2 -0.3 * 2.4 Output leakage current BC1 and BC2=VIH or S1=VIH or S2=VIH or OE=VIH, VI/O=0 ~ Vcc Icc 1 Activ e supply c urrent ( AC,MOS lev el ) < 0.2V, S2 Vcc-0.2V BC1 and BC2< = 0.2V, S1= > other inputs < = 0.2V or = Vcc-0.2V Output - open (duty 100%) f = 10MHz BC1 and BC2=V IL , S=V IL ,S2=V IH other pins =V IH or V IL Output - open (duty 100%) f = 10MHz Icc 2 Activ e supply c urrent ( AC,TTL lev el ) Low-lev el input v oltage High-level output voltage 1 High-level output voltage 2 Low-lev el output v oltage Input leakage current I OH= -0.5mA I OH= -0.05mA I OL=2mA V I =0 ~ Vcc -LW, -LI S1 => Vcc - 0.2V, <2> ( AC,MOS lev el ) S2 0.2V, -H, -HW, -HI > S1 < = 0.2V, S2 = Vcc - 0.2V Other inputs=0~Vcc +70°C +70 ~ +85°C +40 ~ +70°C - - 10 48 24 24 12 +25 ~ +40°C 1 0.3 0.3 3.6 1.2 1.2 +70 ~ +85°C -HW - 20 ~ +25°C - -HI - 40 ~ +25°C - 0.3 1.2 - - 0.5 0 ~ +25°C BC1 and BC2=VIH or S1=VIH or S2=VIL Other inputs= 0 ~ Vcc µA mA µA mA * -3.0V in case of AC (Pulse width < = 30ns) (Vcc=2.7 ~ 3.6V, unless otherwise noted) CAPACITANCE Conditions Min CI CO 0.4 ±1 ±1 50 10 50 5 - Note 2: Typical value is for Vcc=3.0V and Ta=25° C Parameter V - f = 1MHz Note 1: Direction for current flowing into IC is indicated as positive (no mark) Symbol 0.6 40 5 40 -H BC1 and BC2 => Vcc - 0.2V Icc 4 -HW, -HI other inputs = 0 ~ Vcc <3> Stand by s upply current ( AC,TTL lev el ) Units Vcc+0.3V - f = 1MHz -L, -LW, -LI other inputs = 0 ~ Vcc Icc 3 Max Vcc-0.5V <1> Stand by s upply current Ty p Input capacitance V I =GND, VI =25mVrms, f =1MHz Output capacitance V O = GND,VO =25mVrms, f =1MHz MITSUBISHI ELECTRIC Limits Ty p Max 10 10 Units pF 3 MITSUBISHI LSIs revision-P04, ' 98.12.16 M5M5V416BTP,RT PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM AC ELECTRICAL CHARACTERISTICS (1) TEST CONDITIONS (Vcc=2.7 ~ 3.6V, unless otherwise noted) 2.7V~3.6V Input pulse V IH=2.4V,V IL=0.4V Input rise time and f all time 5ns Supply v oltage 1TTL DQ CL V OH=V OL=1.5V Ref erence lev el Transition is measured ±500mV f rom steady state voltage.(f or ten,t dis ) Including scope and jig capacitance Fig.1,CL=30pF CL=5pF (for ten,tdis) Output loads Fig.1 Output load (2) READ CYCLE Limits Parameter Symbol t CR t a(A) t a(S1) t a(S2) t a(BC1) t a(BC2) t a(OE) t dis (S1) t dis (S2) t dis (BC1) t dis (BC2) t dis (OE) t en(S1) t en(S2) t en(BC1) t en(BC2) t en(OE) t V(A) 70L,70H,70LW 70HW,70LI,70HI Read cy cle time Address access time Chip select 1 access time Chip select 2 access time By te control 1 access time By te control 2 access time Output enable access time Output disable time af t er S1 high Output disable time af t er S2 low Output disable time af t er BC1 high Output disable time af t er BC2 high Output disable time af t er OE high Output enable time af ter S1 low Output enable time af ter S2 high Output enable time af ter BC1 low Output enable time af ter BC2 low Output enable time af ter OE low Min 70 Max Min 85 Max 10 10 10 10 5 10 10 10 10 10 10L,10H,10LW 10HW,10LI,10HI Min 100 Units Max 100 100 100 100 100 50 35 35 35 35 35 85 85 85 85 85 45 30 30 30 30 30 70 70 70 70 70 35 25 25 25 25 25 10 Data v alid time after address 85L,85H,85LW 85HW,85LI,85HI 10 10 10 10 5 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (3) WRITE CYCLE Limits Symbol t CW t w(W) t su(A) t su(A-WH) t su(BC1) t su(BC2) t su(S1) t su(S2) t su(D) t h(D) t rec (W) t dis (W) t dis (OE) t en(W) t en(OE) 70L,70H,70LW 85L,85H,85LW 70HW,70LI,70HI 85HW,85LI,85HI Parameter Write cy cle time Write pulse width Address setup time Address setup time with respect to W By te control 1 setup time By te control 2 setup time Chip select 1 setup time Chip select 2 setup time Data setup time Data hold time Write recov ery time Output disable time f rom W low Output disable time f rom OE high Output enable time f rom W high Output enable time f rom OE low Min 70 55 0 65 65 65 65 65 35 0 0 Max Min 85 60 0 70 70 70 70 70 35 0 0 25 25 5 5 Max 10L,10H,10LW 10HW,10LI,10HI Min 100 75 0 85 85 85 85 85 40 0 0 5 5 5 5 MITSUBISHI ELECTRIC ns ns ns ns ns ns ns ns ns ns ns 35 35 30 30 Units Max ns ns ns ns 4 MITSUBISHI LSIs revision-P04, ' 98.12.16 M5M5V416BTP,RT PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM (4)TIMING DIAGRAMS Read cycle t CR A 0~17 t a(A) t a(BC1) t v (A) t a(BC2) or BC1,BC2 (Note3) t dis (BC1) or t dis (BC1) (Note3) t a(S1) S1 (Note3) t dis (S1) (Note3) t dis (S2) (Note3) t a(S2) S2 (Note3) t a (OE) OE (Note3) t en (OE) W = "H" lev el DQ 1~16 Write cycle ( W control mode ) t dis (OE) t en (BC1) t en (BC2) t en (S1) t en (S2) (Note3) VALID DATA t CW A 0~17 t su (BC1) or t su (BC2) BC1,BC2 (Note3) (Note3) t su (S1) S1 (Note3) (Note3) t su (S2) S2 (Note3) (Note3) OE t su (A) t su (A-WH) t w (W) t rec (W) t dis (W) W t en (OE) t en (W) t dis (OE) DQ 1~16 DATA IN STABLE t su (D) t h (D) MITSUBISHI ELECTRIC 5 MITSUBISHI LSIs revision-P04, ' 98.12.16 M5M5V416BTP,RT PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM Write cycle (BC control mode) t CW A 0~17 t su (A) t su (BC1) or t su (BC2) t rec (W) BC1,BC2 S1 (Note3) (Note3) S2 (Note3) W (Note4) (Note3) DQ 1~16 (Note3) (Note5) t su (D) t h (D) (Note3) DATA IN STABLE Note 3: Hatching indicates the state is "don't care". Note 4: A Write occurs during S1 low, S2 high ov erlaps BC1 and/or BC2 low and W low. Note 5: When the f alling edge of W is simultaneously or prior to the f alling edge of BC1 and/or BC2 or the f alling edge of S1 or rising edge of S2, the outputs are maintained in the high impedance state. Note 6: Don't apply inv erted phase signal externally when DQ pin is in output mode. MITSUBISHI ELECTRIC 6 MITSUBISHI LSIs revision-P04, ' 98.12.16 M5M5V416BTP,RT PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM Write cycle (S1 control mode) t CW A 0~17 BC1,BC2 (Note3) t su (S1) t su (A) t rec (W) (Note3) S1 S2 (Note3) (Note3) (Note5) W (Note4) (Note3) t su (D) t h (D) (Note3) DATA IN STABLE DQ 1~16 Write cycle (S2 control mode) t CW A 0~17 BC1,BC2 (Note3) t su (A) t su (S2) t rec (W) (Note3) S1 S2 (Note3) (Note3) (Note5) W (Note4) (Note3) DQ 1~16 t su (D) t h (D) (Note3) DATA IN STABLE MITSUBISHI ELECTRIC 7 MITSUBISHI LSIs revision-P04, ' 98.12.16 M5M5V416BTP,RT PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS Symbol Vcc Limits Parameter Test conditions (PD) Power down supply voltage V I (BC) Chip select input S1 V I (S2) Chip select input S2 -LW, -LI Vcc=3.0V (PD) Power down supply c urrent 1) BC1 and BC2 > = Vcc-0.2V S1 < =0.2V or S2 > = Vcc-0.2V other inputs=0~3V 2) S1 > =Vcc - 0.2V other inputs=0~3V 3) S2 0.2V other inputs=0~3V +70 ~ +85°C t su (PD) t rec (PD) Max -L, -LW, -LI +70°C -HW, -HI +70 ~ +85°C -H, -HW, -HI +40 ~ +70°C +25 ~ +40°C 0 ~ +25°C -H -HW -20 ~ +25°C -HI -40 ~ +25°C Units V V V - - - 1 0.3 0.3 0.3 0.2 40 20 20 10 3 1 1 1 V µA µA µA µA µA µA µA µA Typical value is for Ta=25°C (2) TIMING REQUIREMENTS Symbol Ty p 2.0 2.0 2.0 Byte control input BC1 & BC2 V I (S1) Icc Min Limits Parameter Test conditions Min Ty p 0 5 Power down set up time Power down recov ery t ime Max Units ns ms (3) TIMING DIAGRAM BC control mode Vcc t su (PD) BC1 2.7V 2.7V t rec (PD) 2.2V 2.2V BC1 , BC2 > = Vcc - 0.2V BC2 S1 control mode Vcc t su (PD) 2.7V 2.7V t rec (PD) 2.2V 2.2V S1 > = Vcc - 0.2V S1 S2 control mode Vcc S2 t su (PD) 0.2V 2.7V 2.7V t rec (PD) S2 0.2V MITSUBISHI ELECTRIC 0.2V 8 MITSUBISHI LSIs revision-P04, ' 98.12.16 M5M5V416BTP,RT PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM Revision History Revision No. P01 P02 P03 P04 History Date Remark The first edition Pin#28: NC --> S2 Font problem fixed 70ns version added '98 . 07 . 07 '98 . 07 . 14 '98 . 08 . 27 '98 . 12 . 16 Preliminary Preliminary Preliminary Preliminary MITSUBISHI ELECTRIC 9 G Z1 z e Detail G y D b x M 22 1 Weight(g) 0.47 23 JEDEC Code 44 EIAJ Package Code TSOPII44-P-400-0.80 Scale: 3/1 44P3W-H 2 Detail F A A3 Lead Material Alloy 42 A1 A F A A1 A2 b c D E e HE L L1 Lp Symbol ME l2 b2 z Z1 x y A3 b2 0.5 Dimension in Millimeters Max Nom Min 1.2 0.05 0.125 0.2 1.0 0.45 0.3 0.35 0.125 0.175 0.105 18.31 18.51 18.41 10.06 10.26 10.16 0.8 11.56 11.96 11.76 0.4 0.5 0.6 0.8 0.45 0.75 0.6 0.25 0.805 0.955 0.16 0.1 10 0 10.36 0.9 Recommended Mount Pad e Plastic 44pin 400mil TSOP(II) G Z1 z e Detail G y D b x M 23 44 Weight(g) 0.47 22 JEDEC Code 1 EIAJ Package Code TSOPII44-P-400-0.80 Scale: 3/1 44P3W-J Detail F A2 A3 Lead Material Alloy 42 A1 A F A A1 A2 b c D E e HE L L1 Lp Symbol ME l2 b2 z Z1 x y A3 b2 Dimension in Millimeters Max Nom Min 1.2 0.05 0.125 0.2 1.0 0.3 0.35 0.45 0.105 0.125 0.175 18.31 18.51 18.41 10.06 10.26 10.16 0.8 11.56 11.96 11.76 0.6 0.4 0.5 0.8 0.45 0.6 0.75 0.25 0.805 0.955 0.16 0.1 0 10 10.36 0.9 0.5 Recommended Mount Pad e Plastic 44pin 400mil TSOP(II)