INNOVASIC IA80C152 Universal communications controller Datasheet

IA80C152
Universal Communications Controller
Data Sheet
July 29, 2010
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Universal Communications Controller
Data Sheet
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Copyright
Data Sheet
July 29, 2010
2010 by Innovasic Semiconductor, Inc.
Published by Innovasic Semiconductor, Inc.
3737 Princeton Drive NE, Suite 130, Albuquerque, NM 87107
Intel® is a registered trademark of Intel Corporation.
MILES™ is a trademark of Innovasic Semiconductor, Inc.
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TABLE OF CONTENTS
List of Figures ..................................................................................................................................5
List of Tables ...................................................................................................................................6
1.
Introduction.............................................................................................................................7
1.1 General Description.......................................................................................................7
1.2 Features .........................................................................................................................8
2.
Packaging, Pin Descriptions, and Physical Dimensions .........................................................9
2.1 Packages and Pinouts ....................................................................................................9
2.1.1 JA/JC...............................................................................................................10
2.1.2 JB/JD...............................................................................................................13
2.1.3 Physical Dimensions .......................................................................................16
2.2 I/O Signal Description .................................................................................................17
3.
Maximum Ratings, Thermal Characteristics, and DC Parameters .......................................20
4.
Device Architecture ..............................................................................................................22
4.1 Functional Block Diagram ..........................................................................................22
4.2 Memory Space .............................................................................................................23
5.
Peripheral Architecture .........................................................................................................25
5.1 Registers and Interrupts ...............................................................................................25
5.2 Register Set Descriptions ............................................................................................27
5.2.1 A* (0E0h) .......................................................................................................27
5.2.2 ADR0,1,2,3 (095h, 0A5h, 0B5h, 0c5h) ..........................................................27
5.2.3 AMSK0,1 (0D5h, 0E5h) .................................................................................28
5.2.4 B* (0F0h) ........................................................................................................28
5.2.5 BAUD (094h) .................................................................................................28
5.2.6 BCRL0, BCRH0 (0E2h, 0E3h) ......................................................................28
5.2.7 BCRL1, BCRH1 (0F2h, 0F3h) .......................................................................28
5.2.8 BKOFF (0C4h) ...............................................................................................28
5.2.9 DARL0, DARH0 (0C2h, 0C3h) .....................................................................28
5.2.10 DARL1, DARH1 (0D2h, 0D3h) .....................................................................29
5.2.11 DCON0,1 (092h, 093h) ..................................................................................29
5.2.12 DPL, DPH (082h, 083h) .................................................................................30
5.2.13 GMOD (084h) ................................................................................................30
5.2.14 IE* (0A8h) ......................................................................................................31
5.2.15 IEN1* (0C8h) .................................................................................................32
5.2.16 IFS (0A4h) ......................................................................................................32
5.2.17 IP* (0B8h) ......................................................................................................33
5.2.18 IPN1* (0F8h) ..................................................................................................33
5.2.19 MYSLOT (0F5h) ............................................................................................34
5.2.20 P0*, P1*, P2*, P3*, P4*, P5, P6 (080h, 090h, 0A0h, 0Boh, 0C0h,
091h, 0A1h) ....................................................................................................34
5.2.21 PCON (087h) ..................................................................................................35
5.2.22 PRBS (0E4h) ..................................................................................................36
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6.
7.
8.
9.
10.
11.
Data Sheet
July 29, 2010
5.2.23 PSW* (0D0h)..................................................................................................36
5.2.24 RFIFO (0F4h) .................................................................................................37
5.2.25 RSTAT* (0E8h)..............................................................................................37
5.2.26 SARL0, SARH0 (0A2h, 0A3h) ......................................................................38
5.2.27 SARL1, SARH1 (0B2h, 0B3h) ......................................................................38
5.2.28 SBUF (099h) ...................................................................................................38
5.2.29 SCON* (098h) ................................................................................................38
5.2.30 SLOTTM (0B4h) ............................................................................................39
5.2.31 SP (081h) ........................................................................................................39
5.2.32 TCDCNT (0D4h) ............................................................................................39
5.2.33 TCON* (088h) ................................................................................................39
5.2.34 TFIFO (085h)..................................................................................................40
5.2.35 TH0, TL0 (08Ch, 08Ah) .................................................................................40
5.2.36 TH1, TL1 (08Dh, 08Bh) .................................................................................41
5.2.37 TMOD (089h) .................................................................................................41
5.2.38 TSTAT* (0D8h) .............................................................................................41
5.3 Power Conservation Modes ........................................................................................42
5.4 Oscillator Pins .............................................................................................................43
Instruction Set Summary Table ............................................................................................50
AC Characteristics ................................................................................................................56
Innovasic/Intel Part Number Cross-Reference Table ...........................................................57
Errata.....................................................................................................................................58
9.1 Errata Summary...........................................................................................................58
9.2 Errata Detail ................................................................................................................58
Revision History ...................................................................................................................60
For Additional Information...................................................................................................61
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LIST OF FIGURES
Figure 1. JA/JC Versions Package Diagram .................................................................................10
Figure 2. JB/JD Versions Package Diagram .................................................................................13
Figure 3. Package Dimensions ......................................................................................................16
Figure 4. Functional Block Diagram ............................................................................................22
Figure 5. Memory Space ...............................................................................................................24
Figure 6. External Program Memory Read Cycle ........................................................................44
Figure 7. External Data Memory Read Cycle ...............................................................................44
Figure 8. External Data Memory Write Cycle ..............................................................................45
Figure 9. External Clock Drive Waveform ...................................................................................46
Figure 10. Shift Register Mode Timing Waveforms ....................................................................47
Figure 11. GSC Receiver Timings (Internal Baud Rate Generator) .............................................48
Figure 12. GSC Transmit Timings (Internal Baud Rate Generator) .............................................48
Figure 13. GSC Timings (External Clock) ...................................................................................49
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LIST OF TABLES
Table 1. IC Version Differences .....................................................................................................7
Table 2. JA/JC Versions Numeric Pin Listing ..............................................................................11
Table 3. JA/JC Versions Alphabetic Pin Listing ..........................................................................12
Table 4. JB/JD Versions Numeric Pin Listing ..............................................................................14
Table 5. JB/JD Versions Alphabetic Pin Listing ..........................................................................15
Table 6. I/O Signal Descriptions ...................................................................................................17
Table 7. Absolute Maximum Ratings ...........................................................................................20
Table 8. Thermal Characteristics ..................................................................................................20
Table 9. DC Parameters ................................................................................................................21
Table 10. Summary of Program Memory Fetches ........................................................................25
Table 11. List of Registers ............................................................................................................25
Table 12. List of Interrupts ...........................................................................................................27
Table 13. DCON0,1 Register ........................................................................................................29
Table 14. GMOD Register ............................................................................................................30
Table 15. IE* Register ..................................................................................................................31
Table 16. IEN1* Register .............................................................................................................32
Table 17. IP* Register...................................................................................................................33
Table 18. IPN1* Register ..............................................................................................................33
Table 19. MYSLOT Register ........................................................................................................34
Table 20. P0*, P1*, P2*, P3*, P4*, P5, P6 Register.....................................................................35
Table 21. PCON Register .............................................................................................................35
Table 22. PSW* Register ..............................................................................................................36
Table 23. RSTAT* Register .........................................................................................................37
Table 24. SCON* Register ...........................................................................................................38
Table 25. TCON* Register ...........................................................................................................40
Table 26. TMOD Register ............................................................................................................41
Table 27. TMOD Register ............................................................................................................41
Table 28. Power Conservation Modes ..........................................................................................43
Table 29. External Clock Drive ....................................................................................................46
Table 30. Local Serial Channel Timing—Shift Register Mode ...................................................46
Table 31. Global Serial Port Timing—Internal Baud Rate Generator..........................................47
Table 32. Global Serial Port Timing—External Clock .................................................................49
Table 33. Instruction Set Summary ..............................................................................................50
Table 34. External Program and Data Memory Characteristics ...................................................56
Table 35. Innovasic/Intel Part Number Cross-Reference .............................................................57
Table 36. Summary of Errata ........................................................................................................58
Table 37. Revision History ...........................................................................................................60
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IA80C152
Universal Communications Controller
1.
Data Sheet
July 29, 2010
Introduction
The IA80C152 is a ―plug-and-play‖ drop-in replacement for the original Intel 80C152.
Innovasic produces replacement ICs using its MILES, or Managed IC Lifetime Extension
System, cloning technology. This technology produces replacement ICs far more complex than
―emulation‖ while ensuring they are compatible with the original IC. MILES captures the design
of a clone so it can be produced even as silicon technology advances. MILES also verifies the
clone against the original IC so that even the ―undocumented features‖ are duplicated. This data
sheet presents engineering information about the IA80C152 including functional and I/O
descriptions, electrical characteristics, and applicable timing.
1.1
General Description
The IA80C152 is a Universal Communications Controller (UCC) that is pin-for-pin compatible
with the Intel 80C152. This version of the UCC is a ROM-less version. The ROM version is
identified as the 83C152 and can be easily derived from the 80C152 using a customer furnished
ROM program. The IA80C152 can be programmed with the same software development tools
and can transmit and receive using the same communication protocols as the Intel 80C152
making the IA80C152 a drop-in replacement.
Table 1 below cross-references IA80C152 versions with protocol, package, and I/O Port
capability. Pinout diagrams are provided in Figures 1, 2, and 3.
Table 1. IC Version Differences
Innovasic
Part Number
IA80C152JA
IA80C152JB
IA80C152JC
IA80C152JD
CSMA/CD,
SDLC/HDLC, User-Defined
5 I/O
Ports





7 I/O
Ports
68-Lead
PLCC







The only difference between The Innovasic IA80C152 and the Intel 80C152 is that all protocols
are available in all IC versions. Originally, the Intel 80C152 JC and JD versions were limited to
SDLC/HDLC only. Also, Innovasic will support a ROM version (83152) in any of the JA, JB,
JC, or JD versions.
Note: If you are using the IA80C152JB/JD in a system that originally used an Intel 80C152JA/JC,
please note that the EBEN pin on the Innovasic part has an internal pull down, so it is recommended
that you do not connect that pin (NC) on your board for proper functionality. In addition, the two
ports that are unused on the JA/JC device (Ports 5 and 6) have internal pullups on the Innovasic
device, so it is recommended that you do not connect (NC) these pins.
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The IA80C152 is partitioned into three major functional units identified as the C8051, the Direct
Memory Access (DMA) Controller, and the Global Serial Channel (GSC). The C8051 is
implemented using a CAST, Inc. Intellectual Property (IP) core. This core is instruction set
compatible with the 80C51BH, and contains compatible peripherals including a UART interface
and timers. The special function registers (SFRs) and interrupts are modified from the original
8051BH to accommodate the additional DMA controller and GSC peripherals.
The DMA Controller is a 2 channel, 8-bit device that is 16-bit addressable. Either channel can
access any combination of reads and writes to external memory, internal memory, or the SFR's.
Various modes allow the DMA to access the UART, GSC, SFRs, and internal and external
memory as well as provide for external control. Since there is only 1 data/program memory bus,
only one DMA channel or the microcontroller can have control at any given time. Arbitration
within the device makes this control transparent to the programmer.
The GSC is a serial interface that can be programmed to support CSMA/CD, SDLC, user
definable protocols, and limited HDLC. Protocol specific features are supported in hardware
such as address recognition, collision resolution, CRC generation and errors, automatic
re-transmission, and hardware acknowledge. The CSMA/CD protocol meets the requirements of
ISO/IEC 8802-3 and ANSI/IEEE Std 802.3 to the extent implemented in the original IC. The
SDLC protocol meets the requirements of IBM GA27-3093-04 to the extent implemented in the
original IC.
1.2
Features
Form, Fit, and Function Compatible with the Intel 80C152
Packaging options available in both standard and RoHS-Compliant:
– 68-Pin PLCC (plastic leaded chip carrier)
8051 Core with:
– Direct Memory Access (DMA)
– Global Serial Channel (GSC)
– MCS 51-compatible UART
– Two Timers/Counters
– Maskable Interrupts
Memory:
– 256 bytes internal RAM
– 64K bytes program memory
– 64K bytes data memory
5 or 7 I/O Ports
Up to 16.5-MHz Clock Frequency
Two-Channel DMA With Multiple Transfer Modes
GSC Provides Support for Multiple Protocols:
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–
–
–
Data Sheet
July 29, 2010
CSMA/CD
SDLC/HDLC
User Definable
Separate Transmit & Receive FIFOs
Special Protocol Features:
– Up to 2.0625 Mbps Serial Operation
– CSMA and SDLC Frame Formats with CRC Checking
– Manchester, NRZ, & NRZI Data Encoding
– Collision Detection & Resolution in CSMA Mode
Selectable Full/Half Duplex
2.
Packaging, Pin Descriptions, and Physical Dimensions
Information on the packages and pin descriptions is provided in this chapter.
2.1
Packages and Pinouts
The IA80C152 is available in the following packages:
68-Pin PLCC pinout JA/JC versions
68-Pin PLCC pinout JB/JD versions
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2.1.1
Data Sheet
July 29, 2010
JA/JC
(HLDAn) P1.6
P1.5 (HLDn)
P1.4 (RXCn)
P1.3 (TXCn)
P1.2 (DENn)
P1.1 (GTXD)
P1.0 (GRXD)
Vss
VDD
N.C.
N.C.
N.C.
N.C.
P4.0
P4.1
P4.2
P4.3
P4.4
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
The pinout for the JA/JC package is as shown in Figure 1. The corresponding numeric and
alphabetic pin listings are provided in Tables 2 and 3.
10
60
P4.5
P1.7
11
59
P4.6
N.C.
12
58
P4.7
RESETn
13
57
N.C.
(RXD) P3.0
14
56
EAn
(TXD) P3.1
®
15
55
ALE
(INT0n) P3.2
16
54
PSENn
N.C.
17
53
N.C.
(INT1n) P3.3
18
52
N.C.
(T0) P3.4
19
51
N.C.
N.C.
20
50
N.C.
49
N.C.
N.C.
21
IA80C152
68-Pin LCC
JA/JC
36
37
38
39
40
41
42
43
(A/D6) P0.6
(A/D7) P0.7
N.C.
N.C.
N.C.
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A/D0) P0.0
35
P2.3 (A11)
(A/D5) P0.5
26
34
P2.4 (A12)
44
(A/D4) P0.4
45
33
25
N.C.
Vss
(RDn) P3.7
32
P2.5 (A13)
XTAL1
46
31
24
XTAL2
(WRn) P3.6
30
P2.6 (A14)
(A/D3) P0.3
47
29
23
(A/D2) P0.2
P2.7 (A15)
28
48
(A/D1) P0.1
22
27
N.C.
(T1) P3.5
Figure 1. JA/JC Versions Package Diagram
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Table 2. JA/JC Versions Numeric Pin Listing
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Name
N.C.
VDD
Vss
P1.0 (GRXD)
P1.1 (GTXD)
P1.2 (DENn)
P1.3 (TXCn)
P1.4 (RXCn)
P1.5 (HLDn)
(HLDAn) P1.6
P1.7
N.C.
RESETn
(RXD) P3.0
(TXD) P3.1
(INT0n) P3.2
N.C.
(INT1n) P3.3
(T0) P3.4
N.C.
N.C.
N.C.
(T1) P3.5
(WRn) P3.6
(RDn) P3.7
N.C.
(A/D0) P0.0
(A/D1) P0.1
(A/D2) P0.2
(A/D3) P0.3
XTAL2
XTAL1
Vss
(A/D4) P0.4
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
®
Name
(A/D5) P0.5
(A/D6) P0.6
(A/D7) P0.7
N.C.
N.C.
N.C.
(A8) P2.0
(A9) P2.1
(A10) P2.2
P2.3 (All)
P2.4 (A12)
P2.5 (A13)
P2.6 (A14)
P2.7 (A15)
NC
NC
N.C.
N.C.
N.C.
PSENn
ALE
EAn
NC
P4.7
P4.6
P4.5
P4.4
P4.3
P4.2
P4.1
P4.0
NC
NC
NC
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Table 3. JA/JC Versions Alphabetic Pin Listing
Pin
27
28
29
30
34
35
36
37
41
42
43
44
45
46
47
48
55
6
56
4
5
10
9
16
18
1
12
17
20
21
22
26
38
39
Name
(A/D0) P0.0
(A/D1) P0.1
(A/D2) P0.2
(A/D3) P0.3
(A/D4) P0.4
(A/D5) P0.5
(A/D6) P0.6
(A/D7) P0.7
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4
(A13) P2.5
(A14) P2.6
(A15) P2.7
ALE
(DENn) P1.2
EAn
(GRXD) P1.0
(GTXD) P1.1
(HLDAn) P1.6
(HLDn) P1.5
(INT0n) P3.2
(INT1n) P3.3
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
Pin
40
49
50
51
52
53
57
66
67
68
11
65
64
63
62
61
60
59
58
54
25
13
8
14
19
23
7
15
2
3
33
24
32
31
®
Name
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
P1.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
PSENn
(RDn) P3.7
RESETn
(RXCn) P1.4
(RXD) P3.0
(T0) P3.4
(T1) P3.5
(TXCn) P1.3
(TXD) P3.1
VDD
Vss
Vss
(WRn) P3.6
XTAL1
XTAL2
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2.1.2
Data Sheet
July 29, 2010
JB/JD
P4.4
61
67
P4.3
N.C.
68
62
N.C.
1
P4.2
N.C.
2
63
VDD
3
P4.1
Vss
4
64
P1.0 (GRXD)
5
N.C.
P1.1 (GTXD)
6
P4.0
P1.2 (DENn)
7
65
P1.3 (TXCn)
8
66
P1.5 (HLDn)
P1.4 (RXCn)
9
The pinout for the JB/JD package is as shown in Figure 2. The corresponding pin listings are
provided in Tables 4 and 5.
(HLDAn) P1.6
10
60
P4.5
P1.7
11
59
P4.6
EBEN
12
58
P4.7
RESETn
13
57
P6.3
®
(RXD) P3.0
14
56
EAn
(TXD) P3.1
15
55
ALE
(INT0n) P3.2
16
54
PSENn
P5.0
17
53
EPSENn
(INT1n) P3.3
18
52
P6.2
(T0) P3.4
19
51
P6.7
P5.1
20
50
P6.4
P5.2
21
49
P5.7
P5.3
22
48
P2.7 (A15)
(T1) P3.5
23
47
P2.6 (A14)
(WRn) P3.6
24
46
P2.5 (A13)
(RDn) P3.7
25
45
P2.4 (A12)
N.C
.
26
44
P2.3 (A11)
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
(A/D0) P0.0
(A/D1) P0.1
(A/D2) P0.2
(A/D3) P0.3
XTAL2
XTAL1
Vss
(A/D4) P0.4
(A/D5) P0.5
(A/D6) P0.6
(A/D7) P0.7
P5.4
P5.5
P5.6
(A8) P2.0
(A9) P2.1
(A10) P2.2
IA80C152
68-Pin LCC
JB/JD
Figure 2. JB/JD Versions Package Diagram
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Table 4. JB/JD Versions Numeric Pin Listing
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Name
N.C.
VDD
Vss
P1.0 (GRXD)
P1.1 (GTXD)
P1.2 (DENn)
P1.3 (TXCn)
P1.4 (RXCn)
P1.5 (HLDn)
(HLDAn) P1.6
P1.7
EBEN
RESETn
(RXD) P3.0
(TXD) P3.1
(INT0n) P3.2
P5.0
(INT1n) P3.3
(T0) P3.4
P5.1
P5.2
P5.3
(T1) P3.5
(WRn) P3.6
(RDn) P3.7
N.C.
(A/D0) P0.0
(A/D1) P0.1
(A/D2) P0.2
(A/D3) P0.3
XTAL2
XTAL1
Vss
(A/D4) P0.4
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
®
Name
(A/D5) P0.5
(A/D6) P0.6
(A/D7) P0.7
P5.4
P5.5
P5.6
(A8) P2.0
(A9) P2.1
(A10) P2.2
P2.3 (A11)
P2.4 (A12)
P2.5 (A13)
P2.6 (A14)
P2.7 (A15)
P5.7
P6.4
P6.7
P6.2
EPSENn
PSENn
ALE
EAn
P6.3
P4.7
P4.6
P4.5
P4.4
P4.3
P4.2
P4.1
P4.0
N.C.
N.C.
N.C.
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Table 5. JB/JD Versions Alphabetic Pin Listing
Pin
27
28
29
30
34
35
36
37
41
42
43
44
45
46
47
48
55
6
56
12
53
4
5
10
9
16
18
1
26
66
67
68
11
65
Name
(A/D0) P0.0
(A/D1) P0.1
(A/D2) P0.2
(A/D3) P0.3
(A/D4) P0.4
(A/D5) P0.5
(A/D6) P0.6
(A/D7) P0.7
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4
(A13) P2.5
(A14) P2.6
(A15) P2.7
ALE
(DENn) P1.2
EAn
EBEN
EPSENn
(GRXD) P1.0
(GTXD) P1.1
(HLDAn) P1.6
(HLDn) P1.5
(INT0n) P3.2
(INT1n) P3.3
N.C.
N.C.
N.C.
N.C.
N.C.
P1.7
P4.0
Pin
64
63
62
61
60
59
58
17
20
21
22
38
39
40
49
52
57
50
51
54
25
13
8
14
19
23
7
15
2
3
33
24
32
31
®
Name
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P6.2
P6.3
P6.4
P6.7
PSENn
(RDn) P3.7
RESETn
(RXCn) P1.4
(RXD) P3.0
(T0) P3.4
(T1) P3.5
(TXCn) P1.3
(TXD) P3.1
VDD
Vss
Vss
(WRn) P3.6
XTAL1
XTAL2
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2.1.3
Data Sheet
July 29, 2010
Physical Dimensions
1.22/1.07
2 PLCS
The package dimensions are as shown in Figure 3.
D
PIN 1
IDENTIFIER & ZONE
E1
E
E3
D1
D3
TOP VIEW
BOTTOM VIEW
.81 / .66
Legend:
A1
A
SEATING PLANE
.10
e
.51 MIN.
.53 / .33
R 1.14 / .64
D2 / E2
Symbol
A
A1
D1
D2
D3
E1
E2
E3
e
D
E
68 (in Millimeters)
Min
Max
4.20
5.08
2.29
3.30
24.13
24.33
22.61
23.62
20.32 BSC
24.13
24.33
22.61
23.62
20.32 BSC
1.27 BSC
25.02
25.27
25.02
25.27
SIDE VIEW
Figure 3. Package Dimensions
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2.2
Data Sheet
July 29, 2010
I/O Signal Description
Table 6 below describes the I/O characteristics for each signal on the IC. The signal names
correspond to the signal names on the pinout diagrams provided above. The (n) denotes active
low.
Table 6. I/O Signal Descriptions
Signal Name
Description
External Access enable. Since there is no internal ROM in the IA80C152,
this signal has no function in the JA and JC versions and should be set to 0.
For the JB and JD versions with EBEN, it controls program memory fetches
from ports 0, 2 or ports 5, 6. See Table 3.
E-bus Program Store ENable. When EBEN is 1, this signal is the read
strobe for external program memory. JB/JD versions only.
Program Store ENable. When EBEN is 0, this signal is the read strobe for
external program memory.
Reset. When this signal is low for 3 machine cycles, the device is put into
reset. The GSC may continue transmitting after reset is applied. An
internal pull-up allows the use of an external capacitor to generate a poweron reset.
Address Latch Enable. Latches the low-byte of external memory.
E-Bus ENable. In conjunction with EAn, EBEN designates program
memory fetches from either Port 0,2 or Port 5,6. See Table 3.
Port 0 - open drain 8-bit bi-directional port that is bit addressable and can
drive up to 8 LS TTL inputs. The port signals can be used as high
impedance inputs.
EAn
EPSENn
PSENn
RESETn
ALE
EBEN
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
This port also provides the low-byte of the multiplexed address and data
bus depending on the state of EBEN.
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Table 6. I/O Signal Descriptions (Continued)
Signal Name
P1.0 - GRXD, GSC
Receive
P1.1 - GTXD, GSC
Transmit
P1.2 - DENn, Driver Enable
P1.3 - TXCn, External
Transmit Clock
P1.4 - RXCn, External
Receive Clock
P1.5 - HLDn, DMA Hold
P1.6 - HLDAn, DMA Hold
Acknowledge
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0 - RXD, UART Receive
P3.1 - TXD, UART
Transmit
P3.2 - INT0n, External
Interrupt 0
P3.3 - INT1n, External
Interrupt 1
P3.4 - T0, Timer 0 External
Input
P3.5 - T1, Timer 1 External
Input
P3.6 - WRn, External Data
Memory Write Strobe
P3.7 - RDn, External Data
Memory Read Strobe
®
Description
Port 1—8-bit bi-directional port that is bit addressable. To use a port signal
as an input, write a 1 to the port location. Internal pull-ups pull the input
high and source current when the input is driven low. To use a port signal
as an output, a 1 or 0 written to the port location is presented at the output.
Port signals in this port also serve as I/O for IA80C152 functions. These I/O
signals are defined next to the port name.
Port 2—8-bit bi-directional port that is bit addressable. To use a port signal
as an input, write a 1 to the port location. Internal pull-ups pull the input
high and source current when the input is driven low. To use a port signal
as an output, a 1 or 0 written to the port location is presented at the output.
This port also provides the high-byte of the multiplexed address and data
bus depending on the state of EBEN.
Port 3—8-bit bi-directional port that is bit addressable. To use a port signal
as an input, write a 1 to the port location. Internal pull-ups pull the input
high and source current when the input is driven low. To use a port signal
as an output, a 1 or 0 written to the port location is presented at the output.
Port signals in this port also serve as I/O for IA80C152 functions. These I/O
signals are defined next to the port name.
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Table 6. I/O Signal Descriptions (Continued)
Signal Name
Description
Port 4—8-bit bi-directional port that is bit addressable. To use a port signal
as an input, write a 1 to the port location. Internal pull-ups pull the input
high and source current when the input is driven low. To use a port signal
as an output, a 1 or 0 written to the port location is presented at the output.
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
VCC
VSS
XTAL1
XTAL2
Port 5—8-bit bi-directional port that is NOT bit addressable. To use the port
as an input, write a 1 to the port location. Internal pull-ups pull the input
high and source current when the input is driven low. To use the port as an
output, 1s or 0s written to the port are presented at the output.
This port also provides the low-byte of the multiplexed address and data
bus depending on the state of EBEN.
Port 6—8-bit bi-directional port that is NOT bit addressable. To use the port
as an input, write a 1 to the port location. Internal pull-ups pull the input
high and source current when the input is driven low. To use the port as an
output, 1s or 0s written to the port are presented at the output.
This port also provides the high-byte of the multiplexed address and data
bus depending on the state of EBEN.
Supply Voltage
Device Ground
Input to the internal clock generator
Output from the internal oscillator amplifier
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3.
Data Sheet
July 29, 2010
Maximum Ratings, Thermal Characteristics, and DC Parameters
The absolute maximum ratings, thermal characteristics, and DC parameters are provided in
Tables 7 through 9, respectively. The input and output parametric values in the DC and AC
characteristics are directly related to ambient temperature and DC supply voltage. A temperature
or supply voltage range other than those specified in the operating conditions may affect these
values as well as adversely affect part performance and reliability.
Stresses beyond those listed in Table 7, Absolute Maximum Ratings, may cause permanent
damage to the device. Operating the device at or beyond the conditions indicated is not
recommended.
Table 7. Absolute Maximum Ratings
Parameter
Storage temperature
Voltage on any pin to vss
Operating temperature
Power dissipation
Rating
−40°C to +125°C
−0.3V to +(vDD + 0.3) V
-40°C to +85°C
391.1 mW (95°C, 16MHz, 15% Toggle)
Table 8. Thermal Characteristics
Symbol
TA
Characteristic
Ambient Temperature
®
Value
-40°C to 85°C
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Table 9. DC Parameters
Symbol
VCC
VIL
VIH
VOL
VOH
Parameter
Supply Voltage
Input Low Voltage (All Except XTAL1)
Input High Voltage (All Except XTAL1)
Output Low Voltage
Output High Voltage (All Except Port 0 in
port mode)
Typ
–
–
–
–
–
–
–
–
–
Max
5.5
0.9
–
0.4
–
–
–
–
1
Unit
V
V
V
V
V
Logical 0 Input Current
Min
4.5
–
2.1
–
3.5
–
3.5
–
-1
IIH
Logical 1 Input Current
-1
–
1
µA
Ioz
Input Leakage ( Port 0,1,2,3,4,5,6,
ALE,PSEN, EPSEN)
Pull-up Resistor, Pull-down Resistor
-10
–
10
µA
–
50
–
kW
Test Conditions
–
–
–
–
–
–
–
–
No pullup or
pulldown
No pullup or
pulldown
Tri-state leakage
current
–
VOH1
Output High Voltage (Port 0 in External Bus
Mode)
IIL
–
–
50
mA
–
–
–
–
–
mA
µA
–
–
Rup,
Rdn
IDDa
Power Supply Current: Active (16.5 MHz)
Idle (16.5 MHz) Power Down Mode
V
–
µA
aStatic Idd current is exclusive of input/output drive requirements and is measured with the clocks stopped and all
inputs tied to Vdd or Vss configured to draw minimum current.
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4.
Device Architecture
4.1
Functional Block Diagram
Data Sheet
July 29, 2010
Figure 4 shows the major functional blocks of the IA80C152. Each version of the IA80C152
function identically to each other with the exception of the 2 additional I/O ports (Port 5 and
Port 6) in the JB and JD versions.
I/O for Memory, GSC, DMA, UART, Interrupts, and Timers
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Memory
Control
XTAL
Clock Gen.
& Timing
Reset
C8051
CPU
256x8 RAM
Control
Address/Data
Interrupts
UART
Timers
DMA
GSC
= JB and JD versions only.
Figure 4. Functional Block Diagram
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4.2
Data Sheet
July 29, 2010
Memory Space
Memory space is divided up into program and data memory. Program memory is all external to
the IA80C152. Data memory is divided up into external and internal data memory. There can
be up to 64K bytes of external program and data memory. Internal data memory is 256 bytes
that is mapped between RAM, SFRs, and Register Banks. Figure 5 diagrams the organization of
the IA80C152 memory space. See the C8051 section for further details.
Program memory is accessed using control signals and ports. On the JA and JC versions of the
IA80C152 this access is performed through ports P0 and P2. Further, because there is no
internal ROM, the entire program memory space is accessed via ports P0 and P2. On the JB and
JD version of the IA80C152, program memory access can be through either ports P0 and P2, or
ports P5 and P6. Which set of ports program memory fetches are made through is controlled by
the input signals EAn and EBEN. Table 10 summarizes the IA80C152 versions and the
relationship to program memory fetches.
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Data Sheet
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FFFFH
C000H
8000H
FFH
Upper
128 Bytes
SFR Space
80H
4000H
7FH
Lower
128 Bytes
0000H
00H
External RAM
Internal RAM
Figure 5. Memory Space
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Table 10. Summary of Program Memory Fetches
Version
JA, JC
JB, JD
Fetch Control
EBEN EAn
NA
0 or 1
0
0
1
0
1
1
Fetch Signal
PSENn EPSENn
Active
–
Active
–
–
Active
–
Active
Active
–
Fetch Ports
P0, P2
P0, P2
P5, P6
P5, P6
P0, P2
5.
Peripheral Architecture
5.1
Registers and Interrupts
Memory Space
0h–FFFFh
0h–FFFFh
0h–FFFFh
0h–1FFFh
2000h–FFFFh
The IA80C152 combines the register set of the 8051BH and additional SFRs for the DMA and
GSC functions. Likewise, the IA80C152 combines the interrupts of the 8051BH and the
interrupts required by the DMA and GSC. Tables 11 and 12 list the IA80C152 registers
interrupts, respectively.
Table 11. List of Registers
Item
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Register
Name
A
ADR0
ADR1
ADR2
ADR3
AMSK0
AMSK1
B
BAUD
BCRL0
BCRH0
BCRL1
BCRH1
BKOFF
DARL0
DARH0
DARL1
DARH1
DCON0
DCON1
DPH
DPL
GMOD
IE
IEN1
Register
Address
0E0h
095h
0A5h
0B5h
0C5h
0D5h
0E5h
0F0h
094h
0E2h
0E3h
0F2h
0F3h
0C4h
0C2h
0C3h
0D2h
0D3h
092h
093h
083h
082h
084h
0A8h
0C8h
®
Functional
Block
C8051
GSC
GSC
GSC
GSC
GSC
GSC
C8051
GSC
DMA
DMA
DMA
DMA
GSC
DMA
DMA
DMA
DMA
DMA
DMA
C8051
C8051
GSC
C8051
DMA, GSC
Description
Accumulator
Address Match 0
Address Match 1
Address Match 2
Address Match 3
Address Mask 0
Address Mask 1
B Register
Baud Rate
Byte Count Register (Low) 0
Byte Count Register (High) 0
Byte Count Register (Low) 1
Byte Count Register (High) 1
Backoff Timer
Destination Address Register (Low) 0
Destination Address Register (High) 0
Destination Address Register (Low) 1
Destination Address Register (High) 1
DMA Control 0
DMA Control 1
Data Pointer High
Data Pointer Low
GSC Mode
Interrupt Enable
Interrupt Enable 1
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Initial
Value
00h
00h
00h
00h
00h
00h
00h
00h
00h
X
X
X
X
X
X
X
X
X
00h
00h
00h
00h
X0000000b
0XX00000b
XX000000b
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Table 11. List of Registers (Continued)
Item
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
Register
Name
IFS
IP
IPN1
MYSLOT
P0
P1
P2
P3
P4
P5
P6
PCON
PRBS
PSW
RFIFO
RSTAT
SARL0
SARH0
SARL1
SARH1
SBUF
SCON
SLOTTM
SP
TCDCNT
TCON
TFIFO
TH0
TH1
TL0
TL1
TMOD
TSTAT
Register
Address
0A4h
0B8h
0F8h
0F5h
080h
090h
0A0h
0B0h
0C0h
091h
0A1h
087h
0E4h
0D0h
0F4h
0E8h
0A2h
0A3h
0B2h
0B3h
099h
098h
0B4h
081h
0D4h
088h
085h
08Ch
08Dh
08Ah
08Bh
089h
0D8h
®
Functional
Block
GSC
C8051
DMA, GSC
GSC
C8051
C8051
C8051
C8051
C8051
C8051
C8051
C8051
GSC
C8051
GSC
GSC
DMA
DMA
DMA
DMA
C8051
C8051
GSC
C8051
GSC
C8051
GSC
C8051
C8051
C8051
C8051
C8051
GSC
Description
Interframe Space
Interrupt Priority
Interrupt Priority 1
GSC Slot Address
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Power Control
Pseudo-Random Sequence
Program Status Word
Receive FIFO
Receive Status
Source Address Register (Low) 0
Source Address Register (High) 0
Source Address Register (Low) 1
Source Address Register (High) 1
Serial Channel Buffer (UART)
Serial Channel Control (UART)
GSC Slot Time
Stack Pointer
Transmit Collision Counter
Timer Control
Transmit FIFO
Timer (High) 0
Timer (High) 1
Timer (Low) 0
Timer (Low) 1
Timer Mode
Transmit Status
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Initial
Value
00h
XXX00000b
XX000000b
00h
0FFh
0FFh
0FFh
0FFh
0FFh
0FFh
0FFh
0XXX0000b
00h
00h
X
00h
X
X
X
X
X
00h
00h
07h
X
00h
X
00h
00h
00h
00h
00h
XX000100b
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Table 12. List of Interrupts
Interrupt
Priority
–
1
2
3
4
5
6
7
8
9
10
11
5.2
Interrupt
Name
Enable All Interrupts
External Interrupt 0
GSC Receive Valid
Timer 0 Overflow
GSC Receive Error
DMA Channel 0 Done
External Interrupt 1
GSC Transmit Valid
DMA Channel 1 Done
Timer 1 Overflow
GSC Transmit Error
UART Transmit/Receive
Priority
Symbol
Name
–
PX0
PGSRV
PT0
PGSRE
PDMA0
PX1
PGSTV
PDMA1
PT1
PGSTE
PS
Enable
Symbol
Name
EA
EX0
EGSRV
ET0
EGSRE
EDMA0
EX1
EGSTV
EDMA1
ET1
EGSTE
ES
Priority
Address
–
0B8h
0F8h
0B9h
0F9h
0FAh
0BAh
0FBh
0FCh
0BBh
0FDh
0BCh
Enable
Address
0AFh
0A8h
0C8h
0A9h
0C9h
0CAh
0AAh
0CBh
0CCh
0ABh
0CDh
0ACh
Vector
Address
–
03h
2Bh
0Bh
33h
3Bh
13h
43h
53h
1Bh
4Bh
23h
Register Set Descriptions
The following are detailed descriptions for the IA80C152 register set. This register set is the
same for all versions of the IA80C152. There is no difference between the IA80C152 register
set and the register set for the original device.
In addition to the registers listed below, there are four banks of eight general purpose registers
(R0 through R7) which reside within internal RAM space. Selection of these register banks is
controlled through the Program Status Word (PSW).
The register descriptions are listed in alphanumeric order. The asterisk (*) indicates the register
is bit addressable.
5.2.1
A* (0E0h)
Accumulator register used for various memory, arithmetic, and logic operations.
5.2.2
ADR0,1,2,3 (095h, 0A5h, 0B5h, 0c5h)
Address match registers contain the values which determine which data will be accepted as valid
by the GSC. If using 8 bit addressing mode a match with any of the four registers will cause the
data to be accepted. If using 16 bit addressing mode a match with the pairs ADR1 and ADR0 or
ADR3 and ADR2 will cause the data to be accepted. A received address of all 1s will be
accepted regardless of whether the address mode is 16 bit or 8 bit.
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AMSK0,1 (0D5h, 0E5h)
Address Match Mask registers are used to set the corresponding bit in Address match registers to
don’t care. Setting the bit to a one in the AMSK register sets the corresponding bit in the ADR
register to don’t care.
5.2.4
B* (0F0h)
The B register used for multiply and divide instructions. May also be used as a general purpose
register.
5.2.5
BAUD (094h)
Contains the value to be used by the baud rate determining equation. The value written to
BAUD will actually be stored in a reload register. When the BAUD register contents are
decremented to 00H the BAUD register will be reloaded from the reload register. Reading the
BAUD register yields the current baud rate timer value. A read during a GSC operation may not
give the current value because the value in BAUD could decrement after it is read and before the
read value can be stored in its destination. BAUD rate = Fosc/((BAUD + 1)*8)
5.2.6
BCRL0, BCRH0 (0E2h, 0E3h)
Byte count register low and high bytes for DMA channel 0. The two registers provide a 16-bit
value representing the number of DMA transfers via channel 0. Valid count range is from 0
to 65535.
5.2.7
BCRL1, BCRH1 (0F2h, 0F3h)
Byte count register low and high bytes for DMA channel 1. The two registers provide a 16-bit
value representing the number of DMA transfers via channel 1. Valid count range is from 0
to 65535.
5.2.8
BKOFF (0C4h)
An 8 bit count down timer with a clock period equal to one slot time. A user may read the
register, but the register is clocked asynchronously to the CPU so invalid data can result.
Writing to BKOFF will have no effect.
5.2.9
DARL0, DARH0 (0C2h, 0C3h)
Destination address register low and high bytes for DMA channel 0. The two registers provide a
16-bit value representing the address of the destination for a DMA transfer via channel 0. Valid
address range is from 0 to 65535.
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5.2.10 DARL1, DARH1 (0D2h, 0D3h)
Destination address register low and high bytes for DMA channel 1. The two registers provide a
16-bit value representing the address of the destination for a DMA transfer via channel 1. Valid
address range is from 0 to 65535.
5.2.11 DCON0,1 (092h, 093h)
DCON0 and DCON1 control DMA channel 0 or 1, respectively. Each bit in these 8-bit registers
control the DMA transfer as described in Table 13.
Table 13. DCON0,1 Register
7
DAS
6
IDA
5
SAS
4
ISA
3
DM
2
TM
1
DONE
0
GO
Bit [7]—DAS → This bit in conjunction with IDA determines the destination address
space.
Bit [6]—IDA → If IDA is set to 1 then the destination address is automatically
incremented after the transfer of each byte.
DAS
0
0
1
1
IDA
0
1
0
1
Destination
External Ram
External Ram
SFR
Internal RAM
Auto-Increment
NO
YES
NO
YES
Bit [5]—SAS → This bit in conjunction with ISA determines the source address space.
Bit [4]—ISA → If ISA is set to 1, the source address is automatically incremented after
the transfer of each byte.
SAS
0
0
1
1
ISA
0
1
0
1
Source
External Ram
External Ram
SFR
Internal RAM
Auto-Increment
NO
YES
NO
YES
Bit [3]—DM → If this bit is set to 1, the DMA channel operates in demand mode. In this
mode the DMA is initiated by either an external signal or by a serial port flag depending
on the value of the TM bit. If the DM bit is set to 0, DMA is initiated by setting the GO
bit.
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Bit [2]—TM → If DM is 1, TM selects if DMA is initiated by an external signal (TM=1)
or by a serial port bit (TM=0). If DM is 0, TM selects whether DMA transfers are in
burst mode (TM=1) or in alternate cycles mode (TM=0).
DM
0
0
1
1
TM
0
1
0
1
Mode
Alternate Cycles
Burst
LSC/GSC Interrupt Demand
External Interrupt Demand
Bit [1]—DONE → This bit indicates that the DMA operation has completed. It also
causes an interrupt. This bit is set to 1 when BCRn equals 0 and is set to 0 when the
interrupt is vectored. The user can also set and clear this bit.
Bit [0]—GO → If this bit is set to 1, it enables the DMA channel.
5.2.12 DPL, DPH (082h, 083h)
DPTR, or the ―data pointer‖ consists of the two 8-bit registers, DPL and DPH. The DPTR must
be used for accesses to external memory requiring 16-bit addresses.
5.2.13 GMOD (084h)
An 8-bit register that controls the GSC Modes as described in Table 14.
Table 14. GMOD Register
7
XTCLK
6
M1
5
M0
4
AL
3
CT
2
PL1
1
PL0
0
PR
Bit [7]—XTCLK → This bit enables the use of an external transmit clock. A 1 enables
the external clock (input on port 1, bit 3), a zero enables the internal baud rate generator.
Bits [6–5]—M1, M0 → These bits are the backoff mode and test mode select bits as
defined in the following table.
M1
0
0
1
1
M0
0
1
0
1
Mode
Normal
Raw Transmit
Raw Receive
Alternate Backoff
In Raw Receive mode the transmitter operates normally. The receiver operates normally
except that all the bytes following the BOF are loaded into the receive FIFO including the
CRC.
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In the Raw Transmit mode the receiver operates as normal and zero bit detection is
performed in SDLC mode. The transmit output is internally connected to the receiver
input for loopback testing. Data transmitted is done so without a preamble, flag or zero
bit insertion and without a CRC.
In the Alternate Backoff mode the backoff is modified so it is delayed until the end of the
IFS. Since the IFS time is generally longer than the slot time this should help to prevent
collisions.
Bit [4]—AL → This bit determines the address length used. If set to a 1, the 16-bit
addressing is used. If set to a 0, the 8 bit addressing is used.
Bit [3]—CT → This bit determines the CRC type used. If set to a 1, the 32-bit
AUTODIN II-32 is used. If set to a 0, the 16 bit CRC-CCITT is used.
Bits [2–1]—PL0, PL1 → Preamble length:
PL1
0
0
1
1
PL0
0
1
0
1
Preamble length in bits
0
8
32
64
The length noted in the table includes the two-bit BOF in CSMA/CD mode but not the
SDLC flag. Zero length preamble is not compatible with CSMA/CD mode.
Bit [0]—PR → If set to a 1, the GSC is in SDLC mode. If set to a 0, the GSC is in
CSMA/CD mode.
5.2.14 IE* (0A8h)
The Interrupt Enable register allows the software to select which interrupts are enabled as shown
in Table 15. If a bit is 0, the interrupt is disabled. If a bit is 1, the interrupt is enabled.
Table 15. IE* Register
7
EA
6
Reserved
5
Reserved
4
ES
3
ET1
2
EX1
1
ET0
0
EX0
Bit [7]—EA → Enable All interrupts. This bit globally enables or disables all interrupts
regardless of the state of the individual bits.
Bit [6]—Reserved.
Bit [5]—Reserved.
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Bit [4]—ES → Enable or disable serial port interrupt.
Bit [3]—ET1 → Enable or disable Timer 1 overflow interrupt.
Bit [2]—EX1 → Enable or disable External Interrupt 1.
Bit [1]—ET0 → Enable or disable Timer 0 overflow interrupt.
Bit [0]—EX0 → Enable or disable External Interrupt 0.
5.2.15 IEN1* (0C8h)
The Interrupt Enable Number 1 register allows the software to select which interrupts are
enabled as shown in Table 16. If a bit is 0, the interrupt is disabled. If a bit is 1, the interrupt is
enabled.
Table 16. IEN1* Register
7
Reserved
6
Reserved
5
EGSTE
4
EDMA1
3
EGSTV
2
EDMA0
1
EGSRE
0
EGSRV
Bit [7]—Reserved.
Bit [6]—Reserved.
Bit [5]—EGSTE → Enable or disable GSC Transmit Error interrupt.
Bit [4]—EDMA1 → Enable or disable DMA channel 1 interrupt.
Bit [3]—EGSTV → Enable or disable GSC Transmit Valid interrupt.
Bit [2]—EDMA0 → Enable or disable DMA channel 0 interrupt.
Bit [1]—EGSRE → Enable or disable GSC Receive Error interrupt.
Bit [0]—EGSRV → Enable or disable GSC Receive Valid interrupt.
5.2.16 IFS (0A4h)
The Interframe Spacing register determines the number of bit times between transmitted frames
in both CSMA/CD and SDLC. Only even bit times can be used. The number written to this
register is divided by two and loaded into the seven most significant bits. An interframe space is
created by counting down this seven bit number twice. The value read from this register is the
current count value in the upper seven bits and the first or second count down in the LSB. A 1
indicates the first count down and a 0 indicates the second count down. The value may not be
valid because the register is clocked asynchronously to the CPU.
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5.2.17 IP* (0B8h)
The Interrupt Priority register allows the software to select which interrupts have a higher than
normal priority. If a bit is 0, the interrupt has normal priority. If a bit is 1, the interrupt has a
higher priority. When multiple bits are set to higher priority, interrupts are resolved in the same
order as their normal priority setting (see Table 17).
Table 17. IP* Register
7
Reserved
6
Reserved
5
Reserved
4
PS
3
PT1
2
PX1
1
PT0
0
PX0
Bit [7]—Reserved.
Bit [6]—Reserved.
Bit [5]—Reserved.
Bit [4]—PS → Set normal or high priority level for serial port interrupt.
Bit [3]—PT1 → Set normal or high priority level for Timer 1 overflow interrupt.
Bit [2]—PX1 → Set normal or high priority level for External Interrupt 1.
Bit [1]—PT0 → Set normal or high priority level for Timer 0 overflow interrupt.
Bit [0]—PX0 → Set normal or high priority level for External Interrupt 0.
5.2.18 IPN1* (0F8h)
The Interrupt Priority Number 1 register allows the software to select which interrupts have a
higher than normal priority. If a bit is 0, the interrupt has normal priority. If a bit is 1, the
interrupt has a higher priority. When multiple bits are set to higher priority, interrupts are
resolved in the same order as their normal priority setting (see Table 18).
Table 18. IPN1* Register
7
Reserved
6
Reserved
5
PGSTE
4
PDMA1
3
PGSTV
2
PDMA0
1
PGSRE
0
PGSRV
Bit [7]—Reserved.
Bit [6]—Reserved.
Bit [5]—PGSTE → Set normal or high priority level for GSC Transmit Error interrupt.
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Bit [4]—PDMA1 → Set normal or high priority level for DMA channel 1 interrupt.
Bit [3]—PGSTV → Set normal or high priority level for GSC Transmit Valid interrupt.
Bit [2]—PDMA0 → Set normal or high priority level for DMA channel 0 interrupt.
Bit [1]—PGSRE → Set normal or high priority level for GSC Receive Error interrupt.
Bit [0]—PGSRV → Set normal or high priority level for GSC Receive Valid interrupt.
5.2.19 MYSLOT (0F5h)
Register that controls the slot address for the devices as well as the type of Jam used and which
backoff algorithm is used during a collision (see Table 19).
Table 19. MYSLOT Register
7
DCJ
6
DCR
5
SA5
4
SA4
3
SA3
2
SA2
1
SA1
0
SA0
Bit [7]—DCJ → A 1 selects DC type jam. A 0 selects AC type jam.
Bit [6]—DCR → The Deterministic Collision Resolution register determines which
resolution algorithm to use. Setting this bit to a 1 selects the deterministic resolution
algorithm. The user must initialize TCDCNT with the maximum number of slots that are
appropriate for the system. To disable the PBRS this register must be set to all 1s. If
DCR is cleared to 0 then a random slot assignment is used. The type of random backoff
used is selected by bits M1, M0 of the GMOD register.
Bits [5–0]—SA5–SA0 → The six-slot address bits determine not only the address but
also the priority. Addresses 0 through 63 are available with 63 having the highest priority
and 1 the lowest. An address of 0 will prevent a station from transmitting during the
collision resolution period.
5.2.20 P0*, P1*, P2*, P3*, P4*, P5, P6 (080h, 090h, 0A0h, 0Boh, 0C0h, 091h, 0A1h)
These registers are for I/O as defined in Table 20. Most registers have a dual function. P5 and
P6 are not bit addressable and are only available in the JB and JD versions of the IC.
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Table 20. P0*, P1*, P2*, P3*, P4*, P5, P6 Register
P0
P1
P2
P3
P4
P5
P6
Port
Function
Bit Address
Function
Bit Address
Function
Bit Address
Function
Bit Address
Function
Bit Address
Function
Bit Address
Function
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Multiplexed Address/Data
087h
086h
085h
084h
083h
082h
–
HLDAn HLDn RXCn TXCn DENn
097h
096h
095h
094h
093h
092h
Address and User Defined
0A7h
0A6h
0A5h 0A4h
0A3h
0A2h
RDn
WRn
T1
T0
INT1n INT0n
0B7h
0B6h
0B5h 0B4h
0B3h
0B2h
User Defined
0C7h
0C6h
0C5h 0C4h 0C3h
0C2h
User Defined
091h
User Defined
0A1h
Bit 1
Bit 0
081h
GTXD
091h
080h
GRXD
090h
0A1h
TXD
0B1h
0A0h
RXD
0B0h
0C1h
0C0h
5.2.21 PCON (087h)
The Power Control register controls the power down and idle states of the IA80C152 as well as
various UART, GSC, and DMA functions as defined in Table 21.
Table 21. PCON Register
7
SMOD
6
ARB
5
REQ
4
GAREN
3
XRCLK
2
GFIEN
1
PD
0
IDL
Bit [7]—SMOD → Doubles the baud rate of the UART if the bit is set to 1.
Bit [6]—ARB → The DMA (both channels) is put into Arbiter mode if the bit is set to 1.
Bit [5]—REQ → The DMA (both channels) is put into Requester mode if the bit is set
to 1.
Bit [4]—GAREN → The GSC Auxiliary Receive Enable allows the GSC to receive
back-to-back SDLC frames by setting the bit to 1. This bit has no effect in CSMA mode.
Bit [3]—XRCLK → Setting this bit enables the External Receive Clock to be used by the
receiver portion of the GSC.
Bit [2]—GFIEN → The GSC Flag Idle Enable bit generates idle flags between
transmitted SDLC frames when this bit is set to a 1. This bit has no effect in CSMA
mode.
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Bit [1]—PD → The Power Down bit puts the IA80C152 into the power down power
saving mode by setting this bit to a 1.
Bit [0]—IDL → The Idle bit puts the IA80C152 into the idle power saving mode by
setting this bit to a 1.
5.2.22 PRBS (0E4h)
This register contains the pseudo-random number to be used in the CSMA/CD backoff
algorithm. The number is generated by using a feedback shift register clocked by the CPU phase
clocks. Writing all 1s to this register will cause the register to freeze at all 1s. Writing any other
value to it will cause it to start again. A read of this register will not always give the seed value
due to the register being clocked by the CPUs phase clocks.
5.2.23 PSW* (0D0h)
The Program Status Word register provides arithmetic and other microcontroller status as well as
control for the selection of register banks 0 through 4 (see Table 22).
Table 22. PSW* Register
7
CY
6
AC
5
F0
4
RS1
3
RS0
2
OV
1
Reserved
0
P
Bit [7]—CY → Carry Flag set to 1 if an instruction execution results in a carry/borrow
from/to bit 7.
Bit [6]—AC → Auxiliary Carry Flag set to 1 if an instruction execution results in a
carry/borrow from/to bit 3.
Bit [5]—F0 → Flag 0 available for user defined general purpose.
Bits [4–3]—RS1, RS0 → Register bank Select 1 bit and Register bank Select 0 bit in
combination define the current register bank to be used by the microprocessor. See table
below.
Register Bank
0
1
2
3
RS1
0
0
1
1
RS0
0
1
0
1
Register Bank Addresses
00h-07h
08h-0Fh
10h-17h
18h-1Fh
Bit [2]—OV → The Overflow bit indicates an arithmetic overflow when set to a 1.
Bit [1]—Reserved.
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Bit [0]—P → Parity flag set or cleared by the hardware each instruction to indicate odd
or even number of 1s in the accumulator.
5.2.24 RFIFO (0F4h)
This is a three-byte buffer which points to the oldest data in the buffer. The buffer is loaded with
receive data every time the GSC receiver receives a new byte of data.
5.2.25 RSTAT* (0E8h)
This register provides status of the GSC receiver as defined in Table 23.
Table 23. RSTAT* Register
7
OVR
6
RCABT
5
AE
4
CRCE
3
RDN
2
RFNE
1
GREN
0
HABEN
Bit [7]—OVR → This bit is set by the GSC to indicate that the receive FIFO was full and
then new data was shifted into it. AE and /or CRCE may also be set. This flag is cleared
by the user.
Bit [6]—RCABT → This bit is set by the GSC when a collision is detected after data has
been loaded into the receive FIFO in CSMA/CD mode. In SDLC mode this bit indicates
that 7 consecutive 1s were detected before an end flag but after data was loaded into the
receive FIFO. AE may also be set.
Bit [5]—AE → This bit is set by the GSC in CSMA/CD mode to indicate that the
receiver shift register is not full and the CRC is bad when the EOF was detected. If the
CRC is correct AE will not be set and a misalignment will be assumed to be caused by
―dribble bits‖ as the line went idle. In SDLC mode AE is set if a non-byte aligned flag is
received. CRCE may also be set.
Bit [4]—CRCE → This bit is controlled by the GSC and if set indicates that a properly
aligned frame was received with a mismatched CRC.
Bit [3]—RDN → This bit is controlled by the GSC and if set indicates a successful
receive operation has occurred. This bit will not be set if a CRC, alignment, abort, or
FIFO overrun error occurred.
Bit [2]—RFNE → This bit if set indicates that the receive FIFO is not empty. This flag is
controlled by the GSC. If all the data is read from the FIFO the GSC will clear the bit.
Bit [1]—GREN → When this bit is set the receiver is enabled to accept incoming frames.
RFIFO should be cleared before setting this bit by reading RFIFO until RFNE = 0. This
should be done because setting GREN to a 1 clears RFIFO. It takes twelve clock cycles
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for the status of RFNE to be updated after a read of RFIFO. Setting GREN also clears
RDN, CRCE, AE and RCABT. GREN is cleared by hardware at the end of a reception
or if receive errors are encountered. The user is responsible for setting this bit to a 1.
The user or the GSC can set this bit to a 0. In CSMA/CD mode the status of GREN has
no effect on whether the receiver detects a collision because the receiver always
monitors the receive pin.
Bit [0]—HABEN → The Hardware Based Acknowledge Enable when set to a 1 enables
this feature.
5.2.26 SARL0, SARH0 (0A2h, 0A3h)
Source address register low and high bytes for DMA channel 0. The two registers provide a
16-bit value representing the address of the source for a DMA transfer via channel 0. Valid
address range is from 0 to 65535.
5.2.27 SARL1, SARH1 (0B2h, 0B3h)
Source address register low and high bytes for DMA channel 1. The two registers provide a
16-bit value representing the address of the source for a DMA transfer via channel 1. Valid
address range is from 0 to 65535.
5.2.28 SBUF (099h)
Writes to this register load the transmit register, and reads access the receive register of the LSC.
5.2.29 SCON* (098h)
This register controls the set up of the UART as defined by Table 24.
Table 24. SCON* Register
7
SM0
6
SM1
5
SM2
4
REN
3
TB8
2
RB8
1
TI
0
RI
Bits [7–6]—SM0, SM1 → The combination of these 2 bits controls the mode and type of
baud rate.
Mode
0
1
2
3
SM0
0
0
1
1
®
SM1
0
1
0
1
Description
Shift Register
8-bit UART
9-bit UART
9-bit UART
Baud Rate
(Osc. Freq.)/12
Variable
(Osc. Freq.)/64 or (Osc. Freq.)/32
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Bit [5]—SM2 → When this bit is set and the UART mode is 1, RI will not be activated
unless a valid stop bit is received. When this bit is set and the UART mode is 2 or 3, RI
will not be activated if the 9th bit is 0. In mode 0 SM2 should be set to 0.
Bit [4]—REN → Setting this bit enables the UART to receive. Clearing this bit disables
UART reception.
Bit [3]—TB8 → In modes 2 and 3, the value of this bit is transmitted during the 9th bit
time. This bit is set or cleared by software.
Bit [2]—RB8 → In modes 2 and 3, this bit is the value of the 9th bit that was received by
the UART. In mode 1 with SM2 = 1, this bit is the value of the stop bit received by the
UART. In mode 0 RB8 is not used.
Bit [2]—TI → Transmit Interrupt flag set by hardware at the end of the 8th bit in mode 0
or at the beginning of the stop bit in modes 1, 2, or 3. This bit must be cleared by
software to clear the interrupt.
Bit [0]—RI → Receive Interrupt flag set by hardware at the end of the 8th bit in mode 0
or halfway through the stop bit in modes 1, 2, or 3. This bit must be cleared by software
to clear the interrupt.
5.2.30 SLOTTM (0B4h)
Determines the length of the slot time in CSMA/CD mode. A slot time equals SLOTTM *
(1/baud rate). Reads from this location are unreliable because this register is clocked
asynchronously to the CPU. Loading a value of 0 results in a slot time of 256 bit times.
5.2.31 SP (081h)
This register is the stack pointer. Its value points to the memory location that is the beginning of
the stack.
5.2.32 TCDCNT (0D4h)
If probabilistic CSMA/CD is used this register contains the number of collisions. The user must
clear this register before transmitting a new frame so the GSC can distinguish between a new
frame and the retransmit of a frame. In deterministic backoff mode TCDCNT is used to hold the
maximum number of slots.
5.2.33 TCON* (088h)
This register controls the operation of the Timers 0 and 1 and External Interrupts 0 and 1 as
defined by Table 25.
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Table 25. TCON* Register
7
TF1
6
TR1
5
TF0
4
TR0
3
IE1
2
IT1
1
IE0
0
IT0
Bit [7]—TF1 → Timer overFlow 1 interrupt flag set by hardware when timer 1
overflows. Hardware clears this flag when the processor vectors to the interrupt service
routine.
Bit [6]—TR1 → Timer Run 1 flag set by software to turn on timer 1 and cleared by
software to turn off timer 1.
Bit [5]—TF0 → Timer overFlow 0 interrupt flag set by hardware when timer 0
overflows. Hardware clears this flag when the processor vectors to the interrupt service
routine.
Bit [4]—TR0 → Timer Run 0 flag set by software to turn on timer 0 and cleared by
software to turn off timer 0.
Bit [3]—IE1 → Interrupt External 1 flag set by hardware when an edge is detected on
External Interrupt 1. Hardware clears this flag when the processor vectors to the interrupt
service routine.
Bit [2]—IT1 → Interrupt Type 1 flag is set by software to specify a falling edge triggered
interrupt for External Interrupt 1. The flag is cleared by software to specify a low level
triggered interrupt for External Interrupt 1.
Bit [1]—IE0 → Interrupt External 0 flag set by hardware when an edge is detected on
External Interrupt 0. Hardware clears this flag when the processor vectors to the interrupt
service routine.
Bit [0]—IT0 → Interrupt Type 0 flag is set by software to specify a falling edge triggered
interrupt for External Interrupt 0. The flag is cleared by software to specify a low level
triggered interrupt for External Interrupt 0.
5.2.34 TFIFO (085h)
This is the 3 byte buffer used for storing GSC transmit data. If TEN is set to a 1 transmission
begins as soon as data is written to TFIFO.
5.2.35 TH0, TL0 (08Ch, 08Ah)
These registers provide the high byte (TH0) and low byte (TL0) values for Timer 0. These
registers may be used together or separately depending on Timer 0 mode bits.
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5.2.36 TH1, TL1 (08Dh, 08Bh)
These registers provide the high byte (TH0) and low byte (TL0) values for Timer 0. These
registers may be used together or separately depending on Timer 0 mode bits.
5.2.37 TMOD (089h)
This register controls the set up and modes of Timers 0 and 1 as defined by Table 26.
Table 26. TMOD Register
7
GATE
6
5
Timer 1
C/Tn M1
4
3
M0
GATE
2
1
Timer 0
C/Tn M1
0
M0
Bits [7,3]—GATE → When this bit is set, Timers/Counters may be turned on or off by
the corresponding External Interrupt being high, if the appropriate TR bit is set. When
this bit is cleared, Timers/Counters may only be turned on or off by the appropriate TR
bit.
Bits [6,2]—C/Tn → Counter/Timer flag. Set by software for Counter operation, cleared
by software for Timer operation.
Bit [5,4,1,0]—M1, M0 → Set the mode of the Timers/Counters as defined by the table
below.
Mode
0
1
2
3
M1
0
0
1
1
M0
0
1
0
1
Description
8-bit Timer (THx) with 5-bit Prescalar (TLx)
16-bit Timer/Counter (THx cascaded with TLx)
8-bit Auto Reload Timer/Counter (THx), Reload Value (THx)
One 8-bit Timer/Counter (TL0) controlled by Timer 0 control bits.
One 8-bit Timer/Counter (TH0) controlled by Timer 1 control bits. Timer 1 is
stopped.
5.2.38 TSTAT* (0D8h)
This register provides status of the GSC transmitter as defined by Table 27.
Table 27. TMOD Register
7
LNI
6
NOACK
5
UR
4
TCDT
3
TDN
2
TFNF
1
TEN
0
DMA
Bit [7]—LNI → The GSC sets this bit to indicate that the receive line is idle. In
CSMA/CD mode LNI is set if GRXD remains high for ~ 1.6 bit times. LNI is cleared
after a transition on GRXD. In SDLC node LNI is set if 15 consecutive ones are
received.
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Bit [6]—NOACK → The GSC sets this bit to indicate that an acknowledge was not
received for the previous frame. This bit will be set only if HABEN is set and no
acknowledge is received before the end of the IFS. NOACK will not be set following a
broadcast or a multi-cast packet.
Bit [5]—UR → The GSC sets this bit to indicate that in DMA mode the last bit was
shifted out of the transmit register and that the DMA byte count did not equal 0. When
this occurs the transmitter stops without sending the CRC and the end flag.
Bit [4]—TCDT → The GSC sets this bit to indicate that the transmission stopped due to a
collision. The bit is set by a collision occurring during the data, the CRC or if there are
more than 8 collisions.
Bit [3]—TDN → The GSC sets this bit to indicate that a frame transmission completed
successfully. If HABEN is set, TDN will not be set until the end of the IFS so that the
acknowledge can be checked. TDN will not be set if an acknowledge is expected but not
received. An acknowledge will not be expected after a broadcast or a multi-cast packet.
Bit [2]—TFNF → If this bit is a 1 TFIFO is not full and new data may be written to it.
Bit [1]—TEN → When TEN is set it will cause TDN, UR, TCDT and NOACK to be
reset and the TFIFO to be cleared. The transmitter will clear TEN after a successful
transmission, a collision during data, CRC or end flag. The user sets the bit and the user
of the GSC can clear the bit. If the bit is cleared during a transmission the transmit pin
goes to a high level. This is the method used to send an abort character in SDLC. DEN
is also forced to a high level. An end of transmission occurs whenever the TFIFO is
emptied.
Bit [0]—DMA → If this bit is set it indicates that the DMA channels are used to service
the RFIFO and TFIFO and that GSC interrupts occur on TDN and RDN. If set it also
enables UR to become set. If this bit is cleared it indicates that the GSC is operating in
normal mode and interrupts occur on TFNF and RFNE.
5.3
Power Conservation Modes
There are 2 power conservation modes identified as Idle Mode and Power Down Mode. The
IA80C152 pins will have values according to the Table 28 below.
Idle Mode is entered through software control of the PCON register. Idle halts processor
execution and the DMA. The GSC continues to operate to the extent that it can without the
processor or DMA servicing its requests. Idle mode is exited upon receipt of any enabled
interrupt or invoking a hardware reset.
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Power Down Mode is entered through software control of the PCON register. Power Down
disables the oscillator causing all functions to stop. RAM data is maintained because power is
not removed from the device. The only way to exit power down mode is to invoke a hardware
reset.
Table 28. Power Conservation Modes
Mode
Idle
Power
Down
Program
Fetch
P0, P2
P5, P6a
P0, P2
P5, P6a
ALE
1
1
0
0
aJB
and JD versions only.
5.4
Oscillator Pins
PSENn
1
1
0
1
EPSENna
1
1
1
0
Port
0
Float
Data
Float
Data
Port
1
Data
Data
Data
Data
Port
2
Addr.
Data
Data
Data
Port
3
Data
Data
Data
Data
Port
4
Data
Data
Data
Data
Port
5a
Data
0FFh
Data
0FFh
Port
6a
Data
Addr.
Data
0FFh
There are 2 methods for providing a clock to the IA80C152. One method is to provide a crystal
oscillator and the other method is to provide an external clock source. When providing a crystal
oscillator, the XTAL1 pin is the input and XTAL2 is the output. The min and max crystal
frequencies are 3.5 and 16.5 MHz, respectively.
When providing an external clock source, XTAL1 is the input and XTAL2 has no connection.
Duty cycle does not matter to the device, however, the external clock source requires a minimum
pulse width of 20 ns.
Figures 6 through 13 present the external program memory read cycle, the external data memory
read cycle, the external data memory write cycle, the external clock drive waveform, the shift
register mode timing waveforms, the GSC receiver timings (internal baud rate generator), the
GSC transmit timings (internal baud rate generator), the GSC timings (external clock)
respectively. Tables 29 through 32 present the external clock drive, the local serial channel
timing—shift register mode, the global serial port timing—internal baud rate generator, and the
global serial port timing—external clock, respectively.
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TLHLL
ALE
TLLPL
TLLIV
TPLIV
TAVLL
TPLPH
PSENn/EPSENn
TPLAZ
TLLAX
PORT0/PORT5
A0-A7
TPXIZ
TPXIX
INSTR IN
A0-A7
TAVIV
PORT2/PORT6
A8-A15
A8-A15
Figure 6. External Program Memory Read Cycle
ALE
TLLDV
TWHLH
PSENn
TLLWL
TRLRH
RDn
TLLAX
TAVLL
PORT 0
TRLAZ
TRHDZ
TRLDV
TRHDX
DATA IN
A0-A7 FROM R OR DPL
A0-A7 FROM PCL
INSTR. IN
TAVWL
TAVDV
PORT 2
P2.0–P2.7 OR A8–A15 FROM DPH
A8–A15 FROM PCH
Figure 7. External Data Memory Read Cycle
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ALE
PSENn
TLLWL
TWLWH
TWHLH
WRn
TLLAX
TAVLL
PORT0
A0-A7 FROM R OR DPL
TQVWX
DATA OUT
TWHQX
A0-A7 FROM PCL
INSTR. IN
TAVWL
PORT2
P2.0-P2.7 OR A8-A15 FROM DPH
A8-A15 FROM PCH
Figure 8. External Data Memory Write Cycle
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Table 29. External Clock Drive
Symbol
Parameter
Min
Max
Units
1/TCLCL
Oscillator Frequency
0
16.5
MHz
TCHCX
High Time
20
–
ns
TCLCX
Low Time
20
–
ns
TCLCH
Rise Time
–
TBD
ns
TCHCL
Fall Time
–
TBD
ns
Vcc - 0.5
0.7 Vcc
0.2 Vcc - 0.1
0.45V
TCHCL
TCHCX
TCLCH
TCLCX
TCLCL
Figure 9. External Clock Drive Waveform
Table 30. Local Serial Channel Timing—Shift Register Mode
Symbol
TXLXL
TQVXH
TXHQX
TXHDX
TXHDV
Parameter
Serial Port Clock Cycle Time
Output Data Setup to Clock Rising Edge
Output Data Hold After Clock Rising Edge
Input Data Hold After Clock Rising Edge
Clock Rising Edge to Input Data Valid
®
16.5 MHz
Min
Max
727
–
570
–
10
–
0
–
–
480
Variable Oscillator
Min
Max
12TCLCL
–
10TCLCL-133
–
2TCLCL-117
–
0
–
–
10TCLCL-133
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ns
ns
ns
ns
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|
0
|
1
|
2
Data Sheet
July 29, 2010
|
3
|
4
|
5
|
6
|
7
|
8
|
ALE
TXLXL
CLOCK
TQVXH
OUTPUT_DATA
0
|_________|
^|
WRITE TO SBUF
INPUT_DATA
VALID
TXHQ
X
1
2
3
4
5
6
7
^|
SET T1
TXHD
X
TXHDV
VALID
VALID
VALID
VALID
VALID
VALID
VALID
^|
|____________
| ^|
SET R1
CLEAR R1
Figure 10. Shift Register Mode Timing Waveforms
Table 31. Global Serial Port Timing—Internal Baud Rate Generator
Symbol
HBTJR
FBTJR
HBTJT
FBTJT
DRTR
DFTR
Parameter
Allowable jitter on the Receiver for 1/2
bit time (Manchester encoding only)
Allowable jitter on the Receiver for one
full bit time (NRZI and Manchester)
Jitter of data from Transmitter for 1/2
bit time (Manchester encoding only)
Jitter of data from Transmitter for one
full bit time (NRZI and Manchester)
Data rise time for Receiver
Data fall time for Receiver
®
16.5 MHz
(BAUD = 0)
Min
Max
–
0.06
Min
–
Variable Oscillator
Max
(0.125 × (BAUD + 1)
× 8TCLCL) - 25ns
(0.125 × (BAUD + 1)
× 8TCLCL) - 25ns
±10
Unit
µs
–
0.06
–
–
±10
–
–
±10
–
±10
ns
–
–
TBD
TBD
–
–
20.00
20.00
ns
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HBTJR
FBTJR
HBTJR
FBTJR
MANCHESTER
GRxD
BT
FBTJR
FBTJR
NRZI
GRxD
Figure 11. GSC Receiver Timings (Internal Baud Rate Generator)
HBTJT
FBTJT
HBTJT
FBTJT
GTxD
MANCHESTER
BT
FBTJT
FBTJT
NRZI
GTxD
Figure 12. GSC Transmit Timings (Internal Baud Rate Generator)
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Table 32. Global Serial Port Timing—External Clock
16.5 MHz
Min Max
–
2.4
Symbol
1/ECBT
Parameter
GSC frequency with an external clock
ECH
ECL
ECRT
ECFT
ECDVT
External clock high
External clock low
External clock rise time
External clock fall time
External clock to data valid out—transmit
(to external clock negative edge)
External clock to data hold—transmit (to
external clock negative edge)
External clock to data set-up—receiver (to
external clock positive edge)
External clock to data hold—receiver (to
external clock positive edge)
ECDHT
ECDSR
ECDHR
170
170
–
–
–
Variable Oscillator
Min
Max
–
Fosc ×
0.145
– 2TCLCL + 45
–
– 2TCLCL + 45
–
TBD
–
20
TBD
–
20
33
–
150
Unit
MHz
ns
ns
ns
ns
ns
3
–
0
–
ns
55
–
45
–
ns
63
–
50
–
ns
ECBT
ECL
ECH
EXTERNAL_CLOCK
ECDHT
TRANSMIT_DATA
ECBT
ECDVT
EXTERNAL_CLOCK
ECDHR
ECDSR
RECEIVE_DATA
Figure 13. GSC Timings (External Clock)
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6.
Data Sheet
July 29, 2010
Instruction Set Summary Table
Table 33 provides a summary of the instruction set organized by hexadecimal opcode. Please
refer to the original Intel Data Book for individual instruction set details.
Table 33. Instruction Set Summary
Opcode
00 H
01 H
02 H
03 H
04 H
05 H
06 H
07 H
08 H
09 H
0A H
0B H
0C H
0D H
0E H
0F H
10 H
11 H
12 H
13 H
14 H
15 H
16 H
17 H
18 H
19 H
1A H
1B H
1C H
1D H
1E H
1F H
20 H
21 H
22 H
23 H
24 H
25 H
26 H
27 H
28 H
Mnemonic
NOP
AJMP addr11
LJMP addr16
RR A
INC A
INC direct
INC @R0
INC @R1
INC R0
INC R1
INC R2
INC R3
INC R4
INC R5
INC R6
INC R7
JBC bit,rel
ACALL addr11
LCALL addr16
RRC A
DEC A
DEC direct
DEC @R0
DEC @R1
DEC R0
DEC R1
DEC R2
DEC R3
DEC R4
DEC R5
DEC R6
DEC R7
JB bit.rel
AJMP addr11
RET
RL A
ADD A,#data
ADD A,direct
ADD A,@R0
ADD A,@R1
ADD A,R0
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Table 33. Instruction Set Summary (Continued)
Opcode
29 H
2A H
2B H
2C H
2D H
2E H
2F H
30 H
31 H
32 H
33 H
34 H
35 H
36 H
37 H
38 H
39 H
3A H
3B H
3C H
3D H
3E H
3F H
40 H
41 H
42 H
43 H
44 H
45 H
46 H
47 H
48 H
49 H
4A H
4B H
4C H
4D H
4E H
4F H
50 H
51 H
52 H
53 H
54 H
55 H
56 H
Mnemonic
ADD A,R1
ADD A,R2
ADD A,R3
ADD A,R4
ADD A,R5
ADD A,R6
ADD A,R7
JNB bit.rel
ACALL addr11
RETI
RLC A
ADDC A,#data
ADDC A,direct
ADDC A,@R0
ADDC A,@R1
ADDC A,R0
ADDC A,R1
ADDC A,R2
ADDC A,R3
ADDC A,R4
ADDC A,R5
ADDC A,R6
ADDC A,R7
JC rel
AJMP addr11
ORL direct,A
ORL direct,#data
ORL A,#data
ORL A,direct
ORL A,@R0
ORL A,@R1
ORL A,R0
ORL A,R1
ORL A,R2
ORL A,R3
ORL A,R4
ORL A,R5
ORL A,R6
ORL A,R7
JNC rel
ACALL addr11
ANL direct,A
ANL direct,#data
ANL A,#data
ANL A,direct
ANL A,@R0
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Table 33. Instruction Set Summary (Continued)
Opcode
57 H
58 H
59 H
5A H
5B H
5C H
5D H
5E H
5F H
60 H
61 H
62 H
63 H
64 H
65 H
66 H
67 H
68 H
69 H
6A H
6B H
6C H
6D H
6E H
6F H
70 H
71 H
72 H
73 H
74 H
75 H
76 H
77 H
78 H
79 H
7A H
7B H
7C H
7D H
7E H
7F H
80 H
81 H
82 H
83 H
84 H
Mnemonic
ANL A,@R1
ANL A,R0
ANL A,R1
ANL A,R2
ANL A,R3
ANL A,R4
ANL A,R5
ANL A,R6
ANL A,R7
JZ rel
AJMP addr11
XRL direct,A
XRL direct,#data
XRL A,#data
XRL A,direct
XRL A,@R0
XRL A,@R1
XRL A,R0
XRL A,R1
XRL A,R2
XRL A,R3
XRL A,R4
XRL A,R5
XRL A,R6
XRL A,R7
JNZ rel
ACALL addr11
ORL C, bit
JMP @A+DPTR
MOV A,#data
MOV direct,#data
MOV @R0,#data
MOV @R1,#data
MOV R0.#data
MOV R1.#data
MOV R2.#data
MOV R3.#data
MOV R4.#data
MOV R5.#data
MOV R6.#data
MOV R7.#data
SJMP rel
AJMP addr11
ANL C,bit
MOVC A,@A+PC
DIV AB
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Table 33. Instruction Set Summary (Continued)
Opcode
85 H
86 H
87 H
88 H
89 H
8A H
8B H
8C H
8D H
8E H
8F H
90 H
91 H
92 H
93 H
94 H
95 H
96 H
97 H
98 H
99 H
9A H
9B H
9C H
9D H
9E H
9F H
A0 H
A1 H
A2 H
A3 H
A4 H
A5 H
A6 H
A7 H
A8 H
A9 H
AA H
AB H
AC H
AD H
AE H
AF H
B0 H
B1 H
B2 H
Mnemonic
MOV direct,direct
MOV direct,@R0
MOV direct,@R1
MOV direct,R0
MOV direct,R1
MOV direct,R2
MOV direct,R3
MOV direct,R4
MOV direct,R5
MOV direct,R6
MOV direct,R7
MOV DPTR,#data16
ACALL addr11
MOV bit,C
MOVC A,@A+DPTR
SUBB A,#data
SUBB A,direct
SUBB A,@R0
SUBB A,@R1
SUBB A,R0
SUBB A,R1
SUBB A,R2
SUBB A,R3
SUBB A,R4
SUBB A,R5
SUBB A,R6
SUBB A,R7
ORL C,bit
AJMP addr11
MOV C,bit
INC DPTR
MUL AB
–
MOV @R0,direct
MOV @R1,direct
MOV R0,direct
MOV R1,direct
MOV R2,direct
MOV R3,direct
MOV R4,direct
MOV R5,direct
MOV R6,direct
MOV R7,direct
ANL C,bit
ACALL addr11
CPL bit
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Table 33. Instruction Set Summary (Continued)
Opcode
B3 H
B4 H
B5 H
B6 H
B7 H
B8 H
B9 H
BA H
BB H
BC H
BD H
BE H
BF H
C0 H
C1 H
C2 H
C3 H
C4 H
C5 H
C6 H
C7 H
C8 H
C9 H
CA H
CB H
CC H
CD H
CE H
CF H
D0 H
D1 H
D2 H
D3 H
D4 H
D5 H
D6 H
D7 H
D8 H
D9 H
DA H
DB H
DC H
DD H
DE H
Mnemonic
CPL C
CJNE A,#data,rel
CJNE A,direct,rel
CJNE
@R0,#data,rel
CJNE
@R1,#data,rel
CJNE R0,#data,rel
CJNE R1,#data,rel
CJNE R2,#data,rel
CJNE R3,#data,rel
CJNE R4,#data,rel
CJNE R5,#data,rel
CJNE R6,#data,rel
CJNE R7,#data,rel
PUSH direct
AJMP addr11
CLR bit
CLR C
SWAP A
XCH A,direct
XCH A,@R0
XCH A,@R1
XCH A,R0
XCH A,R1
XCH A,R2
XCH A,R3
XCH A,R4
XCH A,R5
XCH A,R6
XCH A,R7
POP direct
ACALL addr11
SETB bit
SETB C
DA A
DJNZ direct,rel
XCHD A,@R0
XCHD A,@R1
DJNZ R0,rel
DJNZ R1,rel
DJNZ R2,rel
DJNZ R3,rel
DJNZ R4,rel
DJNZ R5,rel
DJNZ R6,rel
®
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Table 33. Instruction Set Summary (Continued)
Opcode
DF H
E0 H
E1 H
E2 H
E3 H
E4 H
E5 H
E6 H
E7 H
E8 H
E9 H
EA H
EB H
EC H
ED H
EE H
EF H
F0 H
F1 H
F2 H
F3 H
F4 H
F5 H
F6 H
F7 H
F8 H
F9 H
FA H
FB H
FC H
FD H
FE H
FF H
Mnemonic
DJNZ R7,rel
MOVX A,@DPTR
AJMP addr11
MOVX A,@R0
MOVX A,@R1
CLR A
MOV A,direct
MOV A,@R0
MOV A,@R1
MOV A,R0
MOV A,R1
MOV A,R2
MOV A,R3
MOV A,R4
MOV A,R5
MOV A,R6
MOV A,R7
MOVX @DPTR,A
ACALL addr11
MOVX @R0,A
MOVX @R1,A
CPL A
MOV direct,A
MOV @R0,A
MOV @R1,A
MOV R0,A
MOV R1,A
MOV R2,A
MOV R3,A
MOV R4,A
MOV R5,A
MOV R6,A
MOV R7,A
®
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7.
Data Sheet
July 29, 2010
AC Characteristics
Table 34. External Program and Data Memory Characteristics
Symbol
1/TCLCL
TLHLL
TAVLL
TLLAX
TLLIV
TLLPL
TPLPH
TPLIV
TPXIX
TPXIZ
TAVIV
TPLAZ
TRLRH
TWLWH
TRLDV
TRHDX
TRHDZ
TLLDV
TAVDV
TLLWL
TAVWL
TQVWX
TWHQX
TRLAZ
TWHLH
Parameter
Oscillator Frequency 80C152JA/
JC 83C152JA/JC 83C152JB/JD
80C152JA/JC-1 83C152JA/
JC-1 80C152JB/JD-1
ALE Pulse Width
Address Valid to ALE Low
Address Hold After ALE Low
ALE Low to Valid Instruction In
ALE Low to PSENn Low
PSENn Pulse Width
PSENn Low to Valid Instruction In
Input Instruction Hold After PSENn
Input Instruction Float After PSENn
Address to Valid Instruction In
PSENn Low to Address Float
RDn Pulse Width
WRn Pulse Width
RDn Low to Valid Data In
Data Hold After RDn
Data Float After RDn
ALE Low to Valid Data In
Address to Valid Data In
ALE Low to RDn or WRn Low
Address to RDn or WRn Low
Data Valid to WRn Transition
Data Hold After WRn
RDn Low to Address Float
RDn or WRn High to ALE High
®
16.5 MHz
Min Max
–
16.5
Variable Oscillator
Min
Max
–
16.5
Unit
MHZ
–
16.5
–
16.5
MHZ
125
48
60
–
61
186
–
0
–
–
–
351
351
–
0
–
–
–
179
236
344
41
–
61
–
–
–
232
–
–
172
–
80
274
4
–
–
280
–
62
478
542
181
–
–
–
3
61
2TCLCL+4
TCLCL-8
TCLCL-9
–
TCLCL
3TCLCL+4
–
0
–
–
–
6TCLCL-13
6TCLCL-13
–
0
–
–
–
3TCLCL
4TCLCL-8
TCLCL-7
TCLCL+3
–
TCLCL
–
–
–
4TCLCL-35
–
–
3TCLCL-35
–
TCLCL-7
5TCLCL-43
–
–
–
5TCLCL-35
–
2TCLCL-2
8TCLCL-34
9TCLCL-42
3TCLCL
–
–
–
9
TCLCL
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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8.
Data Sheet
July 29, 2010
Innovasic/Intel Part Number Cross-Reference Table
Table 35 shows Innovasic part numbers cross-referenced with the corresponding Intel part
number.
Table 35. Innovasic/Intel Part Number Cross-Reference
Innovasic Part Number
Intel Part Number
N80C152A
N80C152JA
IA80C152JA/JC-PLC68I-R-01
N80C152JA1
(RoHS-compliant package)
N80C152JC
N80C152JC1
N80C152JB
IA80C152JB/JD-PLC68I-R-01 N80C152JB1
(RoHS-compliant package)
N80C152JD
N80C152JD1
®
Package Type
Temperature Grades
68 Lead Plastic Leaded
Chip Carrier (PLCC)
Industrial
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9.
Data Sheet
July 29, 2010
Errata
The following errata are associated with all versions of the IA80C152. A workaround to the
identified problem has been provided where possible.
9.1
Errata Summary
Table 36 presents a summary of errata.
Table 36. Summary of Errata
Errata
No.
Rev.
01
Problem
1
Under certain circumstances, the DMA arbiter will ―lock up‖ in alternate
cycles mode. This problem occurs when one DMA channel has finished
performing a transfer and another DMA initiates a transfer with the byte
Count Register having been set to 0001 by the CPU.
Exists
2
Original Intel device has a linear resistor as the pullup on input RESET.
Exists
3
DMA can interfere with processing of interrupts of different priority.
Exists
4
Corruption of read data may occur if Port 0 bit written to 0.
Exists
9.2
Errata Detail
Errata No. 1
Problem: Under certain circumstances, the DMA arbiter will ―lock up‖ in alternate cycles
mode. This problem occurs when one DMA channel has finished performing a transfer and
another DMA initiates a transfer with the byte Count Register having been set to 0001 by the
CPU.
Workaround: Avoid using the alternate cycles DMA mode in conjunction with a byte count of
one.
Errata No. 2
Problem: Original Intel device has a linear resistor as the pullup on input RESET.
Workaround: None. A non-linear resistor is on the Innovasic device. This may affect
operation of certain R/C reset circuits.
®
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Errata No. 3
Problem: DMA can interfere with processing of interrupts of different priority.
Description: The following sequence of events must occur for this issue to occur:
1. A low-priority (associated priority bit not set) interrupt is accepted by the processor, but
vector fetch is delayed by a DMA cycle.
2. During DMA cycle, a high-priority (associated priority bit set) interrupt is accepted.
3. After DMA cycle, the high-priority vector is fetched. No further processing of any lowpriority interrupts will occur.
Workaround: Use inherent prioritization of interrupts (all interrupts set to high or low priority
only) if DMA is enabled.
Errata No. 4
Problem: Corruption of read data may occur if Port 0 bit written to 0.
Description: If any bit in Port 0 is written to a 0 while the device is configured to use P0 as
address/data bus, corruption of read data may occur.
Workaround: Write all Port 0 register bits to a 1 while using P0 as address/data bus.
®
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Revision History
Table 37 presents the sequence of revisions to document IA211040524.
Table 37. Revision History
Date
August 17, 2005
July 27, 2007
August 31, 2007
Revision
1
2
3
June 18, 2009
4
August 17, 2009
5
July 29, 2010
6
®
Description
Edition released.
Renamed data sheet for clarity
Updated Errata and RoHS information
Document reformatted to meet publication
standards. Added Conventions, Acronyms
and Abbreviations, and Summary of Errata
table. Added new errata and added range for
supply voltage in Table 9.
Added a note regarding recommendations
for using the JB/JD version of the device in
JA/JC applications. Revised Tables 2, 3 and
5.
Errata 3 and 4 added.
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10.
Data Sheet
July 29, 2010
For Additional Information
The IA80C152 is a ―plug-and-play‖ drop-in replacement for the original Intel 80C152.
Innovasic produces replacement ICs using its MILES, or Managed IC Lifetime Extension
System, cloning technology. This technology produces replacement ICs far more complex than
―emulation‖ while ensuring they are compatible with the original IC. MILES captures the design
of a clone so it can be produced even as silicon technology advances. MILES also verifies the
clone against the original IC so that even the ―undocumented features‖ are duplicated. This data
sheet presents engineering information about the IA80C152 including functional and I/O
descriptions, electrical characteristics, and applicable timing.
The Innovasic Support Team wants its information to be complete, accurate, useful, and easy to
understand. Please feel free to contact experts at Innovasic with suggestions, comments, or
questions at any time.
Innovasic Support Team
3737 Princeton NE
Suite 130
Albuquerque, NM 87107
(505) 883-5263
Fax: (505) 883-5477
Toll Free: (888) 824-4184
E-mail: [email protected]
Website: http://www.Innovasic.com
®
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