Renesas H8S20103 16-bit single-chip microcomputer h8s family / h8s/tiny sery Datasheet

REJ09B0465-0100
16
H8S/20103, H8S/20203, H8S/20223 Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family / H8S/Tiny Series
H8S/20103
H8S/20203
H8S/20223
R4F20103
R4F20203
R4F20223
All information contained in this material, including products and product
specifications at the time of publication of this material, is subject to change by
Renesas Technology Corp. without notice. Please review the latest information
published by Renesas Technology Corp. through various means, including the
Renesas Technology Corp. website (http://www.renesas.com).
Rev.1.00
Revision Date: Oct. 03, 2008
Rev. 1.00 Oct. 03, 2008 Page ii of xxvi
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
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light of the total system before deciding about the applicability of such information to the intended application.
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information in this document or Renesas products.
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products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
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traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
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8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
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Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
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approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
Rev. 1.00 Oct. 03, 2008 Page iii of xxvi
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
 The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
 The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
 The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
 When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different type number, confirm
that the change will not lead to problems.
 The characteristics of MPU/MCU in the same group but having different type numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different type numbers, implement a system-evaluation test for
each of the products.
Rev. 1.00 Oct. 03, 2008 Page iv of xxvi
How to Use This Manual
1. Objective and Target Users
This manual was written to explain the hardware functions and electrical characteristics of this
LSI to the target users, i.e. those who will be using this LSI in the design of application
systems. Target users are expected to understand the fundamentals of electrical circuits, logic
circuits, and microcomputers.
This manual is organized in the following items: an overview of the product, descriptions of
the CPU, system control functions, and peripheral functions, electrical characteristics of the
device, and usage notes.
When designing an application system that includes this LSI, take all points to note into
account. Points to note are given in their contexts and at the final part of each section, and
in the section giving usage notes.
The list of revisions is a summary of major points of revision or addition for earlier versions.
It does not cover all revised items. For details on the revised points, see the actual locations
in the manual.
The following documents have been prepared for the H8S/20103 Group, H8S/20203 Group,
H8S/20223 Group. Before using any of the documents, please visit our web site to verify that
you have the most up-to-date available version of the document.
Document Type
Contents
Document Title
Document No.
Data Sheet
Overview of hardware and electrical 
characteristics
Hardware Manual
Hardware specifications (pin
assignments, memory maps,
peripheral specifications, electrical
characteristics, and timing charts)
and descriptions of operation
H8S/20103 Group
H8S/20203 Group
H8S/20223 Group
Hardware Manual
This manual
Software Manual
Detailed descriptions of the CPU
and instruction set
H8S/2600 Series
H8S/2000 Series
Software Manual
REJ09B0143
Application Note
Examples of applications and
sample programs
The latest versions are available from our
web site.
Renesas Technical
Update
Preliminary report on the
specifications of a product,
document, etc.

Rev. 1.00 Oct. 03, 2008 Page v of xxvi
2. Description of Numbers and Symbols
Aspects of the notations for register names, bit names, numbers, and symbolic names in this
manual are explained below.
(1) Overall notation
In descriptions involving the names of bits and bit fields within this manual, the modules and
registers to which the bits belong may be clarified by giving the names in the forms
"module name"."register name"."bit name" or "register name"."bit name".
(2) Register notation
The style "register name"_"instance number" is used in cases where there is more than one
instance of the same function or similar functions.
[Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0.
(3) Number notation
Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary),
hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn.
[Examples] Binary:
B'11 or 11
Hexadecimal: H'EFA0 or 0xEFA0
Decimal:
1234
(4) Notation for active-low
An overbar on the name indicates that a signal or pin is active-low.
[Example] WDTOVF
(4)
(2)
14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1)
CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter
input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0.
14.3 Operation
14.3.1 Interval Count Operation
When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in
CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in
CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000
and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time,
a f/4 clock is selected.
Rev. 0.50, 10/04, page 416 of 914
(3)
Note: The bit names and sentences in the above figure are examples and have nothing to do
with the contents of this manual.
Rev. 1.00 Oct. 03, 2008 Page vi of xxvi
3. Description of Registers
Each register description includes a bit chart, illustrating the arrangement of bits, and a table of
bits, describing the meanings of the bit settings. The standard format and notation for bit charts
and tables are described below.
[Bit Chart]
Bit:
Initial value:
R/W:
15
14


13
12
11
ASID2 ASID1 ASID0
10
9
8
7
6
5
4






Q
3
2
1
ACMP2 ACMP1 ACMP0
0
IFE
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(1)
[Table of Bits]
Bit
(2)
(3)
(4)
(5)
Bit Name
−
−
Initial Value R/W
0
0
R
R
Reserved
These bits are always read as 0.
13 to 11
ASID2 to
ASID0
All 0
R/W
Address Identifier
These bits enable or disable the pin function.
10
−
0
R
Reserved
This bit is always read as 0.
9
−
1
R
Reserved
This bit is always read as 1.
−
0
15
14
Description
Note: The bit names and sentences in the above figure are examples, and have nothing to do with the contents of this
manual.
(1) Bit
Indicates the bit number or numbers.
In the case of a 32-bit register, the bits are arranged in order from 31 to 0. In the case
of a 16-bit register, the bits are arranged in order from 15 to 0.
(2) Bit name
Indicates the name of the bit or bit field.
When the number of bits has to be clearly indicated in the field, appropriate notation is
included (e.g., ASID[3:0]).
A reserved bit is indicated by "−".
Certain kinds of bits, such as those of timer counters, are not assigned bit names. In such
cases, the entry under Bit Name is blank.
(3) Initial value
Indicates the value of each bit immediately after a power-on reset, i.e., the initial value.
0: The initial value is 0
1: The initial value is 1
−: The initial value is undefined
(4) R/W
For each bit and bit field, this entry indicates whether the bit or field is readable or writable,
or both writing to and reading from the bit or field are impossible.
The notation is as follows:
R/W: The bit or field is readable and writable.
R/(W): The bit or field is readable and writable.
However, writing is only performed to flag clearing.
R:
The bit or field is readable.
"R" is indicated for all reserved bits. When writing to the register, write
the value under Initial Value in the bit chart to reserved bits or fields.
W:
The bit or field is writable.
(5) Description
Describes the function of the bit or field and specifies the values for writing.
Rev. 1.00 Oct. 03, 2008 Page vii of xxvi
4. Description of Abbreviations
The abbreviations used in this manual are listed below.
•
Abbreviations specific to this product
Abbreviation
Description
BSC
Bus controller
CPG
INT
SCI
TPU
WDT
Clock pulse generator
Interrupt controller
Serial communications interface
16-bit timer pulse unit
Watchdog timer
• Abbreviations other than those listed above
Abbreviation
Description
ACIA
Asynchronous communications interface adapter
bps
Bits per second
CRC
DMA
DMAC
GSM
Hi-Z
IEBus
I/O
IrDA
LSB
MSB
NC
PLL
PWM
SFR
SIM
Cyclic redundancy check
Direct memory access
Direct memory access controller
Global System for Mobile Communications
High impedance
Inter Equipment Bus (IEBus is a trademark of NEC Electronics Corporation.)
Input/output
Infrared Data Association
Least significant bit
Most significant bit
No connection
Phase-locked loop
Pulse width modulation
Special function register
Subscriber Identity Module
UART
VCO
Universal asynchronous receiver/transmitter
Voltage-controlled oscillator
All trademarks and registered trademarks are the property of their respective owners.
Rev. 1.00 Oct. 03, 2008 Page viii of xxvi
Contents
Section 1 Overview................................................................................................1
1.1
1.2
1.3
1.4
Features................................................................................................................................. 1
1.1.1
Applications .......................................................................................................... 1
1.1.2
Overview of Functions.......................................................................................... 1
List of Products..................................................................................................................... 6
Block Diagram...................................................................................................................... 8
Pin Assignments ................................................................................................................. 11
1.4.1
Pin Functions ...................................................................................................... 14
Section 2 CPU......................................................................................................21
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Features............................................................................................................................... 21
2.1.1
Differences between H8S/2600 CPU and H8S/2000 CPU ................................. 22
2.1.2
Differences from H8/300 CPU ........................................................................... 23
2.1.3
Differences from H8/300H CPU......................................................................... 23
CPU Operating Modes........................................................................................................ 24
2.2.1
Advanced Mode.................................................................................................. 24
Address Space..................................................................................................................... 27
Register Configuration........................................................................................................ 31
2.4.1
General Registers................................................................................................ 32
2.4.2
Program Counter (PC) ........................................................................................ 33
2.4.3
Extended Control Register (EXR) ...................................................................... 33
2.4.4
Condition-Code Register (CCR)......................................................................... 34
2.4.5
Initial Register Values......................................................................................... 36
Data Formats....................................................................................................................... 37
2.5.1
General Register Data Formats ........................................................................... 37
2.5.2
Memory Data Formats ........................................................................................ 39
Instruction Set ..................................................................................................................... 40
2.6.1
Table of Instructions Classified by Function ...................................................... 41
2.6.2
Basic Instruction Formats ................................................................................... 51
Addressing Modes and Effective Address Calculation....................................................... 53
2.7.1
Register Direct—Rn ........................................................................................... 53
2.7.2
Register Indirect—@ERn ................................................................................... 53
2.7.3
Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)............. 54
2.7.4
Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or
@–ERn................................................................................................................ 54
2.7.5
Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32................................... 54
Rev. 1.00 Oct. 03, 2008 Page ix of xxvi
2.8
2.9
2.7.6
Immediate—#xx:8, #xx:16, or #xx:32................................................................ 55
2.7.7
Program-Counter Relative—@(d:8, PC) or @(d:16, PC) .................................. 55
2.7.8
Memory Indirect—@@aa:8 ............................................................................... 56
2.7.9
Effective Address Calculation ............................................................................ 57
Processing States ................................................................................................................ 59
Usage Notes ........................................................................................................................ 61
2.9.1
TAS Instruction .................................................................................................. 61
2.9.2
STM and LDM Instructions................................................................................ 61
2.9.3
Note on Bit Manipulation Instructions................................................................ 61
2.9.4
EEPMOVE Instruction ....................................................................................... 62
Section 3 Exception Handling ............................................................................. 63
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
Exception Handling Types and Priority.............................................................................. 63
Exception Handling Sources and Vector Table .................................................................. 63
Reset ................................................................................................................................... 64
3.3.1
Reset Sources...................................................................................................... 64
3.3.2
Reset Exception Handling .................................................................................. 67
3.3.3
Interrupts immediately after Reset...................................................................... 68
3.3.4
On-Chip Peripheral Functions after Reset Release............................................. 68
Trace Exception Handling .................................................................................................. 69
Interrupt Exception Handling ............................................................................................. 70
Trap Instruction Exception Handling.................................................................................. 70
Stack Status after Exception Handling ............................................................................... 71
Usage Note ......................................................................................................................... 72
Section 4 Interrupt Controller.............................................................................. 73
4.1
4.2
4.3
4.4
Features............................................................................................................................... 73
Register Descriptions.......................................................................................................... 75
4.2.1
Interrupt Control Register (INTCR) ................................................................... 76
4.2.2
Interrupt Priority Registers A to I (IPRA to IPRI).............................................. 77
4.2.3
IRQ Enable Register (IER) ................................................................................. 79
4.2.4
IRQ Sense Control Register H and L (ISCRH and ISCRL) ............................... 80
4.2.5
IRQ Status Register (ISR)................................................................................... 83
4.2.6
IRQ Noise Canceler Control Register (INCCR)................................................. 84
4.2.7
Interrupt Vector Offset Register (VOFR) ........................................................... 85
4.2.8
Event Link Interrupt Control Status Register (ELCSR) ..................................... 86
Interrupt Sources................................................................................................................. 87
4.3.1
External Interrupt sources ................................................................................... 87
4.3.2
Internal Interrupts ............................................................................................... 88
Interrupt Exception Handling Vector Table........................................................................ 89
Rev. 1.00 Oct. 03, 2008 Page x of xxvi
4.5
4.6
Interrupt Control Modes and Interrupt Operation ............................................................... 96
4.5.1
Interrupt Control Mode 0 .................................................................................... 96
4.5.2
Interrupt Control Mode 2 .................................................................................... 98
4.5.3
Interrupt Exception Handling Sequence ........................................................... 100
4.5.4
Interrupt Response Time................................................................................... 102
4.5.5
DTC Activation by Interrupt............................................................................. 102
Usage Notes ...................................................................................................................... 103
4.6.1
Conflict between Interrupt Generation and Disabling ...................................... 103
4.6.2
Instructions that Disable Interrupts ................................................................... 104
4.6.3
Time when Interrupts are Disabled................................................................... 104
4.6.4
Interrupts during Execution of EEPMOV Instruction....................................... 104
4.6.5
Changing PMR, ISCRH, ISCRL and INCCR................................................... 105
4.6.6
IRQ Status Register (ISR)................................................................................. 105
4.6.7
NMI Pin ............................................................................................................ 106
Section 5 Clock Pulse Generator .......................................................................107
5.1
5.2
5.3
5.4
5.5
Overview........................................................................................................................... 108
Register Descriptions........................................................................................................ 110
5.2.1
Backup Control Register (BACKR) ................................................................. 111
5.2.2
System Clock Control Register (SYSCCR)...................................................... 113
5.2.3
Power-Down Control Register 1 (LPCR1) ....................................................... 115
5.2.4
Power-Down Control Register 2 (LPCR2) ....................................................... 117
5.2.5
Power-Down Control Register 3 (LPCR3) ....................................................... 118
5.2.6
OSC Oscillation Settling Control Status Register (OSCCSR).......................... 120
5.2.7
High-Speed OCO Control Register (HOCR).................................................... 121
5.2.8
High-Speed OCO Trimming Data Protect Register (HOTRMDPR) ................ 122
5.2.9
High-Speed OCO Trimming Data Register 1 (HOTRMDR1).......................... 123
5.2.10
High-Speed OCO Trimming Data Register 2 (HOTRMDR2).......................... 124
5.2.11
High-Speed OCO Trimming Data Register 3 (HOTRMDR3).......................... 124
5.2.12
High-Speed OCO Trimming Data Register 4 (HOTRMDR4).......................... 125
Operation of Selection of System Base Clock .................................................................. 126
5.3.1
Switching System Base Clock to φhoco ........................................................... 129
5.3.2
Switching System Base Clock to φosc.............................................................. 131
5.3.3
Clock Change Timing ....................................................................................... 132
5.3.4
Backup Operation ............................................................................................. 135
High-Speed On-Chip Oscillator........................................................................................ 139
5.4.1
Procedures for Switching to 32MHz................................................................. 139
5.4.2
Trimming of High-Speed OCO......................................................................... 140
Main Clock Oscillator....................................................................................................... 142
5.5.1
Connecting Crystal Resonator .......................................................................... 142
Rev. 1.00 Oct. 03, 2008 Page xi of xxvi
5.6
5.7
5.8
5.5.2
Connecting Ceramic Resonator ........................................................................ 143
5.5.3
External Clock Input Method............................................................................ 143
Subclock Generator .......................................................................................................... 144
5.6.1
Connecting 32.768-kHz Crystal Resonator ...................................................... 144
5.6.2
Pin Connection when not Using Subclock........................................................ 144
Prescaler............................................................................................................................ 145
Usage Notes ...................................................................................................................... 146
5.8.1
Note on Resonators........................................................................................... 146
5.8.2
Notes on Board Design ..................................................................................... 146
Section 6 Power-Down Modes.......................................................................... 147
6.1
6.2
6.3
6.4
6.5
Register Descriptions........................................................................................................ 148
6.1.1
Power-Down Control Registers 1, 2, and 3 (LPCR1, LPCR2, LPCR3) ........... 148
6.1.2
Module Standby Control Register 1 (MSTCR1) .............................................. 148
6.1.3
Module Standby Control Register 2 (MSTCR2) .............................................. 150
6.1.4
Module Standby Control Register 3 (MSTCR3) .............................................. 151
Mode Transitions and States of LSI.................................................................................. 153
6.2.1
Active Mode ..................................................................................................... 155
6.2.2
Sleep Mode ....................................................................................................... 155
6.2.3
Standby Mode................................................................................................... 156
Bus Master Clock Division Function................................................................................ 156
6.3.1
Reset States....................................................................................................... 156
Module Standby Function................................................................................................. 157
PSC Divider Stop Function............................................................................................... 157
Section 7 ROM .................................................................................................. 159
7.1
7.2
7.3
7.4
7.5
Overview .......................................................................................................................... 159
Block Configuration ......................................................................................................... 160
CPU Reprogramming Mode ............................................................................................. 163
7.3.1
EW0 Mode........................................................................................................ 165
7.3.2
EW1 Mode........................................................................................................ 165
Register Descriptions........................................................................................................ 166
7.4.1
Flash Memory Control Register 1 (FLMCR1).................................................. 166
7.4.2
Flash Memory Control Register 2 (FLMCR2).................................................. 168
7.4.3
Flash Memory Data Flash Protect Register (DFPR)......................................... 170
7.4.4
Flash Memory Status Register (FLMSTR)....................................................... 171
On-Board Programming ................................................................................................... 174
7.5.1
Boot Mode ........................................................................................................ 174
7.5.2
Specifications of Standard Serial Communication Interface in Boot Mode ..... 180
7.5.3
Programming/Erasing in User Mode ................................................................ 207
Rev. 1.00 Oct. 03, 2008 Page xii of xxvi
7.6
7.7
7.8
7.9
Programming/Erasing ....................................................................................................... 208
7.6.1
Software Commands......................................................................................... 208
Protection.......................................................................................................................... 225
7.7.1
Software Protection........................................................................................... 225
7.7.2
Lock-Bit Protection........................................................................................... 225
7.7.3
PROM Programmer Protection/Boot Mode Protection .................................... 226
Programmer Mode ............................................................................................................ 227
Usage Notes ...................................................................................................................... 228
Section 8 RAM ..................................................................................................231
Section 9 Peripheral I/O Mapping Controller....................................................233
9.1
9.2
Register Descriptions........................................................................................................ 235
9.1.1
Peripheral Function Mapping Register Write-Protect Register (PMCWPR).... 236
9.1.2
Port Group 1 Peripheral Function Mapping Registers 1 to 4
(PMCRn1 to PMCRn4 (n = 1, 2, 3, 5, and 6)) .................................................. 237
9.1.3
Port Group 2 Peripheral Function Mapping Registers 1 to 4
(PMCRn1 to PMCRn4 (n = 8, 9, and A) .......................................................... 258
Usage Notes ...................................................................................................................... 266
9.2.1
Procedures for Setting Multiplexed Port Functions .......................................... 266
9.2.2
Notes on Setting PMC Registers....................................................................... 266
Section 10 I/O Ports ...........................................................................................267
10.1
10.2
10.3
Port 1................................................................................................................................. 267
10.1.1
Port Mode Register 1 (PMR1) .......................................................................... 268
10.1.2
Port Control Register 1 (PCR1) ........................................................................ 269
10.1.3
Port Data Register 1 (PDR1)............................................................................. 270
10.1.4
Port Pull-Up Control Register 1 (PUCR1)........................................................ 271
10.1.5
Port Drive Control Register 1 (PDVR1) ........................................................... 272
Port 2................................................................................................................................. 273
10.2.1
Port Mode Register 2 (PMR2) .......................................................................... 274
10.2.2
Port Control Register 2 (PCR2) ........................................................................ 275
10.2.3
Port Data Register 2 (PDR2)............................................................................. 276
10.2.4
Port Pull-Up Control Register 2 (PUCR2)........................................................ 277
10.2.5
Port Drive Control Register 2 (PDVR2) ........................................................... 278
Port 3................................................................................................................................. 279
10.3.1
Port Mode Register 3 (PMR3) .......................................................................... 280
10.3.2
Port Control Register 3 (PCR3) ........................................................................ 281
10.3.3
Port Data Register 3 (PDR3)............................................................................. 282
10.3.4
Port Pull-Up Control Register 3 (PUCR3)........................................................ 283
Rev. 1.00 Oct. 03, 2008 Page xiii of xxvi
10.4
10.5
10.6
10.7
10.8
10.3.5
Port Drive Control Register 3 (PDVR3) ........................................................... 284
Port 5................................................................................................................................. 285
10.4.1
Port Mode Register 5 (PMR5) .......................................................................... 286
10.4.2
Port Control Register 5 (PCR5) ........................................................................ 287
10.4.3
Port Data Register 5 (PDR5) ............................................................................ 288
10.4.4
Port Pull-Up Control Register 5 (PUCR5)........................................................ 289
10.4.5
Port Drive Control Register 5 (PDVR5) ........................................................... 290
Port 6................................................................................................................................. 291
10.5.1
Port Mode Register 6 (PMR6) .......................................................................... 292
10.5.2
Port Control Register 6 (PCR6) ........................................................................ 293
10.5.3
Port Data Register 6 (PDR6) ............................................................................ 294
10.5.4
Port Pull-Up Control Register 6 (PUCR6)........................................................ 295
10.5.5
Port Drive Control Register 6 (PDVR6) ........................................................... 296
Port 8................................................................................................................................. 297
10.6.1
Port Mode Register 8 (PMR8) .......................................................................... 298
10.6.2
Port Control Register 8 (PCR8) ........................................................................ 299
10.6.3
Port Data Register 8 (PDR8) ............................................................................ 300
10.6.4
Port Pull-Up Control Register 8 (PUCR8)........................................................ 301
10.6.5
Port Drive Control Register 8 (PDVR8) ........................................................... 302
10.6.6
Notes on Using Port 8....................................................................................... 302
Port 9................................................................................................................................. 303
10.7.1
Port Mode Register 9 (PMR9) .......................................................................... 304
10.7.2
Port Control Register 9 (PCR9) ........................................................................ 305
10.7.3
Port Data Register 9 (PDR9) ............................................................................ 306
10.7.4
Port Pull-Up Control Register 9 (PUCR9)........................................................ 307
10.7.5
Port Drive Control Register 9 (PDVR9) ........................................................... 308
Port A................................................................................................................................ 309
10.8.1
Port Mode Register A (PMRA) ........................................................................ 310
10.8.2
Port Control Register A (PCRA) ...................................................................... 311
10.8.3
Port Data Register A (PDRA)........................................................................... 312
10.8.4
Port Pull-Up Control Register A (PUCRA)...................................................... 313
10.8.5
Port Mode Register A (PMRA) ........................................................................ 314
10.8.6
Port Control Register A (PCRA) ...................................................................... 315
10.8.7
Port Data Register A (PDRA)........................................................................... 316
10.8.8
Port Pull-Up Control Register A (PUCRA)...................................................... 317
10.8.9
Port Mode Register A (PMRA) ........................................................................ 318
10.8.10 Port Control Register A (PCRA) ...................................................................... 319
10.8.11 Port Data Register A (PDRA)........................................................................... 320
10.8.12 Port Pull-Up Control Register A (PUCRA)...................................................... 321
10.8.13 Notes on Using Port A ...................................................................................... 321
Rev. 1.00 Oct. 03, 2008 Page xiv of xxvi
10.9
Port B ................................................................................................................................ 322
10.9.1
Port Control Register B (PCRB)....................................................................... 323
10.9.2
Port Data Register B (PDRB) ........................................................................... 324
10.9.3
Port Pull-Up Control Register B (PUCRB) ...................................................... 325
10.9.4
Notes on Using Port B ...................................................................................... 325
10.10 Port J ................................................................................................................................. 326
10.10.1 Port Mode Register J (PMRJ) ........................................................................... 327
10.10.2 Port Control Register J (PCRJ) ......................................................................... 328
10.10.3 Port Data Register J (PDRJ) ............................................................................. 329
10.10.4 Port Pull-Up Control Register J (PUCRJ)......................................................... 330
Section 11 Data Transfer Controller (DTC) ......................................................331
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Features............................................................................................................................. 331
Register Descriptions........................................................................................................ 333
11.2.1
DTC Mode Register A (MRA) ......................................................................... 334
11.2.2
DTC Mode Register B (MRB).......................................................................... 336
11.2.3
DTC Source Address Register (SAR)............................................................... 337
11.2.4
DTC Destination Address Register (DAR)....................................................... 337
11.2.5
DTC Transfer Count Register A (CRA) ........................................................... 338
11.2.6
DTC Transfer Count Register B (CRB)............................................................ 338
11.2.7
DTC Enable Registers A to H (DTCERA to DTCERH) .................................. 339
11.2.8
DTC Vector Register (DTVECR)..................................................................... 341
Activation Sources............................................................................................................ 342
Location of Register Information and DTC Vector Table ................................................ 344
Operation .......................................................................................................................... 349
11.5.1
Normal Mode.................................................................................................... 351
11.5.2
Repeat Mode ..................................................................................................... 352
11.5.3
Block Transfer Mode ........................................................................................ 353
11.5.4
Chain Transfer .................................................................................................. 354
11.5.5
Interrupt Sources............................................................................................... 355
11.5.6
Operation Timing.............................................................................................. 356
11.5.7
Number of DTC Execution States .................................................................... 357
Procedures for Using DTC................................................................................................ 359
11.6.1
Activation by Interrupt...................................................................................... 359
11.6.2
Activation by Software ..................................................................................... 359
Examples of Use of the DTC ............................................................................................ 360
11.7.1
Normal Mode.................................................................................................... 360
11.7.2
Chain Transfer when Transfer Counter = 0 ...................................................... 361
11.7.3
Software Activation .......................................................................................... 363
Usage Notes ...................................................................................................................... 364
Rev. 1.00 Oct. 03, 2008 Page xv of xxvi
11.8.1
11.8.2
11.8.3
Module Standby Mode Setting ......................................................................... 364
DTCE Bit Setting.............................................................................................. 364
DTC Activation by SCI3, IIC2/SSU and A/D Converter Interrupt Sources..... 364
Section 12 Event Link Controller...................................................................... 365
12.1
12.2
12.3
Overview .......................................................................................................................... 365
Register Descriptions........................................................................................................ 367
12.2.1
Event Link Control Register (ELCR) ............................................................... 367
12.2.2
Event Link Setting Registers 0 to 32 (ELSR0 to ELSR32) .............................. 368
12.2.3
Event Link Option Setting Register A (ELOPA).............................................. 372
12.2.4
Event Link Option Setting Register B (ELOPB) .............................................. 373
12.2.5
Event Link Option Setting Register C (ELOPC) .............................................. 373
12.2.6
Port-Group Setting Registers 1 and 2 (PGR1 and PGR2)................................. 374
12.2.7
Port-Group Control Registers 1 and 2 (PGC1 and PGC2)................................ 375
12.2.8
Port Buffer Registers 1 and 2 (PDBF1 and PDBF2)......................................... 376
12.2.9
Event Link Port Setting Registers 0 to 3 (PEL0 to PEL3) ................................ 377
12.2.10 Event-Generation Timer Control Register (ELTMCR) .................................... 378
12.2.11 Event-Generation Timer Interval Setting Register A (ELTMSA) .................... 379
12.2.12 Event-Generation Timer Interval Setting Register B (ELTMSB)..................... 381
12.2.13 Event-Generation Timer Delay Selection Register (ELTMDR)....................... 383
12.2.14 ELC Timer Counter (ELTMCNT).................................................................... 384
Operation .......................................................................................................................... 385
12.3.1
Relation between Interrupt Processing and Event Linking............................... 385
12.3.2
Event Linkage................................................................................................... 385
12.3.3
Operation of Peripheral Timer Modules When Event is Input ......................... 387
12.3.4
Operation of A/D and D/A Converters When Event is Input ........................... 387
12.3.5
Port Operation upon Event Input and Event Generation................................... 388
12.3.6
Event-Generation Timer ................................................................................... 394
12.3.7
Procedure for Linking Events ........................................................................... 396
Section 13 Timer RA......................................................................................... 397
13.1
13.2
13.3
Overview .......................................................................................................................... 397
Register Descriptions........................................................................................................ 398
13.2.1
Timer RA Control Register (TRACR).............................................................. 399
13.2.2
Timer RA I/O Control Register (TRAIOC)...................................................... 401
13.2.3
Timer RA Mode Register (TRAMR)................................................................ 403
13.2.4
Timer RA Interrupt Enable Status Register (TRAIR)....................................... 404
13.2.5
Timer RA Prescaler Register (TRAPRE) ......................................................... 405
13.2.6
Timer RA Timer Register (TRATR) ................................................................ 406
Operation .......................................................................................................................... 407
Rev. 1.00 Oct. 03, 2008 Page xvi of xxvi
13.4
13.3.1
Operations Common to Various Modes............................................................ 407
13.3.2
Timer Mode ...................................................................................................... 408
13.3.3
Pulse Output Mode ........................................................................................... 408
13.3.4
Event Counter Mode ......................................................................................... 409
13.3.5
Pulse Width Measurement Mode...................................................................... 409
13.3.6
Pulse Cycle Measurement Mode....................................................................... 411
13.3.7
Operation through an Event Link...................................................................... 412
Usage Notes ...................................................................................................................... 414
Section 14 Timer RB .........................................................................................415
14.1
14.2
14.3
14.4
14.5
Overview........................................................................................................................... 415
Register Descriptions........................................................................................................ 416
14.2.1
Timer RB Control Register (TRBCR) .............................................................. 417
14.2.2
Timer RB One-Shot Control Register (TRBOCR) ........................................... 418
14.2.3
Timer RB I/O Control Register (TRBIOC) ...................................................... 419
14.2.4
Timer RB Mode Register (TRBMR) ................................................................ 421
14.2.5
Timer RB Interrupt Enable Status Register (TRBIR) ....................................... 422
14.2.6
Timer RB Prescaler Register (TRBPRE).......................................................... 423
14.2.7
Timer RB Secondary Register (TRBSC) .......................................................... 423
14.2.8
Timer RB Primary Register (TRBPR) .............................................................. 424
Operation .......................................................................................................................... 425
14.3.1
Timer Mode ...................................................................................................... 425
14.3.2
Programmable Waveform Generation Mode .................................................... 426
14.3.3
Programmable One-Shot Generation Mode...................................................... 428
14.3.4
Programmable Wait One-Shot Generation Mode ............................................. 430
14.3.5
Timing at Which Values Take Effect in Prescaler or Counter Depending on
TWRC Bit......................................................................................................... 432
14.3.6
TOCNT Settings and Pin State Update Conditions .......................................... 434
14.3.7
Operation through an Event Link...................................................................... 435
Interrupt Request............................................................................................................... 435
Usage Notes ...................................................................................................................... 436
Section 15 Timer RC .........................................................................................437
15.1
15.2
Features............................................................................................................................. 437
Register Descriptions........................................................................................................ 440
15.2.1
Timer RC Mode Register (TRCMR) ................................................................ 441
15.2.2
Timer RC Control Register 1 (TRCCR1) ......................................................... 442
15.2.3
Timer RC Control Register 2 (TRCCR2) ......................................................... 444
15.2.4
Timer RC Interrupt Enable Register (TRCIER) ............................................... 445
15.2.5
Timer RC Status Register (TRCSR) ................................................................. 446
Rev. 1.00 Oct. 03, 2008 Page xvii of xxvi
15.3
15.4
15.5
15.2.6
Timer RC I/O Control Register 0 (TRCIOR0) ................................................. 449
15.2.7
Timer RC I/O Control Register 1 (TRCIOR1) ................................................. 451
15.2.8
Timer RC Output Enable Register (TRCOER)................................................. 453
15.2.9
Timer RC Digital Filtering Function Select Register (TRCDF) ....................... 454
15.2.10 Timer RC A/D Conversion Start Trigger Control Register (TRCADCR) ........ 455
15.2.11 Timer RC Counter (TRCCNT) ......................................................................... 456
15.2.12 General Registers A, B, C, and D (GRA, GRB, GRC, and GRD).................... 457
Operation .......................................................................................................................... 459
15.3.1
Timer Mode Operation ..................................................................................... 461
15.3.2
PWM Mode Operation...................................................................................... 466
15.3.3
PWM2 Mode Operation.................................................................................... 471
15.3.4
Digital Filtering Function for Input Capture Inputs.......................................... 477
15.3.5
A/D Conversion Start Trigger Setting Function ............................................... 478
15.3.6
Function of Changing Output Pins for GR ....................................................... 480
15.3.7
Operation through an Event Link ..................................................................... 482
Operation Timing.............................................................................................................. 483
15.4.1
TRCCNT Counting Timing .............................................................................. 483
15.4.2
Output Compare Output Timing....................................................................... 484
15.4.3
Input Capture Timing........................................................................................ 485
15.4.4
Timing of Counter Clearing by Compare Match .............................................. 485
15.4.5
Buffer Operation Timing .................................................................................. 486
15.4.6
Timing of IMFA to IMFD Flag Setting at Compare Match ............................. 487
15.4.7
Timing of IMFA to IMFD Setting at Input Capture ......................................... 488
15.4.8
Timing of Status Flag Clearing......................................................................... 489
15.4.9
Timing of A/D Conversion Start Trigger Generation on Compare Match ....... 490
Usage Notes ...................................................................................................................... 491
Section 16 Timer RD......................................................................................... 495
16.1
16.2
Features............................................................................................................................. 495
Register Descriptions........................................................................................................ 503
16.2.1
Timer RD Start Register (TRDSTR) ................................................................ 505
16.2.2
Timer RD Mode Register (TRDMDR)............................................................. 507
16.2.3
Timer RD PWM Mode Register (TRDPMR) ................................................... 508
16.2.4
Timer RD Function Control Register (TRDFCR) ............................................ 509
16.2.5
Timer RD Output Master Enable Register 1 (TRDOER1) ............................... 511
16.2.6
Timer RD Output Master Enable Register 2 (TRDOER2) ............................... 513
16.2.7
Timer RD Output Control Register (TRDOCR)............................................... 513
16.2.8
Timer RD A/D Conversion Start Trigger Control Register (TRDADCR)........ 515
16.2.9
Timer RD Counter (TRDCNT)......................................................................... 516
16.2.10 General Registers A, B, C, and D (GRA, GRB, GRC, and GRD).................... 517
Rev. 1.00 Oct. 03, 2008 Page xviii of xxvi
16.3
16.4
16.5
16.2.11 Timer RD Control Register (TRDCR).............................................................. 519
16.2.12 Timer RD I/O Control Registers (TRDIORA and TRDIORC) ........................ 521
16.2.13 Timer RD Status Register (TRDSR)................................................................. 525
16.2.14 Timer RD Interrupt Enable Register (TRDIER) ............................................... 528
16.2.15 PWM Mode Output Level Control Register (POCR) ....................................... 529
16.2.16 Timer RD Digital Filtering Function Select Register (TRDDF)....................... 530
16.2.17 Interface with CPU ........................................................................................... 531
Operation .......................................................................................................................... 532
16.3.1
Counter Operation............................................................................................. 541
16.3.2
Waveform Output by Compare Match.............................................................. 544
16.3.3
Input Capture Function ..................................................................................... 547
16.3.4
Synchronous Operation..................................................................................... 550
16.3.5
PWM Mode ...................................................................................................... 551
16.3.6
Reset Synchronous PWM Mode ....................................................................... 557
16.3.7
Complementary PWM Mode............................................................................ 561
16.3.8
PWM3 Mode Operation.................................................................................... 567
16.3.9
Buffer Operation ............................................................................................... 573
16.3.10 Timer RD Output Timing ................................................................................. 581
16.3.11 Digital Filtering Function for Input Capture Inputs .......................................... 584
16.3.12 Function of Changing Output Pins for GR ....................................................... 585
16.3.13 A/D Conversion Start Trigger Setting Function ............................................... 587
16.3.14 Operation by Event Clear.................................................................................. 589
Interrupt Sources............................................................................................................... 590
16.4.1
Status Flag Set Timing...................................................................................... 590
16.4.2
Status Flag Clearing Timing ............................................................................. 592
Usage Notes ...................................................................................................................... 592
Section 17 Timer RE..........................................................................................603
17.1
17.2
17.3
Features............................................................................................................................. 603
Register Descriptions........................................................................................................ 605
17.2.1
Timer RE Second Data Register/Counter Data Register (TRESEC) ................ 606
17.2.2
Timer RE Minute Data Register/Compare Data Register (TREMIN) .............. 607
17.2.3
Timer RE Hour Data Register (TREHR) .......................................................... 608
17.2.4
Timer RE Day-of-Week Data Register (TREWK) ........................................... 609
17.2.5
Timer RE Control Register 1 (TRECR1).......................................................... 610
17.2.6
Timer RE Control Register 2 (TRECR2).......................................................... 613
17.2.7
Timer RE Interrupt Flag Register (TREIFR) .................................................... 614
17.2.8
Timer RE Clock Source Select Register (TRECSR) ........................................ 616
Operation of Realtime Clock Mode .................................................................................. 618
17.3.1
Initial Settings of Registers after Power-On ..................................................... 618
Rev. 1.00 Oct. 03, 2008 Page xix of xxvi
17.4
17.5
17.6
17.3.2
Initial Setting Procedure ................................................................................... 618
17.3.3
Data Reading Procedure in Realtime Clock Mode ........................................... 620
17.3.4
Operation in Realtime Clock Mode .................................................................. 621
Operation of Output Compare Mode ................................................................................ 622
Interrupt Sources............................................................................................................... 625
Usage Notes ...................................................................................................................... 626
Section 18 Timer RG......................................................................................... 627
18.1
18.2
18.3
18.4
Features............................................................................................................................. 627
Register Descriptions........................................................................................................ 630
18.2.1
Timer RG Mode Register (TRGMDR)............................................................. 631
18.2.2
Timer RG Counter Control Register (TRGCNTCR) ........................................ 632
18.2.3
Timer RG Control Register (TRGCR).............................................................. 633
18.2.4
Timer RG I/O Control Register (TRGIOR)...................................................... 634
18.2.5
Timer RG Status Register (TRGSR)................................................................. 636
18.2.6
Timer RG Interrupt Enable Register (TRGIER)............................................... 637
18.2.7
Timer RG Counter (TRGCNT)......................................................................... 638
18.2.8
General Registers A and B (GRA, GRB), GRA and GRB Buffer Registers
(BRA, BRB) ..................................................................................................... 639
Operation .......................................................................................................................... 641
18.3.1
Timer Mode ...................................................................................................... 642
18.3.2
PWM Mode ...................................................................................................... 648
18.3.3
Phase Counting Mode....................................................................................... 653
18.3.4
Buffer Operation............................................................................................... 658
18.3.5
Operation through an Event Link ..................................................................... 661
18.3.6
Digital Filtering Function for Input Capture Inputs.......................................... 662
Usage Note ....................................................................................................................... 663
18.4.1
Restrictions on Access to Registers when Internal φ40 Clock is Selected as
Counter Clock................................................................................................... 663
Section 19 Watchdog Timer (WDT) ................................................................. 665
19.1
19.2
19.3
Features............................................................................................................................. 666
Register Descriptions........................................................................................................ 667
19.2.1
Timer Control/Status Register WD (TCSRWD) .............................................. 667
19.2.2
Timer Counter WD (TCWD)............................................................................ 668
19.2.3
Timer Mode Register WD (TMWD) ................................................................ 669
19.2.4
Timer Interrupt Control Register WD (TICRWD) ........................................... 670
19.2.5
Timer Interrupt Flag Register WD (TIFRWD)................................................. 671
Operation .......................................................................................................................... 672
19.3.1
Watchdog Timer Overflow Reset ..................................................................... 672
Rev. 1.00 Oct. 03, 2008 Page xx of xxvi
19.4
19.3.2
Watchdog Timer Setting Flow.......................................................................... 673
19.3.3
Watchdog Timer Periodic Interrupt .................................................................. 674
Usage Notes ...................................................................................................................... 675
19.4.1
Notes on System Design ................................................................................... 675
19.4.2
Notes on Stopping the Watchdog Timer or Switching the Count Clock .......... 675
Section 20 Serial Communication Interface 3 (SCI3, IrDA).............................677
20.1
20.2
20.3
20.4
20.5
20.6
20.7
20.8
20.9
Features............................................................................................................................. 677
Register Descriptions........................................................................................................ 682
20.2.1
Receive Shift Register (RSR) ........................................................................... 683
20.2.2
Receive Data Register (RDR) ........................................................................... 683
20.2.3
Transmit Shift Register (TSR) .......................................................................... 683
20.2.4
Transmit Data Register (TDR).......................................................................... 684
20.2.5
Serial Mode Register (SMR) ............................................................................ 684
20.2.6
Serial Control Register 3 (SCR3)...................................................................... 686
20.2.7
Serial Status Register (SSR) ............................................................................. 688
20.2.8
Bit Rate Register (BRR) ................................................................................... 690
20.2.9
Sampling Mode Register (SPMR) .................................................................... 695
20.2.10 IrDA Control Register (IrCR) ........................................................................... 695
Operation in Asynchronous Mode .................................................................................... 697
20.3.1
Clock................................................................................................................. 697
20.3.2
SCI3 Initialization............................................................................................. 698
20.3.3
Data Transmission ............................................................................................ 700
20.3.4
Data Reception.................................................................................................. 702
Operation in Clocked Synchronous Mode ........................................................................ 706
20.4.1
Clock................................................................................................................. 706
20.4.2
SCI3 Initialization............................................................................................. 706
20.4.3
Data Transmission ............................................................................................ 707
20.4.4
Data Reception (Clocked Synchronous Mode)................................................. 709
20.4.5
Simultaneous Data Transmission and Reception .............................................. 711
Multiprocessor Communication Function......................................................................... 713
20.5.1
Multiprocessor Data Transmission ................................................................... 714
20.5.2
Multiprocessor Data Reception......................................................................... 716
IrDA Operation ................................................................................................................. 720
20.6.1
Transmission..................................................................................................... 721
20.6.2
Reception .......................................................................................................... 721
20.6.3
High-Level Pulse Width Selection.................................................................... 722
Noise Canceler.................................................................................................................. 723
Interrupt Requests ............................................................................................................. 724
Usage Notes ...................................................................................................................... 725
Rev. 1.00 Oct. 03, 2008 Page xxi of xxvi
20.9.1
20.9.2
20.9.3
20.9.4
20.9.5
20.9.6
Break Detection and Processing ....................................................................... 725
Mark State and Break Sending ......................................................................... 725
Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only) ................................................................. 725
Receive Data Sampling Timing and Reception Margin in
Asynchronous Mode ......................................................................................... 726
Relation between Writes to TDR and TDRE Flag............................................ 727
Restrictions on Using DTC............................................................................... 727
Section 21 I2C Bus Interface 2 (IIC2)................................................................ 729
21.1
21.2
21.3
21.4
21.5
21.6
Features............................................................................................................................. 729
Register Descriptions........................................................................................................ 732
21.2.1
IIC2/SSU Select Register (ICSUSR) ................................................................ 733
21.2.2
I2C Bus Control Register 1 (ICCR1)................................................................. 733
21.2.3
I2C Bus Control Register 2 (ICCR2)................................................................. 736
21.2.4
I2C Bus Mode Register (ICMR)........................................................................ 738
21.2.5
I2C Bus Interrupt Enable Register (ICIER)....................................................... 739
21.2.6
I2C Bus Status Register (ICSR)......................................................................... 741
21.2.7
Slave Address Register (SAR).......................................................................... 745
21.2.8
I2C Bus Transmit Data Register (ICDRT) ........................................................ 745
21.2.9
I2C Bus Receive Data Register (ICDRR).......................................................... 746
21.2.10 I2C Bus Shift Register (ICDRS)........................................................................ 746
Operation .......................................................................................................................... 747
21.3.1
I2C Bus Format.................................................................................................. 747
21.3.2
Master Transmit Operation............................................................................... 748
21.3.3
Master Receive Operation ................................................................................ 750
21.3.4
Slave Transmit Operation ................................................................................. 752
21.3.5
Slave Receive Operation................................................................................... 755
21.3.6
Clock Synchronous Serial Format .................................................................... 756
21.3.7
Noise Filter Circuit ........................................................................................... 759
21.3.8
Example of Use................................................................................................. 760
Interrupt Request .............................................................................................................. 764
Bit Synchronous Circuit.................................................................................................... 765
Usage Notes ...................................................................................................................... 766
21.6.1
SCL and SDA pins selected by PMC ............................................................... 766
21.6.2
Restriction on Use of Bit Manipulation Instructions to Set MST and
TRS in Multi-Master Usage.............................................................................. 766
Section 22 Synchronous Serial Communication Unit (SSU) ............................ 767
22.1
Features............................................................................................................................. 767
Rev. 1.00 Oct. 03, 2008 Page xxii of xxvi
22.2
22.3
22.4
22.5
Register Descriptions........................................................................................................ 769
22.2.1
IIC2/SSU Select Register (ICSUSR) ................................................................ 769
22.2.2
SS Control Register H (SSCRH) ...................................................................... 770
22.2.3
SS Control Register L (SSCRL) ....................................................................... 771
22.2.4
SS Mode Register (SSMR) ............................................................................... 773
22.2.5
SS Mode Register 2 (SSMR2) .......................................................................... 774
22.2.6
SS Enable Register (SSER) .............................................................................. 776
22.2.7
SS Status Register (SSSR) ................................................................................ 777
22.2.8
SS Receive Data Register (SSRDR) ................................................................. 779
22.2.9
SS Transmit Data Register (SSTDR)................................................................ 779
22.2.10 SS Shift Register (SSTRSR)............................................................................. 780
Operation .......................................................................................................................... 780
22.3.1
Transfer Clock .................................................................................................. 780
22.3.2
Relationship between Clock Polarity and Phase, and Data............................... 780
22.3.3
Relationship between Data Input/Output Pin and Shift Register ...................... 782
22.3.4
Communication Modes and Pin Functions ....................................................... 783
22.3.5
Operation in Clocked Synchronous Communication Mode.............................. 784
22.3.6
Operation in Four-Line Bus Communication Mode ......................................... 791
22.3.7
SCS Pin Control and Arbitration ...................................................................... 797
Interrupt Requests ............................................................................................................. 798
Usage Notes ...................................................................................................................... 799
Section 23 Hardware LIN ..................................................................................801
23.1
23.2
23.3
23.4
23.5
Overview........................................................................................................................... 801
Register Configuration...................................................................................................... 802
23.2.1
LIN Control Register (LINCR)......................................................................... 802
23.2.2
LIN Status Register (LINST)............................................................................ 804
Operation .......................................................................................................................... 805
23.3.1
Master Mode ..................................................................................................... 805
23.3.2
Slave Mode ....................................................................................................... 808
23.3.3
Bus Conflict Detection Function....................................................................... 813
23.3.4
Terminating Hardware LIN .............................................................................. 814
Interrupt Requests ............................................................................................................. 815
Usage Note........................................................................................................................ 815
Section 24 A/D Converter..................................................................................817
24.1
24.2
Features............................................................................................................................. 817
Register Description ......................................................................................................... 821
24.2.1
A/D Data Registers 0 to 7 (ADDR0 to ADDR7) .............................................. 822
24.2.2
A/D Control/Status Register (ADCSR) ............................................................ 823
Rev. 1.00 Oct. 03, 2008 Page xxiii of xxvi
24.3
24.4
24.5
24.6
24.7
24.8
24.2.3
A/D Control Register (ADCR) ......................................................................... 825
24.2.4
A/D Mode Register (ADMR) ........................................................................... 827
24.2.5
Compare Data Register (CMPR) ...................................................................... 828
24.2.6
Compare Control Status Register (CMPCSR) .................................................. 830
24.2.7
Compare Analog Level Registers H and L (CMPVALH and CMPVALL) ..... 832
Operation .......................................................................................................................... 834
A/D Conversion Mode Operation..................................................................................... 835
24.4.1
Single Mode in A/D Conversion Mode ............................................................ 835
24.4.2
Scan Mode in A/D Conversion Mode............................................................... 837
Compare Mode Operation ................................................................................................ 839
24.5.1
Single Mode in Compare Mode........................................................................ 839
24.5.2
Scan Mode in Comparison Mode ..................................................................... 840
24.5.3
Input Sampling and A/D Conversion Time ...................................................... 841
24.5.4
External Trigger Input Timing.......................................................................... 843
Interrupt Source ................................................................................................................ 844
A/D Conversion Accuracy Definitions ............................................................................. 845
Usage Notes ...................................................................................................................... 847
24.8.1
Module Standby Mode Setting ......................................................................... 847
24.8.2
Permissible Signal Source Impedance .............................................................. 847
24.8.3
Influences on Absolute Precision...................................................................... 848
24.8.4
Setting Range of Analog Power Supply and Other Pins................................... 848
24.8.5
Notes on Board Design ..................................................................................... 848
24.8.6
Notes on Noise Countermeasures ..................................................................... 849
24.8.7
Notes on Analog Input Pins .............................................................................. 850
Section 25 D/A Converter ................................................................................. 851
25.1
25.2
25.3
25.4
Features............................................................................................................................. 851
Register Descriptions........................................................................................................ 852
25.2.1
D/A Data Registers 0 and 1 (DADR0 and DADR1)......................................... 852
25.2.2
D/A Control Register (DACR) ......................................................................... 853
Operation .......................................................................................................................... 854
Usage Notes ...................................................................................................................... 856
25.4.1
Setting for Module Stop Mode ......................................................................... 856
25.4.2
Operation in Standby Mode .............................................................................. 856
Section 26 Low-Voltage Detection Circuits...................................................... 857
26.1
26.2
Features............................................................................................................................. 858
Register Descriptions........................................................................................................ 860
26.2.1
Low-Voltage Detection Circuit Control Protect Register (VDCPR) ................ 861
26.2.2
Low-Voltage Detection Circuit 2 Control Register H (LD2CRH) ................... 862
Rev. 1.00 Oct. 03, 2008 Page xxiv of xxvi
26.3
26.2.3
Low-Voltage Detection Circuit 2 Control Register L (LD2CRL) .................... 864
26.2.4
Low-Voltage Detection Circuit 1 Control Register H (LD1CRH) ................... 865
26.2.5
Low-Voltage Detection Circuit 1 Control Register L (LD1CRL) .................... 867
26.2.6
Low-Voltage Detection Circuit 0 Control Register H (LD0CRH) ................... 868
26.2.7
Low-Voltage Detection Circuit 0 Control Register L (LD0CRL) .................... 869
Operation .......................................................................................................................... 870
26.3.1
Power-On Reset Function ................................................................................. 870
26.3.2
Low-Voltage Detection Circuit......................................................................... 871
Section 27 List of Registers ...............................................................................883
27.1
27.2
Register Addresses (Address Order)................................................................................. 884
Register Bits...................................................................................................................... 900
Section 28 Electrical Characteristics .................................................................915
28.1
28.2
Absolute Maximum Ratings ............................................................................................. 915
Electrical Characteristics .................................................................................................. 916
28.2.1
Power Supply Voltage and Operating Ranges .................................................. 916
28.3 DC Characteristics ............................................................................................................ 918
28.4 AC Characteristics ............................................................................................................ 928
28.5 A/D Converter Characteristics .......................................................................................... 934
28.6 D/A Converter Characteristics .......................................................................................... 936
28.7 Flash Memory Characteristics .......................................................................................... 937
28.8 Electrical Characteristics for Low-Voltage Detection Circuits......................................... 939
28.9 Electrical Characteristics for Power-On Reset Function................................................... 942
28.10 Timing Charts ................................................................................................................... 943
28.11 Output Load Circuit .......................................................................................................... 951
Appendix..............................................................................................................953
A.
B.
Package Dimensions ......................................................................................................... 953
Handling of Unused Pins .................................................................................................. 957
Index ....................................................................................................................959
Rev. 1.00 Oct. 03, 2008 Page xxv of xxvi
Rev. 1.00 Oct. 03, 2008 Page xxvi of xxvi
Section 1 Overview
Section 1 Overview
1.1
Features
The H8S/Tiny series is a 16-bit CISC (complex instruction set computer) microcontroller, each
member of the H8S/Tiny series has the powerful H8S/2000 CPU with an internal 32-bit
architecture as its core. The H8S/2000 CPU provides upwards-compatibility with the other
members of the Renesas Technology H8 Family: H8/300, H8/300H Tiny and H8/300H.
The on-chip peripheral function modules include a data transfer controller, event link controller,
serial communication interface, I2C bus interface 2, synchronous serial communication unit,
hardware LIN communication interface, A/D and D/A converters, low-voltage detection circuit,
and versatile timers. These modules realize low-cost systems. The power consumption of these
modules can be controlled dynamically using power-down modes.
1.1.1
Applications
Examples of the applications include home appliances, office automation equipment, consumer
equipment, and industrial equipment.
1.1.2
Overview of Functions
Table 1.1 lists the specifications of the products of this series.
Table 1.1
Overview of Functions
Classification
Module/
Function
Description
Memory
ROM
•
Flash memory version
Program memory: 128 kbytes or 96 kbytes
Number of program/erase times: 1000 times
Data flash: 4 kbytes × two blocks
Number of program/erase times: 10000 times
RAM
•
Capacity: 8 kbytes
Rev. 1.00 Oct. 03, 2008 Page 1 of 962
REJ09B0465-0100
Section 1 Overview
Classification
Module/
Function
Description
CPU
CPU
•
16-bit high-speed H8S/2000 CPU (CISC type)
Upwardly compatible with H8/300 and H8/300H CPUs at object
level
•
General-register architecture (sixteen 16-bit general registers)
•
Eight addressing modes
•
16-Mbyte address space
 Program: 16 Mbytes available
 Data: 16 Mbytes available
Interrupt
(source)
•
65 basic instructions including bit operation instructions,
multiply and divide instructions, bit manipulation instructions,
and others
•
Minimum instruction execution time: 50 ns (for an ADD
instruction) while system clock φ = 20 MHz and
VCC = 2.7 to 5.5 V
Operating
mode
Advanced single-chip mode
Interrupt
controller
(INTC)
•
Nine external interrupt pins (NMI, and IRQ7 to IRQ0)
•
Internal interrupt sources
 55 (H8S/20103 group)
 61 (H8S/20203 group)
 63 (H8S/20223 group)
Clock
Clock pulse
generator
(CPG)
•
Two interrupt control modes (specified by the interrupt control
register)
•
Four interrupt priority orders specifiable (by setting the interrupt
priority register)
•
Independent vector addresses
•
Two clock generation circuits: main and sub-clock oscillators
•
Two on-chip oscillators
 High speed: 40 MHz
 Low speed: 125 kHz
•
Rev. 1.00 Oct. 03, 2008 Page 2 of 962
REJ09B0465-0100
Three power-down modes: sleep mode, software standby
mode, and module standby mode
Section 1 Overview
Classification
Module/
Function
Description
Voltage
detection
Voltage
Voltage drop detected
detection
circuit (LVD)
DMA
Data transfer •
controller
•
(DTC)
A/D converter
A/D
converter
(ADC)
Transfer via any number of channels possible
Three transfer modes
•
•
•
•
10-bit resolution × eight to sixteen input channels
Sample and hold function included
Conversion time: 2 µs per channel
Two operating modes: single mode and scan mode
•
Three ways to start A/D conversion: software, timer trigger,
and external pin trigger.
8-bit resolution × two input channels
D/A converter
D/A
converter
(DAC)
•
Timers
Timer RA
8 bits × one channel (with 8-bit prescaler)
Timer RB
8 bits × one channel (with 8-bit prescaler)
Timer RC
16 bits × one channel (only available with H8S/20103 group)
Timer RD
16 bits × two channels (× two units in H8S/20203 and H8S/20223
groups)
Timer RE
8 bits × one channel with real-time clock function
Timer RG
16 bits × one channel with phase-counting mode
Watchdog
8 bit × one channel
timer (WDT)
Serial interfaces Serial
communication
interface
(SCI3)
Synchronous serial
communication unit
(SSU)
•
Three channels (either for asynchronous or clock-synchronous
communication)
• Full-duplex communication capability
• Any desired bit rate selectable
IrDA (only available with channel 2)
•
•
One channel (IIC2 and selection format)
Clock-synchronous communication with chip-select function
Rev. 1.00 Oct. 03, 2008 Page 3 of 962
REJ09B0465-0100
Section 1 Overview
Classification
Module/
Function
2
Serial interfaces I C bus
interface 2
(IIC2)
Description
•
•
One channel (SSU and selection format)
Continuous transmission and reception possible
•
Two transmission/reception formats
 I C bus format: generates start and stop conditions in
master mode automatically, acknowledge bit, master or
slave operation
2
 Clock-synchronous serial format: no acknowledge bit,
master operation only
Hardware
One channel (timer RA and SCI3 used)
LIN interface
Event link controller (ELC)
Events (interrupts) generated by peripheral modules can be
interconnected between modules, enabling cooperation between
the modules without CPU intervention.
I/O ports
•
I/O pins
 55 (H8S/20103 group)
 69 (H8S/20203 and H8S/20223 groups)
•
•
Rev. 1.00 Oct. 03, 2008 Page 4 of 962
REJ09B0465-0100
Pull-up resistors settable for all ports
LED driving capability
Section 1 Overview
Classification
Module/
Function
Packages
Description
•
64-pin QFP package (PLQP0064KB-A)
 Former code: 64P6Q-A
 Body size: 10 × 10 mm
 Pin pitch: 0.50 mm
•
64-pin QFP package (PLQP0064GA-A)
 Former code: 64P6U-A
 Body size: 14 × 14 mm
 Pin pitch: 0.80 mm
•
80-pin QFP package (PLQP0080JA-A)
 Former code: FP-80W
 Body size: 14 × 14 mm
 Pin pitch: 0.65 mm
•
80-pin QFP package (PLQP0080KB-A)
 Former code: 80P6Q-A
 Body size: 12 × 12 mm
 Pin pitch: 0.50 mm
Operating frequency/
Power supply voltage
Operating ambient
temperature (°C)
•
•
•
•
Operating frequency: 4 to 20 MHz
Power supply voltage: Vcc = 2.7 to 5.5 V, Avcc = 2.7 to 5.5 V
−20 to +85°C (version N)
−40 to +85°C (version D)
Rev. 1.00 Oct. 03, 2008 Page 5 of 962
REJ09B0465-0100
Section 1 Overview
1.2
List of Products
Table 1.2 lists products of this series, and figure 1.1 shows how to read the part number.
Table 1.2
List of Products
Group
Part No.
H8S/20103
R4F20103NFA 128 kbytes
8 kbytes
PLQP0064KB-A
R4F20102NFA 96 kbytes
8 kbytes
(LQFP1010-64)
R4F20103NFB 128 kbytes
8 kbytes
PLQP0064GA-A
R4F20102NFB 96 kbytes
8 kbytes
(LQFP1414-64)
H8S/20203
H8S/20223
ROM Capacity RAM Capacity Package
R4F20103DFA 128 kbytes
8 kbytes
PLQP0064KB-A
R4F20102DFA 96 kbytes
8 kbytes
(LQFP1010-64)
R4F20103DFB 128 kbytes
8 kbytes
PLQP0064GA-A
R4F20102DFB 96 kbytes
8 kbytes
(LQFP1414-64)
R4F20203NFC 128 kbytes
8 kbytes
PLQP0080KB-A
R4F20202NFC 96 kbytes
8 kbytes
(LQFP1212-80)
R4F20203NFD 128 kbytes
8 kbytes
PLQP0080JA-A
R4F20202NFD 96 kbytes
8 kbytes
(LQFP1414-80)
R4F20203DFC 128 kbytes
8 kbytes
PLQP0080KB-A
R4F20202DFC 96 kbytes
8 kbytes
(LQFP1212-80)
R4F20203DFD 128 kbytes
8 kbytes
PLQP0080JA-A
R4F20202DFD 96 kbytes
8 kbytes
(LQFP1414-80)
R4F20223NFC 128 kbytes
8 kbytes
PLQP0080KB-A
R4F20222NFC 96 kbytes
8 kbytes
(LQFP1212-80)
R4F20223NFD 128 kbytes
8 kbytes
PLQP0080JA-A
R4F20222NFD 96 kbytes
8 kbytes
(LQFP1414-80)
R4F20223DFC 128 kbytes
8 kbytes
PLQP0080KB-A
R4F20222DFC 96 kbytes
8 kbytes
(LQFP1212-80)
R4F20223DFD 128 kbytes
8 kbytes
PLQP0080JA-A
R4F20222DFD 96 kbytes
8 kbytes
(LQFP1414-80)
Rev. 1.00 Oct. 03, 2008 Page 6 of 962
REJ09B0465-0100
Remarks
Version N
Version D
Version N
Version D
Version N
Version D
Section 1 Overview
Part number R
4
F
20103
N
FA
Package type
FA: PLQP0064KB-A (64-pin version) or FC: PLQP0080KB-A (80-pin version)
FB: PLQP0064GA-A (64-pin version) or FD: PLQP0080JA-A (80-pin version)
Operating temperature
N: -20°C to +85°C
D: -40°C to +85°C
Product-specific code
H8S/20103
Memory type
F: On-chip flash memory
Product classification
4: Microcomputer
Indicates Renesas semiconductor product
Figure 1.1 How to Read the Part Number
Rev. 1.00 Oct. 03, 2008 Page 7 of 962
REJ09B0465-0100
Section 1 Overview
1.3
Block Diagram
X1
X2
Sub-clock
oscillator
Port 2
Main clock
oscillator
P20/SCK3
P21/RXD
P22/TXD
P23/TRCOI
P24/TRDOI_0
P25/SCK3_2
P26/RXD_2
P27/TXD_2
P30/FTIOA
P31/FTIOB
P32/FTIOC
P33/FTIOD
P34/FTCI
P35/SCK3_3
P36/RXD_3
P37/TXD_3
P50/TCLKA
P51/TCLKB
P52/TGIOA
P53/TGIOB
P54/SSO
P55/SSCK
P56/SDA/SCS
P57/SCL/SSI
Low-voltage
detection circuit
ELC
High-speed OCO
Low-speed OCO
P15/IRQ5
P16/IRQ6
P17/IRQ7
Port 3
PJ0/OSC1
PJ1/OSC2
P11/IRQ1
P12/IRQ2
P13/IRQ3
Port 5
DTC
RAM
Peripheral address bus
Peripheral data bus
Bus controller
Internal address bus
H8S/2000
CPU
ROM
Internal data bus
RES
TEST
Port 1
VCC
VSS
PMC
Interrupt controller
NMI
SCI3 × 3 channels
LIN × 1 channel
Port B
10-bit A/D
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6/DA0
PB7/AN7/DA1
8-bit timer
× 4 channels
· Timer RA
· Timer RB
· Timer RE
· WDT
16-bit timer
× 4 channels
· Timer RC
· Timer RD
· Timer RG
Port A
8-bit D/A
PA4
PA5
PA6
PA7
AVCC
AVss
Port 8
P85/TRAIO
P86/TRBO
P87/TREO
Figure 1.2 Block Diagram of H8S/20103 Group
Rev. 1.00 Oct. 03, 2008 Page 8 of 962
REJ09B0465-0100
Port 6
IIC2
SSU
P60/FTIOA0
P61/FTIOB0
P62/FTIOC0
P63/FTIOD0
P64/FTIOA1
P65/FTIOB1
P66/FTIOC1
P67/FTIOD1
Section 1 Overview
VCC
VSS
Port 2
P20/SCK3
P21/RXD
P22/TXD
P23
P24/TRDOI_0
P25/SCK3_2
P26/RXD_2
P27/TXD_2
Port 3
P30
P31
P32
P33
P34
P35/SCK3_3
P36/RXD_3
P37/TXD_3
P50/TCLKA
P51/TCLKB
P52/TGIOA
P53/TGIOB
P54/SSO
P55/SSCK
P56/SDA/SCS
P57/SCL/SSI
Low-voltage
detection circuit
Sub-clock
oscillator
X1
X2
ELC
High-speed OCO
Low-speed OCO
P10/IRQ0
P11/IRQ1
P12/IRQ2
P13/IRQ3
P14/IRQ4
P15/IRQ5
P16/IRQ6
P17/IRQ7
Port 5
Main clock
oscillator
Peripheral address bus
Peripheral data bus
DTC
RAM
PJ0/OSC1
PJ1/OSC2
Bus controller
H8S/2000
CPU
ROM
Internal data bus
RES
TEST
Internal address bus
Port 1
VSS
PMC
Interrupt controller
NMI
SCI3 × 3 channels
LIN × 1 channel
16-bit timer
× 5 channels
· Timer RD_0
· Timer RD_1
· Timer RG
P60/FTIOA0
P61/FTIOB0
P62/FTIOC0
P63/FTIOD0
P64/FTIOA1
P65/FTIOB1
P66/FTIOC1
P67/FTIOD1
8-bit D/A
Port A
PA0/AN8
PA1/AN9
PA2/AN10
PA3/AN11
PA4
PA5
PA6
PA7
Port B
10-bit A/D
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6/DA0
PB7/AN7/DA1
8-bit timer
× 4 channels
· Timer RA
· Timer RB
· Timer RE
· WDT
Port 6
IIC2
SSU
AVCC
AVSS
Port 9
Port 8
P90/FTIOA2
P91/FTIOB2
P92/FTIOC2
P93/FTIOD2
P94/FTIOA3
P95/FTIOB3
P96/FTIOC3
P97/FTIOD3
P85/TRAIO
P86/TRBO
P87/TREO
Figure 1.3 Block Diagram of H8S/20203 Group
Rev. 1.00 Oct. 03, 2008 Page 9 of 962
REJ09B0465-0100
Section 1 Overview
Sub-clock
oscillator
Port 1
X1
X2
Port 2
Main clock
oscillator
P20/SCK3
P21/RXD
P22/TXD
P23
P24/TRDOI_0
P25/SCK3_2
P26/RXD_2
P27/TXD_2
Port 3
PJ0/OSC1
PJ1/OSC2
Peripheral address bus
DTC
RAM
Peripheral data bus
Bus controller
Internal address bus
H8S/2000
CPU
ROM
Internal data bus
RES
TEST
P10/IRQ0
P11/IRQ1
P12/IRQ2
P13/IRQ3
P14/IRQ4
P15/IRQ5
P16/IRQ6
P17/IRQ7
P30
P31
P32
P33
P34
P35/SCK3_3
P36/RXD_3
P37/TXD_3
Port 5
VSS
P50/TCLKA
P51/TCLKB
P52/TGIOA
P53/TGIOB
P54/SSO
P55/SSCK
P56/SDA/SCS
P57/SCL/SSI
Port 6
VCC
VSS
P60/FTIOA0
P61/FTIOB0
P62/FTIOC0
P63/FTIOD0
P64/FTIOA1
P65/FTIOB1
P66/FTIOC1
P67/FTIOD1
Low-voltage
detection circuit
ELC
High-speed OCO
Low-speed OCO
PMC
Interrupt controller
NMI
SCI3 × 3 channels
LIN × 1 channel
IIC2
SSU
PA0/AN8
PA1/AN9
PA2/AN10
PA3/AN11
PA4/AN0_2
PA5/AN1_2
PA6/AN2_2
PA7/AN3_2
Port B
10-bit A/D
(unit 1)
10-bit A/D
(unit 2)
16-bit timer
× 5 channels
· Timer RD_0
· Timer RD_1
· Timer RG
8-bit D/A
Port A
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6/DA0
PB7/AN7/DA1
8-bit timer
× 4 channels
· Timer RA
· Timer RB
· Timer RE
· WDT
AVCC
AVSS
Port 9
Port 8
P85/TRAIO
P86/TRBO
P87/TREO
P90/FTIOA2
P91/FTIOB2
P92/FTIOC2
P93/FTIOD2
P94/FTIOA3
P95/FTIOB3
P96/FTIOC3
P97/FTIOD3
Figure 1.4 Block Diagram of H8S/20223 Group
Rev. 1.00 Oct. 03, 2008 Page 10 of 962
REJ09B0465-0100
Section 1 Overview
Pin Assignments
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
49
32
50
31
51
30
52
29
53
28
H8S/20103 Group
PLQP0064KB-A
64P6Q-A/FP-64K
PLQP0064GA-A
64P6U-A
(top view)
54
55
56
57
58
59
27
26
25
24
23
22
16
15
14
13
12
11
9
10
8
17
7
18
64
6
63
5
19
4
20
62
3
61
2
21
1
60
P63/FTIOD0
P50/TCLKA
P51/TCLKB
P52/TGIOA
P53/TGIOB
P57/SCL/SSI
P56/SDA/SCS
P55/SSCK
P54/SSO
P17/IRQ7
P16/IRQ6
P15/IRQ5
P30/FTIOA
P31/FTIOB
P32/FTIOC
P33/FTIOD
PB6/AN6/DA0
PB7/AN7/DA1
AVCC
X2
X1
AVSS
RES
TEST
Vss
PJ1/OSC2
PJ0/OSC1
VCC
P37/TXD_3
P36/RXD_3
P35/SCK3_3
P34/FTCI
P26/RXD_2
P27/TXD_2
P24/TRDOI_0
P11/IRQ1
P12/IRQ2
P13/IRQ3
PA4
PA5
PA6
PA7
PB3/AN3
PB2/AN2
PB1/AN1
PB0/AN0
PB4/AN4
PB5/AN5
48
P25/SCK3_2
P23/TRCOI
P22/TXD
P21/RXD
P20/SCK3
P87/TREO
P86/TRBO
P85/TRAIO
P67/FTIOD1
P66/FTIOC1
P65/FTIOB1
P64/FTIOA1
P60/FTIOA0
NMI
P61/FTIOB0
P62/FTIOC0
1.4
Figure 1.5 Pin Assignment of H8S/20103 Group
Rev. 1.00 Oct. 03, 2008 Page 11 of 962
REJ09B0465-0100
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
61
40
62
39
63
38
64
37
65
36
66
35
67
34
H8S/20203 Group
PLQP0080JA-A
FP-80W
PLQP0080KB-A
80P6Q-A
(top view)
68
69
70
71
72
73
33
32
31
30
29
28
20
19
18
17
16
15
14
13
12
11
PB6/AN6/DA0
PB7/AN7/DA1
AVCC
X2
X1
NC
RES
TEST
Vss
PJ1/OSC2
PJ0/OSC1
VCC
NMI
P87/TREO
P86/TRBO
P85/TRAIO
P37/TXD_3
P36/RXD_3
P35/SCK3_3
P34
9
10
21
8
22
80
7
23
79
6
24
78
5
25
77
4
26
76
3
27
75
2
74
1
P97/FTIOD3
P90/FTIOA2
P91/FTIOB2
P92/FTIOC2
P93/FTIOD2
PA4
PA5
PA6
PA7
PA0/AN8
PA1/AN9
PA2/AN10
PA3/AN11
AVss
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
59
60
P96/FTIOC3
P95/FTIOB3
P94/FTIOA3
P13/IRQ3
P12/IRQ2
P23
P22/TXD
P21/RXD
P20/SCK3
P24/TRDOI_0
VSS
P67/FTIOD1
P66/FTIOC1
P65/FTIOB1
P64/FTIOA1
P63/FTIOD0
P62/FTIOC0
P61/FTIOB0
P60/FTIOA0
P25/SCK3_2
Section 1 Overview
Note: Do not connect any pin to NC.
Figure 1.6 Pin Assignment of H8S/20203 Group
Rev. 1.00 Oct. 03, 2008 Page 12 of 962
REJ09B0465-0100
P26/RXD_2
P27/TXD_2
P11/IRQ1
P10/IRQ0
P50/TCLKA
P51/TCLKB
P52/TGIOA
P53/TGIOB
P54/SSO
P55/SSCK
P56/SDA/SCS
P57/SCL/SSI
P17/IRQ7
P16/IRQ6
P15/IRQ5
P14/IRQ4
P30
P31
P32
P33
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
61
40
62
39
63
38
64
37
65
36
66
35
67
34
H8S/20223 Group
PLQP0080JA-A
FP-80W
PLQP0080KB-A
80P6Q-A
(top view)
68
69
70
71
72
73
33
32
31
30
29
28
20
19
18
17
16
15
14
13
12
11
P26/RXD_2
P27/TXD_2
P11/IRQ1
P10/IRQ0
P50/TCLKA
P51/TCLKB
P52/TGIOA
P53/TGIOB
P54/SSO
P55/SSCK
P56/SDA/SCS
P57/SCL/SSI
P17/IRQ7
P16/IRQ6
P15/IRQ5
P14/IRQ4
P30
P31
P32
P33
PB6/AN6/DA0
PB7/AN7/DA1
AVCC
X2
X1
NC
RES
TEST
Vss
PJ1/OSC2
PJ0/OSC1
VCC
NMI
P87/TREO
P86/TRBO
P85/TRAIO
P37/TXD_3
P36/RXD_3
P35/SCK3_3
P34
9
10
21
8
22
80
7
23
79
6
24
78
5
25
77
4
26
76
3
27
75
2
74
1
P97/FTIOD3
P90/FTIOA2
P91/FTIOB2
P92/FTIOC2
P93/FTIOD2
PA4/AN0_2
PA5/AN1_2
PA6/AN2_2
PA7/AN3_2
PA0/AN8
PA1/AN9
PA2/AN10
PA3/AN11
AVss
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
59
60
P96/FTIOC3
P95/FTIOB3
P94/FTIOA3
P13/IRQ3
P12/IRQ2
P23
P22/TXD
P21/RXD
P20/SCK3
P24/TRDOI_0
VSS
P67/FTIOD1
P66/FTIOC1
P65/FTIOB1
P64/FTIOA1
P63/FTIOD0
P62/FTIOC0
P61/FTIOB0
P60/FTIOA0
P25/SCK3_2
Section 1 Overview
Note: Do not connect any pin to NC.
Figure 1.7 Pin Assignment of H8S/20223 Group
Rev. 1.00 Oct. 03, 2008 Page 13 of 962
REJ09B0465-0100
Section 1 Overview
1.4.1
Table 1.3
Pin Functions
Pin Functions
Pin No.
Classification Symbol
H8S/20203 and
H8S/20103 H8S/20223
Group
Groups
I/O
Power supply
VCC
12
12
Input
Power supply pin.
Connect this pin to the
system power supply.
VSS
9
9, 50
Input
Ground pin. Connect this
pin to the system power
supply (0 V).
AVCC
3
3
Input
Analog power supply pin
for A/D and D/A
converters. When A/D
and D/A converters are
not used, connect this pin
to the system power
supply.
AVSS
6
74
Input
Analog ground pin for A/D
and D/A converters.
Connect this pin to the
system power supply (0
V).
OSC1
11
11
Input
OSC2/CLKOUT 10
10
Clock
Rev. 1.00 Oct. 03, 2008 Page 14 of 962
REJ09B0465-0100
Description
Pins to be connected to a
crystal or ceramic
Output
resonator for the system
clock. An external clock
can also be input to
OSC1. When the on-chip
oscillator is not used, the
system clock signal can
be output from OSC2. For
connection examples, see
section 5, Clock Pulse
Generator.
Section 1 Overview
Pin No.
Classification
Symbol
H8S/20203 and
H8S/20103 H8S/20223
Group
Groups
I/O
Clock
X1
5
5
X2
4
4
RES
7
7
Input
Reset pin. Applying a low
level signal to this pin
resets this LSI.
TEST
8
8
Input
Test pin. Connect this pin
to VSS.
NMI
35
13
Input
Non-maskable interrupt
request input pin. Be sure
to pull up this pin with a
resistor.
IRQ0 to IRQ7
52 to 54*1
37, 38
Input
21 to 23
56, 57
External interrupt request
input pins. Either rising,
falling, or rising/falling
edge of these pins can be
detected.
Pin for pulse output, count
source input, and input of
pulses to be measured.
System control
External
interrupt
Pins to be connected to a
Output crystal resonator for the
32.768-kHz sub-clock. For
connection examples, see
section 5, Clock Pulse
Generator.
Input
25 to 28
Timer RA
Timer RB
Timer RC*3
Description
TRAIO
41
16
I/O
TRAO
*2
*2
Output Pin for inverted pulse
output.
TRGB
*2
*2
Input
TRBO
42
15
Output Pin for pulse output and
PWM output.
FTCI
16

Input
Pin for external event
input.
FTIOA to
FTIOD
20 to 17

I/O
Pins for output-compare
output, input-capture
input, and PWM output.
Pin for trigger input.
Rev. 1.00 Oct. 03, 2008 Page 15 of 962
REJ09B0465-0100
Section 1 Overview
Pin No.
Classification Symbol
Timer RC*
3
Timer RD_0
H8S/20203 and
H8S/20103 H8S/20223
Group
Groups
I/O
TRGC
20

Input
Pin for external trigger
input.
TRCOI
47

Input
Pin for inputting the timeroutput enable or disable
signal.
FTIOA0
36
42
I/O
Pin for output-compare
output, input-capture input,
and external clock input.
FTIOB0
34
43
I/O
Pin for output-compare
output, input-capture input,
and PWM output.
FTIOC0
33
44
I/O
Pin for output-compare
output, input-capture input,
and PWM synchronous
output (at reset or in
complementary PWM
mode).
FTIOD0
32
45
I/O
Pin for output-compare
output, input-capture input,
and PWM output.
FTIOA1
37
46
I/O
Pin for output-compare
output, input-capture input,
and PWM output (at reset
or in complementary PWM
mode).
FTIOB1 to
FTIOD1
38 to 40
47 to 49
I/O
Pins for output-compare
output, input-capture input,
and PWM output.
TRDOI_0
51
51
Input
Pin for inputting the timeroutput enable or disable
signal.
Rev. 1.00 Oct. 03, 2008 Page 16 of 962
REJ09B0465-0100
Description
Section 1 Overview
Pin No.
Classification Symbol
H8S/20203 and
H8S/20103 H8S/20223
Group
Groups
I/O
Description
FTIOA2

62
I/O
Pin for output-compare
output, input-capture
input, and external clock
input.
FTIOB2

63
I/O
Pin for output-compare
output, input-capture
input, and PWM output.
FTIOC2

64
I/O
Pin for output-compare
output, input-capture
input, and PWM
synchronous output (at
reset or in complementary
PWM mode).
FTIOD2

65
I/O
Pin for output-compare
output, input-capture
input, and PWM output.
FTIOA3

58
I/O
Pin for output-compare
output, input-capture
input, and PWM output (at
reset or in complementary
PWM mode).
FTIOB3 to
FTIOD3

59 to 61
I/O
Pins for output-compare
output, input-capture
input, and PWM output.
TRDOI_1

*4
Input
Pin for inputting the timeroutput enable or disable
signal.
Timer RE
TREO
43
14
Output Pin for clock signal output.
Timer RG
TCLKA
31
36
Input
TCLKB
30
35
Pins for external clock
input.
TGIOA
29
34
I/O
TGIOB
28
33
Pins for output-compare
output, input-capture
input, and PWM output.
5
Timer RD_1*
Rev. 1.00 Oct. 03, 2008 Page 17 of 962
REJ09B0465-0100
Section 1 Overview
Pin No.
Classification
Symbol
H8S/20203 and
H8S/20103 H8S/20223
Group
Groups
I/O
Serial
TXD
communication TXD_2
interface 3
TXD_3
(SCI3)
RXD
46
54
50
39
13
17
45
53
RXD_2
49
40
RXD_3
14
18
SCK3
44
52
SCK3_2
48
41
SCK3_3
15
19
SDA
26
SCL
2
I C bus
interface 2
(IIC2)
Output Output pins for data
transmission.
Input
Input pins for data
reception.
I/O
Input/output pins for clock
signals.
30
I/O
Input/output pin for I2C
data. Bus can be directly
driven by the NMOS
open-drain output. When
this pin is used, an
external pull-up resistor is
required.
27
29
I/O
Input/output pin for I2C
clock signal. Bus can be
directly driven by the
NMOS open-drain output.
When this pin is used, an
external pull-up resistor is
required.
26
30
I/O
Input/output pin for the
chip select signal.
25
31
I/O
Input/output pin for the
clock signal.
SSI
27
29
I/O
Input/output pin for data
transmission/reception.
SSO
24
32
I/O
Input/output pin for data
transmission/reception.
Synchronous
SCS
serial
communication SSCK
unit (SSU)
Rev. 1.00 Oct. 03, 2008 Page 18 of 962
REJ09B0465-0100
Description
Section 1 Overview
Pin No.
H8S/20203 and
H8S/20103 H8S/20223
Group
Groups
I/O
Classification Symbol
AD
converter_1
AD
8
converter_2*
DA converter
I/O ports
6
AN11 to AN0*
2, 1, 64,
63, 59 to
62
73 to 70, 2, 1
ADTRG1
*7
AN3_2 to
AN0_2
Description
Input
Analog input pins.
*7
Input
Input pin for the
conversion-start trigger
signal.

69 to 66
Input
Analog input pins.
ADTRG2

*7
Input
Input pin for the
conversion-start trigger
signal.
Output Analog output pins.
80 to 75
DA1
2
2
DA0
1
1
P17 to P10*9
23 to 21,
54 to 52
28 to 25, 57, 56, I/O
38, 37
P27 to P20
50, 49, 51, 39 to 41, 51, 55
48 to 44
to 52
I/O
8-bit input/output port pins.
P37 to P30
20 to 13
17 to 24
I/O
8-bit input/output port pins.
P57 to P50
31 to 28
29 to 36
I/O
8-bit input/output port pins.
36, 34 to
32, 37 to
40
49 to 42
I/O
8-bit input/output port pins.
41 to 43
14 to 16
I/O
3-bit input/output port pins.

61 to 58
I/O
8-bit input/output port pins.
I/O
8-bit input/output port pins.
8-bit input/output port pins.
24 to 27
P67 to P60
P87 to P85
10
P97 to P90*
65 to 62
PA7 to PA0*
11
58 to 55
69 to 66
73 to 70
Rev. 1.00 Oct. 03, 2008 Page 19 of 962
REJ09B0465-0100
Section 1 Overview
Pin No.
Classification Symbol
I/O ports
H8S/20203 and
H8S/20103 H8S/20223
Group
Groups
I/O
Description
PB7 to PB0
62 to 59,
2, 1, 80 to 75
63, 64, 1, 2
I/O
8-bit input/output port pins.
PJ1 and PJ0
10, 11
I/O
2-bit input/output port pins.
10, 11
Notes: 1. In the H8S/20103 group, the IRQ0 and IRQ4 pins are not available with the initial
setting of the PMC.
2. The TRAO and TRGB pins are not available with the initial setting of the PMC.
3. The H8S/20203 and H8S/20223 groups do not incorporate timer RC.
4. The TRDOI_1 pin is not available with the initial setting of the PMC.
5. The H8S/20103 group does not incorporate timer RD_1.
6. In the H8S/20103 group, AN8 to AN11 are not available.
7. The ADTRG1 and ADTRG2 functions are not available due to the initial setting of the
PMC.
8. The H8S/20103 and H8S/20203 group do not incorporate A/D converter_2.
9. The H8S/20103 group does not provide P14 or P10.
10. The H8S/20103 group does not provide P97 to P90.
11. The H8S/20103 group does not provide PA3 to PA0.
Rev. 1.00 Oct. 03, 2008 Page 20 of 962
REJ09B0465-0100
Section 2 CPU
Section 2 CPU
The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit
general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
This section describes the H8S/2000 CPU.
2.1
Features
• Upward-compatibility with H8/300 and H8/300H CPUs
Can execute H8/300 and H8/300H CPU object programs
• General-register architecture
Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers
• Sixty-five basic instructions
 8/16/32-bit arithmetic and logic instructions
 Multiply and divide instructions
 Powerful bit-manipulation instructions
• Eight addressing modes
 Register direct [Rn]
 Register indirect [@ERn]
 Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]
 Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
 Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
 Immediate [#xx:8, #xx:16, or #xx:32]
 Program-counter relative [@(d:8,PC) or @(d:16,PC)]
 Memory indirect [@@aa:8]
• 16-Mbyte address space
 Program: 16 Mbytes
 Data: 16 Mbytes
Rev. 1.00 Oct. 03, 2008 Page 21 of 962
REJ09B0465-0100
Section 2 CPU
• High-speed operation
All frequently-used instructions are executed in one or two states
 8/16/32-bit register-register add/subtract: 1 state
 8 × 8-bit register-register multiply: 12 states (MULXU.B), 13 states (MULXS.B)
 16 ÷ 8-bit register-register divide: 12 states (DIVXU.B)
 16 × 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W)
 32 ÷ 16-bit register-register divide: 20 states (DIVXU.W)
• Two CPU operating modes
 Normal mode
 Advanced mode
• Power-down state
Transition to power-down state by SLEEP instruction
Selectable CPU clock speed
2.1.1
Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
• Register configuration
The MAC register is supported only by the H8S/2600 CPU.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.
• The number of execution states of the MULXU and MULXS instructions
Execution States
Instruction
MULXU
MULXS
Mnemonic
H8S/2600
H8S/2000
MULXU.B Rs, Rd
3
12
MULXU.W Rs, ERd
4
20
MULXS.B Rs, Rd
4
13
MULXS.W Rs, ERd
5
21
In addition, there are differences in address space, CCR and EXR register functions, power-down
modes, etc., depending on the model.
Rev. 1.00 Oct. 03, 2008 Page 22 of 962
REJ09B0465-0100
Section 2 CPU
2.1.2
Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements.
• More general registers and control registers
Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been
added.
• Expanded address space
Normal mode supports the same 64-kbyte address space as the H8/300 CPU.
Advanced mode supports a maximum 16-Mbyte address space.
• Enhanced addressing
The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
• Enhanced instructions
Addressing modes of bit-manipulation instructions have been enhanced.
Signed multiply and divide instructions have been added.
Two-bit shift and two-bit rotate instructions have been added.
Instructions for saving and restoring multiple registers have been added.
A test and set instruction has been added.
• Higher speed
Basic instructions are executed twice as fast.
2.1.3
Differences from H8/300H CPU
In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements.
• Additional control register
One 8-bit control register has been added.
• Enhanced instructions
Addressing modes of bit-manipulation instructions have been enhanced.
Two-bit shift and two-bit rotate instructions have been added.
Instructions for saving and restoring multiple registers have been added.
A test and set instruction has been added.
• Higher speed
Basic instructions are executed twice as fast.
Rev. 1.00 Oct. 03, 2008 Page 23 of 962
REJ09B0465-0100
Section 2 CPU
2.2
CPU Operating Modes
The H8S/2000 CPU has two operating modes: normal and advanced. Note that this LSI supports
only advanced mode. Advanced mode supports a maximum 16-Mbyte address space.
2.2.1
Advanced Mode
• Address space
Linear access to a maximum address space of 16 Mbytes is possible.
• Extended registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers. They can also be used as the
upper 16-bit segments of 32-bit registers or address registers.
• Instruction set
All instructions and addressing modes can be used.
• Exception vector table and memory indirect branch addresses
In advanced mode, the top area starting at H'00000000 is allocated to the exception vector
table in 32-bit units. In each 32 bits, the upper 8 bits are ignored and a branch address is stored
in the lower 24 bits (see figure 2.1). For details of the exception vector table, see section 3,
Exception Handling.
Rev. 1.00 Oct. 03, 2008 Page 24 of 962
REJ09B0465-0100
Section 2 CPU
H'00000000
Reserved
Reset exception vector
H'00000003
H'00000004
Reserved
(Reserved for system use)
H'00000007
H'00000008
Exception vector table
(Reserved for system use)
H'00000014
Reserved
Exception vector 1
Figure 2.1 Exception Vector Table (Advanced Mode)
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In advanced mode, the operand is a 32-bit longword operand,
providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is
regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF.
Note that the top area of this range is also used for the exception vector table.
Rev. 1.00 Oct. 03, 2008 Page 25 of 962
REJ09B0465-0100
Section 2 CPU
• Stack structure
In advanced mode, the program counter (PC) is pushed onto the stack in a subroutine call, and
the PC and condition-code register (CCR) are pushed onto the stack in exception handling.
They are stored as shown in figure 2.2. EXR is not pushed onto the stack in interrupt control
mode 0. For details, see section 3, Exception Handling.
SP
PC
(16 bits)
EXR*1
SP
(SP
*2
Reserved*1*3
)
CCR
CCR*3
PC
(16 bits)
(a) Subroutine Branch
(b) Exception Handling
Notes: 1. When EXR is not used, it is not stored on the stack.
2. SP when EXR is not used.
3. lgnored when returning.
Figure 2.2 Stack Structure in Advanced Mode
Rev. 1.00 Oct. 03, 2008 Page 26 of 962
REJ09B0465-0100
Section 2 CPU
2.3
Address Space
Figure 2.3 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear
access to a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The
usable modes and address spaces differ depending on the product.
Rev. 1.00 Oct. 03, 2008 Page 27 of 962
REJ09B0465-0100
Section 2 CPU
H8S/20103
H'000000
H8S/20102
H'000000
Interrupt vectors
Interrupt vectors
On-chip flash ROM
(96 kbytes)
On-chip flash ROM
(128 kbytes)
H'017FFF
H'018000
H'01FFFF
H'020000
Reserved area
Reserved area
H'EFFFFF
H'F00000
H'F01FFF
H'F02000
Data flash area
(8 kbytes)
H'EFFFFF
H'F00000
H'F01FFF
H'F02000
Reserved area
Data flash area
(8 kbytes)
Reserved area
H'FF0000
H'FF0000
On-chip I/O registers
On-chip I/O registers
H'FF0FFF
H'FF1000
H'FF0FFF
H'FF1000
Reserved area
H'FFDF7F
H'FFDF80
Reserved area
H'FFDF7F
H'FFDF80
On-chip RAM
(8 kbytes)
H'FFFF7F
H'FFFF80
On-chip RAM
(8 kbytes)
H'FFFF7F
H'FFFF80
On-chip I/O registers
H'FFFFFF
On-chip I/O registers
H'FFFFFF
Figure 2.3 Memory Map (1) (H8S/20103 Group)
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Section 2 CPU
H8S/20203
H'000000
H8S/20202
H'000000
Interrupt vectors
Interrupt vectors
On-chip flash ROM
(96 kbytes)
On-chip flash ROM
(128 kbytes)
H'017FFF
H'018000
H'01FFFF
H'020000
Reserved area
Reserved area
H'EFFFFF
H'F00000
H'F01FFF
H'F02000
Data flash area
(8 kbytes)
H'EFFFFF
H'F00000
H'F01FFF
H'F02000
Reserved area
Data flash area
(8 kbytes)
Reserved area
H'FF0000
H'FF0000
On-chip I/O registers
On-chip I/O registers
H'FF0FFF
H'FF1000
H'FF0FFF
H'FF1000
Reserved area
H'FFDF7F
H'FFDF80
Reserved area
H'FFDF7F
H'FFDF80
On-chip RAM
(8 kbytes)
H'FFFF7F
H'FFFF80
On-chip RAM
(8 kbytes)
H'FFFF7F
H'FFFF80
On-chip I/O registers
H'FFFFFF
On-chip I/O registers
H'FFFFFF
Figure 2.3 Memory Map (2) (H8S/20203 Group)
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Section 2 CPU
H8S/20223
H'000000
H8S/20222
H'000000
Interrupt vectors
Interrupt vectors
On-chip flash ROM
(96 kbytes)
On-chip flash ROM
(128 kbytes)
H'017FFF
H'018000
H'01FFFF
H'020000
Reserved area
Reserved area
H'EFFFFF
H'F00000
H'F01FFF
H'F02000
Data flash area
(8 kbytes)
H'EFFFFF
H'F00000
H'F01FFF
H'F02000
Reserved area
Data flash area
(8 kbytes)
Reserved area
H'FF0000
H'FF0000
On-chip I/O registers
On-chip I/O registers
H'FF0FFF
H'FF1000
H'FF0FFF
H'FF1000
Reserved area
H'FFDF7F
H'FFDF80
Reserved area
H'FFDF7F
H'FFDF80
On-chip RAM
(8 kbytes)
H'FFFF7F
H'FFFF80
On-chip RAM
(8 kbytes)
H'FFFF7F
H'FFFF80
On-chip I/O registers
H'FFFFFF
On-chip I/O registers
H'FFFFFF
Figure 2.3 Memory Map (3) (H8S/20223 Group)
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Section 2 CPU
2.4
Register Configuration
The H8S/2000 CPU has the internal registers shown in figure 2.4. There are two types of registers:
general registers and control registers. Control registers are a 24-bit program counter (PC), an 8bit extended control register (EXR), and an 8-bit condition code register (CCR).
General Registers (Rn) and Extended Registers (En)
15
0 7
0 7
0
ER0
E0
R0H
R0L
ER1
E1
R1H
R1L
ER2
E2
R2H
R2L
ER3
E3
R3H
R3L
ER4
E4
R4H
R4L
ER5
E5
R5H
R5L
ER6
E6
R6H
R6L
ER7 (SP)
E7
R7H
R7L
Control Registers
23
0
PC
7 6 5 4 3 2 1 0
- - - - I2 I1 I0
EXR T
7 6 5 4 3 2 1 0
CCR I UI H U N Z V C
Legend:
SP
PC
EXR
T
I2 to I0
CCR
I
UI
: Stack pointer
: Program counter
: Extended control register
: Trace bit
: Interrupt mask bits
: Condition-code register
: Interrupt mask bit
: User bit or interrupt mask bit*
H
U
N
Z
V
C
: Half-carry flag
: User bit
: Negative flag
: Zero flag
: Overflow flag
: Carry flag
Note: * For this LSI, the interrupt mask bit is not available.
Figure 2.4 CPU Internal Registers
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Section 2 CPU
2.4.1
General Registers
The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally
alike and can be used as both address registers and data registers. When a general register is used
as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.5 illustrates the
usage of the general registers. When the general registers are used as 32-bit registers or address
registers, they are designated by the letters ER (ER0 to ER7).
When the general registers are used as 16-bit registers, the ER registers are divided into 16-bit
general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are
functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7)
are also referred to as extended registers.
When the general registers are used as 8-bit registers, the R registers are divided into 8-bit general
registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are
functionally equivalent, providing a maximum sixteen 8-bit registers.
The usage of each register can be selected independently.
General register ER7 has the function of the stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.6 shows the
stack.
• Address registers
• 32-bit registers
• 16-bit registers
• 8-bit registers
E registers (extended registers)
(E0 to E7)
ER registers
(ER0 to ER7)
RH registers
(R0H to R7H)
R registers
(R0 to R7)
RL registers
(R0L to R7L)
Figure 2.5 Usage of General Registers
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Section 2 CPU
Free area
SP (ER7)
Stack area
Figure 2.6 Stack
2.4.2
Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched for read, the least significant PC bit is regarded as 0.)
2.4.3
Extended Control Register (EXR)
EXR is an 8-bit register that can be operated by the LDC, STC, ANDC, ORC, and XORC
instructions. When an instruction other than STC is executed, all interrupts including NMI are
masked in three states after the instruction is completed.
Bit
Symbol
Bit Name
Description
R/W
7
T
Trace bit
0: Consecutively executes instructions.
R/W
1: Starts trace exception processing each time an
instruction is executed.
6 to 3 
Reserved
These bits are always read as 1.

2 to 0 I2*
I1
I0
Interrupt
request mask
level 2 to 0
These bits specify interrupt request mask levels
(0 to 3). For details, see section 4, Interrupt
Controller.
R/W
Note:
*
The I2-bit is reserved in this product. The I2 bit is set to 1 if an interrupt is accepted, but
this does not affect the mask level for interrupt requests.
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Section 2 CPU
2.4.4
Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
Bit
Symbol
Bit Name
Description
R/W
7
I
Interrupt mask
bit
0: Does not mask interrupts.
R/W
1: Masks interrupts.
6
UI
User bit or
interrupt mask
bit
This bit does not affect this LSI operation.
R/W
5
H
Half-carry flag
[Setting conditions]
R/W
•
•
•
If there is a carry or borrow bit 3 when the
ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B or
NEG.B instruction is executed.
If there is a carry or borrow at bit 11 when the
ADD.W, SUB.W, CMP.W, or NEG.W instruction
is executed.
If there is a carry or borrow at bit 27 when the
ADD.L, SUB.L, CMP.L, or NEG.L instruction is
executed.
[Clearing condition]
When none of the above setting conditions are
satisfied.
4
U
User bit
3
N
Negative flag
This bit does not affect the LSI operation.
R/W
[Setting condition]
R/W
When the execution result is negative.
[Clearing condition]
When the execution result is not negative.
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Section 2 CPU
Bit
Symbol
Bit Name
Description
R/W
2
Z
Zero flag
[Setting condition]
R/W
When data is zero.
[Clearing condition]
When data is not zero.
1
V
Overflow flag
[Setting condition]
R/W
When an overflow occurs after an arithmetic
instruction has been executed.
[Clearing condition]
When no overflow occurs after an arithmetic
instruction has been executed.
0
C
Carry flag
[Setting condition]
R/W
When a carry occurs after an instruction has been
executed.
[Clearing condition]
When no carry occurs after an instruction has been
executed.
• I (interrupt mask bit)
This bit masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit
setting. The I bit is set to 1 at the start of an exception-handling sequence. For details, see
section 4, Interrupt Controller.
• UI (user bit/interrupt mask bit)
This bit can be written to and read from by software using the LDC, STC, ANDC, ORC, and
XORC instructions.
For this LSI, interrupt mask bit is not available.
• H (half carry flag)
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B or NEG.B instruction is executed, this
flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the
ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is
a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or
NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and
cleared to 0 otherwise.
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Section 2 CPU
• U (user bit)
This bit can be written to and read from by software using the LDC, STC, ANDC, ORC, and
XORC instructions.
• N (negative bit)
This bit stores the value of the most significant bit of data as a sign bit.
• C (carry flag)
This flag is set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
 Add instructions, to indicate a carry
 Subtract instructions, to indicate a borrow
 Shift and rotate instructions, to indicate a carry
The carry flag is also used as a bit accumulator by bit manipulation instructions.
2.4.5
Initial Register Values
Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the
trace (T) bit in EXR to 0, and sets the interrupt mask (I) bits in CCR and EXR to 1. The other
CCR bits and the general registers are not initialized. Note that the stack pointer (ER7) is
undefined. The stack pointer should therefore be initialized by an MOV.L instruction executed
immediately after a reset.
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Section 2 CPU
2.5
Data Formats
The H8S/2000 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.
2.5.1
General Register Data Formats
Figure 2.7 shows the data formats of general registers.
Data Type
Register Number
Data Format
7
RnH
1-bit data
0
Don't care
7 6 5 4 3 2 1 0
0
7
1-bit data
RnL
4-bit BCD data
RnH
4-bit BCD data
RnL
Byte data
RnH
Don't care
7
7 6 5 4 3 2 1 0
4 3
Upper
0
Lower
Don't care
7
Don't care
7
4 3
Upper
0
Don't care
MSB
LSB
7
Byte data
RnL
0
Lower
0
Don't care
MSB
LSB
Figure 2.7 General Register Data Formats (1)
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Section 2 CPU
Data Type
Register Number
Word data
Rn
Data Format
15
0
MSB
Word data
15
0
MSB
Longword data
LSB
En
LSB
ERn
31
16 15
MSB
En
0
Rn
Legend:
ERn
En
Rn
RnH
RnL
MSB
LSB
: General register ER
: General register E
: General register R
: General register RH
: General register RL
: Most significant bit
: Least significant bit
Figure 2.7 General Register Data Formats (2)
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REJ09B0465-0100
LSB
Section 2 CPU
2.5.2
Memory Data Formats
Figure 2.8 shows the data formats in memory. The H8S/2000 CPU can access word data and
longword data in memory, but word or longword data must begin at an even address. If an attempt
is made to access word or longword data at an odd address, no address error occurs but the least
significant bit of the address is regarded as 0, so the access starts at the preceding address. This
also applies to instruction fetches.
When SP (ER7) is used as an address register to access the stack, the operand size should be word
size or longword size.
Data Type
Address
Data Format
7
1-bit data
Address L
7
Byte data
Address L
MSB
Address 2M
MSB
Word data
0
6
5
4
3
2
Address 2N
0
LSB
LSB
Address 2M+1
Longword data
1
MSB
Address 2N+1
Address 2N+2
LSB
Address 2N+3
Figure 2.8 Memory Data Formats
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REJ09B0465-0100
Section 2 CPU
2.6
Instruction Set
The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as
shown in table 2.1.
Table 2.1
Instruction Classification
Function
Instructions
Size
Types
Data transfer
MOV
POP*1, PUSH*1
B/W/L
5
Arithmetic
operations
W/L
LDM* , STM*
MOVFPE*3, MOVTPE*3
B
ADD, SUB, CMP, NEG
B/W/L
ADDX, SUBX, DAA, DAS
B
5
5
L
19
INC, DEC
B/W/L
ADDS, SUBS
L
MULXU, DIVXU, MULXS, DIVXS
B/W
EXTU, EXTS
TAS*4
W/L
Logic operations
AND, OR, XOR, NOT
B/W/L
4
Shift
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,
ROTXR
B/W/L
8
Bit manipulation
BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST,
BAND, BIAND, BOR, BIOR, BXOR, BIXOR
BCC*2, JMP, BSR, JSR, RTS
B
14

5
System control
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, 
NOP
9
Block data transfer
EEPMOV

1
Branch
B
Total: 65
Notes: B: Byte size; W: Word size; L: Longword size.
1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,
@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L
ERn, @-SP.
2. BCC is the general name for conditional branch instructions.
3. Cannot be used in this LSI.
4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
5. The ER7 register is used as a stack pointer in an STM and LDM instructions.
Accordingly, ER7 cannot be stored by STM or loaded by LDM.
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Section 2 CPU
2.6.1
Table of Instructions Classified by Function
Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in
tables 2.3 to 2.10 is defined below.
Table 2.2
Operation Notation
Symbol
Description
Rd
Rs
General register (destination)*
General register (source)*
Rn
General register*
ERn
General register (32-bit register)
(EAd)
Destination operand
(EAs)
Source operand
EXR
Extended control register
CCR
Condition-code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
PC
Program counter
SP
Stack pointer
#IMM
Immediate data
disp
Displacement
+
Addition
–
Subtraction
×
Multiplication
÷
Division
∧
Logical AND
∨
Logical OR
⊕
Logical exclusive OR
→
Move
∼
NOT (logical complement)
:8/:16/:24/:32
Note:
*
8-, 16-, 24-, or 32-bit length
General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
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Section 2 CPU
Table 2.3
Data Transfer Instructions
Instruction
1
Size*
Function
MOV
B/W/L
(EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general
register and memory, or moves immediate data to a general register.
MOVFPE
B
Cannot be used in this LSI.
MOVTPE
B
Cannot be used in this LSI.
POP
W/L
@SP+ → Rn
Pops a general register from the stack. POP.W Rn is identical to
MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn
PUSH
W/L
Rn → @-SP
Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP.
2
LDM*
L
@SP+ → Rn (register list)
Pops two or more general registers from the stack.
STM*
2
L
Rn (register list) → @-SP
Pushes two or more general registers onto the stack.
Notes: 1. Size refers to the operand size.
B:
Byte
W:
Word
L:
Longword
2. The ER7 register is used as a stack pointer in the STM and LDM instructions.
Accordingly, ER7 cannot be stored by STM or loaded by LDM.
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REJ09B0465-0100
Section 2 CPU
Table 2.4
Arithmetic Operations Instructions (1)
Instruction
Size*
Function
ADD
B/W/L
Rd ± Rs → Rd, Rd ± #IMM → Rd
SUB
Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register. (Subtraction on
immediate data and data in a general register cannot be performed in
bytes. Use the SUBX or ADD instruction.)
ADDX
B
SUBX
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry on data in two general
registers, or on immediate data and data in a general register.
INC
B/W/L
DEC
Rd ± 1 → Rd, Rd ± 2 → Rd
Adds or subtracts the value 1 or 2 to or from data in a general register.
(Only the value 1 can be added to or subtracted from byte operands.)
ADDS
L
SUBS
Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit
register.
DAA
B
DAS
Rd (decimal adjust) → Rd
Decimal-adjusts an addition or subtraction result in a general register
by referring to CCR to produce 4-bit BCD data.
MULXU
B/W
Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers:
either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
MULXS
B/W
Rd × Rs → Rd
Performs signed multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
DIVXU
B/W
Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either 16
bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits →
16-bit quotient and 16-bit remainder.
Note:
*
Size refers to the operand size.
B:
Byte
W:
Word
L:
Longword
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REJ09B0465-0100
Section 2 CPU
Table 2.4
Arithmetic Operations Instructions (2)
Instruction
1
Size*
Function
DIVXS
B/W
Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits
÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16bit quotient and 16-bit remainder.
CMP
B/W/L
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general
register or with immediate data, and sets the CCR bits according to the
result.
NEG
B/W/L
0 – Rd → Rd
Takes the two's complement (arithmetic complement) of data in a
general register.
EXTU
W/L
Rd (zero extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower
16 bits of a 32-bit register to longword size, by padding with zeros on
the left.
EXTS
W/L
Rd (sign extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower
16 bits of a 32-bit register to longword size, by extending the sign bit.
2
TAS*
B
@ERd – 0, 1 → (<bit 7> of @ERd)
Tests memory contents, and sets the most significant bit (bit 7) to 1.
Notes: 1. Size refers to the operand size.
B:
Byte
W:
Word
L:
Longword
2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
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REJ09B0465-0100
Section 2 CPU
Table 2.5
Logic Operations Instructions
Instruction
Size*
Function
AND
B/W/L
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR
B/W/L
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR
B/W/L
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT
B/W/L
∼ Rd → Rd
Takes the one's complement (logical complement) of data in a general
register.
Note:
*
Size refers to the operand size.
B:
Byte
W:
Word
L:
Longword
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REJ09B0465-0100
Section 2 CPU
Table 2.6
Shift Instructions
Instruction
Size*
Function
SHAL
B/W/L
Rd (shift) → Rd
SHAR
Performs an arithmetic shift on data in a general register. 1-bit or 2 bit
shift is possible.
SHLL
B/W/L
SHLR
Performs a logical shift on data in a general register. 1-bit or 2 bit shift
is possible.
ROTL
B/W/L
ROTR
Rd (rotate) → Rd
Rotates data in a general register. 1-bit or 2 bit rotation is possible.
ROTXL
B/W/L
ROTXR
Note:
Rd (shift) → Rd
*
Rd (rotate) → Rd
Rotates data including the carry flag in a general register. 1-bit or 2 bit
rotation is possible.
Size refers to the operand size.
B:
Byte
W:
Word
L:
Longword
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Section 2 CPU
Table 2.7
Bit Manipulation Instructions (1)
Instruction
Size*
Function
BSET
B
1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory operand to 1. The
bit number is specified by 3-bit immediate data or the lower three bits
of a general register.
BCLR
B
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0.
The bit number is specified by 3-bit immediate data or the lower three
bits of a general register.
BNOT
B
∼ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BTST
B
∼ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand and sets
or clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower three bits of a general register.
BAND
B
C ∧ (<bit-No.> of <EAd>) → C
Logically ANDs the carry flag with a specified bit in a general register
or memory operand and stores the result in the carry flag.
BIAND
B
C ∧ (<bit-No.> of <EAd>) → C
Logically ANDs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the result in the carry
flag.
The bit number is specified by 3-bit immediate data.
BOR
B
C ∨ (<bit-No.> of <EAd>) → C
Logically ORs the carry flag with a specified bit in a general register or
memory operand and stores the result in the carry flag.
BIOR
B
C ∨ (∼ <bit-No.> of <EAd>) → C
Logically ORs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the result in the carry
flag.
The bit number is specified by 3-bit immediate data.
Note:
*
Size refers to the operand size.
B:
Byte
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Section 2 CPU
Table 2.7
Bit Manipulation Instructions (2)
Instruction
Size*
Function
BXOR
B
C ⊕ (<bit-No.> of <EAd>) → C
Logically exclusive-ORs the carry flag with a specified bit in a general
register or memory operand and stores the result in the carry flag.
BIXOR
B
C ⊕ ∼ (<bit-No.> of <EAd>) → C
Logically exclusive-ORs the carry flag with the inverse of a specified bit
in a general register or memory operand and stores the result in the
carry flag.
The bit number is specified by 3-bit immediate data.
BLD
B
(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to
the carry flag.
BILD
B
∼ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST
B
C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or
memory operand.
BIST
B
∼ C → (<bit-No.>. of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a
general register or memory operand.
The bit number is specified by 3-bit immediate data.
Note:
*
Size refers to the operand size.
B:
Byte
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Section 2 CPU
Table 2.8
Branch Instructions
Instruction
Size
Function
Bcc

Branches to a specified address if a specified condition is true. The
branching conditions are listed below.
Mnemonic
Description
Condition
BRA (BT)
Always (true)
Always
BRN (BF)
Never (false)
Never
BHI
High
C∨Z=0
BLS
Low or same
C∨Z=1
BCC (BHS)
Carry clear
(high or same)
C=0
BCS (BLO)
Carry set (low)
C=1
BNE
Not equal
Z=0
BEQ
Equal
Z=1
BVC
Overflow clear
V=0
BVS
Overflow set
V=1
BPL
Plus
N=0
BMI
Minus
N=1
BGE
Greater or equal
N⊕V=0
BLT
Less than
N⊕V=1
BGT
Greater than
Z ∨ (N ⊕ V) = 0
BLE
Less or equal
Z ∨ (N ⊕ V) = 1
JMP

Branches unconditionally to a specified address
BSR

Branches to a subroutine at a specified address
JSR

Branches to a subroutine at a specified address
RTS

Returns from a subroutine
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Section 2 CPU
Table 2.9
System Control Instructions
Instruction
Size*
Function
TRAPA

Starts trap-instruction exception handling.
RTE

Returns from an exception-handling routine.
SLEEP

Causes a transition to a power-down state.
LDC
B/W
(EAs) → CCR, (EAs) → EXR
Moves the memory operand contents or immediate data to CCR or
EXR. Although CCR and EXR are 8-bit registers, word-size transfers
are performed between them and memory. The upper 8 bits are valid.
STC
B/W
CCR → (EAd), EXR → (EAd)
Transfers CCR or EXR contents to a general register or memory
operand. Although CCR and EXR are 8-bit registers, word-size
transfers are performed between them and memory. The upper 8 bits
are valid.
ANDC
B
CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR
Logically ANDs the CCR or EXR contents with immediate data.
ORC
B
CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR
XORC
B
CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR
Logically ORs the CCR or EXR contents with immediate data.
Logically exclusive-ORs the CCR or EXR contents with immediate
data.

NOP
PC + 2 → PC
Only increments the program counter.
Note:
*
Size refers to the operand size.
B:
Byte
W:
Word
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Section 2 CPU
Table 2.10 Block Data Transfer Instructions
Instruction
Size
Function
EEPMOV.B

if R4L ≠ 0 then
Repeat @ER5+ → @ER6+
R4L–1 → R4L
Until R4L = 0
else next:
EEPMOV.W

if R4 ≠ 0 then
Repeat @ER5+ → @ER6+
R4–1 → R4
Until R4 = 0
else next:
Transfers a data block. Starting from the address set in ER5, transfers
data for the number of bytes set in R4L or R4 to the address location
set in ER6.
Execution of the next instruction begins as soon as the transfer is
completed.
2.6.2
Basic Instruction Formats
The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op), a register field (r), an effective address extension (EA), and a condition field
(cc).
Figure 2.9 shows examples of instruction formats.
• Operation field
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.
• Register field
Specifies a general register. Address registers are specified by 3 bits, and data registers by 3
bits or 4 bits. Some instructions have two register fields, and some have no register field.
• Effective address extension
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.
• Condition field
Specifies the branching condition of Bcc instructions.
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Section 2 CPU
(1) Operation field only
op
NOP, RTS, etc.
(2) Operation field and register fields
op
rm
rn
ADD.B Rn, Rm, etc.
(3) Operation field, register fields, and effective address extension
op
rn
rm
MOV.B @(d:16, Rn), Rm, etc.
EA (disp)
(4) Operation field, effective address extension, and condition field
op
cc
EA (disp)
BRA d:16, etc.
Figure 2.9 Instruction Formats (Examples)
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Section 2 CPU
2.7
Addressing Modes and Effective Address Calculation
The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses
a subset of these addressing modes.
Arithmetic and logic operations instructions can use the register direct and immediate addressing
modes. Data transfer instructions can use all addressing modes except program-counter relative
and memory indirect. Bit manipulation instructions can use register direct, register indirect, or
absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and
BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.
Table 2.11 Addressing Modes
No.
Addressing Mode
Symbol
1
Register direct
Rn
2
Register indirect
@ERn
3
Register indirect with displacement
@(d:16,ERn)/@(d:32,ERn)
4
Register indirect with post-increment
@ERn+
Register indirect with pre-decrement
@–ERn
5
Absolute address
@aa:8/@aa:16/@aa:24/@aa:32
6
Immediate
#xx:8/#xx:16/#xx:32
7
Program-counter relative
@(d:8,PC)/@(d:16,PC)
8
Memory indirect
@@aa:8
2.7.1
Register Direct—Rn
The register field of the instruction code specifies an 8-, 16-, or 32-bit general register which
contains the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7
and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
2.7.2
Register Indirect—@ERn
The register field of the instruction code specifies an address register (ERn) which contains the
address of a memory operand. If the address is a program instruction address, the lower 24 bits are
valid and the upper 8 bits are all assumed to be 0 (H'00).
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2.7.3
Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)
A 16-bit or 32-bit displacement contained in the instruction code is added to an address register
(ERn) specified by the register field of the instruction, and the sum gives the address of a memory
operand. A 16-bit displacement is sign-extended when added.
2.7.4
(1)
Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn
Register Indirect with Post-Increment—@ERn+
The register field of the instruction code specifies an address register (ERn) which contains the
address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address
register contents and the sum is stored in the address register. The value added is 1 for byte access,
2 for word access, and 4 for longword access. For word or longword transfer instructions, the
register value should be even.
(2)
Register Indirect with Pre-Decrement—@–ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in
the instruction code, and the result becomes the address of a memory operand. The result is also
stored in the address register. The value subtracted is 1 for byte access, 2 for word access, and 4
for longword access. For word or longword transfer instructions, the register value should be even.
2.7.5
Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32
The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long
(@aa:32). Table 2.12 indicates the accessible absolute address ranges.
To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF).
For a 16-bit absolute address, the upper 16 bits are a sign extension. For a 32-bit absolute address,
the entire address space is accessed.
A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8
bits are all assumed to be 0 (H'00).
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Section 2 CPU
Table 2.12 Absolute Address Access Ranges
Absolute Address
Data address
Program instruction address
2.7.6
Advanced Mode
8 bits (@aa:8)
H'FFFF00 to H'FFFFFF
16 bits (@aa:16)
H'000000 to H'007FFF, H'FF8000 to H'FFFFFF
32 bits (@aa:32)
H'000000 to H'FFFFFF
24 bits (@aa:24)
Immediate—#xx:8, #xx:16, or #xx:32
The 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data contained in an instruction
code can be used directly as an operand.
The ADDS, SUBS, INC, and DEC instructions implicitly contain immediate data in their
instruction codes. Some bit manipulation instructions contain 3-bit immediate data in the
instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data
in its instruction code, specifying a vector address.
2.7.7
Program-Counter Relative—@(d:8, PC) or @(d:16, PC)
This mode can be used by the Bcc and BSR instructions. An 8-bit or 16-bit displacement
contained in the instruction code is sign-extended to 24 bits and added to the 24-bit address
indicated by the PC value to generate a 24-bit branch address. Only the lower 24 bits of this
branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which
the displacement is added is the address of the first byte of the next instruction, so the possible
branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to
+16384 words) from the branch instruction. The resulting value should be an even number.
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Section 2 CPU
2.7.8
Memory Indirect—@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand which contains a branch address. The upper bits of
the 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (H'000000 to
H'0000FF in advanced mode).
In advanced mode, the memory operand is a longword operand, the first byte of which is assumed
to be 0 (H'00).
Note that the top area of the address range in which the branch address is stored is also used for
the exception vector area. For further details, see section 3, Exception Handling.
If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or the instruction code to be
fetched at the address preceding the specified address. (For further information, see section 2.5.2,
Memory Data Formats.)
Specified
by @aa:8
Reserved
Branch address
Advanced Mode
Figure 2.10 Branch Address Specification in Memory Indirect Addressing Mode
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Section 2 CPU
2.7.9
Effective Address Calculation
Table 2.13 indicates how effective addresses are calculated in each addressing mode.
Table 2.13 Effective Address Calculation
No
1
Addressing Mode and Instruction Format
op
2
Effective Address Calculation
Effective Address (EA)
Register direct (Rn)
rm
Operand is general register contents.
rn
Register indirect (@ERn)
0
31
op
3
31
24 23
0
Don't care
General register contents
r
Register indirect with displacement
@(d:16,ERn) or @(d:32,ERn)
0
31
General register contents
op
r
31
disp
Sign extension
Register indirect with post-increment or
pre-decrement
• Register indirect with post-increment @ERn+
op
disp
31
0
31
24 23
0
Don't care
General register contents
r
• Register indirect with pre-decrement @-ERn
0
0
31
4
24 23
Don't care
1, 2, or 4
31
0
General register contents
31
24 23
0
Don't care
op
r
1, 2, or 4
Operand Size
Byte
Word
Longword
Offset
1
2
4
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Section 2 CPU
No
5
Addressing Mode and Instruction Format
Effective Address Calculation
Effective Address (EA)
Absolute address
@aa:8
31
op
@aa:16
31
op
0
H'FFFF
24 23
16 15
0
Don't care Sign extension
abs
@aa:24
31
op
8 7
24 23
Don't care
abs
24 23
0
Don't care
abs
@aa:32
op
31
6
Immediate
#xx:8/#xx:16/#xx:32
op
7
0
24 23
Don't care
abs
Operand is immediate data.
IMM
0
23
Program-counter relative
PC contents
@(d:8,PC)/@(d:16,PC)
op
disp
23
0
Sign
extension
disp
31
24 23
0
Don't care
8
Memory indirect @@aa:8
• Normal mode*
8 7
31
op
abs
0
abs
H'000000
15
0
31
24 23
Don't care
Memory contents
16 15
0
H'00
• Advanced mode
31
op
abs
8 7
H'000000
31
0
Memory contents
Note: * For this LSI, normal mode is not available.
Rev. 1.00 Oct. 03, 2008 Page 58 of 962
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0
abs
31
24 23
Don't care
0
Section 2 CPU
2.8
Processing States
The H8S/2000 CPU has five main processing states: the reset state, exception handling state,
program execution state, bus-released state, and program stop state. Figure 2.11 indicates the state
transitions.
• Reset state
In this state the CPU and internal peripheral modules are all initialized and stopped. When the
RES input goes low, all current processing stops and the CPU enters the reset state. All
interrupts are masked in the reset state. Reset exception handling starts when the RES signal
changes from low to high. For details, see section 3, Exception Handling.
The reset state can also be entered by a watchdog timer overflow.
• Exception-handling state
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction.
The CPU fetches a start address (vector) from the exception vector table and branches to that
address. For further details, see section 3, Exception Handling.
• Program execution state
In this state the CPU executes program instructions in sequence.
• Bus-released state
The bus-released state occurs when the bus has been released in response to a bus request from
a bus master other than the CPU. While the bus is released, the CPU halts operations.
• Program stop state
This is a power-down state in which the CPU stops operating. The program stop state occurs
when a SLEEP instruction is executed. For details, see section 6, Power-Down Modes.
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Section 2 CPU
st
ue
qu
e
t re
se
st
tr
eq
et
Re
s
se
Re
t
Bus-released state
Re
ex que
ce st
pti fo
on r
ha
nd
lin
SLEEP instruction
Program execution state
Note: * A transition to the reset state occurs in any of the following cases.
1. When RES goes low in any state
2. When the watchdog timer overflows
3. When an LVD reset is caused by a low-voltage detection
Figure 2.11 State Transitions
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REJ09B0465-0100
Bus request
t
ues
d
En
bu
q
re
t req
s
of
st
ue
Bu
End of bus request
t
es
u
eq
sr
e
Res
Request for exception handling
Re
Exception
handling state
End of exception handling
es
qu
t re
se
Re
re
le
a
se
Reset state*
g
Program stop state
Section 2 CPU
2.9
Usage Notes
2.9.1
TAS Instruction
Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The H8S
and H8/300 Series C/C++ Compiler of Renesas Technology Corp. does not generate a TAS
instruction. Accordingly, when a TAS instruction is used as a user-defined embedded function,
register ER0, ER1, ER4, or ER5 should be used.
2.9.2
STM and LDM Instructions
The ER7 register is used as a stack pointer in an STM and LDM instructions. Accordingly, ER7
cannot be stored by STM or loaded by LDM. Two, three, or four registers can be stored or loaded
by a single STM or LDM instruction. The combination of registers that can be stored or loaded are
as follows.
• Two registers: ER0 and ER1, ER2 and ER3, or ER4 and ER5
• Three registers: ER0 to ER2 or ER4 to ER6
• Four registers: ER0 to ER3
The H8S and H8/300 Series C/C++ Compiler of Renesas Technology Corp. does not generate an
STM or LDM instruction that uses ER7.
2.9.3
Note on Bit Manipulation Instructions
Bit manipulation instructions such as BSET, BCLR, BNOT, BST, and BIST read data in byte
units, perform bit manipulation, and write data in byte units. Thus, care must be taken when these
bit manipulation instructions are executed for a register or port including write-only bits.
In addition, the BCLR instruction can be used to clear the flag of an internal I/O register. In this
case, if the flag to be cleared has been set by an interrupt processing routine, the flag need not be
read before executing the BCLR instruction.
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Section 2 CPU
2.9.4
EEPMOVE Instruction
1. The EEPMOVE instruction performs a block transfer. As shown in the following figure,
EEPMOV transfers data whose start address is indicated by R5 for the number of bytes
indicated by R4L to the address indicated by R6.
R5
R6
R5 + R4L
R6 + R4L
2. R4L and R6 should be set so that the end address (R6 + R4L) of the transfer destination does
not exceed H'FFFF (R6 should not change from H'FFFF to H'0000 during EEPMOV
instruction execution).
R5
R6
R5 + R4L
Cannot
be set
Rev. 1.00 Oct. 03, 2008 Page 62 of 962
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H'FFFF
R6 + R4L
Section 3 Exception Handling
Section 3 Exception Handling
3.1
Exception Handling Types and Priority
As table 3.1 indicates, exception handling is caused by a reset, trace, NMI interrupt, trap
instruction, or interrupt. Exception handling is prioritized as shown in table 3.1. If two or more
exceptions occur simultaneously, they are accepted and processed in order of priority. Exception
sources, the stack structure, and operation of the CPU vary depending on the interrupt control
mode. For details on the interrupt control mode, see section 4, Interrupt Controller.
Table 3.1
Exception Handling Types and Priority
Priority
Exception Type
Start Timing of Exception Handling
High
Reset
Started immediately after a low-to-high transition at the RES pin,
or by other reset sources. The CPU enters the reset state when
the RES pin is low.
Trace*1
Started when execution of the current instruction or exception
handling ends, if the trace (T) bit in EXR is set to 1.
NMI
Generated when an edge of the NMI pin is input. An NMI
interrupt request has the highest priority among interrupt
requests. It is always accepted regardless of the value of the I bit
in CCR.
Trap instruction*3
Started by execution of a trap instruction (TRAPA).
Interrupt
Started when execution of the current instruction or exception
handling ends, if an interrupt request has been issued.*2
Low
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
executed after execution of an RTE instruction.
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
instruction execution, or on completion of reset exception handling.
3. Trap instruction exception handling requests are accepted at all times in program
execution state.
3.2
Exception Handling Sources and Vector Table
Different vector addresses are assigned to different exception sources. For details on the exception
sources and their vector addresses, see section 4, Interrupt Controller.
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Section 3 Exception Handling
3.3
Reset
A reset has the highest exception handling priority. When the RES pin goes low, all processing
halts and this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for the
specified time at power-on and during operation, hold the RES pin low for the specified time. A
reset initializes the internal state of the CPU and the registers of on-chip peripheral modules, and
selects low-speed on-chip oscillator as a system clock. The chip can also be reset by detection of
the low-voltage, overflow of the watchdog timer, or software.
The interrupt control mode is 0 immediately after reset.
3.3.1
Reset Sources
This LSI enters the reset state by reset sources listed in table 3.2. If multiple reset sources occur
simultaneously, a reset source having the highest priority will be accepted. A reset source can be
identified by reading the reset source flag register (RSTFR).
For details on a low-voltage detection reset, see section 26, Low-Voltage Detection Circuits. For
details on a watchdog timer overflow reset, see section 19, Watchdog Timer (WDT).
Table 3.2
List of Reset Sources
Reset Source
Description
Reset by RES pin
This LSI enters the reset state if the RES pin is held low for High
at least a specified period.
Low-voltage detection
reset
This LSI enters the reset state if the power voltage
becomes the specified voltage or lower.
Watchdog timer overflow
reset
This LSI enters the reset state if the counter in the
watchdog timer overflows.
Software reset
This LSI enters the reset state if the SRST bit in RSTCR is
set to 1.
Low
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Priority
Section 3 Exception Handling
(1)
Reset Source Flag Register (RSTFR)
Address: H'FF0620
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0


SWRST
PRST
LVD2RST
LVD1RST
PORRST
WRST
0
0
(0)
(0)
(0)
(0)
(0)
(0)
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is read as 0. The write value should be 0.

6

5
SWRST
Software reset
detection flag
1: Indicates that a reset by a software reset occurs. R/W
RES pin reset
detection flag
1: Indicates that a reset by a RES pin reset occurs. R/W
LVD2 reset
detection flag
1: Indicates that a reset by a LVD2 reset occurs.
LVD1 reset
detection flag
1: Indicates that a reset by a LVD1 reset occurs.
LVD0 reset
detection flag
1: Indicates that a reset by a LVD0 reset occurs.
4
3
2
1
0
PRST
LVD2RST
LVD1RST
PORRST
WRST
0: Indicates that a reset by a software reset does
not occur.
0: Indicates that a reset by a RES pin reset does
not occur.
R/W
0: Indicates that a reset by a LVD2 reset does not
occur.
R/W
0: Indicates that a reset by a LVD1 reset does not
occur.
R/W
0: Indicates that a reset by a LVD0 reset does not
occur.
Watchdog timer 1: Indicates that a reset by a watchdog timer
reset detection
overflows.
flag
0: Indicates that a reset by a watchdog timer does
not occur.
R/W
Note: Each flag in this register can be cleared by writing 0 to it. The write value to the reserved
bits should always be 0.
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Section 3 Exception Handling
(2)
Reset Control Register (RSTCR)
Address:
H'FF06DA
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
WI
WE





SRST
1
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
WI
Write inhibit
0: Writing is permitted.
W
1: Writing is inhibited.
6
WE
Write enable
0: Writing is disabled.
R/W
1: Writing is enabled.
[Setting condition]
When 0 is written to WI and 1 is written to WE.
[Clearing condition]
When 0 is written to WI and WE.
5 to 1

Reserved
These bits are read as 0. The write value should
be 0.

0
SRST
Software reset
0: Normal operation
R/W
1: A software reset is generated.
Note:
A MOV instruction should be used to write to this register.
• WI bit (write inhibit)
This register can be written to only when this bit is 0. This bit is always read as 1.
• WE bit (write enable)
Bit 0 in this register can be written to when this bit is 1.
• SRST bit (software reset)
A software reset is generated when this bit is 1.
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Section 3 Exception Handling
3.3.2
Reset Exception Handling
When the RES pin goes high after being held low for the necessary time, this LSI starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip peripheral modules are
initialized, VOFR is cleared to H'0000, the T bit in EXR is cleared to 0, and the I bit in EXR
and CCR is set to 1.
2. The low-speed on-chip oscillator is selected as a system clock.
3. After the reset exception handling vector address is read and transferred to the PC, program
execution starts from the address indicated by the PC.
Figure 3.1 shows an example of the reset sequence.
Internal
Prefetch of first
processing program instruction
Vector fetch
φ
RES
(1)
Internal
address bus
(3)
(5)
Internal
read signal
High
Internal
write signal
Internal
data bus
(2)
(1) (3)
(2) (4)
(5)
(6)
(4)
(6)
:Reset exeption handling vector address (when reset, (1) = H'000000, (3) = H'000002)
:Start address (contents of reset exception handling vector address)
:Start address ((5) = (2)(4))
:First program instruction
Figure 3.1 Reset Sequence
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Section 3 Exception Handling
3.3.3
Interrupts immediately after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32, SP).
3.3.4
On-Chip Peripheral Functions after Reset Release
After release from a reset, MSTCR is initialized, and the DTC and all modules other than timer
RE enter module standby mode.
Consequently, on-chip peripheral module registers cannot be read or written to. Register reading
and writing is enabled when module standby mode is exited.
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Section 3 Exception Handling
3.4
Trace Exception Handling
Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control
mode 0, irrespective of the state of the T bit. For details on interrupt control modes, see section 4,
Interrupt Controller.
If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on
completion of each instruction. Trace mode is not affected by the interrupt masking bit in CCR.
Table 3.3 shows the state of CCR and EXR after execution of trace exception handling. Trace
mode is canceled by clearing the T bit in EXR to 0. The T bit saved on the stack retains its value
of 1, and trace mode resumes when control is returned from the trace exception handling routine
by the RTE instruction. Trace exception handling is not carried out after execution of the RTE
instruction.
Interrupts are accepted even within the trace exception handling routine.
Table 3.3
Status of CCR and EXR after Trace Exception Handling
CCR
Interrupt Control Mode
I
0
2
UI
EXR
I2 to I0
T
Trace exception handling cannot be used.
1


0
[Legend]
1:
Set to 1
0:
Cleared to 0
:
Retains value prior to execution.
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Section 3 Exception Handling
3.5
Interrupt Exception Handling
Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt
control modes and can assign interrupts other than NMI to four priority/mask levels to enable
multiplexed interrupt control. The source to start interrupt exception handling and the vector
address differ depending on the product. For details, see section 4, Interrupt Controller.
The interrupt exception handling is as follows:
1. The values in the program counter (PC), condition code register (CCR), and extended register
(EXR) are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. A vector address corresponding to the interrupt source is generated, the start address is loaded
from the vector table to the PC, and program execution starts from that address.
3.6
Trap Instruction Exception Handling
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
The trap instruction exception handling is as follows:
1. The values in the program counter (PC), condition code register (CCR), and extended register
(EXR) are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. A vector address corresponding to the interrupt source is generated, the start address is loaded
from the vector table to the PC, and program execution starts from that address.
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 3.4 shows the status of CCR and EXR after execution of trap instruction exception handling.
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Section 3 Exception Handling
Table 3.4
Status of CCR and EXR after Trap Instruction Exception Handling
CCR
EXR
Interrupt Control Mode
I
UI
I2 to I0
T
0
1



2
1


0
[Legend]
1:
Set to 1
0:
Cleared to 0
:
Retains value prior to execution.
3.7
Stack Status after Exception Handling
Figure 3.2 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
Advanced Modes
SP
EXR
Reserved*
SP
CCR
PC (24 bits)
Interrupt control mode 0
CCR
PC (24 bits)
Interrupt control mode 2
Note: * Ignored on return.
Figure 3.2 Stack Status after Exception Handling
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Section 3 Exception Handling
3.8
Usage Note
When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The
stack should always be accessed by word transfer instruction or longword transfer instruction, and
the value of the stack pointer (SP, ER7) should always be kept even.
Use the following instructions to save registers:
PUSH.W
Rn
(or MOV.W Rn, @-SP)
PUSH.L
ERn
(or MOV.L ERn, @-SP)
Use the following instructions to restore registers:
POP.W
Rn
(or MOV.W @SP+, Rn)
POP.L
ERn
(or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 3.3 shows an example of operation
when the SP value is odd.
Address
CCR
SP→
R1L
SP→
H'FFFEFA
H'FFFEFB
PC
PC
H'FFFEFC
H'FFFEFD
H'FFFEFE
SP→
H'FFFEFF
MOV.B R1L,@-ER7
Instruction executed
Data saved above SP
Contents of CCR lost
TRAPA instruction executed
SP set to H'FFFEFF
[Legend]
CCR : Condition code register
PC : Program counter
R1L : General register R1L
SP : Stack pointer
Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode.
Figure 3.3 Operation when SP Value Is Odd
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Section 4 Interrupt Controller
Section 4 Interrupt Controller
4.1
Features
• Two interrupt control modes
Either of the two interrupt control modes can be selected by means of the INTM1 and INTM0
bits in the interrupt control register (INTCR).
• Priorities settable with IPR
An interrupt priority register (IPR) is provided for setting interrupt priorities. Four priority
levels can be set for each module for all interrupts except NMI. NMI and some flash memory
interrupts are assigned the highest priority level of 3, and can be accepted at all times.
• Independent vector addresses
Most interrupt sources are assigned independent vector addresses, making it unnecessary for
the source to be identified in the interrupt handling routine.
• Nine external interrupts
NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge
can be selected for NMI. Falling edge, rising edge, or both edges can be selected independently
for IRQ7 to IRQ0.
• DTC control
DTC activation is performed by means of interrupt requests.
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Section 4 Interrupt Controller
A block diagram of the interrupt controller is shown in figure 4.1.
CPU
INTM1 INTM0
INTCR
NMIEG
NMI input
NMI input unit
IRQ input
IRQ input unit
ISR
Interrupt
request
Vector
number
ISCR IER
Priority
determination
Internal
interrupt
sources
IAD to
ITGUD
I
I1 to I0
CCR
EXR
IPR
Interrupt controller
Figure 4.1 Block Diagram of Interrupt Controller
Table 4.1 shows the pin configuration of the interrupt controller.
Table 4.1
Pin Configuration
Name
I/O
Function
NMI
Input
Nonmaskable external interrupt
Rising or falling edge can be selected.
IRQ7 to IRQ0
Input
Maskable external interrupts
Rising, falling, or both edges can be selected independently.
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Section 4 Interrupt Controller
4.2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Register Descriptions
Interrupt control register (INTCR)
IRQ sense control register H (ISCRH)
IRQ sense control register L (ISCRL)
IRQ enable register (IER)
IRQ status register (ISR)
Interrupt priority register A (IPRA)
Interrupt priority register B (IPRB)
Interrupt priority register C (IPRC)
Interrupt priority register D (IPRD)
Interrupt priority register E (IPRE)
Interrupt priority register F (IPRF)
Interrupt priority register G (IPRG)
Interrupt priority register H (IPRH)
Interrupt priority register I (IPRI)
Interrupt vector offset register (VOFR)
IRQ noise canceler control register (INCCR)
Event link interrupt control status register (ELCSR)
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Section 4 Interrupt Controller
4.2.1
Interrupt Control Register (INTCR)
Address: H'FF0520
Bit:
b7
b6


0
0
Value after reset:
b5
b4
INTM[1:0]
0
b3
b2
b1
b0
NMIEG
ADTRG1
ADTRG0

0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
These bits are read as 0. The write value should
be 0.

INTM[1:0]
Interrupt control
select mode 1
and 0
00: Interrupt control mode 0
Interrupts are controlled by the I bit.
R/W
6
5
4
01: Setting prohibited
10: Interrupt control mode 2
Interrupts are controlled by bits I1 and I0, and
IPR.
11: Setting prohibited
3
NMIEG
NMI edge select 0: Interrupt request is generated at falling edge of
NMI input.
R/W
1: Interrupt request is generated at rising edge of
NMI input.
2
ADTRG1
ADTRG2 edge
select
0: AD1 or AD2 conversion is started at falling edge R/W
of ADTRG2 input.
1: AD1 or AD2 conversion is started at rising edge
of ADTRG2 input.
1
ADTRG0
ADTRG1 edge
select
0: AD1 or AD2 conversion is started at falling edge R/W
of ADTRG1 input.
1: AD1 or AD2 conversion is started at rising edge
of ADTRG1 input.
0

Reserved
This bit is read as 0. The write value should be 0.
• INTM1 and INTM0 bits (interrupt control select mode 1 and 0)
These bits select the interrupt control mode for the interrupt controller.
• NMIEG bit (NMI edge select)
Selects the input edge for the NMI pin.
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
Section 4 Interrupt Controller
• ADTRG1 and ADTRG0 bits (ADTRG2 and ADTRG1 edge select)
These bits select the input edge for the ADTRG2 and ADTRG1 pins.
4.2.2
Interrupt Priority Registers A to I (IPRA to IPRI)
• IPRA to IPRK
Address: H'FF0529 to H'FF0531
Bit:
b7
b6
b5
IPRn[7:6]
Value after reset:
1
b4
b3
IPRn[5:4]
1
1
b2
b1
IPRn[3:2]
1
1
b0
IPRn[1:0]
1
1
1
(n = A to I)
Bit
Symbol
Bit Name
7
IPRn[7:6]
Interrupt priority 00: Priority level 0 (lowest)
7 and 6
01: Priority level 1
10: Priority level 2
11: Priority level 3 (highest)
R/W
IPRn[5:4]
Interrupt priority 00: Priority level 0 (lowest)
5 and 4
01: Priority level 1
10: Priority level 2
11: Priority level 3 (highest)
R/W
IPRn[3:2]
Interrupt priority 00: Priority level 0 (lowest)
3 and 2
01: Priority level 1
10: Priority level 2
11: Priority level 3 (highest)
R/W
IPRn[1:0]
Interrupt priority 00: Priority level 0 (lowest)
1 and 0
01: Priority level 1
10: Priority level 2
11: Priority level 3 (highest)
R/W
6
5
4
3
2
1
0
Description
R/W
[Legend]
n = A to I
• IPR7 to IPR0 bits (Interrupt priority 7 to 0)
IPR are nine 8-bit readable/writable registers that set priorities (levels 3 to 0) for interrupt sources
other than Nonmaskable interrupt request (NMI). The correspondence between interrupt sources
and IPR settings is shown in table 4.2. Setting a value in the range from H'0 to H'3 in the 2-bit
groups of bits 7 and 6, 5and 4, 3 and 2, and, 1 and 0 determines the priority of the corresponding
interrupt requests.
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Section 4 Interrupt Controller
Table 4.2
Correspondence between Interrupt Sources and IPR Settings
Register Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IPRA
Flash memory
WDT
LVD
CPG
IPRB
IRQ0
IRQ1
IRQ2
IRQ3
IPRC
IRQ4
IRQ5
IRQ6
IRQ7
IPRD
A/D converter
unit 1
A/D converter
unit 2*1
DTC
ELC
IPRE
SCI3 channel 1
SCI3 channel 2
SCI3 channel 3

IPRF


IIC2/SSU

IPRG

Timer RA
Timer RB
Timer RC*2
IPRH
Timer RD unit 0
channel 0
Timer RD unit 0
channel 1
Timer RD unit 1
channel 2*3
Timer RD unit 1
channel 3*3
IPRI
Timer RE

Timer RG

Notes: : Reserved
1. Provided for the H8S/20223 group only.
2. Provided for the H8S/20103 group only.
3. Not provided for the H8S/20103 group.
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Section 4 Interrupt Controller
4.2.3
IRQ Enable Register (IER)
Address: H'FF0521
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
IRQ7E
IRQ6E
IRQ5E
IRQ4E
IRQ3E
IRQ2E
IRQ1E
IRQ0E
0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
IRQ7E
IRQ7 enable
0: IRQ7 interrupts are disabled.
R/W
1: IRQ7 interrupts are enabled.
6
IRQ6E
IRQ6 enable
0: IRQ6 interrupts are disabled.
R/W
1: IRQ6 interrupts are enabled.
5
IRQ5E
IRQ5 enable
0: IRQ5 interrupts are disabled.
R/W
1: IRQ5 interrupts are enabled.
4
IRQ4E
IRQ4 enable
0: IRQ4 interrupts are disabled.
R/W
1: IRQ4 interrupts are enabled.
3
IRQ3E
IRQ3 enable
0: IRQ3 interrupts are disabled.
R/W
1: IRQ3 interrupts are enabled.
2
IRQ2E
IRQ2 enable
0: IRQ2 interrupts are disabled.
R/W
1: IRQ2 interrupts are enabled.
1
IRQ1E
IRQ1 enable
0: IRQ1 interrupts are disabled.
R/W
1: IRQ1 interrupts are enabled.
0
IRQ0E
IRQ0 enable
0: IRQ0 interrupts are disabled.
R/W
1: IRQ0 interrupts are enabled.
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Section 4 Interrupt Controller
4.2.4
IRQ Sense Control Register H and L (ISCRH and ISCRL)
• ISCRH
Address: H'FF0522
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
IRQ7SCB
IRQ7SCA
IRQ6SCB
IRQ6SCA
IRQ5SCB
IRQ5SCA
IRQ4SCB
IRQ4SCA
0
1
0
1
0
1
0
1
b7
b6
b5
b4
b3
b2
b1
b0
IRQ3SCB
IRQ3SCA
IRQ2SCB
IRQ2SCA
IRQ1SCB
IRQ1SCA
IRQ0SCB
IRQ0SCA
0
1
0
1
0
1
0
1
Value after reset:
• ISCRL
Address: H'FF0523
Bit:
Value after reset:
• ISCRH
Bit
Symbol
Bit Name
Description
R/W
7
IRQ7SCB
00: Reserved (setting prohibited)
R/W
6
IRQ7SCA
IRQ7 sense
control B and A
01: Interrupt request is generated at falling edge
of IRQ7 input.
10: Interrupt request is generated at rising edge
of IRQ7 input.
11: Interrupt request is generated at both falling
and rising edges of IRQ7 input.
5
IRQ6SCB
4
IRQ6SCA
IRQ6 sense
control B and A
00: Reserved (setting prohibited)
01: Interrupt request is generated at falling edge
of IRQ6 input.
10: Interrupt request is generated at rising edge
of IRQ6 input.
11: Interrupt request is generated at both falling
and rising edges of IRQ6 input.
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R/W
Section 4 Interrupt Controller
Bit
Symbol
Bit Name
Description
R/W
3
IRQ5SCB
00: Reserved (setting prohibited)
R/W
2
IRQ5SCA
IRQ5 sense
control B and A
01: Interrupt request is generated at falling edge
of IRQ5 input.
10: Interrupt request is generated at rising edge
of IRQ5 input.
11: Interrupt request is generated at both falling
and rising edges of IRQ5 input.
1
IRQ4SCB
0
IRQ4SCA
IRQ4 sense
control B and A
00: Reserved (setting prohibited)
R/W
01: Interrupt request is generated at falling edge
of IRQ4 input.
10: Interrupt request is generated at rising edge
of IRQ4 input.
11: Interrupt request is generated at both falling
and rising edges of IRQ4 input.
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Section 4 Interrupt Controller
• ISCRL
Bit
Symbol
Bit Name
Description
R/W
7
IRQ3SCB
00: Reserved (setting prohibited)
R/W
6
IRQ3SCA
IRQ3 sense
control B and A
01: Interrupt request is generated at falling edge
of IRQ3 input.
10: Interrupt request is generated at rising edge
of IRQ3 input.
11: Interrupt request is generated at both falling
and rising edges of IRQ3 input.
5
IRQ2SCB
4
IRQ2SCA
IRQ2 sense
control B and A
00: Reserved (setting prohibited)
R/W
01: Interrupt request is generated at falling edge
of IRQ2 input.
10: Interrupt request is generated at rising edge
of IRQ2 input.
11: Interrupt request is generated at both falling
and rising edges of IRQ2 input.
3
IRQ1SCB
2
IRQ1SCA
IRQ1 sense
control B and A
00: Reserved (setting prohibited)
R/W
01: Interrupt request is generated at falling edge
of IRQ1 input.
10: Interrupt request is generated at rising edge
of IRQ1 input.
11: Interrupt request is generated at both falling
and rising edges of IRQ1 input.
1
IRQ0SCB
0
IRQ0SCA
IRQ0 sense
control B and A
00: Reserved (setting prohibited)
01: Interrupt request is generated at falling edge
of IRQ0 input.
10: Interrupt request is generated at rising edge
of IRQ0 input.
11: Interrupt request is generated at both falling
and rising edges of IRQ0 input.
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R/W
Section 4 Interrupt Controller
4.2.5
IRQ Status Register (ISR)
Address: H'FF0524
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
IRQ7F
IRQ7 flag
[Setting condition]
R/W
6
IRQ6F
IRQ6 flag
•
R/W
5
IRQ5F
IRQ5 flag
4
IRQ4F
When the interrupt source selected by ISCR
occurs.
IRQ4 flag
[Clearing conditions]
•
3
IRQ3F
IRQ3 flag
2
IRQ2F
IRQ2 flag
1
IRQ1F
IRQ1 flag
0
IRQ0F
IRQ0 flag
•
•
R/W
R/W
When 1 is read from the bit and then 0 is written to R/W
the same bit.
R/W
When IRQn interrupt exception handling is
R/W
executed while falling, rising, or both-edge
R/W
detection is set.
When the DTC is activated by an IRQn interrupt
and the DISEL bit in MRB of the DTC is 0.
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Section 4 Interrupt Controller
4.2.6
IRQ Noise Canceler Control Register (INCCR)
Address: H'FF0525
Bit:
Value after reset:
b7
b6


0
0
b5
b4
b3
INCCR[5:4]
1
b2
b1
INCCR[3:2]
1
1
b0
INCCR[1:0]
1
1
1
Bit
Bit Name
Initial Value
Description
R/W
7

Reserved
These bits are always read as 0. The write
value should always be 0.

INCCR[5:4]
Noise cancel
00: TBD
performance setting 01: Twice of the TBD
5 and 4 for NMI pin
10: Four times of the TBD
6
5
4
R/W
11: Eight times of the TBD
3
INCCR[3:2]
Noise cancel
00: TBD
performance setting 01: Twice of the TBD
3 and 2 for IRQ7 to
10: Four times of the TBD
IRQ4 pins
11: Eight times of the TBD
R/W
INCCR[1:0]
Noise cancel
00: TBD
performance setting 01: Twice of the TBD
1 and 0 for IRQ3 to
10: Four times of the TBD
IRQ0 pins
11: Eight times of the TBD
R/W
2
1
0
Note: Noise cancel performance varies according to the manufacturing condition, temperature,
and VCC.
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Section 4 Interrupt Controller
4.2.7
Interrupt Vector Offset Register (VOFR)
Address: H'FF0526
Bit:
b15
b14
bit15 bit14
Value after reset:
0
0
b13
b12
b11
bit13 bit12 bit11 bit10
0
0
0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
0
0
0
0
0
0
0
0
0
0
b10
0
MSB
bit15 bit14 bit13 bit12 bit11 bit10 bit9
LSB
bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
VOFR
0
0
0
0
0
+
Interrupt vector
base address
0
0
0
0
0
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Vector address
VOFR is a 16-bit readable/writable register that sets an offset for an interrupt vector address.
Interrupt vector areas other than the trace interrupt area and trap instruction interrupt area can be
varied with the offset. The upper 13 bits are used to set the offset for the interrupt vector address
(A23 to A11). Bits 2 to 0 are reserved. The write value should always be 0. This register also can
be accessed in 8-bit units.
The vector address can be obtained by adding the VOFR value to the interrupt vector base address
as shown above, except for the trace interrupt and trap instruction interrupt.
This register is initialized to H'0000 by a reset.
Rev. 1.00 Oct. 03, 2008 Page 85 of 962
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Section 4 Interrupt Controller
4.2.8
Event Link Interrupt Control Status Register (ELCSR)
Address: H'FF0528
Bit:
b7
b6
b5
b4
b3
b2
b1
b0




ELIE2
ELIE1
ELF2
ELF1
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7 to 4

Reserved
These bits are read as 0. The write value should
be 0.

3
ELIE2
ELC interrupt 2 0: ELF2 interrupts are disabled.
enable
1: ELF2 interrupts are enabled.
R/W
2
ELIE1
ELC interrupt 1 0: ELF1 interrupts are disabled.
enable
1: ELF1 interrupts are enabled.
R/W
1
ELF2
ELC interrupt
flag 2
R/W
[Setting condition]
•
When the event selected by ELSR30 occurs*
1
[Clearing conditions]
0
ELF1
ELC interrupt
flag 1
•
When 1 is read from this bit and then 0 is
written to the same bit.
•
When the DTC is activated by an ELF2
interrupt, and the DISEL bit in MRB of the DTC
2
is 0.*
R/W
[Setting condition]
•
When the event selected by ELSR12 occurs*
1
[Clearing conditions]
•
When 1 is read from this bit and then 0 is
written to the same bit.
•
When the DTC is activated by an ELF1
interrupt, and the DISEL bit in MRB of the DTC
is 0.*2
Notes: 1. For details, see section 12, Event Link Controller.
2. When the DTC is activated by an ELF1 or ELF2 interrupt, the event link source module
is not affected.
Rev. 1.00 Oct. 03, 2008 Page 86 of 962
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Section 4 Interrupt Controller
4.3
Interrupt Sources
4.3.1
External Interrupt sources
There are nine external interrupts: NMI and IRQ7 to IRQ0. These external interrupts can be used
to cause the device to exit from standby mode.
(1)
NMI Interrupt
The nonmaskable interrupt request (NMI) is the highest-priority interrupt, and always accepted by
the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The
NMIEG bit in INTCR can be used to select whether an interrupt is requested at a rising edge or a
falling edge on the NMI pin.
(2)
IRQ7 to IRQ0 Interrupts
Interrupts IRQ7 to IRQ0 are generated by an input signal at pins IRQ7 to IRQ0. IRQ7 to IRQ0
interrupts have the following features:
• Using ISCR, it is possible to select whether an interrupt on the IRQ7 to IRQ0 input pins is
generated by a falling edge, rising edge, or both edges.
• Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER.
• The interrupt priority level can be set with IPR.
• The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0
by software.
A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 4.2.
Rev. 1.00 Oct. 03, 2008 Page 87 of 962
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Section 4 Interrupt Controller
IRQnE
INCCRn
IRQnSCB, IRQnSCA
IRQnF
Noise cancel
circuit
Edge detection
circuit
S
Q
IRQn interrupt
request
R
IRQn input
Clear signal
n = 7 to 0
Figure 4.2 Block Diagram of IRQ7 to IRQ0 Interrupt
4.3.2
Internal Interrupts
The sources for internal interrupts from on-chip peripheral modules have the following features:
• For each on-chip peripheral module there are flags that indicate the interrupt request status,
and enable bits that select enabling or disabling of these interrupts. They can be controlled
independently. When the enable bit is set to 1, an interrupt request is issued to the interrupt
controller.
• The interrupt priority level can be set by means of IPR.
• The DTC can be activated by a peripheral module interrupt request.
• When the DTC is activated by an interrupt request, it is not affected by the interrupt control
mode or CPU interrupt mask bit.
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Section 4 Interrupt Controller
4.4
Interrupt Exception Handling Vector Table
Table 4.3 shows interrupt exception handling sources, vector addresses, and interrupt priorities.
For default priorities, the lower the vector number, the higher the priority. When interrupt control
mode 2 is set, priorities among modules can be changed by the IPR. Modules set at the same
priority will conform to their default priorities. Priorities within a module are fixed.
Rev. 1.00 Oct. 03, 2008 Page 89 of 962
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Section 4 Interrupt Controller
Table 4.3
Interrupt Sources, Vector Addresses, and Interrupt Priorities
Origin of
Interrupt
Source
Interrupt Source
Vector
1
Number Vector Address*
DTCER
IPR
Priority
RES Pin
Reset
0
H'0000 to H'0003


High
WDT
1. RES pin reset
VLD
2. WDT overflow
3. LVD reset
4. Software reset

Reserved
1 to 4
H'0004 to H'0013


CPU
Trace
5
H'0014 to H'0017



Reserved
6
H'0018 to H'001B


External
pin
NMI
7
H'001C to H'001F


CPU
TRAPA0 (TRAPA #0 8
instruction)
H'0020 to H'0023


TRAPA0 (TRAPA #1 9
instruction)
H'0024 to H'0027


TRAPA0 (TRAPA #2 10
instruction)
H'0028 to H'002B


TRAPA0 (TRAPA #3 11
instruction)
H'002C to H'002F



Reserved
12 to 15
H'0030 to H'003F


FLASH
IFMBSYA (access
when flash memory
busy)
16
H'0040 to H'0043


IFLRDY (flash
memory ready)
17
H'0044 to H'0047

IPRA7 and
IPRA6
WDT
IWDT (WDT periodic 18
interrupt)
H'0048 to H'004B

IPRA5 and
IPRA4
LVD
ILVINT1 (low-voltage 19
detected interrupt 1)
H'004C to H'004F

IPRA3 and
IPRA2
ILVINT2 (low-voltage 20
detected interrupt 2)
H'0050 to H'0053

ICKSW (clock
switching interrupt)
H'0054 to H'0057

CPG
21
Rev. 1.00 Oct. 03, 2008 Page 90 of 962
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IPRA1 and
IPRA0
Low
Section 4 Interrupt Controller
Origin of
Interrupt
Source
Interrupt Source
Vector
1
Number Vector Address*
DTCER
IPR
Priority
IRQ0
22
H'0058 to H'005B
DTCEA7
IPRB7 and
IPRB6
High
IRQ1
23
H'005C to H'005F
DTCEA6
IPRB5 and
IPRB4
IRQ2
24
H'0060 to H'0063
DTCEA5
IPRB3 and
IPRB2
IRQ3
25
H'0064 to H'0067
DTCEA4
IPRB1 and
IPRB0
IRQ4
26
H'0068 to H'006B
DTCEA3
IPRC7 and
IPRC6
IRQ5
27
H'006C to H'006F
DTCEA2
IPRC5 and
IPRC4
IRQ6
28
H'0070 to H'0073
DTCEA1
IPRC3 and
IPRC2
IRQ7
29
H'0074 to H'0077
DTCEA0
IPRC1 and
IPRC0
IADEND_1
(conversion end)
30
H'0078 to H'007B
DTCEB7
IPRD7 and
IPRD6
IADCMP_1
(compare condition
match)
31
H'007C to H'007F
DTCEB6
IADEND_2
(conversion end)
32
H'0080 to H'0083
DTCEB5
IADCMP_2
(compare condition
match)
33
H'0084 to H'0087
DTCEB4
DTC
ISWDTEND (data
transfer end)
34
H'0088 to H'008B

IPRD3 and
IPRD2
ELC
ELC1FP (ELSR12
event generation)
35
H'008C to H'008F
DTCEB3
IPRD1 and
IPRD0
ELC2FP (ELSR30
event generation)
36
H'0090 to H'0093
DTCEB2
External
pin
A/D
converter
unit 1
A/D
converter
unit 2*2
IPRD5 and
IPRD4
Low
Rev. 1.00 Oct. 03, 2008 Page 91 of 962
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Section 4 Interrupt Controller
Origin of
Interrupt
Source
Interrupt Source
Vector
1
Number Vector Address*
DTCER
IPR
37
H'0094 to H'0097

IPRE7 and High
IPRE6
SCI3_1 RXI
38
H'0098 to H'009B
DTCEB1
SCI3_1 TXI
39
H'009C to H'009F
DTCEB0
SCI3_1 TEI
40
H'00A0 to H'00A3

41
H'00A4 to H'00A7

42
H'00A8 to H'00AB
DTCEC7
SCI3_1 ERI
SCI3
channel 1 1. Overrun error
2. Parity error
3. Framing error
SCI3
SCI3_2 ERI
channel 2 1. Overrun error
2. Parity error
3. Framing error
SCI3_2 RXI

IPRE5 and
IPRE4
SCI3_2 TXI
43
H'00AC to H'00AF
DTCEC6
SCI3_2 TEI
44
H'00B0 to H'00B3

45
H'00B4 to H'00B7

SCI3_3 RXI
46
H'00B8 to H'00BB
DTCEC5
SCI3_3 TXI
47
H'00BC to H'00BF
DTCEC4
SCI3_3 TEI
48
H'00C0 to H'00C3

Reserved
49 to 58 H'00C4 to H'00EB


59
H'00EC to H'00EF

IPRF3 and
IPRF2
RXI
60
H'00F0 to H'00F3
DTCED7
TXI
61
H'00F4 to H'00F7
DTCED6
TEI
62
H'00F8 to H'00FB

SCI3
SCI3_3 ERI
channel 3 1. Overrun error
2. Parity error
3. Framing error
IIC2/SSU 1. IIC-BUS mode
 NAKI
 STPI
2. Clock
synchronous mode
 Overrun
3. SSU mode
Priority
IPRE3 and
IPRE2
 Overrun (OEI)
 Conflict (CEI)
Rev. 1.00 Oct. 03, 2008 Page 92 of 962
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Low
Section 4 Interrupt Controller
Origin of
Interrupt
Source
Interrupt Source
Vector
1
Number Vector Address* DTCER

Reserved
63 to 68 H'00FC to H'0113
Timer RA/
HW-LIN
1. Timer RA
69
ITBUD
IPR
Priority


High
H'0114 to H'0117

IPRG5 and
IPRG4
70
H'0118 to H'011B

IPRG3 and
IPRG2
Timer RC*3 ITCMA (input
capture A/compare
match A)
71
H'011C to H'011F
DTCED3
IPRG1 and
IPRG0
ITCMB (input
capture B/compare
match B)
72
H'0120 to H'0123
DTCED2
ITCMC (input
capture C/compare
match C)
73
H'0124 to H'0127
DTCED1
ITCMD (input
capture D/compare
match D)
74
H'0128 to H'012B
DTCED0
ITCOV counter
overflow
75
H'012C to H'012F

ITDMA0_0 (input
capture A/compare
match A)
76
H'0130 to H'0133
DTCEE7
ITDMB0_0 (input
capture B/compare
match B)
77
H'0134 to H'0137
DTCEE6
 ITAUD
2. HW-LIN
 Bus conflict
detection
(BCDCT)
 Sync Break
detection
(SBDCT)
 Sync Field
measurement
end (SFDCT)
Timer RB
Timer RD
unit 0
channel 0
IPRH7 and
IPRH6
Low
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Section 4 Interrupt Controller
Origin of
Interrupt
Source
Interrupt Source
Timer RD
unit 0
channel 0
ITDMC0_0 (input
capture C/compare
match C)
78
H'0138 to H'013B
DTCEE5
ITCMD0_0 (input
capture D/compare
match D)
79
H'013C to H'013F
DTCEE4
ITDOV0_0 overflow
Timer RD
unit 0
channel 1
Vector
Number Vector Address*1 DTCER
80
H'0140 to H'0143

ITDUD0_0 underflow 81
H'0144 to H'0147

ITDMA0_1 (input
capture A/compare
match A)
82
H'0148 to H'014B
DTCEE3
ITDMB0_1 (input
capture B/compare
match B)
83
H'014C to H'014F
DTCEE2
ITDMC0_1 (input
capture C/compare
match C)
84
H'0150 to H'0153
DTCEE1
ITCMD0_1 (input
capture D/compare
match D)
85
H'0154 to H'0157
DTCEE0
ITDOV0_1 overflow
86
H'0158 to H'015B

Timer RD ITDMA1_2 (input
unit 1
capture A/compare
4
channel 2* match A)
87
H'015C to H'015F
DTCEF7
ITDMB1_2 (input
capture B/compare
match B)
88
H'0160 to H'0163
DTCEF6
ITDMC1_2 (input
capture C/compare
match C)
89
H'0164 to H'0167
DTCEF5
ITCMD1_2 (input
capture D/compare
match D)
90
H'0168 to H'016B
DTCEF4
ITDOV1_2 overflow
91
H'016C to H'016F

ITDUD1_2 underflow 92
H'0170 to H'0173

Rev. 1.00 Oct. 03, 2008 Page 94 of 962
REJ09B0465-0100
IPR
Priority
IPRH7 and High
IPRH6
IPRH5 and
IPRH4
IPRH3 and
IPRH2
Low
Section 4 Interrupt Controller
Origin of
Interrupt
Source
Interrupt Source
Vector
1
Number Vector Address* DTCER
IPR
Priority
Timer RD
ITDMA1_3 (input
unit 1
capture A/compare
3
channel 3* match A)
93
H'0174 to H'0177
ITDMB1_3 (input
capture B/compare
match B)
94
H'0178 to H'017B DTCEE2
ITDMC1_3 (input
capture C/compare
match C)
95
H'017C to H'017F DTCEE1
ITCMD1_3 (input
capture D/compare
match D)
96
H'0180 to H'0183
DTCEE0
ITDOV1_3 overflow
97
H'0184 to H'0187


Reserved
98, 99
H'0188 to H'018F


Timer RE
Second interrupt
100
H'0190 to H'0193
DTCEG4
Minute interrupt
101
H'0194 to H'0197
DTCEG3
IPRI7 and
IPRI6
Hour interrupt
102
H'0198 to H'019B DTCEG2
Day interrupt
103
H'019C to H'019F DTCEG1
DTCEE3
IPRH1 and High
IPRH0
Week interrupt
104
H'01A0 to H'01A3 DTCEG0
Compare match
105
H'01A4 to H'01A7 

Reserved
106 to
108
H'01A8 to H'01B3 

Timer RG
ITGMA (input
capture A/compare
match A)
109
H'01B4 to H'01B7 DTCEH3
IPRI3 and
IPRI2
ITGMB (input
capture B/compare
match B)
110
H'01B8 to H'01BB DTCEH2
ITGOV
111
H'01BC to H'01BF 
ITGUD
112
H'01C0 to H'01C3 
Notes: 1.
2.
3.
4.
Low
Lower 16 bits of the vector address when VOFR = H'0000
Provided for the H8S/20223 group only. This area is reserved for the other groups.
Provided for the H8S/20103 group only. This area is reserved for the other groups.
Not provided for the H8S/20103 group.
Rev. 1.00 Oct. 03, 2008 Page 95 of 962
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Section 4 Interrupt Controller
4.5
Interrupt Control Modes and Interrupt Operation
The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2.
Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is
selected by INTCR. Table 4.4 shows the differences between interrupt control mode 0 and
interrupt control mode 2.
Table 4.4
Interrupt Control Modes
Interrupt
Control Mode
Priority Setting
Registers
Interrupt
Mask Bits
0
Default
I
Description
The priorities of interrupt sources are fixed at
the default settings.
Interrupt sources except for NMI is masked by
the I bit.
2
IPR
I1 and I0
Four priority levels except for NMI can be set
with IPR.
Four-level interrupt mask control is performed
by bits I1 and I0.
4.5.1
Interrupt Control Mode 0
In interrupt control mode 0, interrupt requests except for NMI is masked by the I bit in CCR of the
CPU. Figure 4.3 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
2. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held
pending. If the I bit is cleared, an interrupt request is accepted.
3. When interrupt requests are sent to the interrupt controller, the highest-ranked interrupt request
according to the priority system is accepted, and other interrupt requests are retained.
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
execution of the current instruction has been completed.
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
6. The I bit in CCR is set to 1. This masks all interrupts except NMI.
7. The CPU generates a vector address for the accepted interrupt request and starts execution of
the interrupt handling routine at the address indicated by the contents of the start address in the
vector table.
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Section 4 Interrupt Controller
Program execution status
No
Interrupt generated
Yes
Yes
NMI
No
Yes
IFMBSYA*
No
I=0
No
Retained
Yes
No
IRQ0
Yes
No
IRQ1
Yes
ITGUD
Yes
Save PC and CCR
I←1
Read vector address
Branch to interrupt handling routine
Note: * Access interrupt when flash memory busy.
Figure 4.3 Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 0
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Section 4 Interrupt Controller
4.5.2
Interrupt Control Mode 2
In interrupt control mode 2, mask control is executed in four levels for interrupt requests except
NMI by comparing the EXR interrupt mask level (I1 and I0 bits*) in the CPU and the IPR setting.
Figure 4.4 shows a flowchart of the interrupt acceptance operation.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
2. When interrupt requests are sent to the interrupt controller, the interrupt with the highest
priority according to the interrupt priority levels set in IPR is selected, and lower-priority
interrupt requests are held pending. If the same priority are generated at the same time, the
interrupt request is selected according to the default priority system shown in table 4.3.
3. Next, the priority of the selected interrupt request is compared with the interrupt mask level set
in EXR. An interrupt request with a priority no higher than the mask level set at that time is
held pending, and only an interrupt request with a priority higher than the interrupt mask level
is accepted.
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
execution of the current instruction has been completed.
5. The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC
saved on the stack shows the address of the first instruction to be executed after returning from
the interrupt handling routine.
6. The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of
the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'3.
7. The CPU generates a vector address for the accepted interrupt request and starts execution of
the interrupt handling routine at the address indicated by the contents of the start address in the
vector table.
Note: * The I2 bit does not affect the mask control.
Rev. 1.00 Oct. 03, 2008 Page 98 of 962
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Section 4 Interrupt Controller
Program execution status
Interrupt generated
No
Yes
Yes
NMI
No
Yes
IFMBSYA*
No
Level 3 interrupt
No
Yes
Mask level 2
or below
Yes
Level 2 interrupt
No
No
Yes
Level 1 interrupt
Mask level 1
or below
No
No
Yes
Yes
Mask level 0
No
Yes
Save PC, CCR, and EXR
Retained
Clear T bit to 0
Update mask level
Read vector address
Branch to interrupt handling routine
Note: * Access interrupt when flash memory busy.
Figure 4.4 Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 2
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Section 4 Interrupt Controller
4.5.3
Interrupt Exception Handling Sequence
Figure 4.5 shows the interrupt exception handling sequence. The example shown is for the case
where interrupt control mode 0, the program area, and stack area are in on-chip memory.
Rev. 1.00 Oct. 03, 2008 Page 100 of 962
REJ09B0465-0100
(1)
(2)
(4)
(3)
Internal
operation
Instruction prefetch address (Not executed.
This is the contents of the saved PC, the return address.)
(2) (4) Instruction code (Not executed.)
(3)
Instruction prefetch address (Not executed.)
(5)
SP-2
(7)
SP-4
(1)
Internal
data bus
Internal
write signal
Internal
read signal
Internal
address bus
Interrupt
request signal
φ
Interrupt level determination Instruction
Wait for end of instruction
prefetch
Interrupt
acceptance
(7)
(8)
(10)
(9)
Vector fetch
(12)
(11)
(14)
(13)
Saved PC and saved CCR
Vector address
Interrupt handling routine start address (Vector address contents)
Interrupt handling routine start address ((13) = (10)(12))
First instruction of interrupt handling routine
(6)
(6) (8)
(9) (11)
(10) (12)
(13)
(14)
(5)
Stack
Interrupt handling
Internal
routine instruction
operation prefetch
Section 4 Interrupt Controller
Figure 4.5 Interrupt Exception Handling
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Section 4 Interrupt Controller
4.5.4
Interrupt Response Time
Table 4.5 shows interrupt response time, the interval between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine.
Table 4.5
Interrupt Response Times
Interrupt Control
Mode 0
Interrupt Control
Mode 2
No.
Execution Status
1
Interrupt priority determination*1
2
Number of wait states until executing
2
instruction ends*
3
PC, CCR, EXR stack
4
Vector fetch
2
5
Instruction fetch*3
2
6
Internal processing*4
2
Total (using on-chip memory)
Notes: 1.
2.
3.
4.
4.5.5
3
1 to 21
2
12 to 32
3
13 to 33
Two states in case of internal interrupt
Refers to MULXS and DIVXS instructions.
Prefetch after interrupt acceptance and interrupt handling routine prefetch
Internal processing after interrupt acceptance and internal processing after vector fetch
DTC Activation by Interrupt
The DTC can be activated by an interrupt request. In this case, the following options are available:
1.
2.
3.
Interrupt request to CPU
Activation request to DTC
Both of the above
For details of interrupt requests that can be used to activate the DTC, see table 4.3 and section 11,
Data Transfer Controller (DTC).
Rev. 1.00 Oct. 03, 2008 Page 102 of 962
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Section 4 Interrupt Controller
4.6
Usage Notes
4.6.1
Conflict between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to mask interrupt requests, the masking becomes
effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an
instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction,
the interrupt concerned is still enabled on completion of the instruction, and so interrupt exception
handling for that interrupt will be executed after completion of the instruction. However, if there is
an interrupt request of higher priority than that interrupt, interrupt exception handling with the
higher-priority interrupt is executed, and that lower-priority interrupt will be ignored. The same
also applies when an interrupt source flag is cleared to 0. Figure 4.6 shows an example in which
the IRQ0E bit in IER is cleared to 0. The above conflict does not occur if an enable bit or interrupt
source flag is cleared to 0 while the interrupt is masked.
IER write cycle by CPU
IRQ0 exception handling
φ
Internal
address bus
IER address
Internal
write signal
IRQ0E
IRQ0 flag
IRQ0
interrupt signal
Figure 4.6 Conflict between Interrupt Generation and Disabling
Rev. 1.00 Oct. 03, 2008 Page 103 of 962
REJ09B0465-0100
Section 4 Interrupt Controller
4.6.2
Instructions that Disable Interrupts
Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions is executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit is set by one of these instructions, the new value becomes valid
after two states that execution of the instruction ends.
4.6.3
Time when Interrupts are Disabled
There are time when interrupt acceptance is disabled by the interrupt controller. The interrupt
controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask
level with an LDC, ANDC, ORC, or XORC instruction.
4.6.4
Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the transfer is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction. Therefore, if an interrupt is generated during execution
of an EEPMOV.W instruction, the following coding should be used.
L1:
EEPMOV.W
MOV.W
R4,R4
BNE
L1
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Section 4 Interrupt Controller
4.6.5
Changing PMR, ISCRH, ISCRL and INCCR
When the PMR, ISCRH, ISCRL, and INCCR are modified to change an IRQ7 to IRQ0 interrupt
function, the interrupt request flag bit may be set to 1 at an unintended time. To prevent this, the
pin function should be changed when the interrupt request is disabled, then the interrupt request
flag should be cleared to 0 after a specific interval time*.
Figure 4.7 shows the procedure to modify PMR (port mode register), ISCRH, ISCRL, and INCCR
and clear the interrupt request flags.
Note: Two states + a minimum interval for input (tIH/tIL)
Set I bit in CCR
to 1.
The interrupt is disabled.
(Interrupts can also be
disabled by setting IER.)
Modify PMR, ISCRH,
ISCRL, and INCCR.
Wait for a specific
period.
After setting each register,
the interrupt request flag
should be cleared to 0 after
waiting for a specific period.
Clear interrupt request
flag to 0.
Clear I bit in CCR
to 0.
The Interrupt is enabled.
Figure 4.7 Procedure to Modify PMR, ISCRH, ISCRL, and INCCR and Clear Interrupt
Request Flag
4.6.6
IRQ Status Register (ISR)
Depending on the pin state after a reset, IRQnF may be set to 1. Therefore, always read ISR and
clear it to 0 after resets.
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Section 4 Interrupt Controller
4.6.7
NMI Pin
The NMI pin is also used to set up entry to boot mode on exit from the reset state. In using the
NMI pin, note that the low-level should not be being applied to the NMI pins on exit from the
reset state (including power-on reset). In general, it is recommended that the connection of a pullup resistor to the NMI pin.
Rev. 1.00 Oct. 03, 2008 Page 106 of 962
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Section 5 Clock Pulse Generator
Section 5 Clock Pulse Generator
The clock pulse generator is comprised of a high-speed on-chip oscillator (OCO), a 1/2 divider for
the high-speed OCO, the main oscillator, a duty correction circuit, a low-speed, OCO, a suboscillator, a clock selection circuit, a system clock divider, a PSC divider for peripheral modules,
and a φs divider for the bus master and memory.
Table 5.1 lists clock source symbols and their meanings used in this manual.
Table 5.1
Clock Source Symbols
Symbol
Description
φ40
High-speed OCO output
φhoco
High-speed OCO frequency/2
φloco
Low-speed OCO output
φosc
Main oscillator output clock
φsub
Sub-oscillator output clock
φhigh
High-speed clock (φhoco or φosc)
φlow
Low-speed clock (φloco or φsub)
φbase
System base clock
φ
System operation clock
φs
Bus master operation clock
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Section 5 Clock Pulse Generator
5.1
Overview
• Choice of four clock sources:
φloco, φsub, φhoco and φosc
• Choice of two frequencies of the high-speed OCO by the user software:
40 MHz and 32 MHz
The signal generated by dividing the above clock by 2 can be used as a φbase and the above
clock can be used as the clock source for timer RA, timer RC, timer RD, and timer RG.
• Trimmable high-speed OCO oscillation frequencies
Although the high-speed OCO is trimmed to 40 MHz in its initial state, it can also be trimmed
to accommodate specific user operation conditions.
• Main oscillation backup function
By detecting a φosc stop, it is possible to automatically switch the system clock to either φhoco
or φlow.
• Clock switching interrupt function
When the system clock is switched from φosc to φhoco or φloco, a CPU interrupt can be
generated if enabled.
Figure 5.1 shows a block diagram of the clock pulse generation circuit.
To timers RA, RC, RD, and RG
φ
Highspeed
OCO
OSC1
OSC2
X2
φhoco
1/2
divider
Duty
correction
circuit
Main
clock
oscillator
Lowspeed
OCO
X1
φ40
Subclock
oscillator
φosc
Highspeed
clock
select
circuit
φ/2
φbase
φhigh
φbase/2
φbase/4
High-speed/
low-speed
clock select
circuit
φloco
Noise
canceller
φsub
Lowspeed
clock
select
circuit
PSC
divider
φbase
System
clock
divider
φbase/8
φbase/16
φ
φ
φbase/32
φ/2
φbase/64
φlow
φbase/128
φs
divider
φ/4
φ/8
φ/16
Clock select circuit
φ/32
To WDT
To WDT, timer RA, and timer RE
Clock pulse generator
Figure 5.1 Block Diagram of Clock Pulse Generation Circuit
Rev. 1.00 Oct. 03, 2008 Page 108 of 962
REJ09B0465-0100
Peripheral
module
φ/4
.
.
.
φ/8192
φs
CPU
DTC
internal
memory
Section 5 Clock Pulse Generator
The system base clock (φbase) is the basic clock on which the CPU and on-chip peripheral
modules operate. φbase can be divided by a value from 1 to 128 in the system clock divider, and
the divided clock is supplied as the system clock φ. The system clock φ is divided by a value from
2 to 8192 in the PSC divider, and the divided clock can be supplied to on-chip peripheral modules.
The system clock φ is also divided by a value from 1 to 32 in the φs divider, and the divided clock
can be supplied to the bus master and memory.
After release from a reset, φbase is switched to the low-speed OCO.
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Section 5 Clock Pulse Generator
5.2
•
•
•
•
•
•
•
•
•
•
•
•
Register Descriptions
Backup control register (BAKCR)
System clock control register (SYSCCR)
Power-down control register 1 (LPCR1)
Power-down control register 2 (LPCR2)
Power-down control register 3 (LPCR3)
OSC oscillation settling control status register (OSCCSR)
High-speed OCO control register (HOCR)
High-speed OCO trimming data protect register (HOTRMDPR)
High-speed OCO trimming data register 1 (HOTRMDR1)
High-speed OCO trimming data register 2 (HOTRMDR2)
High-speed OCO trimming data register 3 (HOTRMDR3)
High-speed OCO trimming data register 4 (HOTRMDR4)
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Section 5 Clock Pulse Generator
5.2.1
Backup Control Register (BACKR)
Address: H'FF06D4
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
WI
WE
OSCBAKE
BAKCKSEL
CKSWIE
CKSWIF
OSCHLT

1
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
WI
Write inhibit
0: Writing is permitted.
W
1: Writing is inhibited.
6
WE
Write enable
0: Writing is disabled.
R/W
1: Writing is enabled.
[Setting condition]
When 0 is written to WI and 1 is written to WE at the
same time.
[Clearing condition]
When 0 is written to WI and WE at the same time.
5
OSCBAKE
External clock
backup enable
0: External clock backup is disabled.
R/W
1: External clock backup is enabled.
4
BAKCKSEL Backup
0: φlow
destination clock 1: φhoco
source select
R/W
3
CKSWIE
Clock switching 0: Interrupt requests are disabled.
interrupt enable 1: Interrupt requests are enabled.
R/W
2
CKSWIF
Clock switching 0: A clock switching interrupt request has not been
interrupt flag
generated.
R/W
1: A clock switching interrupt request has been
generated.
[Setting condition]
When the system clock for the LSI is switched from
φosc to φhoco or φlow while OSCBAKE is 1.
[Clearing condition]
When 1 is read from the bit and then 0 is written to
the same bit.
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Section 5 Clock Pulse Generator
Bit
Symbol
Bit Name
Description
1
OSCHLT
Main oscillator 0: The external main oscillator is oscillating.
stop detect flag 1: The external main oscillator is stopped.
R/W
R
[Setting condition]
When the external main oscillator is stopped while
OSCBAKE is 1.
0
Note:

Reserved
This bit is read as 0. The write value should be 0.

A MOV instruction should be used to write to this register.
• WI bit (write inhibit)
This register can be written to only when this bit is 0. This bit is always read as 1.
• WE bit (write enable)
Bits 5 to 2 in this register can be written to when this bit is 1.
• OSCBAKE bit (external clock backup enable)
The main oscillator stop detect circuit is enabled when this bit is 1. When this LSI operates at
the external main oscillator clock, the backup function is enabled.
By detecting a φosc stop, the system clock is automatically switched to either φhoco or φlow.
• CKSWIE bit (clock switching interrupt enable)
The main clock switching interrupt requests are enabled when this bit is 1.
• CKSWIF bit (clock switching interrupt enable)
This is a clock switching interrupt request flag.
• OSCHLT bit (main oscillator stop detect flag)
When the OSCBAKE bit is 1, this bit indicates the results of external oscillator stop detection.
This bit, however, simply indicates whether the oscillator is active or not; it does not indicate a
stable oscillation. When OSCBAKE is 0, this bit is always read as 0. An oscillator stop is
detected when the external oscillator is between 0 to 2 MHz.
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Section 5 Clock Pulse Generator
5.2.2
System Clock Control Register (SYSCCR)
Address: H'FF06D0
Bit:
Value after reset:
b7
b6
b5
b4
b3
WI
WE
PHIHSEL
PHILSEL

1
0
0
0
0
b2
b1
SUBNC[1:0]
0
b0

0
0
Bit
Symbol
Bit Name
Description
R/W
7
WI
Write inhibit
0: Writing is permitted.
W
6
WE
Write enable
1: Writing is inhibited.
R/W
0: Writing is disabled.
1: Writing is enabled.
[Setting condition]
When 0 is written to WI and 1 is written to WE at the
same time.
[Clearing condition]
When 0 is written to WI and WE at the same time.
5
PHIHSEL
φhigh clock
source select
0: φhoco
R/W
1: φosc
[Setting condition]
When 1 is written to this bit while CKSWIF in BAKCR
is 0.
[Clearing conditions]
•
When 0 is written to this bit.
•
4
PHILSEL
φlow clock
source select
3

Reserved
When the main oscillator stop state is detected
while the system clock selects φosc and
OSCBAKE and BAKCKSEL in BAKCR are 1,
respectively.
0: φloco
1: φsub
This bit is read as 0. The write value should be 0.
R/W

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Section 5 Clock Pulse Generator
Bit
Symbol
Bit Name
Description
R/W
2, 1
SUBNC
[1:0]*
φsub noise
canceler
sampling
function
setting
00: The sampling circuit is disabled.
R/W
Reserved
This bit is read as 0. The write value should be 0.

0
Note:
01: Sampling is performed at φbase/4.
10: Sampling is performed at φbase/16.
11: Setting prohibited

A MOV instruction should be used to write to this register.
*
When the operation clock of the CPU selects φlow, the sampling circuit is disabled
regardless of this bit setting.
• WI bit (write inhibit)
This register can be written to only when this bit is 0. This bit is always read as 1.
• WE bit (write enable)
Bits 5, 4, 2, and 1 in this register can be written to when this bit is 1.
• PHIHSEL bit (φhigh clock source select)
This bit is 1 when 0 is written to the WI bit in BAKCR at CKSWIF = 0 and WE = 1 and then 1
is written to this bit. If 0 is written to WI and this bit at WE = 1, this bit remains 0. If the main
oscillator stop is detected while the system clock selects φosc and OSCBAKE and
BAKCKSEL in BAKCR are 1, respectively, this bit is 0.
• PHILSEL bit (φlow clock source select)
When 0 is written to WI and 1 is written to this bit at WE = 1, this bit is 1.
When 0 is written to WI and this bit at WE = 1, this bit is 0.
• SUBNC1 and SUBNC0 bits (φsub noise canceler sampling function setting)
Selects a sampling clock for the subclock oscillator noise canceler. The sampling circuit is
disabled in standby mode, when φbase is stopped during clock switching, and when φlow has
been selected as φbase, regardless of the setting of this bit. When timer RE is to be used in
real-time clock mode, the sampling circuit should be enabled.
Note: The frequency of the low-speed on-chip oscillator varies greatly according to the power
supply voltage and operating temperature. In designing application systems, allow
sufficient margins for frequency variation.
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Section 5 Clock Pulse Generator
5.2.3
Power-Down Control Register 1 (LPCR1)
Address: H'FF06D1
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
WI
WE
SSBY
PSCSTP
SLEEPRS
STBYRS

PHIBSEL
1
0
0
1
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
WI
Write inhibit
0: Writing is permitted.
W
1: Writing is inhibited.
6
WE
Write enable
0: Writing is disabled.
R/W
1: Writing is enabled.
[Setting condition]
When 0 is written to WI and 1 is written to WE at
the same time.
[Clearing condition]
When 0 is written to WI and WE at the same time.
5
SSBY
Software standby 0: A transition is made to sleep mode.
R/W
1: A transition is made to standby mode.
4
PSCSTP
PSC divider stop
0: PSC divider is operating.
R/W
1: PSC divider is stopped*.
3
SLEEPRS φ source select for 0: φlow
recovery from
1: φhigh
sleep mode
R/W
2
STBYRS
φ source select for 0: φlow
recovery from
1: φhigh
standby mode
R/W
1

Reserved
This bit is read as 0. The write value should be 0. 
Rev. 1.00 Oct. 03, 2008 Page 115 of 962
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Section 5 Clock Pulse Generator
Bit
Symbol
Bit Name
Description
R/W
0
PHIBSEL
φbase clock
source select
0: φlow
R/W
1: φhigh
[Setting conditions]
•
When 1 is written to this bit.
•
When the system returns from sleep mode while
SLEEPRS is 1.
•
When the system returns from standby mode
while STBYRS is 1.
[Clearing conditions]
•
When 0 is written to this bit.
•
When the main oscillator backup is generated
while BAKCKSEL in BAKCR is 0.
•
When the system returns from sleep mode while
SLEEPRS is 0.
•
When the system returns from standby mode
while STBYRS is 0.
Note: A MOV instruction should be used to write to this register.
* Operations of the peripheral modules using the φ clock are not affected by this bit
setting.
• WI bit (write inhibit)
This register can be written to only when this bit is 0. This bit is always read as 1.
• WE bit (write enable)
Bits 5 to 2 in this register can be written to when this bit is 1.
• SSBY bit (software standby)
Selects a mode to be entered after the SLEEP instruction is executed.
• PSCSTP bit (PSC divider stop)
Stops the PSC divider circuit when this bit is 1. Peripheral modules using φ/2 to φ/8192 clocks
stop operation. (The register values are retained.)
• SLEEPRS bit (φ source select for recovery from sleep mode)
Selects a clock source to be used when a transition is made from sleep mode to active mode.
Rev. 1.00 Oct. 03, 2008 Page 116 of 962
REJ09B0465-0100
Section 5 Clock Pulse Generator
• STBYRS bit (φ source select for recovery from standby mode)
Selects a clock source to be used when a transition is made from standby mode to active mode.
• PHIBSEL bit (φbase clock source select)
Selects a clock source for the φbase to be used in active mode or sleep mode.
5.2.4
Power-Down Control Register 2 (LPCR2)
Address: H'FF06D2
Bit:
b7
b6
b5
b4
b3
WI
WE



1
0
0
0
0
Value after reset:
b2
b1
b0
PHI[2:0]
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
WI
Write inhibit
0: Writing is permitted.
W
1: Writing is inhibited.
6
WE
Write enable
0: Writing is disabled.
R/W
1: Writing is enabled.
[Setting condition]
When 0 is written to WI and 1 is written to WE at
the same time.
[Clearing condition]
When 0 is written to WI and WE at the same time.
5 to 3

Reserved
2 to 0
PHI[2:0]
System clock φ 000: φbase
select
001: φbase/2
These bits are read as 0. The write value should
be 0.

R/W
010: φbase/4
011: φbase/8
100: φbase/16
101: φbase/32
110: φbase/64
111: φbase/128
Note:
A MOV instruction should be used to write to this register.
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Section 5 Clock Pulse Generator
• WI (write inhibit)
This register can be written to only when this bit is 0. This bit is always read as 1.
• WE bit (write enable)
Bits 2 to 0 in this register can be written to when this bit is 1.
• PHI2 bit to PHI0 bit (system clock φ select)
Selects a clock source for the system clock φ to be used in active mode or sleep mode. The
clock is changed immediately after this bit is set.
5.2.5
Power-Down Control Register 3 (LPCR3)
Address: H'FF06D3
Bit:
Value after reset:
b7
b6
b5
b4
b3
WI
WE
STBYINT
SLEEPINT

1
0
0
0
0
b2
b1
b0
PHIS[2:0]
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
WI
Write inhibit
0: Writing is permitted.
W
1: Writing is inhibited.
6
WE
Write enable
0: Writing is disabled.
R/W
1: Writing is enabled.
[Setting condition]
When 0 is written to WI and 1 is written to WE at
the same time.
[Clearing condition]
When 0 is written to WI and WE at the same time.
5
STBYINT
Standby mode 0: No interrupt has occurred in standby mode.
interrupt
1: An interrupt has occurred in standby mode.
generation flag
[Setting condition]
When an interrupt is generated in standby mode.
[Clearing condition]
When an interrupt is generated in states other
than standby mode.
Rev. 1.00 Oct. 03, 2008 Page 118 of 962
REJ09B0465-0100
R/W
Section 5 Clock Pulse Generator
Bit
Symbol
Bit Name
Description
R/W
4
SLEEPINT
Sleep mode
0: No interrupt has occurred in sleep mode.
interrupt
1: An interrupt has occurred in sleep mode.
generation flag
[Setting condition]
R/W
When an interrupt is generated in sleep mode.
[Clearing condition]
When an interrupt is generated in states other
than sleep mode.
3

Reserved
2 to 0
PHIS[2:0]
Bus master
000: φ
operation clock 001: φ/2
φs select
010: φ/4
This bit is read as 0. The write value should be 0.

R/W
011: φ/8
100: φ/16
101: φ/32
110: Setting prohibited
111: Setting prohibited
Note:
A MOV instruction should be used to write to this register.
• WI bit (write inhibit)
This register can be written to only when this bit is 0. This bit is always read as 1.
• WE bit (write enable)
Bits 2 to 0 in this register can be written to when this bit is 1.
• STBYINT bit (standby mode interrupt generation flag)
This bit is set to 1 when an interrupt is generated in standby mode. This bit is cleared to 0
when an interrupt is generated in the other state.
• SLEEPINT bit (sleep mode interrupt generation flag)
This bit is set to 1 when an interrupt is generated in sleep mode. This bit is cleared to 0 when
an interrupt is generated in the other state.
• PHIS2 bit to PHIS0 bit (bus master operation clock φs select)
Selects a clock source for the bus master operation clock φs to be used in active mode or sleep
mode. The clock is changed immediately after this bit is set.
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Section 5 Clock Pulse Generator
5.2.6
OSC Oscillation Settling Control Status Register (OSCCSR)
Address: H'FF06D5
Bit:
Value after reset:
b7
b6
b5
b4




0
0
0
0
b3
b2
b1
b0
1
1
STS[3:0]
1
1
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is read as unknown value. The write value
should be 0.

6 to 4

Reserved
These bits are read as 0. The write value should be 0.

3 to 0
STS[3:0]
φosc oscillation Specifies the number of wait states for a stable φosc
settling time
oscillation. For the relationship between assigned
select 3 to 0
values and the numbers of wait states, see table 5.2.
R/W
• STS3 bit to STS0 bit (φosc oscillation settling time select 3 to 0)
Specifies the number of wait states for a stable φosc oscillation. The count clock is φosc. Table
5.2 shows the relationship between assigned values and the numbers of wait states. If the
system base clock is φosc when the system returns from the standby mode, or when the system
base clock is switched to φosc, set these bits so that wait time will be 6.5 ms or greater
depending on the frequency of the oscillator.
If the φosc is already oscillating stably or the φosc is an external clock input, wait time can be
selected from 16 states (STS[3:0]=B'0000).
Rev. 1.00 Oct. 03, 2008 Page 120 of 962
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Section 5 Clock Pulse Generator
Table 5.2
Relationship between Operation Frequency and Number of Wait States
Bit
STS3
STS2
STS1
STS0
Number of
Wait States
0
0
0
0
0
0
0
1
0
0
1
0
0
0
Operation Frequency
20 MHz 16 MHz 10 MHz 8 MHz
4 MHz
16 states
0.00
0.00
0.00
0.00
0.00
32 states
0.00
0.00
0.00
0.00
0.01
0
64 states
0.00
0.00
0.01
0.01
0.02
1
1
128 states
0.01
0.01
0.01
0.02
0.03
1
0
0
256 states
0.01
0.02
0.03
0.03
0.06
0
1
0
1
512 states
0.03
0.03
0.05
0.06
0.13
0
1
1
0
1024 states
0.05
0.06
0.10
0.13
0.26
0
1
1
1
2048 states
0.10
0.13
0.20
0.26
0.51
1
0
0
0
4096 states
0.20
0.26
0.41
0.51
1.02
1
0
0
1
8192 states
0.41
0.51
0.82
1.02
2.05
1
0
1
0
16384 states
0.82
1.02
1.64
2.05
4.10
1
0
1
1
32768 states
1.64
2.05
3.28
4.10
8.19
1
1
0
0
65536 states
3.28
4.10
6.55
8.19
16.38
1
1
0
1
131072 states 6.55
8.19
13.11
16.38
32.77
1
1
1
0
262144 states 13.11
16.38
26.21
32.77
65.54
1
1
1
1
Reserved




5.2.7

High-Speed OCO Control Register (HOCR)
Address: H'FF062A
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
HOCOE







0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
HOCOE
High-speed
OCO enable
0: The high-speed OCO is not used (standby state).
R/W
Reserved
These bits are read as 0. The write value should be 0.
6 to 0

1: The high-speed OCO is used.

• HOCOE bit (high-speed OCO enable)
Controls operation of the high-speed OCO.
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Section 5 Clock Pulse Generator
5.2.8
High-Speed OCO Trimming Data Protect Register (HOTRMDPR)
Address: H'FF062B
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
WI
WE
LOCKDW
TRMDRWE




1
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
WI
Write inhibit
0: Writing is permitted.
W
1: Writing is inhibited.
6
WE
Write enable 0: Writing is disabled.
R/W
1: Writing is enabled.
[Setting condition]
When 0 is written to WI and 1 is written to WE at the
same time.
[Clearing condition]
When 0 is written to WI and WE at the same time.
5
LOCKDW
Trimming
0: HOTRMDR1 can be written to.
data register 1: HOTRMDR1 cannot be written to.
lock down
[Setting condition]
R/W
When 0 is written to WI and 1 is written to LOCKDW
while WE is 1.
[Clearing condition]
Reset.
4
TRMDRWE
Trimming
0: Writing to HOTRMDR1 is prohibited.
data register 1: Writing to HOTRMDR1 is permitted.
write enable
[Setting condition]
R/W
When 0 is written to WI and 1 is written to TRMDRWE
while WE is 1.
[Clearing condition]
When 0 is written to WI and TRMDRWE while WE is 1.
3 to 0 
Note:
Reserved
These bits are read as 0. The write value should be 0. 
A MOV instruction should be used to write to this register.
Rev. 1.00 Oct. 03, 2008 Page 122 of 962
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Section 5 Clock Pulse Generator
• WI bit (write inhibit)
This register can be written to only when this bit is 0. This bit is always read as 1.
• WE bit (write enable)
Bits 5 and 4 in this register can be written to when this bit is 1.
• LOCKDW bit (trimming data register lock down)
HOTRMDR1 cannot be written to when this bit is 1. Once this bit is set to 1, writing to
HOTRMDR1 is prohibited, even if 0 is written to this bit, until a reset is applied.
• TRMDRWE bit (trimming data register write enable)
Writing to HOTRMDR1 is enabled when LOCKDW is 0 and TRMDRWE is 1.
5.2.9
High-Speed OCO Trimming Data Register 1 (HOTRMDR1)
Address: H'FF062C
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
Undefined
Undefined
Undefined
HOTRMDR1[7:0]
Value after reset:
Undefined
Undefined
Undefined
Undefined
Undefined
Bit
Symbol
Bit Name
Description
R/W
7 to 0
HOTRMDR1
[7:0]
Trimming
data 1
High-speed OCO frequency trimming data (40 MHz)
R/W
• HOTRMDR17 bit to HOTRMDR10 bit (trimming data 17 to 10)
Immediately after a reset, trimming data that produces a 40-MHz oscillation is loaded into the
LSI, and the data is written to this register. Reading these bits yields an undefined value.
If this register is to be used for timing a 32-MHz oscillation, before setting the HOCOE bit in
HOCR to 1, write the value stored in HOTRMDR3 into HOTRMDR1.
By rewriting bits 7 to 0 of this register, the high-speed OCO can be trimmed to the desired
frequency. When these bits are rewritten, the oscillator frequency of the high-speed OCO is
modified after the oscillation has become stable.
The frequency changes as follows:
B'00000000 (minimum frequency) → B'11111111 (maximum frequency)
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Section 5 Clock Pulse Generator
5.2.10
High-Speed OCO Trimming Data Register 2 (HOTRMDR2)
Address: H'FF062D
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
Undefined
Undefined
Undefined
HOTRMDR2[7:0]
Value after reset:
Undefined
Undefined
Undefined
Undefined
Undefined
Bit
Symbol
Bit Name
Description
R/W
7 to 0
HOTRMDR2
[7:0]
Trimming
data 2
High-speed OCO frequency trimming data (40 MHz)
R/W
Note:
Bit 7 should not be modified when the frequency is trimmed to a desired frequency.
• HOTRMDR27 bit to HOTRMDR20 bit (trimming data 27 to 20)
Immediately after a reset, trimming data that produces a 40-MHz oscillation is loaded into the
LSI, and the data is written to this register. Reading these bits yields an undefined value.
If this register is to be used for timing a 32-MHz oscillation, before setting the HOCOE bit in
HOCR to 1, write the value stored in HOTRMDR4 into HOTRMDR2.
5.2.11
High-Speed OCO Trimming Data Register 3 (HOTRMDR3)
Address: H'FF062E
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
Undefined
Undefined
Undefined
HOTRMDR3[7:0]
Value after reset:
Undefined
Undefined
Undefined
Bit Name
Undefined
Undefined
Bit
Symbol
Description
R/W
7 to 0
HOTRMDR3 Trimming
[7:0]
data 3
High-speed OCO frequency trimming data (32 MHz)
R/W
Note:
Bit 7 should not be modified when the frequency is trimmed to a desired frequency.
• HOTRMDR37 bit to HOTRMDR30 bit (trimming data 37 to 30)
Immediately after a reset, trimming data that produces a 32-MHz oscillation is loaded into the
LSI, and the data is written to this register. Reading these bits yields an undefined value.
If 32-MHz oscillation is required then before setting the HOCOE bit in HOCR to 1, copy the
value stored in this register to HOTRMDR1.
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Section 5 Clock Pulse Generator
5.2.12
High-Speed OCO Trimming Data Register 4 (HOTRMDR4)
Address: H'FF062F
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
Undefined
Undefined
Undefined
HOTRMDR4[7:0]
Value after reset:
Undefined
Undefined
Undefined
Undefined
Undefined
Bit
Symbol
Bit Name
Description
R/W
7 to 0
HOTRMDR4
[7:0]
Trimming
data 4
High-speed OCO frequency trimming data (32 MHz) R/W
Note:
Bit 7 should not be modified when the frequency is trimmed to a desired frequency.
• HOTRMDR47 bit to HOTRMDR40 bit (trimming data 47 to 40)
Immediately after a reset, trimming data that produces a 32-MHz oscillation is loaded into the
LSI, and the data is written to this register. Reading these bits yields an undefined value.
If 32-MHz oscillation is required, then before setting the HOCOE bit in HOCR to 1, copy the
value stored in this register to HOTRMDR2.
Rev. 1.00 Oct. 03, 2008 Page 125 of 962
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Section 5 Clock Pulse Generator
5.3
Operation of Selection of System Base Clock
After a reset, this LSI enters active mode operating in low-speed clocks. The user, by means of
software, can change the system base clock from a low-speed OCO clock to a high-speed OCO
clock, the main oscillator clock, or a sub-oscillator clock.
Figure 5.2 shows a transition diagram between system base clock states. Table 5.3 shows
conditions under which clock sources can be switched.
Reset state
Reset released
Operation at
low-speed OCO clock
PHIBSEL=0
PHIHSEL=X
PHILSEL=0
Operation at
high-speed OCO clock
PHIBSEL=1
PHIHSEL=0
PHILSEL=X
Operation at sub-clock
PHIBSEL=0
PHIHSEL=X
PHILSEL=1
Operation at
main oscillator clock
PHIBSEL=1
PHIHSEL=1
PHILSEL=X
The LSI operates on φlow.
The LSI operates on φhigh.
[Legend]
X: Don't care
Figure 5.2 Transition Diagram between LSI System Base Clock States
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Section 5 Clock Pulse Generator
Table 5.3
Clock Source Switching
Bit
PHIBSEL
PHIHSEL
PHILSEL
Switching Operation
0
Don't care
0→1
φloco → φsub
0
Don't care
1→0
φsub → φloco
1
0→1
Don't care
φhoco → φosc
1
1→0
Don't care
φosc → φhoco
0→1
0
0
φloco → φhoco
1→0
0
0
φhoco → φloco
0→1
0
1
φsub → φhoco
1→0
0
1
φhoco → φsub
0→1
1
0
φhoco → φosc
1→0
1
0
φosc → φhoco
0→1
1
1
φsub → φosc
1→0
1
1
φosc → φsub
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Section 5 Clock Pulse Generator
Table 5.4 shows the high-speed OCO, low-speed OCO, main oscillator, and sub-oscillator
operation states in each operating mode (system state).
Table 5.4
Clock Operation States in Each Operating Mode
System State
Main
Oscillator
State
Low-Speed
OCO State
Sub-Oscillator
State
Stopped
Stopped
Oscillating
Oscillating*
φhoco
Oscillating
Depending on
user setting*2
Oscillating
φosc
Depending on
user setting*1
Depending on
user setting*3
Oscillating
φloco
Depending on
1
user setting*
Depending on
user setting*2
Oscillating
φsub
Depending on
user setting*1
Depending on
user setting*2
Oscillating
Stopped
Stopped
Oscillating
High-Speed
System Clock OCO Sate
Reset released φloco
Active mode,
sleep mode
Standby mode None
4
Notes: 1. Can be set with the HOCOE bit in HOCR.
2. Can be set with the PMRJ[1:0] bits in PMRJ.
3. Backup operation is performed by selecting the oscillation stop with the PMRJ[1:0] bits
in PMRJ when the backup function is enabled.
4. A crystal resonator should be connected when a sub-oscillator clock is used. To switch
the system base clock to φsub immediately after the power-on, oscillation settling time
for the sub-oscillator should be ensured.
Rev. 1.00 Oct. 03, 2008 Page 128 of 962
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Section 5 Clock Pulse Generator
5.3.1
Switching System Base Clock to φhoco
Figure 5.3 shows a flowchart of the process in which the LSI automatically ensures oscillation
settling time for the high-speed OCO and switches from φloco to a high-speed OCO. Figure 5.4
shows a flowchart of the process in which a user ensures high-speed OCO settling time and
switches from φloco to a high-speed OCO.
The LSI operates at the low-speed OCO clock.
Start (Reset)
[1] Setting PHIBSEL to 1 switches
φbase from φlow to φhigh.
Set PHIBSEL in LPCR1 to 1.
[1]
The LSI stops and waits for
high-speed OCO oscillation
settling time.
[2]
[2] φhoco is used for counting during
oscillation setting time.
The LSI stops operation until
oscillation is stable.
The LSI operates at the high-speed OCO clock.
The LSI operates at
high-speed OCO clock.
Figure 5.3 Flowchart for Automatically Ensuring Oscillation Settling Time and Switching
from φloco to High-Speed OCO
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Section 5 Clock Pulse Generator
The LSI operates at the low-speed OCO clock.
[1]Setting HOCOE to 1 starts the
high-speed OCO oscillation.
Start (Reset)
Set HOCOE in HOCR to 1.
Wait for the high-speed OCO
settling time (T.B.D µs or more).
Set PHIBSEL in LPCR1 to 1.
[1]
[2]At least T.B.D µs of wait time should
be ensured for a stable oscillation.
[2]
[3]Setting PHIBSEL to 1 switches
φbase from φlow to φhigh.
[3]
The LSI operates at the high-speed OCO clock.
The LSI operates at the
high-speed OCO clock.
Figure 5.4 Flowchart for Ensuring Oscillation Settling Time by User and Switching from
φloco to High-Speed OCO
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Section 5 Clock Pulse Generator
5.3.2
Switching System Base Clock to φosc
Figure 5.5 shows a flowchart of the process in which the system base clock is switched from φloco
to φosc.
The LSI operates at the low-speed OCO clock.
Start (Reset)
[1]
[1] Set at least 6.5 ms of oscillation
settling time according
to the oscillation frequency.
[2] Set the PJ1 and PJ0 pins to
oscillation pins.
[3] Setting PHIBSEL to 1 switches
φhigh from φhoco to φosc.
Set PMRJ[1:0] in PMJR.
[2]
[4] Setting PHIBSEL to 1 switches
φbase from φlow to φhigh.
Set PHIHSEL in SYSCCR to 1.
[3]
Set PHIBSEL in LPCR1 to 1.
[4]
Set oscillation settling time
with STS[3:0] in OSCCSR.
LSI operation is stopped over the
stabilization period of the main
oscillator.
[5] Counting is driven by φosc during
the oscillation settling time.
LSI operation is stopped until
oscillation is stable.
[5]
LSI operation is driven by the main oscillator clock.
LSI operation is driven by the
main oscillator clock.
Figure 5.5 Flowchart of Clock Switching from φloco to φosc
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Section 5 Clock Pulse Generator
5.3.3
(1)
Clock Change Timing
Switching Division Ratio for the Same Clock Source
Figure 5.6 shows a division ratio switching timing chart for the same clock source.
φbase
PHI[2:0]
000 (divided by 1)
010 (divided by 4)
001 (divided by 2)
φ
Figure 5.6 Timing of Division Ratio Switching for the Same Clock Source
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Section 5 Clock Pulse Generator
(2)
Switching System Base Clock Source
Figures 5.7 and 5.8 show clock source switching timing charts for the system base clock.
CLKA
CLKB
SELA
SELB
φbase
Operation at CLKA
Clock
switching
time
Operation at CLKB
Clock
switching
time
Operation at CLKA
[Legend]
CLKA: Clock A
CLKB: Clock B
SELA: CLKA select signal
SELB: CLKB select signal
φbase: System base clock
Note: Clock switching time is a period from the clock select signal change to the second high level of the destination clock.
Figure 5.7 Timing of Clock Source Switching
(When the switching destination clock source is active)
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Section 5 Clock Pulse Generator
CLKA
CLKB
SELA
SELB
φbase
Operation at CLKA
Oscillation settling wait time
Operation at CLKB
[Legend]
CLKA: Clock A
CLKB: Clock B
SELA: CLKA select signal
SELB: CLKB select signal
φbase: System base clock
Note: The oscillation settling time differs according to the clock source.
Figure 5.8 Timing of Clock Source Switching
(When the switching destination clock source is stopped)
Oscillation stabilization wait time varies with switching destination clock sources. If the
destination clock is φosc, wait time is specified by the STS[3:0] bit of the OSCCSR. For
oscillation stabilization wait time values, see table 5.2. If the destination clock is φhoco, wait time
is automatically fixed to approximately TBD us.
During oscillation stabilization wait time, the φbase stops; therefore, any module that operates
with the φbase as a base, including the bus master, stops. The register retains the pre-switching
value.
Rev. 1.00 Oct. 03, 2008 Page 134 of 962
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Section 5 Clock Pulse Generator
5.3.4
Backup Operation
If the operating clock for the system is φosc and the backup function is enabled, when the main
oscillator detects an oscillation halt condition, the system clock automatically switches to either
φhoco or φlow, according to BAKCKSEL in BAKCR. The period from the stopping of the main
oscillator to the time the system clock is operating from φhoco or φlow will be clock halt detection
time + oscillation stabilization wait time for the backup clock. Time to wait for oscillation
stabilization is 0 ms if the target backup clock is already oscillating when stopping of the main
oscillator is detected.
To reduce power consumption, it is also possible to set the target backup clock to a stopped state
when the backup function is enabled. In that case, the target backup clock is automatically
activated when stopping of the main clock oscillator is detected. The system clock is then changed
after a certain amount of oscillation settling time (approximately T.B.D. µs in the case of φhoco).
This LSI circuit may malfunction during operation with the back-up function. Accordingly, usage
with the watchdog timer is recommended.
φOSC
OSCHLT
BAKCLK
φbase
Operation at main oscillator clock
φOSC stops
Clock switching
time
Operation at backup destination clock
[Legend]
φOSC: Main oscillator clock
OSCHLT: Main oscillator clock stop detection signal
BAKCLK: Backup destination clock
φbase: System base clock
Figure 5.9 Timing of Backup Operation When Main Oscillator Stops at High Level
(When the backup destination clock is active)
Rev. 1.00 Oct. 03, 2008 Page 135 of 962
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Section 5 Clock Pulse Generator
φOSC
OSCHLT
BAKCLK
φbase
Operation at main oscillator clock
φOSC stops
Clock
switching
time
Operation at backup destination clock
[Legend]
φOSC: Main oscillator clock
OSCHLT: Main oscillator clock stop detection signal
BAKCLK: Backup destination clock
φbase: System base clock
Figure 5.10 Timing of Backup Operation When Main Oscillator Stops at Low Level
(When the backup destination clock is active)
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Section 5 Clock Pulse Generator
φOSC
OSCHLT
BAKCLK
φbase
Operation at main oscillator clock
φOSC stops.
Oscillation
settling time
Clock
switching
time
Operation at backup
destination clock
[Legend]
φOSC: Main oscillator clock
OSCHLT: Main oscillator clock stop detection signal
BAKCLK: Backup destination clock
φbase: System base clock
Figure 5.11 Timing of Backup Operation When Main Oscillator Stops at High Level
(When the backup destination clock is stopped)
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Section 5 Clock Pulse Generator
φOSC
OSCHLT
BAKCLK
φbase
Operation at main oscillator clock
φOSC stops.
Oscillation
settling time
Clock
switching
time
Operation at backup destination clock
[Legend]
φOSC: Main oscillator clock
OSCHLT: Main oscillator clock stop detection signal
BAKCLK: Backup destination clock
φbase: System base clock
Figure 5.12 Timing of Backup Operation When Main Oscillator Stops at Low Level
(When the backup destination clock is stopped)
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Section 5 Clock Pulse Generator
5.4
High-Speed On-Chip Oscillator
5.4.1
Procedures for Switching to 32MHz
After release from a reset, the high-speed OCO is trimmed so that it will oscillate at 40 MHz.
Figure 5.13 shows a flowchart for the switching of the oscillation frequency of the high-speed
OCO to 32 MHz. Frequencies should be changed when the high-speed OCO is at reset.
Start
Read HOTRMDR3.
[1]
Write the HOTRMDR3 value
to HOTRMDR1.
Read HOTRMDR4.
[2]
Write the HOTRMDR4 value
to HOTRMDR2.
[3]
Set HOCOE in HOCR to 1.
[1] Write the 32-MHz trimming value
in HOTRMDR3 to HOTRMDR1.
[2] Write 32-MHz trimming value
in HOTRMDR4 to HOTRMDR2.
[3] Set the HOCOE bit in HOCR to 1
to enable the high-speed OCO.
End
Figure 5.13 Flowchart for Switching High-Speed OCO Frequency to 32 MHz
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Section 5 Clock Pulse Generator
5.4.2
Trimming of High-Speed OCO
Users can trim the on-chip oscillator frequency, supplying the external reference pulses with the
input capture function in the on-chip timer. An example of trimming flow using timer RC and a
timing chart are shown in figures 5.14 and 5.15, respectively. Because HOTRMDR1 is initialized
by a reset, when users have trimmed the oscillators, some operations after a reset are necessary,
such as trimming it again or saving the trimming value in an external device for later reloading.
Start
Set timer RC
GRA: Input capture
GRC: GRA buffer
Set bit7 to bit0 in HOTRMDR1
to 0.
Supply reference pulse
to P30/FTIOA.
Capture 1
Capture 2
Modify HOTRMDR1*.
Frequency calculation
No
Desired frequency?
Yes
End
Note: Compare the measured frequency and desired frequency, and
determine the HOTRMDR1 value, bit by bit, from the MSB.
Figure 5.14 Example of Flow for Trimming High-Speed OCO Frequency
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Section 5 Clock Pulse Generator
φ40
FTIOA input capture
input
tA (µs)
Timer RC
TRCCNT
GRA
M-1
M
M+α
M+1
N
GRC
M+α
M
N
M
Capture 1
Capture 2
Figure 5.15 Timing Chart of Trimming of High-Speed OCO Frequency
The high-speed OCO frequency is obtained by the expression below. Since the input-capture input
is sampled at the rate of the high-speed OCO, the calculated result includes a sampling error of ±1
clock cycle.
Foco =
(M + α) - M
tA
(MHz)
Foco = High-speed OCO frequency
tA = Cycle of base clock (us)
M = Timer RC counter value
Note: For the H8S/20203 and H8S/20223 groups, timer RD should be used instead of timer RC.
Rev. 1.00 Oct. 03, 2008 Page 141 of 962
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Section 5 Clock Pulse Generator
5.5
Main Clock Oscillator
This LSI has two methods to supply external clock pulses into it: connecting a crystal or ceramic
resonator, and an external clock. For setting the oscillation pins PJ0/OSC1 and
PJ1/OSC2/CLKOUT to resonator pins or an external clock input pin, see section 10.10.1, Port
Mode Register J (PMRJ). Figure 5.16 shows a block diagram of the Main clock oscillator.
OSC2
STBY
OSC1
[Legend]
STBY: Standby mode
Figure 5.16 Block Diagram of Main Clock Oscillator
5.5.1
Connecting Crystal Resonator
Figure 5.17 shows an example of connecting a crystal resonator. An AT-cut parallel-resonance
crystal resonator should be used. A damping resistor Rd should be added, if necessary. Since the
resistor values vary depending on the resonator, use values recommended by the resonator
manufacturer.
C1
PJ0/OSC1
C2
PJ1/OSC2/CLKOUT
C1 = C2 = 10 to 22 pF
Rd
Figure 5.17 Example of Connection to Crystal Resonator
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Section 5 Clock Pulse Generator
5.5.2
Connecting Ceramic Resonator
Figure 5.18 shows an example of connecting a ceramic resonator. A damping resistor Rd should
be added, if necessary. Since the resistor values vary depending on the resonator, use values
recommended by the resonator manufacturer.
C1
PJ0/OSC1
C2
PJ1/OSC2/CLKOUT
C1 = C2 = 5 to 30 pF
Rd
Figure 5.18 Example of Connection to Ceramic Resonator
5.5.3
External Clock Input Method
To use the external clock, input the external clock on pin OSC1. Figure 5.19 shows an example of
connection. The duty cycle of the external clock signal must be 45 to 55%.
PJ0/OSC1
PJ1/OSC2/CLKOUT
External clock input
Open
Figure 5.19 Example of External Clock Input
Note: To input the external clock, set the PMRJ[1:0] bits to 01. Do not input the external clock
while PMRJ[1:0] bits are set to 11.
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Section 5 Clock Pulse Generator
5.6
Subclock Generator
Figure 5.20 shows a block diagram of the subclock generator.
X2
X1
Figure 5.20 Block Diagram of Subclock Generator
5.6.1
Connecting 32.768-kHz Crystal Resonator
Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystal
resonator, as shown in figure 5.21. A damping resistor Rd should be added, if necessary. Since the
resistor values vary depending on the resonator, use values recommended by the resonator
manufacturer.
C1
X1
C2
X2
C1 = C2 = 15 pF (typ.)
Rd
Figure 5.21 Typical Connection to 32.768-kHz Crystal Resonator
5.6.2
Pin Connection when not Using Subclock
When the subclock is not used, connect pin X1 to VSS and leave pin X2 open, as shown in figure
5.22.
X1
VSS
X2
Open
Figure 5.22 Pin Connection when not Using Subclock
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Section 5 Clock Pulse Generator
5.7
Prescaler
The prescaler is a 13-bit counter using the system clock (φ) as its input clock. The outputs, which
are divided clocks, are used as internal clocks by the on-chip peripheral modules. The prescaler is
initialized to H'0000 and stops counting after a reset. It starts counting when the PSCSTP bit in
LPCR1 is cleared. The prescaler counter cannot be accessed by the CPU.
The outputs from the prescaler is shared by the on-chip peripheral modules. The division ratio can
be set separately for each on-chip peripheral module. The clock input to the prescaler is a system
clock with the division ratio specified by bits PHI2 to PHI0 in LPCR2.
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Section 5 Clock Pulse Generator
5.8
Usage Notes
5.8.1
Note on Resonators
Resonator characteristics are closely related to board design and should be carefully evaluated by
the user, referring to the examples shown in this section. Resonator circuit parameters will differ
depending on the resonator element, stray capacitance of the PCB, and other factors. Suitable
values should be determined in consultation with the resonator element manufacturer. Design the
circuit so that the resonator element never receives voltages exceeding its maximum rating.
5.8.2
Notes on Board Design
When using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as
close as possible to pins OSC1 and OSC2. Other signal lines should be routed away from the
oscillator circuit to prevent induction from interfering with correct oscillation (see figure 5.23).
Prohibited
Signal A
Signal B
C1
PJ0/OSC1
C2
PJ1/OSC2/CLKOUT
Figure 5.23 Example of Incorrect Board Design
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Section 6 Power-Down Modes
Section 6 Power-Down Modes
In addition to normal active mode, this LSI can enter either of the two power-down modes after
release from a reset, in which power consumption is reduced. As other measures for reduced
power consumption, this LSI also has a bus-master-clock division function for the low-speedoperation of bus masters, module standby function which allows the selective stopping of on-chip
peripheral modules, and a PSC-divider stopping function. Further power consumption is possible
by selecting the low-speed on-chip oscillator clock φloco, or sub-oscillator clock φsub as the
source of the system clock φ to operate the LSI at a low speed. After release from a reset, all of the
peripheral functions except timer RE are in the module standby state. Make the settings for the
operation of module in the corresponding registers after the module standby state is released.
• Active Mode
The CPU and on-chip peripheral modules operate on the system clock φ. The system clock
frequency can be selected from among φbase to φbase/128, where φbase is the system base
clock.
• Sleep Mode
The CPU is stopped. On-chip peripheral modules operate on the system clock φ.
• Standby Mode
The CPU and all the on-chip peripheral modules are stopped. However, timer RE (TMRE) can
operate when the realtime clock mode is selected. The watchdog timer (WDT) also operates
when the low-speed OCO is selected as the WDT clock source.
• Bus Master Clock Division Function
For the bus masters CPU and DTC, ROM, and RAM, the operating clock φs can be divided
independently of the clock supplied to the peripheral modules. The bus master clock φs can be
selected from among φ to φ/32.
• PSC Divider Stop Function
The PSC divider can be stopped through software setting. Specifically, the peripheral modules
using φ/2 to φ/8192 are stopped (register values are retained), whereas the ones using φ remain
operating.
• Module Standby Function
Power consumption can be reduced by halting individual on-chip peripheral modules that are
not in use.
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Section 6 Power-Down Modes
6.1
Register Descriptions
The registers related to power-down modes are listed below.
•
•
•
•
•
•
Power-down control register 1 (LPCR1)
Power-down control register 2 (LPCR2)
Power-down control register 3 (LPCR3)
Module standby control register 1 (MSTCR1)
Module standby control register 2 (MSTCR2)
Module standby control register 3 (MSTCR3)
6.1.1
Power-Down Control Registers 1, 2, and 3 (LPCR1, LPCR2, LPCR3)
LPCR1, LPCR2, and LPCR3 control power-down modes. For details, see section 5, Clock Pulse
Generator.
6.1.2
Module Standby Control Register 1 (MSTCR1)
Address: H'FFFFDC
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
MSTWDT

MSTAD1
MSTAD2
MSTDA
MSTDTC


1
1
1
1
1
1
1
1
Value after reset:
Bit
Symbol
Bit Name
7
MSTWDT
Watchdog timer 0: Operating state
module standby 1: Standby state
R/W
6

Reserved
This bit is read as 0. The write value should be 0.

5
MSTAD1
A/D converter
unit 1 module
standby
0: Operating state
R/W
A/D converter
unit 2 module
standby*
0: Operating state
4
3
MSTAD2
MSTDA
R/W
1: Standby state
R/W
1: Standby state
D/A converter 0: Operating state
module standby 1: Standby state
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Description
R/W
Section 6 Power-Down Modes
Bit
Symbol
Bit Name
Description
R/W
2
MSTDTC
DTC module
standby
0: Operating state
R/W
Reserved
These bits are read as 0. The write value should be 0. 
1, 0

Notes: *
1: Standby state
When a peripheral module is in the module standby state, the registers of the module
cannot be accessed.
• MSTWDT bit (watchdog timer module standby)
When this bit is set to 1, the WDT enters the standby state. Note that if the low-speed OCO is
selected as the WDT count clock, the WDT operates regardless of the setting of this bit but the
WDT registers cannot be accessed.
• MSTAD1 bit (A/D converter unit 1 module standby)
When this bit is set to 1, A/D converter unit 1 enters the standby state.
• MSTAD2 bit (A/D converter unit 2 module standby)
When this bit is set to 1, A/D converter unit 2 enters the standby state.
A/D converter unit 2 is not available on the H8S/20103 and H8S/20203 groups; this bit is
reserved on these devices. For a write-access, write 1 to this bit.
• MSTDA bit (D/A converter module standby)
When this bit is set to 1, the D/A converter enters the standby state.
• MSTDTC bit (DTC module standby)
When this bit is set to 1, the DTC enters the standby state.
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Section 6 Power-Down Modes
6.1.3
Module Standby Control Register 2 (MSTCR2)
Address: H'FFFFDD
Bit:
b7
b6
b5
MSTSCI3_1 MSTSCI3_2 MSTSCI3_3
Value after reset:
1
1
Bit Name
1
b4
b3
b2
b1
b0


MSTICSU


1
1
1
1
1
Bit
Symbol
Description
7
MSTSCI3_1 SCI3 channel 1 0: Operating state
module standby 1: Standby state
R/W
6
MSTSCI3_2 SCI3 channel 2 0: Operating state
module standby 1: Standby state
R/W
5
MSTSCI3_3 SCI3 channel 3 0: Operating state
module standby 1: Standby state
R/W
4, 3

Reserved

2
MSTICSU
IIC2/SSU
0: Operating state
module standby 1: Standby state
R/W
1, 0

Reserved

These bits are read as 1. The write value should
be 1.
These bits are read as 1. The write value should
be 1.
R/W
Notes: 1. When a peripheral module is in the module standby state, the registers of the module
cannot be accessed.
2. When writing to this register, write 1s to the reserved bits.
• MSTSCI3_1 (SCI3 channel 1 module standby)
When this bit is set to 1, SCI3 channel 1 enters the standby state.
• MSTSCI3_2 (SCI3 channel 2 module standby)
When this bit is set to 1, SCI3 channel 2 enters the standby state.
• MSTSCI3_3 (SCI3 channel 3 module standby)
When this bit is set to 1, SCI3 channel 3 enters the standby state.
• MSTICSU (IIC2/SSU module standby)
When this bit is set to 1, the IIC2 or SSU enters the standby state.
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Section 6 Power-Down Modes
6.1.4
Module Standby Control Register 3 (MSTCR3)
Address: H'FFFFDE
Bit:
b7
b6
b5
MSTTMRA
MSTTMRB
MSTTMRC
1
1
1
Value after reset:
b4
b3
b2
MSTTMRD1 MSTTMRD2 MSTTMRG
1
1
1
b1
b0

MSTTMRE
1
0
Bit
Symbol
Bit Name
Description
R/W
7
MSTTMRA
Timer RA
0: Operating state
module standby 1: Standby state
R/W
6
MSTTMRB
Timer RB
0: Operating state
module standby 1: Standby state
R/W
5
MSTTMRC Timer RC
0: Operating state
module standby 1: Standby state
R/W
4
MSTTMRD1 Timer RD unit 0 0: Operating state
module standby 1: Standby state
R/W
3
MSTTMRD2 Timer RD unit 1 0: Operating state
module standby 1: Standby state
R/W
2
MSTTMRG Timer RG
0: Operating state
module standby 1: Standby state
R/W
1

Reserved

0
MSTTMRE
Timer RE
0: Operating state
module standby 1: Standby state
This bit is read as 1. The write value should be 1.
R/W
Notes: 1. When a peripheral module is in the module standby state, the registers of the module
cannot be accessed.
2. When writing to this register, write 1s to the reserved bits.
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Section 6 Power-Down Modes
• MSTTMRA bit (timer RA module standby)
When this bit is set to 1, timer RA enters the standby state.
• MSTTMRB bit (timer RB module standby)
When this bit is set to 1, timer RB enters the standby state.
• MSTTMRC bit (timer RC module standby)
When this bit is set to 1, timer RC enters the standby state.
Timer RC is not available on the H8S/20203 and H8S/20223 groups; this bit is reserved on
these devices. For a write-access, write 1 to this bit.
• MSTTMRD1 bit (timer RD unit 0 module standby)
When this bit is set to 1, timer RD unit 0 enters the standby state.
• MSTTMRD2 bit (timer RD unit 1 module standby)
When this bit is set to 1, timer RD unit 1 enters the standby state.
Timer RD unit 1 is not available on the H8S/20103 group; this bit is reserved on the device.
For a write-access, write 1 to this bit.
• MSTTMRG bit (timer RG module standby)
When this bit is set to 1, timer RG enters the standby state.
• MSTTMRE bit (timer RE module standby)
When this bit is set to 1, timer RE enters the standby state. Note that if the φsub is selected as
the count clock in realtime clock mode or output-compare mode, timer RE operates regardless
of the setting of this bit but the timer RE registers cannot be accessed.
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Section 6 Power-Down Modes
6.2
Mode Transitions and States of LSI
Figure 6.1 shows the possible transitions among the operating modes. SLEEP instructions are used
to cause a transition from the program execution state to the program halt state. Interrupts are used
to return from the program halt state to the program execution state. When the RES pin is driven
low or any other internal reset occurs, this LSI is placed in the reset state from any mode. After
release from a reset, this LSI is placed in active mode.
Reset state
Operating clock: φloco
Program stop state
Peripheral functions
unavailable
SSBY = 1
SLEEP instruction
Standby mode
Program execution
state
SSBY = 0
SLEEP instruction
Active mode
Interrupt
Program halt state
Peripheral functions
available
Sleep mode
Interrupt
Selectable clock sources:
φhoco
φosc
φloco
φsub
Figure 6.1 Mode Transition Diagram
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Section 6 Power-Down Modes
Table 6.1 shows the internal states of the LSI in each mode.
Table 6.1
Internal State in Each Operating Mode
LPCR1
PSCSTP = 0
LPCR1
PSCSTP = 1
Function
Active Mode Sleep Mode Active Mode Sleep Mode Standby Mode
System clock
Functioning
Functioning Functioning
Functioning
Stopped
CPU
Instruction
execution
Functioning
Stopped
Functioning
Stopped
Stopped
Registers
Functioning
Retained
Functioning
Retained
Retained
Functioning
Functioning Functioning
DTC
Functioning
1
Stopped
1
ELC
Functioning
Functioning Functioning* Functioning* Retained
RAM
Functioning
Functioning Functioning
Functioning
Retained
I/O ports
Functioning
Functioning Functioning
Functioning
Register
contents are
retained, but
output goes to
the highimpedance
state.
Functioning
Functioning Functioning
Functioning
Functioning
Functioning Retained*2
Retained*2
Retained
External
interrupts
IRQ7 to
IRQ0, NMI
Peripheral Timer RA, Functioning
modules timer RB,
timer RC,
timer RD_0,
timer RD_1
Timer RE
Functioning
Functioning Functioning in realtime
clock mode and retained in
output-compare mode.
Functioning
Timer RG
Functioning
Functioning Retained*2
Retained*2
Retained
Watchdog
timer
Functioning
3
Functioning Retained*
3
Retained*
Retained*3
SCI3_1,
SCI3_2,
SCI3_3
Functioning
Functioning Retained*2
Retained*2
Reset
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Section 6 Power-Down Modes
LPCR1
PSCSTP = 0
Function
LPCR1
PSCSTP = 1
Active Mode Sleep Mode Active Mode Sleep Mode Standby Mode
Peripheral IIC2/SSU
Functioning
modules A/D
Functioning
converter_1,
A/D
converter_2
D/A
converter
Functioning
Functioning Retained
Functioning Retained*
Retained
4
Functioning Functioning
Reset
4
Retained*
Reset
Functioning Reset
Notes: 1. The timers are stopped if φ/2 to φ/8192 is selected as the clock source of the eventgeneration timer.
2. The timers operate if φ is selected as the count clock. The timers are stopped if φ/2 to
φ/8192 is selected as the count clock.
3. The WDT operates if the low-speed OCO is selected as its clock source.
4. The A/D converters operate when A/D conversion time = 43 states (max) is selected.
The A/D converters are retained when the other conversion time is set.
6.2.1
Active Mode
In active mode, the CPU, DTC, and all the on-chip peripheral modules operate on the system
clock φ. The system clock frequency can be selected from among φbase, φbase/2, φbase/4,
φbase/8, φbase/16, φbase/32, φbase/64, and φbase/128 according to the PHI[2:0] setting in LPCR2.
6.2.2
Sleep Mode
When a SLEEP instruction is executed in active mode with the SSBY bit = 0 in LPCR1, a
transition to sleep mode is made. In sleep mode, the CPU is stopped but the DTC and all the onchip peripheral modules operate on the system clock. CPU register contents are retained.
When an interrupt is requested, sleep mode is canceled causing a transition to active mode and
interrupt exception handling starts. Sleep mode cannot be canceled if the I bit in CCR is 1 or the
requested interrupt is masked by the interrupt enable bit. After sleep mode is canceled, the highspeed or low-speed clock is selected as the system clock source depending on the SLEEPRS bit
setting in LPCR1.
When the RES pin is driven low or any other internal reset occurs, sleep mode is canceled causing
a transition to the reset state.
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Section 6 Power-Down Modes
6.2.3
Standby Mode
When a SLEEP instruction is executed in active mode with the SSBY bit = 1 in LPCR1, a
transition to standby mode is made. In standby mode, clock oscillation is stopped and thus the
CPU, DTC, and all the on-chip peripheral modules (except timer RE and WDT) are stopped.
However, as long as the rated voltage is supplied, the following contents are retained: the CPU
registers, the registers of some on-chip peripheral modules, and on-chip RAM. Additionally, onchip RAM contents will be retained as long as the voltage rated as the RAM data retention voltage
is provided. The I/O ports go to the high-impedance state.
When an interrupt is requested, standby mode is canceled causing a transition to active mode and
interrupt exception handling starts. Standby mode cannot be canceled if the I bit in CCR is 1 or the
requested interrupt is masked by the interrupt enable bit. After standby mode is canceled, the highspeed or low-speed clock is selected as the system clock source depending on the STBYRS bit
setting in LPCR1.
When the RES pin is driven low or any other internal reset occurs, standby mode is canceled
causing a transition to the reset state.
6.3
Bus Master Clock Division Function
In active or sleep mode, the operating clock for the CPU, DTC, on-chip ROM, and on-chip RAM
can be divided independently of the clock supplied to the peripheral modules. Using a divided
clock can reduce power consumption.
The operating clock φs for the bus masters and the on-chip ROM and on-chip RAM can be
selected from among φ, φ/2, φ/4, φ/8, φ/16, and φ/32 according to the PHIS[2:0] setting in LPCR3.
6.3.1
Reset States
For reset states, see section 3.3, Reset.
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Section 6 Power-Down Modes
6.4
Module Standby Function
The module standby function is available for any peripheral module. When a module is set to the
module standby state, the clock supply to the module stops placing the module in the power-down
state. Setting the corresponding bit to the module in MSTCR to 1 places the module in the module
standby state and clearing the bit cancels the module standby state. After release from a reset, all
the modules except timer RE are in the module standby state; to use a module, cancel the module
standby state of it.
Note that the registers of the module in the module standby state cannot be accessed.
6.5
PSC Divider Stop Function
When the peripheral modules do not use the PSC divider output, the PSC divider can be stopped
by setting the PSCSTP bit in LPCR1 to 1.
When the PSC divider is stopped, the peripheral modules using φ/2 to φ/8192 can be stopped as
shown in table 6.1 (register values are retained). Before setting the PSCSTP bit to 1, set the
peripheral modules using the PSC divider output to the module standby state.
After release from a reset, the PSC divider is stopped since the PSCSTP bit is set to 1. For the
PSCSTP bit, see section 5.2.3, Power-Down Control Register 1 (LPCR1).
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Section 6 Power-Down Modes
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Section 7 ROM
Section 7 ROM
The features of the on-chip flash memory are described below.
7.1
Overview
• Programming/erasing method
Four bytes are programmed simultaneously. A single block is erased at a time; only one block
should be erased at a time even when the entire ROM area is to be erased.
• Programming/erasing time
Program ROM programming time: 150 µs (typ.) for 4-byte simultaneous programming, i.e., 38
µs (typ.) per byte
Data flash programming time: 300 µs (typ.) for 4-byte simultaneous programming, i.e., 75 µs
(typ.) per byte
Erasing time: 200 ms (typ.) per block for the program ROM and data flash areas.
• Reprogramming capability: The program ROM area can be reprogrammed up to 1000 times
and the data flash area can be reprogrammed up to 10000 times.
• Two on-board programming modes
Boot mode: The on-chip SCI can be used for programming/erasing the user ROM area. In this
mode, the communication bit rate between the host and this LSI can be automatically adjusted.
User mode: Any interface can be used for programming/erasing the user ROM area.
• Programmer mode
A PROM programmer is used for programming/erasing.
• Protection function
Flash memory can be protected against erroneous programming and erasure.
Lock-bit protection function can be set through software.
• PROM-programmer protection/Boot-mode protection
By writing specified data to a specified address range in user ROM, protection of the userROM area in boot mode and PROM-programmer mode can be established.
• Access cycle
Program ROM: One state
Data flash: Two states
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Section 7 ROM
7.2
Block Configuration
Figure 7.1 shows the blocks of the flash memory. The user ROM area contains the program ROM
area for storing the microcomputer's operating program and the data flash area for storing data. In
the figure, the thick-line frames each indicate an erasure block (erasing unit); the thin-line frames
each indicate a programming unit. The values in the frames are addresses. Erasure can be done in
erasure-block units shown in the figure 7.1. Programming can be done in 2-word or 4-byte units,
each of which begins at the address whose lower four-bit value is H'0, H'4, H'8, or H'C.
Rev. 1.00 Oct. 03, 2008 Page 160 of 962
REJ09B0465-0100
Section 7 ROM
H8S/20103, H8S/20203, and H8S/20223
(program ROM: 128 kbytes, data flash: 8 kbytes)
Programming unit: 4 bytes
Program ROM block 1
(erasing unit: 16 kbytes)
Program ROM block 2
(erasing unit: 32 kbytes)
Program ROM block 3
(erasing unit: 32 kbytes)
Program ROM block 4
(erasing unit: 32 kbytes)
Program ROM block 5
(erasing unit: 16 kbytes)
Data flash A
(erasing unit: 4 kbytes)
Data flash B
(erasing unit: 4 kbytes)
H'000000
H'000001
H'000002
H'000003
H'000004
H'000005
H'000006
H'000007
H'000008
H'000009
H'00000A
H'00000B
H'00000C
H'00000D
H'00000E
H'00000F
H'003FFC
H'003FFD
H'003FFE
H'003FFF
H'004000
H'004001
H'004002
H'004003
H'00BFFC
H'00BFFD
H'00BFFE
H'00BFFF
H'00C000
H'00C000
H'00C000
H'00C000
H'013FFC
H'013FFD
H'013FFE
H'013FFF
H'014000
H'014001
H'014002
H'014003
H'01BFFC
H'01BFFD
H'01BFFE
H'01BFFF
H'01C000
H'01C001
H'01C002
H'01C003
H'01FFFC
H'01FFFD
H'01FFFE
H'01FFFF
H'F00000
H'F00001
H'F00002
H'F00003
H'F00FFC
H'F00FFD
H'F00FFE
H'F00FFF
H'F01000
H'F01001
H'F01002
H'F01003
H'F01FFC
H'F01FFD
H'F01FFE
H'F01FFF
Figure 7.1 Block Configuration of Flash Memory (1)
Rev. 1.00 Oct. 03, 2008 Page 161 of 962
REJ09B0465-0100
Section 7 ROM
H8S/20102, H8S/20202, and H8S/20222
(program ROM: 96 kbytes, data flash: 8 kbytes)
Programming unit: 4 bytes
Program ROM block 1
(erasing unit: 16 kbytes)
Program ROM block 2
(erasing unit: 32 kbytes)
Program ROM block 3
(erasing unit: 32 kbytes)
Program ROM block 4
(erasing unit: 16 kbytes)
Data flash A
(erasing unit: 4 kbytes)
Data flash B
(erasing unit: 4 kbytes)
H'000000
H'000001
H'000002
H'000003
H'000004
H'000005
H'000006
H'000007
H'000008
H'000009
H'00000A
H'00000B
H'00000C
H'00000D
H'00000E
H'00000F
H'003FFC
H'003FFD
H'003FFE
H'003FFF
H'004000
H'004001
H'004002
H'004003
H'00BFFC
H'00BFFD
H'00BFFE
H'00BFFF
H'00C000
H'00C000
H'00C000
H'00C000
H'013FFC
H'013FFD
H'013FFE
H'013FFF
H'014000
H'014001
H'014002
H'014003
H'017FFC
H'017FFD
H'017FFE
H'017FFF
H'F00000
H'F00001
H'F00002
H'F00003
H'F00FFC
H'F00FFD
H'F00FFE
H'F00FFF
H'F01000
H'F01001
H'F01002
H'F01003
H'F01FFC
H'F01FFD
H'F01FFE
H'F01FFF
Figure 7.1 Block Configuration of Flash Memory (2)
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Section 7 ROM
7.3
CPU Reprogramming Mode
In CPU reprogramming mode, the user ROM area can be reprogrammed by executing the software
commands by the CPU. The software commands should be issued to the specific area to be
reprogrammed in the user ROM area.
If an interrupt is requested during erasure operation in CPU reprogramming mode, erasure can be
suspended to process the interrupt. This is referred to as erase-suspend function. In erase-suspend
mode, the user ROM area can be read through programming.
The CPU has two reprogramming modes, EW0 mode and EW1 mode. Table 7.1 shows
differences between the two modes.
Table 7.1
Differences between EW0 Mode and EW1 Mode
Item
EW0 Mode
EW1 Mode
Area in which a reprogramming- User ROM area
control program can be located
User ROM area
Area in which a reprogramming- A reprogramming-control
control program can be
program must be transferred to
executed
RAM before execution.
A reprogramming-control
program can be executed in the
user ROM area.
Area which can be
reprogrammed
User ROM area
User ROM area excluding the
blocks in which a
reprogramming-control program
is located.
Limitations on software
commands
None
The program and erasure
commands must not be
executed on any block in which
a reprogramming-control
program is located.
Mode after software command
execution
Read-array mode
Read-array mode
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Section 7 ROM
Item
EW0 Mode
EW1 Mode
CPU state during autoprogramming and auto-erasure
Operating state
Hold state (I/O ports retain the
states in which they have been
before the command is
executed.)
Flash memory state detection
Read the FMPRSF, FMERSF, and FMEBSF bits in FLMSTR in a
program.
Conditions of transition to erase- Both the FMSPEN and
The FMSPEN bit in FLMCR2 is
suspend state
FMSPREQ bits in FLMCR2 are set to 1 and an interrupt is
set to 1.
requested.
Or, both the FMSPEN and
FMISPE bits in FLMCR2 are set
to 1 and an interrupt is
requested.
Conditions of Interrupt
generation
Usage of DTC
Note:
•
The flash memory returns
from the busy state to the
ready state*1.
•
The user ROM area is read
1
in the busy state* .
Usable*2
Use of interrupts prohibited.
Usable*2*3
1. To avoid the generation of access to the user ROM area, set VOFR so that the variable
vectors and interrupt processing routines are allocated to RAM.
2. Allocate DTC vectors and processing routines to RAM. Do not use the DTC for access
to the user ROM area during E/W processing. If this is ignored, values read will be
invalid.
3. Do not use the DTC if the reprogramming-control program is allocated to RAM.
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7.3.1
EW0 Mode
EW0 mode can be selected by transferring the reprogramming-control program to the RAM,
branching to the program in the RAM, setting the FMEWMOD bit in FLMCR1 to 0, and setting
the FMCMDEN bit in FLMCR1 to 1 (to enable software commands), in this order.
Programming and erasure operations can be controlled through software commands. Completion
of the software command and related information can be read out from the FLMSTR register.
To cause a transition to erase-suspend mode during erasure, set both the FMSPEN and FMSPREQ
bits in FLMCR2 to 1 (to enable a transition to erase-suspend mode and to request a transition to
erase-suspend mode, respectively). Then wait for the transition time to erase-suspend mode
(approximately 50 µs), check that the FMRDY bit in FLMSTR is 1 (ready state), and access the
user ROM area. Setting the FMSPREQ bit to 0 resumes erasure.
When the interrupt is used, set the interrupt vector offset register (VOFR) such that access to the
user ROM area is not generated. That is, the vectors should have addresses within the RAM and
point to interrupt processing routine that are also in the RAM.
7.3.2
EW1 Mode
EW1 mode can be selected by setting the FMEWMOD bit in FLMCR1 to 1, and then setting the
FMCMDEN bit in FLMCR1 to 1 (to enable software commands).
Programming and erasure operations can be controlled through software commands. Completion
of the software command and related information can be read out from the FLMSTR register.
To cause a transition to erase-suspend mode during erasure, set the FMSPEN bit in FLMCR2 to 1
(to enable a transition to erase-suspend mode), and then execute the erasure command. Note that
the interrupt for causing a transition to erase-suspend mode must be enabled beforehand. This
allows the interrupt request to be accepted when the transition time to erase-suspend mode has
elapsed after the erasure command is executed.
When an interrupt is requested, the FMSPREQ bit is automatically set to 1 (to request a transition
to erase-suspend mode), thus suspending erasure. If erasure has not been completed at the end of
interrupt processing (FMERCF = 1 in FLMSTR), resume erasure by setting the FMSPREQ bit to
0.
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Section 7 ROM
7.4
•
•
•
•
Register Descriptions
Flash memory control register 1 (FLMCR1)
Flash memory control register 2 (FLMCR2)
Flash memory data flash protect register (DFPR)
Flash memory status register (FLMSTR)
7.4.1
Flash Memory Control Register 1 (FLMCR1)
Address: H'FF0660
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0




FMLBD
FMWUS
FMEWMOD
FMCMDEN
0
0
0
0
0
1
0
0
Bit
Symbol
Bit Name
Description
R/W
7, 6

Reserved

5, 4

Reserved
These bits are read as 0. The write value should
be 0.
Lock bit disable
0: The lock bits are enabled.
3
1
2
FMLBD* *

R/W
1: The lock bits are disabled.
2
FMWUS
CPU
0: Reprogramming through byte instructions
reprogramming- 1: Reprogramming through word instructions
instruction select
1
FMEWMOD EW mode select
0: EW0 mode
R/W
R/W
1: EW1 mode
0
FMCMDEN
*1*2*3*4
Flash memory
0: Flash memory software commands are disabled. R/W
software
1: Flash memory software commands are enabled.
command enable
Notes: 1. When setting the bit to 1, first clear the bit to 0 and then immediately set the bit to 1; do
not allow any interrupt to be generated between these operations.
2. The bit is cleared to 0 when the FMRDY bit changes from 0 to 1.
3. Set the FMEWMOD bit and then set the FMCMDEN bit to 1.
4. When setting the FMCMDEN bit to 1 while the FMEWMOD bit is 0, be sure to execute
the program in the RAM.
FLMCR1 enables/disables reprogramming/erasure, selects the reprogramming/erasure mode,
enables/disables lock bits, and selects the reprogramming unit of the flash memory. For specific
use, see section 7.6, Programming/Erasing.
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Section 7 ROM
• FMLBD bit (lock bit disable)
This bit disables the lock-bit function. Setting FMLBD to 1 enables erasing/programming the
block to which the lock-bit protection is applied. For the relationship between the FMLBD bit
and the lock bit for the block, see table 7.2 below. Command sequence error occurs when the
erasing/programming command is executed while disabling the erase program.
Table 7.2
Relationship between FMLBD, Lock Bit, and Corresponding
Erasure/Programming Operation
FMLBD
Lock Bit
Erasure/Programming Operation
1

Erasure/programming possible
0
1 (erased state)
0 (programmed state)
Erasure/programming impossible
• FMWUS bit (CPU reprogramming-instruction select)
Setting the FMWUS bit to 0 enables software commands to be issued through byte
instructions. Setting the FMWUS bit to 1 enables software commands to be issued through
word instructions. For software commands, see section 7.6.1, Software Commands.
• FMEWMOD bit (EW mode select)
Setting the FMEWMOD bit to 0 and the FMCMDEN bit to 1 selects EW0 mode. Setting the
FMEWMOD and FMCMDEN bits to 1 selects EW1.
• FMCMDEN bit (flash memory software command enable)
Setting the FMCMDEN bit to 1 enables software commands to be accepted. For issuing
software commands to the data flash areas, appropriately set the flash memory data flash
protect register (DFPR), which is described in section 7.4.3.
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7.4.2
Flash Memory Control Register 2 (FLMCR2)
Address: H'FF0661
Bit:
b7
b6
b5
b4
b3
b2
b1
b0



FMRDYIE
FMBSYRDIE
FMISPE
FMSPREQ
FMSPEN
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7, 6

Reserved

5

Reserved
These bits are read as 0. The write value should
be 0.
4
FMRDYIE
*1*2
Flash read-ready
interrupt enable
0: The ready interrupt is disabled.
R/W
3

1: The ready interrupt is enabled.
FMBSYRDIE Flash busy-read
0: The busy-read interrupt is disabled.
*1*3
interrupt enable
1: The busy-read interrupt is enabled.
2
FMISPE*4
Suspend-request 0: Transition to erase-suspend mode by an
enable by interrupt
interrupt request is disabled.
request
1: Transition to erase-suspend mode by an
interrupt request is enabled.
R/W
1
FMSPREQ
*1*5*6*7
Erase suspend
R/W
FMSPEN
*4*8
Erase-suspend
enable
0
Notes: 1.
2.
3.
4.
5.
6.
7.
8.
0: Erasure is resumed.
R/W
1: Transition to erase-suspend mode is made.
0: Erase suspend is disabled.
R/W
1: Erase suspend is enabled.
For programming the flash memory, set the FMSPEN bit to 1.
The FMRDYIE bit is cleared to 0 when the FMRDY bit changes from 0 to 1.
The FMBSYRDIE bit is cleared to 0 when the FMRDY bit changes from 0 to 1.
When setting the bit to 1, first clear the bit to 0 and then immediately set the bit to 1; do
not allow any interrupt to be generated between these operations.
The FMSPREQ bit is set to 1 when an interrupt is generated if the FMSPEN bit is 1 in
EW1 mode.
The FMSPREQ bit is set to 1 when an interrupt is generated if the FMSPEN and
FMISPE bits are 1 in EW0 mode.
The FMSPREQ bit is cleared to 0 when the FMRDY bit changes from 0 to 1 upon
completion of E/W.
The FMSPEN bit is cleared to 0 when the FMRDY bit changes from 0 to 1 if the
FMSPREQ bit is 0.
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Section 7 ROM
FLMCR2 enables/disables flash memory interrupts, enables/controls a transition to erase-suspend
mode.
• FMRDYIE bit (flash read-ready interrupt enable)
Setting the FMRDYIE bit to 1 enables an interrupt to be generated when the flash memory
changes from the busy state to the ready state.
• FMBSYRDIE bit (flash busy-read interrupt enable)
Setting the FMBSYRDIE bit to 1 enables an interrupt to be generated when the user ROM area
is accessed while the flash memory is in the busy state.
• FMISPE bit (suspend-request enable by interrupt request)
Setting the FMISPE bit to 1 in EW0 mode allows the FMSPREQ bit to be automatically set to
1 (to request a transition to erase-suspend mode) thus causing a transition to erase-suspend
mode when an interrupt is requested.
• FMSPREQ bit (erase suspend)
Setting the FMSPREQ bit to 1 causes a transition to erase-suspend mode. To resume erasure,
set the FMSPREQ bit to 0.
• FMSPEN bit (erase-suspend enable)
Setting the FMSPEN bit to 1 enables a transition to erase-suspend mode.
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Section 7 ROM
7.4.3
Flash Memory Data Flash Protect Register (DFPR)
Address: H'FF0662
Bit:
Value after reset:
Bit
b6
b5
b4
b3
b2
b1
b0






DFPR1
DFPR0
0
0
0
0
0
0
0
0
Bit Name
Description
R/W
7 to 2 
Reserved
These bits are read as 0. The write value should
be 0.

1
Data flash B
E/W disable*1*2
0: E/W of data flash B is enabled.
R/W
Data flash A
E/W disable*1*2
0: E/W of data flash A is enabled.
0
Symbol
b7
DFPR1
DFPR0
1: E/W of data flash B is disabled.
R/W
1: E/W of data flash A is disabled.
Notes: 1. When setting the bit to 0, first set the bit to 1 and then immediately set the bit to 0; do
not allow any interrupt to be generated between these operations.
2. The DFPR bits are set to 1 when the FMCMDEN bit changes from 0 to 1.
DFPR enables/disables reprogramming of data flash areas in block units. Before reprogramming
the data flash areas, cancel the protection against reprogramming.
• DFPR1 bit (data flash B E/W disable)
Setting the DFPR1 bit to 1 disables software commands to be issued to data flash B. Setting
the DFPR1 bit to 0 enables software commands to be issued to data flash B.
• DFPR0 bit (data flash A E/W disable)
Setting the DFPR0 bit to 1 disables software commands to be issued to data flash A. Setting
the DFPR0 bit to 0 enables software commands to be issued to data flash A.
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Section 7 ROM
7.4.4
Flash Memory Status Register (FLMSTR)
Address: H'FF0663
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
FMRDYIF
FMBSYRDIF
FMEBSF
FMERSF
FMPRSF


FMRDY
0
0
0
0
0
0
1
1
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
FMRDYIF
*1*2*3
Flash readready interrupt
request flag
0: The flash read-ready interrupt is not being
requested.
R/W
1: The flash read-ready interrupt is being requested.
[Setting condition]
• FMRDY changes from 0 to 1.
[Clearing condition]
•
6
FMBSYRDIF Flash busy-
*2*3*4
read interrupt
request flag
"1" is read from FMRDYIF and then the bit is
cleared to 0.
0: The flash busy-read interrupt is not being
requested.
R/W
1: The flash busy-read interrupt is being requested.
[Setting condition]
•
The user ROM area is accessed while the
FMRDY is 0.
[Clearing condition]
•
5
FMEBSF
*3*5
"1" is read from FMBSYRDIF and then the bit is
cleared to 0.
Erasure/blank- 0: Successful end
checking status 1: End with an error
flag
[Setting condition]
R
•
The erasure command is executed and results in
unsuccessful erasure.
• The blank-checking command is executed and it
is detected that the specified block is not blank.
[Clearing condition]
•
The clear-status command is issued.
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Section 7 ROM
Bit
Symbol
Bit Name
Description
4
FMERSF
Erase-suspend 0: Erase-suspend function is not being used.
flag
1: Erase-suspend function is being used.
R/W
R
[Setting condition]
• Erase-suspend mode is being used.
[Clearing condition]
•
3
FMPRSF
*3*5
Programming
status flag
Erase-suspend mode is not being used.
0: Successful end
R
1: End with an error
[Setting conditions]
•
The programming command is executed and
results in unsuccessful programming.
• The lock-bit programming command is executed
and results in unsuccessful programming.
[Clearing condition]
•
The clear-status command is issued.
2

Reserved
This bit is read as 0. The write value should be 0.

1

Reserved
Reading this bit returns the value same as the
FMRDY value. The write value should be 1.

0
FMRDY
Flash memory
ready/busy
status flag
0: Busy (programming or erasure in progress)
R
1: Ready
[Setting condition]
•
The flash memory is not being programmed or
erased.
[Clearing condition]
•
Notes: 1.
2.
3.
4.
The flash memory is being programmed or
erased.
The FMRDYIF bit is set to 1 when the FMRDY bit changes from 0 to 1.
When setting the bit to 0, first read 1 from the bit and then write 0 to the bit.
The bit cannot be set to 1 through software.
The FMBSYRDIF bit is set to 1 when the ROM area is accessed while the FMRDY bit is
0.
5. The bit is cleared to 0 when the clear-status command is executed.
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Section 7 ROM
• FMRDYIF (flash read-ready interrupt request flag)
The FMRDYIF bit indicates that the flash memory has changed from the busy state to the
ready state. When the FMRDYIF bit is set to 1 while the FMRDYIE bit is 1, an interrupt
request is generated.
• FMBSYRDIF (flash busy-read interrupt request flag)
The FMBSYRDIF bit indicates that the user ROM area is accessed while the flash memory is
in the busy state. When the FMBSYRDIF bit is set to 1 while the FMBSYRDIE bit is 1, an
interrupt request is generated.
• FMEBSF (erasure/blank-checking status flag)
The FMEBSF bit is a read-only bit indicating the state when erasure/blank-checking command
is executed.
• FMERSF (erase-suspend flag)
The FMERSF bit is a read-only bit indicating the state of erase-suspend mode.
• FMPRSF (programming status flag)
The FMPRSF bit is a read-only bit indicating the state when programming command is
executed.
• FMRDY (flash memory ready/busy status flag)
The FMRDY bit indicates the state of flash memory operation.
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Section 7 ROM
7.5
On-Board Programming
The flash memory can be programmed/erased on board (boot mode and user mode), or by using a
PROM programmer (programmer mode). When the reset is released, this LSI enters one of these
modes depending on the levels of the signals input on the TEST, NMI, and ports, as shown in
table 7.3. The levels of these signals must be fixed at least TBD states before the reset is released.
When this LSI enters boot mode, the built-in boot program is initiated. The boot program transfers
the programming-control program to the on-chip RAM, erases the flash memory areas entirely,
and then executes the programming-control program. Boot mode is useful for on-board initial
programming as well as forced recovery when programming/erasure in user mode is disabled.
User mode is useful for erasing and reprogramming the specified blocks, which function is
achieved by branching to the programming/erasure processing programs prepared by the user.
Table 7.3
Pin Levels and Programming Mode Selection
TEST
NMI
P85
PB3
PB2
PB1
PB0
LSI Modes after Release from a Reset
0
1
×
×
×
×
×
User mode
0
0
1
×
×
×
×
Boot mode
×
×
0
0
0
0
Programmer mode
1
Note:
×: Do not care.
7.5.1
Boot Mode
In boot mode, control commands and data for programming are transmitted from the externally
connected host via SCI3_1 to program/erase the user ROM area.
In boot mode, it is necessary to prepare the tool for transmitting control commands and data for
programming, and the data for programming in the host. Asynchronous mode is used for serial
communication. Figure 7.2 shows the system configuration in boot mode. Although interrupt
requests are ignored in boot mode, interrupt requests should be disabled by the system.
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Section 7 ROM
This LSI
On-chip control-command
analysis execution software
Flash memory
Host
Control commands and
programming data
Programming tool
and
programming data
RxD
SCI
On-chip ROM
TxD
Returned response
Figure 7.2 System Configuration in Boot Mode
(1)
Serial Interface Settings by Host
SCI3_1 is set to asynchronous mode, in which the serial transmission/reception format is set to 8bit data, one stop-bit, and no parity.
When this LSI enters boot mode, the built-in boot program is initiated. When the boot program is
initiated, this LSI measures the low-level period of asynchronous serial communication data
(H'00) transmitted continuously from the host. This LSI then calculates the bit rate of transmission
from the host, and adjusts the SCI bit rate so that it should match that of the host.
After completing the bit rate adjustment, this LSI transmits one H'00 byte to the host to signal
completion of bit rate adjustment. When successfully having received this completion signal, the
host should transmit one H'55 byte to this LSI. When not, boot mode should be initiated again.
Depending on the combination of the host's transfer bit rate and system clock frequency of this
LSI, there might be a discrepancy between the bit rates of the host and this LSI. To prevent this,
the transfer bit rate of the host and system clock frequency of this LSI should be set in the range of
the value listed in table 7.4.
Start bit
D0
D1
D2
D3
D4
D5
D6
Measures low-level period (9 bits) (data: H'00)
D7
Stop bit
High-level period
of 1 or more bits
Figure 7.3 Automatic Adjustment of Bit Rates
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Section 7 ROM
Table 7.4
System Clock Frequencies at which Automatic Adjustment of Bit Rates is
Possible
Host Bit Rate
System Clock Frequency Range of LSI
9600 bps
On-chip oscillator (10 MHz)
4800 bps
2400 bps
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Section 7 ROM
(2)
State Transition
Figure 7.4 shows the state transitions in boot mode.
(Adjusts bit rates.)
Receives H'00, ..., H'00.
Transmits H'00.
(Signals adjustment completion.)
Boot mode is initiated.
(reset in boot mode)
Adjusts bit rates.
1.
Receives H'55.
2.
Receives an inquiry/
selection command.
Waits for an inquiry/
selection command.
Executes processing
in response to the inquiry/
selection command.
Responds to the inquiry/
selection command.
3.
(Receives an programming/
erasure status transition
command)
Erases the entire
user ROM area.
Receives a reading/checking command.
4.
Executes processing
in response to the reading/
checking command.
Waits for a programming/
erasure command.
Responds to the command.
(Completes
erasure.)
(Completes
programming.)
(Receives a programming
selection command.)
(Receives an erasure
selection command.)
(The erasure block
is specified.)
Waits for erasure
block information.
Waits for the
programming data.
Figure 7.4 State Transitions in Boot Mode
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Section 7 ROM
1. After boot mode is initiated, this LSI adjusts the SCI3_1 bit rate so that it should match the
host's bit rate.
2. This LSI sends the requested information to the host in response to inquiries regarding the size,
configuration, and start addresses of the user ROM areas, information on the supported
devices, etc.
3. On receiving transmission of a programming/erasure status command, this LSI erases the
entire user ROM area automatically.
4. When completing erasure of the user ROM area, this LSI enters the programming/erasurecommand wait state. After transmission of the programming selection command, the host
should transmit the address at which the programming should start and the programming data.
When programming is completed, the host should transmit H'FFFFFFFF as the programming
start address to terminate programming. This allows this LSI to return to the
programming/erasure-command wait state from the programming-data wait state. If the above
programming-termination command is once issued to an area in an erasure block and when
that block is to be programmed again, erase the block before programming. Figure 7.5 shows
an example of an erasure block containing the area that has been already programmed.
On receiving an erasure selection command, this LSI enters the erasure-block-information wait
state. After transmission of the erasure selection command, the host should transmit the erasure
block number. When erasure is completed, the host should transmit H'FF as the erasure block
number. This allows this LSI to return to the programming/erasure-command wait state from
the erasure-block-information wait state. Note that erasure is necessary only when
programming is once done in boot mode and then only a specific block is to be reprogrammed
without applying a reset-start. If the necessary programming can be done in a single operation,
such erasure processing is unnecessary because all the blocks are erased before this LSI enters
the wait state for programming, erasure, or other commands. In addition to the
programming/erasure commands, there are commands for sum checking and blank checking
(erasure checking) of the user ROM areas, memory reading, and acquiring the current state
information.
Note that data can be read from the user ROM area only after the MAT has been automatically
erased and then programmed.
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Section 7 ROM
EB2
EB3
Programming
end area
EB4
Before reprogramming erase blocks EB3 and
EB4 on which the programming end command
is issued, erase the blocks (EB3 and EB4).
EB5
Figure 7.5 Example of Erase Block Including Programmed Area
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Section 7 ROM
7.5.2
Specifications of Standard Serial Communication Interface in Boot Mode
The boot program activated in boot mode communicates with the host via the on-chip SCI3_1.
The following describes the specifications of the serial communication interface between the host
and the boot program.
The boot program has three states.
1. Bit-rate adjustment state
In this state, the boot program adjusts the SCI3_1 bit rate to match that of the host to perform
serial communication with the host. When this LSI is started up in boot mode, the boot
program is activated and enters the bit-rate adjustment state, in which it receives command
from the host and adjusts the bit rate accordingly. After bit rate adjustment is completed, the
boot program enters the inquiry/selection state.
2. Inquiry/selection state
In this state, the boot program responds to inquiry commands from the host. The device, clock
mode, and bit rate are selected. Upon completion of selection, the boot program enters the
programming/erasure state in response to the command for transition-to-programming/erasure
state. Before entering the programming/erasure state, the boot program transfers the erasurerelated libraries to the on-chip RAM and erases the user ROM areas.
3. Programming/erasure state
In this state, the boot program executes programming/erasure. The boot program transfers the
program for programming/erasure to the on-chip RAM according to the command transmitted
from the host and executes programming/erasure. The boot program also executes sum
checking and blank checking as directed using the corresponding commands.
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Section 7 ROM
Figure 7.6 shows the boot program states and processing flow.
Reset
Bit-rate adjustment
state
Inquiry/selection
state
Inquiry
Selection
Processes
inquiry.
Enters the programming/
erasure state.
Processes
selection.
Processes userROM-area erasure.
Programming/
erasure state
Programming
Processes
programming.
Erasure
Checking
Processes
erasure.
Processes
checking.
Figure 7.6 Boot Program States and Processing Flow
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Section 7 ROM
(1)
Bit-Rate Adjustment State
In the bit-rate adjustment state, the boot program measures the low-level period of H'00
transmitted from the host and calculates the bit rate according to the measurement. The bit rate can
be changed using the new-bit-rate selection command. On completion of bit rate adjustment, the
boot program enters the inquiry/selection state. Figure 7.7 shows the sequence of bit rate
adjustment.
Host
Boot program
H'00 (30 times max.)
Measures the length
of one bit.
H'00 (Adjustment completed)
H'55
H'E6 (Response)
H'FF (Error)
Figure 7.7 Sequence of Bit Rate Adjustment
(2)
Communication Protocol
1. One-character command or one-character response
A command or response consisting of one character used for inquiry or ACK code indicating a
successful end.
2. n-character command or n-character response
A command or response requiring 128 bytes of data used as a selection command or a response
to an inquiry. The length of programming data is defined separately and so data size (length) is
omitted here.
3. Error response
Response to a command which has caused an error; two bytes, consisting of the error response
and error code.
4. 128-byte programming command
This command does not include its data size information. The data size can be acquired from
the response to the programming-size inquiry command.
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5. Response to memory reading command
This response includes 4-byte size information.
One-character command
or one-character response
n-character command
or n-character response
Command or response
Data
Data size
Checksum
Command or response
Error response
Error code
Error response
128-byte
programming command
Address
Response to memory
reading command
Data size
Data (128 bytes)
Command
Checksum
Data
Response
Checksum
Figure 7.8 Formats in Communication Protocol
• Command (1 byte): Inquiry, selection, programming, erasure, checking, etc.
• Response (1 byte): Response to an inquiry
• Size (1 or 2 bytes): The size of transmit/receive data excluding the command code, response,
size, and checksum.
• Data (n bytes): Particular data for a command or response
• Checksum (1 byte): This is set so that the total sum of the values from the command- code
field or response through the SUM field should be H'00.
• Error response (1 byte): Error response to a command
• Error code (1 byte): Type of an error that has occurred
• Address (4 bytes): Address for programming
• Data (128 bytes): Data for programming
• Data size (4 bytes): Four-byte length included in the response to the memory reading
command.
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(3)
Inquiry/Selection State
In this state, the boot program returns the information on the flash ROM in response to inquiry
commands from the host, and selects the device, clock mode, and bit rate in response to the
relevant selection commands.
Table 7.5 lists inquiry/selection commands.
Table 7.5
Inquiry/Selection Commands
Command
Command Name
Function
H'20
Supported-device inquiry
Inquires about the device code and product
name.
H'10
Device selection
Selects the device (code).
H'21
Clock mode inquiry
Inquires about the number of selectable
clock modes and each clock mode's value.
H'11
Clock mode selection
Selects the clock mode.
H'22
Frequency-division-ratio inquiry
Inquires about the number of frequency
types, the number of frequency division
ratios, and the specific frequency division
ratio values.
H'23
Operating-frequency inquiry
Inquires about the maximum and minimum
operating frequencies for the main and
peripheral clocks.
H'25
User-ROM-area information inquiry
Inquires about the number of user ROM
areas and first and last addresses of each
MAT area.
H'26
Erasure-block information inquiry
Inquires about the number of blocks and first
and last addresses of each block
H'27
Programming-size inquiry
Inquires about the size of a unit for
programming.
H'3F
New bit-rate selection
Selects the new bit rate.
H'40
Transition-to-programming/erasure
state
Erases the user ROM areas and enters the
programming/erasure state.
H'4F
Boot-program state inquiry
Inquires about the processing state of the
boot program.
The selection commands should be transmitted from the host in the following order: device
selection (H'10), clock mode selection (H'11), and new bit-rate selection (H'3F). If the same
selection command is transmitted more than one time, the last one is valid.
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All the commands in table 7.5 except for the boot-program-state inquiry command (H'4F) are
valid until the boot program accepts the transition-to-programming/erasure-state command (H'40).
That is, until the transition command is accepted, the host can repeatedly send inquiry and
selection commands in table 7.5. The boot-program-state inquiry command (H'4F) is valid even
after the boot program accepts the transition-to-programming/erasure-state command (H'40).
(a)
Inquiry about Supported Devices
In response to the command for inquiry about the supported devices, the boot program returns the
device codes of the supported devices and the product name of the boot program.
Command
H'20
• Command H'20 (1 byte): Inquiry about supported devices
Response
H'30
Size
Number of
devices
Number of Device code
characters
Product name
SUM
• Response H'30 (1 byte): Response to the inquiry about supported devices
• Size (1 byte): The size of transmit/receive data excluding the response-command, size, and
checksum fields. Here, it refers to the total size used by the number-of-devices, number-ofcharacters, device-code, and product-name fields.
• Number of devices (1 byte): The number of device types supported by the boot program in the
microcomputer.
• Number of characters (1 byte): The number of characters in the device-code and product-name
fields.
• Device code (4 bytes): Product names of the supported devices (ASCII code)
• Product name (128 bytes): Product code of the boot program (ASCII code)
• SUM (1 byte): Checksum
This is set so that the total sum of the values from the response-code field through the SUM
field should be H'00.
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(b)
Device Selection
In response to the device selection command, the boot program sets the specified supported device
as the selected device. The boot program will return the information on the selected device in
response to the subsequent inquiries.
Command
H'10
Size
Device code
SUM
• Command H'10 (1 byte): Device selection
• Size (1 byte): The number of characters in the device-code field (fixed to four).
• Device code (4 bytes): The device code that has been returned in response to the inquiry about
supported devices (ASCII code)
• SUM (1 byte): Checksum
Response
H'06
• Response H'06 (1 byte): Response to device selection
The ACK code is returned when the specified device code corresponds to one of the supported
devices.
Error response
H'90
ERROR
• Error response H'90 (1 byte): Error response to device selection
• ERROR (1 byte): Error code
H'11: Checksum error
H'21: Device code error indicating device code disagreement
(c)
Inquiry about Clock Modes
In response to the command for inquiry about clock modes, the boot program returns the
information on the selectable clock modes.
Command
H'21
• Command H'21 (1 byte): Inquiry about clock modes
Response
H'31
Size
Mode
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…
SUM
Section 7 ROM
•
•
•
•
(d)
Response H'31 (1 byte): Response to the inquiry about clock modes
Size (1 byte): The total size of the number-of-modes and mode fields
Mode (1 byte): Selectable clock modes (example: H'01 denotes clock mode 1)
SUM (1 byte): Checksum
Clock Mode Selection
In response to the command for clock mode selection, the boot program sets the specified clock
mode as the selected clock mode. The boot program will return the information on the selected
clock mode in response to the subsequent inquiries.
The clock-mode selection command should be transmitted after the device selection command
(H'10).
Command
H'11
Size
Mode
SUM
• Command H'11 (1 byte): Clock mode selection
• Size (1 byte): The number of characters in the mode field (fixed to one).
• Mode (1 byte): The clock mode that has been returned in response to the inquiry about clock
modes.
• SUM (1 byte): Checksum
Response
H'06
• Response H'06 (1 byte): Response to clock mode selection
The ACK code is returned when the specified clock mode corresponds to one of the selectable
clock modes.
Error response
H'91
ERROR
• Error response H'91 (1 byte): Error response to clock mode selection
• ERROR (1 byte): Error code
H'11: Checksum error
H'22: Clock mode error indicating clock mode disagreement
Even if value H'00 or H'01 has been returned in response to the clock-mode inquiry command as
the number of modes, it is required to select the clock mode for each value.
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(e)
Inquiry about Frequency Division Ratios
In response to the command for inquiry about frequency division ratios, the boot program returns
the information on the selectable frequency division ratios.
Command
H'22
• Command H'22 (1 byte): Inquiry about frequency division ratios
Response
H'32
Size
Number
of types
Number of Frequency …
Frequency division
ratio
division
ratios
…
SUM
• Response H'32 (1 byte): Response to the inquiry about frequency division ratios
• Size (1 byte): The total size of the number-of-types, number-of-frequency-division-ratios, and
frequency-division-ratio fields.
• Number of types (1 byte): The number of operating clock signals for which frequency division
ratios can be selected for the device.
(For example, the value is H'02 if frequency division ratio settings can be made for the
frequencies of the main and peripheral module operating clock signals.)
• Number of frequency division ratios (1 byte): The number of selectable frequency division
ratios for each operating clock signal.
(For example, the number of selectable frequency division ratios for the main or peripheral
module operating clock signal.)
• Frequency division ratio (1 byte):
The negative numerical value by which the frequency is divided. (Example: H'FE (-2) when
the frequency is divided by two.)
As many frequency-division-ratio fields are repeated as the number of corresponding
frequency division ratios; and the combinations of the former and latter fields are repeated as
many times as the number of types (= number of operating clock signals).
• SUM (1 byte): Checksum
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(f)
Inquiry about Operating Frequencies
In response to the command for inquiry about operating frequencies, the boot program returns the
number of operating frequency types and the respective maximum and minimum frequencies.
Command
H'23
• Command H'23 (1 byte): Inquiry about operating frequencies
Response
H'33
Size
Number of
operating
frequencies
Minimum operating Maximum operating
frequency
frequency
…
SUM
• Response H'33 (1 byte): Response to the inquiry about operating frequencies
• Size (1 byte): The total size of the number-of-operating-frequencies, maximum-frequency, and
minimum-frequency fields.
• Number of operating frequencies (1 byte): The number of operating frequency types required
for the device
(For example, the value is H'02 if the main and peripheral module operating frequencies are
required.)
• Minimum operating frequency (2 bytes): The minimum frequency of a frequency-multiplied or
divided clock signal
The values in the minimum- and maximum-operating-frequency fields are obtained by
multiplying the operating frequency (MHz; to the second decimal place) by 100. (For example,
when the frequency is 20.00 MHz, 20.00 is multiplied by 100 to be 2000, and so H'07D0 is
returned here.)
• Maximum operating frequency (2 bytes): The maximum frequency of a frequency-multiplied
or divided clock signal.
As many pairs of the minimum- and maximum-operating-frequency fields are continued as the
number of operating frequencies (= number of operating frequency types).
• SUM (1 byte): Checksum
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(g)
Inquiry about User ROM Area
In response to the command for inquiry about the user ROM area, the boot program returns the
number of user ROM areas and their addresses.
Command
H'25
• Command H'25 (1 byte): Inquiry about user ROM area
Response
H'35
Size
Number
of areas
First address of the area
Last address of the area
…
SUM
• Response H'35 (1 byte): Response to the inquiry about user ROM area
• Size (1 byte): The total size of the number-of-areas, first-address-of-the-area, and last-addressof-the-area fields.
• Number of areas (1 byte): The number of consecutive user ROM areas
(H'01 is returned when the user ROM areas are continuous.)
• First address of the area (4 bytes): The first address of the area
• Last address of the area (4 bytes): The last address of the area
As many pairs of the first-address-of-the-area and last-address-of-the-area fields are continued
as the number of areas.
• SUM (1 byte): Checksum
(h)
Inquiry about Erasure Blocks
In response to the command for inquiry about erasure blocks, the boot program returns the number
of erasure blocks and their addresses.
Command
H'26
• Command H'26 (1 byte): Inquiry about erasure blocks
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Response
H'36
Size
Number of blocks
First address of the block
Last address of the block
…
SUM
• Response H'36 (1 byte): Response to the inquiry about erasure blocks
• Size (2 bytes): The total size of the number-of-blocks, first-address-of-the-block, and lastaddress-of-the-block fields.
• Number of blocks (1 byte): The number of flash memory blocks to be erased
• First address of the block (4 bytes): The first address of the block
• Last address of the block (4 bytes): The last address of the block
As many pairs of the first-address-of-the-block and last-address-of-the-block fields are
continued as the number of blocks.
• SUM (1 byte): Checksum
(i)
Inquiry about Programming Size
In response to the command for inquiry about programming size, the boot program returns the size
of a unit for programming.
Command
H'27
• Command H'27 (1 byte): Inquiry about programming size
Response
H'37
Size
Programming size
SUM
• Response H'37 (1 byte): Response to the inquiry about programming size
• Size (1 byte): The number of characters in the programming-size field (fixed to 2)
• Programming size (2 bytes): The size of a unit for programming
Programming data is received in the unit specified here.
• SUM (1 byte): Checksum
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(j)
New Bit-Rate Selection
In response to the command for new bit-rate selection, the boot program changes the bit rate
settings to those of the specified one, and responds to the acknowledgement from the host at the
new bit rate.
The new bit-rate selection command should be transmitted after the clock-mode selection
command.
Command
H'3F
Size
Bit rate
Input frequency
Number of Frequency Frequency
division
frequency division
ratio 2
division
ratio 1
ratio types
SUM
• Command H'3F (1 byte): New bit-rate selection
• Size (1 byte): The total size of the bit-rate, input-frequency, number-of-frequency-divisionratio-types, and frequency-division-ratio fields.
• Bit rate (2 bytes): New bit rate
The value to be set here is obtained by dividing the desired bit rate by 100. (For example, to
select the bit rate of 19200 bps, 19200 is divided by 100 to be 192, and so H'00C0 should be
set.)
• Input frequency (2 bytes): The frequency of the clock input to the boot program.
The value to be set here is obtained by multiplying the input frequency (MHz; to the second
decimal place) by 100. (For example, to select the input frequency of 20.00 MHz, 20.00 is
multiplied by 100 to be 2000, and so H'07D0 should be set.)
• Number of frequency division ratio types (1 byte): The number of selectable frequency
division ratios for the device.
(The value is usually H'02 because the main and peripheral module operating frequencies can
be usually selected.)
• Frequency division ratio 1 (1 byte): Frequency division ratio for the main operating frequency.
The negative numerical value by which the frequency is divided. (Example: H'FE (-2) when
the frequency is divided by two.)
• Frequency division ratio 2 (1 byte): Frequency division ratio for the peripheral operating
frequency.
The negative numerical value by which the frequency is divided. (Example: H'FE (-2) when
the frequency is divided by two.)
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• SUM (1 byte): Checksum
Response
H'06
• Response H'06 (1 byte): Response to the new bit-rate selection command
The ACK code is returned when selection is possible.
Error response
H'BF
ERROR
• Error response H'BF (1 byte): Error response to new bit-rate selection
• ERROR (1 byte): Error code
H'11: Checksum error
H'24: Bit-rate selection error indicating that the specified bit rate is not selectable.
H'25: Input frequency error indicating that the specified input frequency is not within the range
from the minimum to maximum values.
H'26: Frequency division ratio error indicating disagreement of frequency division ratios
H'27: Operating frequency error indicating that the specified operating frequency is not within
the range from the minimum to maximum values.
(4)
Checking Received Data
The following describes how the received data is checked.
1. Input frequency
The value of the received input frequency is checked to see if it is within the range from
minimum to maximum values of the input frequency of the selected clock mode of the selected
device. If not, an input frequency error is generated.
2. Frequency division ratio
The value of the received frequency division ratio is checked to see if it corresponds to the
frequency division ratio value of the selected clock mode of the selected device. If not, a
frequency division ratio error is generated.
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3. Operating frequency
The operating frequency is calculated from the received input frequency and frequency
division ratio. The input frequency is the frequency of the clock signal supplied to the LSI,
whereas the operating frequency is the frequency at which the LSI actually operates. The
following formula is used for the calculation.
Operating frequency = input frequency/frequency division ratio
The obtained operating frequency is checked to see if it is within the range from the minimum
to maximum values of the operating frequency of the selected clock mode of the selected
device. If not, an operating frequency error is generated.
4. Bit rate
From the peripheral operating frequency (φ) and bit rate (B), the value (n) of the clock select
bits (CKS) in the serial mode register (SMR) and the value (N) in the bit rate register (BRR)
are calculated to determine the error. The error determined is checked to see if it is smaller
than 4%. If not, a bit-rate selection error is generated. The following formula is used for the
calculation.
φ × 106
Error (%) =
(N + 1) × B × 64 × 22n-1
-1
× 100
When selection of the new bit rate is possible, the boot program returns an ACK code to the host
and then makes the necessary register settings to select the new bit rate. The host then transmits an
ACK code at the new bit rate and the boot program responds to it at the new bit rate.
Acknowledge H'06
• Acknowledge H'06 (1 byte): Acknowledgement of the new bit rate
Response
H'06
• Response H'06 (1 byte): Response to acknowledgement of the new bit rate
Figure 7.9 shows the sequence of new bit-rate selection.
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Boot program
Host
Selects the new-bit-rate selection command.
H'06 (ACK)
Waits for one-bit period
at the selected bit rate.
Sets the new bit rate.
Sets the new bit rate.
H'06 (ACK) at the new bit rate
H'06 (ACK) at the new bit rate
Figure 7.9 Sequence of New Bit-Rate Selection
(5)
Transition to Programming/Erasure State
In response to the command for transition-to-programming/erasure state, the boot program
transfers the erasure program to erase the data in the user ROM area. On completion of this
erasure, the boot program returns the ACK code and enters the programming/erasure state.
Before transmitting the programming selection command and data for programming, the host
should select the device, clock mode, and new bit rate for this LSI using the device selection,
clock-mode selection, and new-bit-rate selection commands; and then transmit a transition-toprogramming/erasure-state command to the boot program.
Command
H'40
• Command H'40 (1 byte): Transition to programming/erasure state
Response
H'06
• Response H'06 (1 byte): Response to the transition-to-programming/erasure-state command.
The ACK code is returned when the user ROM area have been successfully erased after
transfer of the erasure program.
Error response
H'C0
H'51
• Error response H'C0 (1 byte): Error response to the transition-to-programming/erasure-state
command.
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• Error code H'51 (1 byte): Erasure error indicating that erasure was unsuccessful because of an
error.
(6)
Command Errors
Command errors are caused by undefined commands, incorrect command sequence, and
unacceptable commands. For example, sending a clock-mode selection command before a device
selection command and sending an inquiry command after a transition-to-programming/erasurestate command both cause command errors.
Error response
H'80
H'xx
• Error response H'80 (1 byte): Command error
• Command H'xx (1 byte): Received command
(7)
Order of Commands
In the inquiry/selection state, commands should be sent in the following order.
1. Send the supported-device inquiry command (H'20) to get the list of supported devices.
2. Select a device according to the returned device information, and send the device selection
command (H'10).
3. Send the clock-mode inquiry command (H'21) to inquire about clock modes.
4. Select a clock mode from among the returned clock modes, and send the clock-mode selection
command (H'11).
5. After selection of the device and clock mode, send the frequency-division-ratio inquiry
command (H'22) and operating-frequency inquiry command (H'23) to get the information
necessary for selecting a new bit rate.
6. Select a new bit rate according to the returned information on the frequency division ratios and
operating frequencies, send the new bit-rate selection command (H'3F).
7. After selection of the new bit rate, send the user-ROM-area-information inquiry command
(H'25), erasure-block-information inquiry command (H'26), and programming-size inquiry
command (H'27) to get the information necessary for programming/erasing the user ROM
area.
8. After each inquiry of step [7], send the transition-to-programming/erasure-state command
(H'40) to cause a transition to the programming/erasure state.
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(8)
Programming/Erasure State
In the programming/erasure state, the boot program selects the form of programming in response
to the programming selection command and then writes the data in response to the 128-byte
programming command; or the boot program erases the desired blocks in response to the erasure
selection and block erasure commands. Table 7.6 lists the programming/erasure commands.
Table 7.6
Programming/Erasure Commands
Command
Command Name
Function
H'43
User-ROM-area programming
selection
Transfers the control program for user-ROM
area programming.
H'50
128-byte programming
Executes 128-byte programming.
H'48
Erasure selection
Transfers the erasure-control program.
H'58
Block erasure
Erases the block data.
H'52
Memory reading
Reads data from memory.
H'4B
Sum checking of user ROM area
Executes sum checking of the user ROM
area.
H'4D
Blank checking of user ROM area
Executes blank checking of the user ROM
area.
H'4F
Boot-program state inquiry
Inquires about the processing state of the
boot program.
1. Programming
Programming is performed by using the programming selection command and the 128-byte
programming command.
First, the host sends the user-ROM-area-programming selection command.
Next, the host sends the 128-byte programming command. The boot program assumes that the
128 bytes of data included in the 128-byte programming command should be programmed
according to the form of programming selected by the preceding programming selection
command. To program more than 128 bytes, repeatedly send 128-byte programming
commands. To terminate programming, the host should send the 128-byte programming
command with address H'FFFFFFFF. On completion of programming, the boot program waits
for the next programming/erasure selection command.
To perform programming according to a different form of programming or to program a
different MAT area subsequently, start the process by sending a programming selection
command.
The sequence of programming by the programming selection command and 128-byte
programming command is shown in figure 7.10.
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Host
Boot program
Programming selection (H'43)
Transfers the
programming-control
program.
ACK
Repeats the steps.
128-byte programming (address and data)
Performs
programming.
ACK
128-byte programming (address = H'FFFFFFFF)
ACK
Figure 7.10 Programming Sequence
2. Erasure
Erasure is performed by using the erasure selection command and the block erasure command.
First, select erasure by the erasure selection command and then actually erase a specific block
using the block erasure command. To erase multiple blocks, repeatedly send block erasure
commands. To terminate erasure, the host should send the block erasure command with block
number H'FF. On completion of erasure, the boot program waits for the next
programming/erasure selection command.
The sequence of erasure by the erasure selection command and block erasure command is
shown in figure 7.11.
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Host
Boot program
Erasure selection (H'48)
Transfers the erasurecontrol program.
ACK
Block erasure (block number)
Repeats the steps.
Performs erasure.
ACK
Block erasure (block number = H'FF)
ACK
Figure 7.11 Erasure Sequence
(a)
Selection of User-Rom Area Programming
In response to the command for selection of user-ROM area programming, the boot program
transfers the relevant programming-control program according to which the user ROM area is
programmed.
Command
H'43
• Command H'43 (1 byte): Selection of programming the user ROM area
Response
H'06
• Response H'06 (1 byte): Response to the user-ROM-area programming selection command.
The ACK code is returned upon completion of transferring the programming-control program.
Error response
H'C3
ERROR
• Error response H'C3 (1 byte): Error response to the user-ROM-area programming selection
command
• ERROR (1 byte): Error code
H'54: Selection processing error (processing was not completed because of a transfer error)
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(b)
128-Byte Programming
In response to the 128-byte programming command, the boot program programs the user ROM
area according to the programming-control program transferred in response to the user-ROM-area
programming selection command.
Command
H'50
Address
Data
…
…
SUM
• Command H'50 (1 byte): 128-byte programming
• Address for programming (4 bytes): Address at which programming starts
The address should be the multiple of the size returned in response to the programming-size
inquiry command.
[Example] H'00, H01, H'00, H'00: H'00010000
• Programming data (128 bytes): Data for programming
The size of the programming data is the size returned in response to the programming-size
inquiry command.
• SUM (1 byte): Checksum
Response
H'06
• Response H'06 (1 byte): Response to the 128-byte programming command.
The ACK code is returned upon completion of the requested programming.
Error response
H'D0
ERROR
• Error response H'D0 (1 byte): Error response to the 128-byte programming command
• ERROR (1 byte): Error code
H'11: Checksum error
H'53: Programming error (programming failed because of an error in programming)
The specified address should be on a boundary corresponding to the unit of programming
(programming size). For example, when the programming size is 128 bytes, the lower 8 bits of the
address should be either H'00 or H'80. When less than 128 bytes of data are to be programmed, the
host should transmit the data after padding the vacant bytes with H'FF.
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To terminate programming, send the 128-byte programming command with H'FFFFFFFF in the
address-for-programming field. This informs the boot program that the data has been completely
sent; the boot program then waits for the next programming/erasure selection command.
Command
H'50
Address
SUM
• Command H'50 (1 byte): 128-byte programming
• Address for programming (4 bytes): Terminating code (H'FF, H'FF, H'FF, H'FF)
• SUM (1 byte): Checksum
Response
H'06
• Response H'06 (1 byte): Response to the 128-byte programming command.
The ACK code is returned upon termination of the programming process.
Error response
H'D0
ERROR
• Error response H'D0 (1 byte): Error response to the 128-byte programming command
• ERROR (1 byte): Error code
H'11: Checksum error
H'53: Programming error (programming failed because of an error in programming)
(c)
Erasure Selection
In response to the erasure selection command, the boot program transfers the relevant erasurecontrol program. The data in the user ROM area is erased using the transferred erasure-control
program.
Command
H'48
• Command H'48 (1 byte): Erasure selection
Response
H'06
• Response H'06 (1 byte): Response to the erasure selection command.
The ACK code is returned upon completion of transferring the erasure-control program.
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Error response
H'C8
ERROR
• Error response H'C8 (1 byte): Error response to Erasure selection command
• ERROR (1 byte): Error code
H'54: Selection processing error (processing was not completed because of a transfer error)
(d)
Block Erasure
In response to the block erasure command, the boot program erases the data in the specified block.
Command
•
•
•
•
H'58
Size
Block
number
SUM
Command H'58 (1 byte): Block erasure
Size (1 byte): The number of characters in the block-number field (fixed to 1)
Block number (1 byte): The number specific to the block to be erased
SUM (1 byte): Checksum
Response
H'06
• Response H'06 (1 byte): Response to the block erasure command.
The ACK code is returned when the specified block has been erased.
Error response
H'D8
ERROR
• Error response H'D8 (1 byte): Error response to the block erasure command
• ERROR (1 byte): Error code
H'11: Checksum error
H'29: Block number error (the specified block number is incorrect)
H'51: Erasure error (an error occurred during erasure)
On receiving the command with H'FF as the block number, the boot program terminates erasure
processing and waits for the next programming/erasure selection command.
Command
H'58
Size
Block
number
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SUM
Section 7 ROM
•
•
•
•
Command H'58 (1 byte): Block erasure
Size (1 byte): The number of characters in the block number field (fixed to 1)
Block number (1 byte): H'FF (erasure terminating code)
SUM (1 byte): Checksum
Response
H'06
• Response H'06 (1 byte): Response to the block erasure command for terminating erasure
processing; ACK code is returned upon termination of the erasure process.
To perform erasure again after issuing the command with H'FF as the block number, start the
process by sending an erasure selection command.
(e)
Memory Reading
In response to the memory reading command, the boot program returns the data stored in the
specified address.
Command
H'52
Size
Area
Reading size
Address for reading
SUM
• Command H'52 (1 byte): Memory reading
• Size (1 byte): The total size of the area, address-for-reading, and reading-size fields (fixed to 9)
• Area (1 byte):
H'01: User ROM area
Specifying an incorrect area causes an address error.
• Address for reading (4 bytes): Address where reading starts
• Reading size (4 bytes): The amount of data to be read
• SUM (1 byte): Checksum
Response
H'52
Reading address
Data
…
SUM
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Section 7 ROM
•
•
•
•
Response H'52 (1 byte): Response to the memory reading command
Reading size (4 bytes): The amount of data to be read
Data (128 bytes): The specified amount of data to be read out starting at the specified address
SUM (1 byte): Checksum
Error response
H'D2
ERROR
• Error response H'D2 (1 byte): Error response to the memory reading command
• ERROR (1 byte): Error code
H'11: Checksum error
H'2A: Address error (the specified address for reading is not in the MAT)
H'2B: Size error (the specified size (amount) is greater than the size of the MAT)
(f)
Sum Checking of User ROM Area
In response to the command for sum checking of the user ROM area, the boot program adds all the
data bytes in the user ROM area and returns the result.
Command
H'4B
• Command H'4B (1 byte): Sum checking of the user ROM area
Response
H'5B
Size
Checksum for the MAT
SUM
• Response H'5B (1 byte): Response to the command for sum checking of the user ROM area
• Size (1 byte): The number of characters in the checksum-for-the-MAT field (fixed to 4)
• Checksum for the MAT (4 bytes): Result of checksum calculation for the user ROM area; the
total of all the data in the MAT, in byte units.
• SUM (1 byte): Checksum (for this response)
(g)
Blank Checking of User ROM Area
In response to the command for blank checking of the user ROM area, the boot program checks to
see if the whole area of the user ROM area is blank and returns the result.
Command
H'4D
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• Command H'4D (1 byte): Blank checking of the user ROM area
Response
H'06
• Response H'06 (1 byte): Response to the command for blank checking of the user ROM area.
The ACK code is returned when the whole area is blank (all bytes are H'FF).
Error response
H'CD
H'52
• Error response H'CD (1 byte): Error response to the command for blank checking of the user
ROM area
• Error code H'52 (1 byte): Non-erased error
(h)
Inquiry about Boot Program State
In response to the command for inquiry about the boot program state, the boot program returns its
current state and error information. This inquiry can be made either in the inquiry/selection state
or the programming/erasure state.
Command
H'4F
• Command H'4F (1 byte): Inquiry about boot program state
Response
H'5F
Size
STATUS ERROR
SUM
•
•
•
•
Response H'5F (1 byte): Response to the inquiry about boot program state
Size (1 byte): The number of characters in the STATUS and ERROR fields (fixed to 2)
STATUS (1 byte): State of the boot program
ERROR (1 byte): Error information
ERROR = 0: Success
ERROR ≠ 0: Error
• SUM (1 byte): Checksum
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Section 7 ROM
Table 7.7
State Codes
Code
Description
H'11
Waiting for device selection
H'12
Waiting for clock mode selection
H'13
Waiting for bit rate selection
H'1F
Waiting for transition to programming/erasure state (bit rate selection completed)
H'31
Programming or erasure state (programming/erasure in progress)
H'3F
Waiting for programming/erasure selection (erasure completed)
H'4F
Waiting to receive data for programming (programming completed)
H'5F
Waiting for erasure block specification (erasure completed)
Table 7.8
Error Codes
Code
Description
H'00
No error
H'11
Checksum error
H'12
Programming size error
H'21
Device-code disagreement error
H'22
Clock-mode disagreement error
H'24
Bit-rate selection disable error
H'25
Input frequency error
H'26
Frequency division ratio error
H'27
Operating frequency error
H'29
Block number error
H'2A
Address error
H'2B
Data size error
H'51
Erasure error
H'52
Non-erased error
H'53
Programming error
H'54
Selection processing error
H'80
Command error
H'FF
Bit-rate-adjustment acknowledge error
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Section 7 ROM
7.5.3
Programming/Erasing in User Mode
On-board programming/erasing of individual flash memory blocks is also possible in user mode
by branching to the user programming/erasure-control program. The user must set the branching
conditions and provide the on-board means of supplying the programming data. The flash memory
must contain the user programming/ erasure-control program or a program that allows the user
programming/erasure-control program to be supplied externally. As the flash memory itself cannot
be read during programming/erasing, transfer the user programming/erasure-control program to
the on-chip RAM to execute, as in boot mode. Figure 7.12 shows a sample procedure for
programming/erasing in user mode. Prepare user programming/erasure-control program in
accordance with the description in section 7.6, Programming/Erasing.
Reset-start
No
Programming/erasing
Yes
Transfer the programming/erasurecontrol program to RAM.
Branch to the application program
in flash memory.
Branch to the programming/erasurecontrol program in RAM.
Execute the programming/erasurecontrol program (reprogram the flash
memory).
Branch to the application program
in flash memory.
Figure 7.12 Sample Programming/Erasing Procedure in User Mode (EW0 Mode)
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7.6
Programming/Erasing
The CPU reprogramming method is employed to program and erase flash memory on board, in
which the CPU executes software commands.
7.6.1
Software Commands
Table 7.9 shows a list of software commands through word instructions and table 7.10 shows a list
of software commands through byte instructions. Whether an instruction is to be byte-length or
word-length is specified by the FMWUS bit in FLMCR1.
Table 7.9
Software Commands (in Word Instructions: FMWUS = 1)
First Command
Cycle
Second
Command Cycle
Third Command Command Use in
Cycle
Modes
Software
Command
Mode Addr. Data
Mode Addr. Data
Erasure
Write ×
H'2020
Write BA
H'D0D0
Programming
Write WA
H'4141
Write WA
WD1 Write WA
Blank checking
Write ×
H'2525
Write BA
H'D0D0
Possible Possible
Lock-bit
programming
Write ×
H'7777
Write BA
H'D0D0
Possible Possible
Read-array
Write ×
H'FFFF
Possible 
Clear-status
Write ×
H'5050
Possible Possible
Lock-bit reading
Write ×
H'7171
Read BA
H'xxxx
Mode Addr. Data
EW0
EW1
Possible Possible
WD2 Possible Possible
Possible
Impossible
[Legend]
×:
Arbitrary address in the user ROM area
xx:
Eight-bit arbitrary data
BA:
Arbitrary address in a block
WA:
Programming address. (The lower two bits of an address are ignored. WA should be the
same in each command cycle.)
WDn: Programming data (16 bits)
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Section 7 ROM
Table 7.10 Software Commands (in Byte Instructions: FMWUS = 0)
First Command
Cycle
Third Command
Second
to Fifth
Command Use in
Command Cycle Command Cycle
Modes
Software
Command
Mode Addr. Data
Erasure
Write ×
H'20 Write BA
H'D0
Programming
Write WA
H'41 Write WA
WD1 Write WA
Blank checking
Write ×
H'25 Write BA
H'D0
Possible Possible
Lock-bit
programming
Write ×
H'77 Write BA
H'D0
Possible Possible
Read-array
Write ×
H'FF
Possible 
Clear-status
Write ×
H'50
Possible Possible
Lock-bit reading
Write ×
H'71 Read BA
Mode Addr. Data
H'xx
Mode Addr. Data
EW0
EW1
Possible Possible
WD2 Possible Possible
to
WD4
Possible
Impossible
[Legend]
×:
Arbitrary address in the user ROM area
xx:
Eight-bit arbitrary data
BA:
Arbitrary address in a block
WA:
Programming address. (The lower two bits of an address are ignored. WA should be the
same in each command cycle.)
WDn: Programming data (8 bits)
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Section 7 ROM
(1)
Initialization for CPU Reprogramming Mode
Before software commands are issued, settings for CPU reprogramming mode must be made and
issuing of software commands must be permitted.
Figure 7.13 shows initialization for CPU reprogramming mode.
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Section 7 ROM
Flow of initialization for EW0 mode*1
1
Start
Transfer the overwriting
program to RAM.
Command issued for
the program region?
No
Yes
Set the interrupt vector offset by
VOFR and place the interrupt
vectors in RAM.*1
FMLBD = 1
Command issued
for data flash?
Jump to the overwriting
program in RAM.
No
Yes
DFPR[x] = 0*2
FMEWMOD = 0
To processing for issuing
commands
FMCMDEN = 1
1
Flow of initialization for EW1 mode*1
Start
FMEWMOD = 1
FMCMDEN = 1
Command issued for
the program region?
No
Yes
FMLBD = 1
Command issued
for data flash?
No
Yes
DFPR[x] = 0*2
To processing for issuing
commands
Notes: For any interrupts that are in use, allocate the interrupt vector entries and interrupt routines to RAM.
If interrupts are not to be used, allocation to RAM is not necessary.
1. Within the flow, set the CPU overwriting unit selection bit (FMWUS) to select the unit of overwriting.
2. Set the DFPR according to the area of data-flash memory for which commands are to be issued.
Figure 7.13 Initialization for E/W Mode
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Section 7 ROM
(2)
Erasure
When H'20 is written in the first command cycle and H'D0 is written to any address in the block in
the second command cycle, erase/erase-verify of the specified block is automatically started.
Completion of erasure is indicated by the FMRDY bit in FLMSTR. The FMRDY bit is read as 0
during erasure, and read as 1 after erasure completion.
After erasure completion, the erasure result can be checked by reading the FMEBSF bit in
FLMSTR. (See the description in (9) below, Full Status Checking.)
Note that if the lock bit is 0 (locked) in the specified block and the FMLBD bit is 0 (lock bit
enabled), an erasure command is not accepted for the specified block.
Figures 7.14 and 7.15 show the flowcharts when the erase-suspend function is not used and when
used, respectively.
When the erase-suspend function is being employed and erasure is resumed immediately after a
period in erase-suspend mode, instruction fetching with normal incrimination of the program
counter will not be possible. To avoid this problem, add two NOP instructions immediately after
the instruction that writes FMSPRE = 0. Furthermore, do not use the DTC when erasure has been
suspended in EW1 mode and the reprogramming control program has been allocated to RAM.
In EW1 mode, do not execute this command for the block in which the reprogramming-control
program is located.
The FMRDY bit in FLMSTR changes to 0 when erasure is started, and changes to 1 when
completed.
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Section 7 ROM
Start
Write software command H'20.
Write H'D0 to any address
in the specified block.
FMRDY = 1?
No
Yes
Full status check
Erasure end
Figure 7.14 Flowchart When Erase-Suspend Function is Not Used
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Section 7 ROM
(EW0 mode)
Interrupt request*1*2
Start
FMSPEN = 1
FMSPREQ = 1
Write software command H'20.
FMRDY = 1?
No
Yes
Write H'D0 to any address
in the specified block.
Access to flash memory
FMSPREQ = 0
FMRDY = 1?
No
RTE
Yes
Full status check
Erasure end
(EW1 mode)
Interrupt request*2
Start
Access to flash memory
FMSPEN = 1
RTE
Write software command H'20.
Write H'D0 to any address
in the specified block.
FMSPREQ = 0
NOP
NOP
FMRDY = 1?
No
Yes
Full status check
Erasure end
Notes: 1. In EW0 mode, set VOFR and, locate the vector and handling routines of the used interrupts in the RAM.
2. When an interrupt request is generated, it takes the transition time to erase-suspend mode for the request to be accepted.
To allow a transition to the erase-suspend state, enable the relevant interrupt beforehand.
Figure 7.15 Flowchart When Erase-Suspend Function is Used
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Section 7 ROM
(3)
Programming
A program command is used to program data in the flash memory in 4-byte units.
Command or data size can be set depending on the FMWUS bit in FLMCR1. Setting the FMWUS
bit to 0 enables using byte instructions. When H'41 is written in the first command cycle and data
is written to the programming address in the second through fifth command cycles, programming
and verifying are automatically started*.
Setting the FMWUS bit to 1 enables using word instructions. When H'4141 is written in the first
command cycle and data is written to the programming address in the second and third command
cycles, programming and verifying are started*.
Completion of programming is indicated by the FMRDY bit in FLMSTR. The FMRDY bit is read
as 0 during programming, and read as 1 after programming completion.
After programming completion, the programming result can be checked by reading the FMPRSF
bit in FLMSTR. (See the description in (9) below, Full Status Checking.)
Figure 7.16 shows the programming flowchart.
Do not additionally program the already-programmed addresses.
Note that if the lock bit is 0 (locked) in the specified block and the FMLBD bit is 0 (lock bit
enabled), a programming command is not accepted for the specified block.
In EW1 mode, do not execute this command for the block in which the reprogramming-control
program is located.
The FMRDY bit in FLMSTR changes to 0 when programming is started, and changes to 1 when
completed.
Note: * The lower two bits of the programming addresses are ignored.
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Section 7 ROM
Start
Write software command H'41 to
the programming address.
Write data to the programming address.
FMRDY = 1?
No
Yes
Full status check
Programming end
Figure 7.16 Programming Flowchart
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Section 7 ROM
(4)
Blank Checking
When H'25 is written in the first command cycle and H'D0 is written to any address in the block in
the second command cycle, blank checking of the specified block is started.
Completion of blank checking is indicated by the FMRDY bit in FLMSTR. The FMRDY bit is
read as 0 during blank checking, and read as 1 after blank checking completion.
After blank checking completion, the blank checking result can be checked by reading the
FMEBSF bit in FLMSTR. (See the description in (9) below, Full Status Checking.)
Figure 7.17 shows the blank checking flowchart.
The FMRDY bit in FLMSTR changes to 0 when blank checking is started, and changes to 1 when
completed.
Start
Write software command H'25.
Write H'D0 to an address
in the specified block.
FMRDY = 1?
No
Yes
Full status check
Blank checking end
Figure 7.17 Blank Checking Flowchart
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Section 7 ROM
(5)
Lock-Bit Programming
When H'77 is written in the first command cycle and H'D0 is written to any address in the block in
the second command cycle, lock-bit programming of the specified block is started.
Completion of lock-bit programming is indicated by the FMRDY bit in FLMSTR. The FMRDY
bit is read as 0 during lock-bit programming, and read as 1 after lock-bit programming completion.
After lock-bit programming completion, the lock-bit programming result can be checked by
reading the FMPRSF bit in FLMSTR. (See the description in (9) below, Full Status Checking.)
Figure 7.18 shows the lock-bit programming flowchart.
The FMRDY bit in FLMSTR changes to 0 when lock-bit programming is started, and changes to 1
when completed.
Start
Write software command H'77.
Write H'D0 to an address
in the specified block.
FMRDY = 1?
No
Yes
Full status check
Lock-bit programming end
Figure 7.18 Lock-Bit Programming Flowchart
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Section 7 ROM
(6)
Read-Array Command
A read-array command is to cause a transition to a mode in which data can be read from flash
memory.
When H'FF is written in the first command cycle, a transition to read array mode is caused. When
the specified addresses are read out in the subsequent command cycles, data is read from the
specified addresses.
Since read-array mode is retained until any other command is written, multiple addresses can be
read successively.
(7)
Lock-Bit Reading Command
A lock-bit reading command is to cause a transition to a mode in which the lock bit in flash
memory can be read.
When H'71 is written in the first command cycle and H'D0 is written to any address in the block in
the second command cycle, lock-bit reading of the specified block is started.
After transition to lock-bit read mode, reading the specified block address BA returns the lock-bit
value in the bit 14 value to be read. Do not execute a lock-bit read command in the ROM.
(8)
Status Clearing Command
A clear-status command is used to clear the status flag to 0.
When H'50 is written in the first command cycle, the FMPRSF and FMEBSF bits in FLMSTR are
cleared to 0.
(9)
Full Status Checking
When any command (other than the read-array command, lock bit reading command and clearstatus command) is issued, full-status checking is performed to confirm whether or not there was
an error.
When an error occurs, the FMPRSF and FMEBSF bits in FLMSTR are set to 1, indicating the
occurrence of the relevant errors.
Table 7.11 shows the bit values in FLMSTR and the corresponding errors. Figure 7.19 shows the
full status checking flowchart and procedures of handling each error.
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Section 7 ROM
Table 7.11 Bit Values in FLMSTR and Corresponding Errors
Bit Values in FLMSTR
FMEBSF
FMPRSF
Error
Error Generation Conditions
0
0
Successful end
0
1
Programming error
The programming command is
executed and results in
unsuccessful programming.
Lock-bit programming error
The lock-bit programming
command is executed and
results in unsuccessful
programming.
Erasure error
The erasure command is
executed and results in
unsuccessful erasure.
Blank checking error
The blank checking command
is executed and it is detected
that the specified block is not
blank.
Command sequence error
•
A command is not written
correctly.
•
A data value other than
H'D0 and H'FF is written in
the last cycle of the
command that consists of
two command cycles.
•
The erasure command is
input in erase-suspend
mode.
•
The programming command
is input for the suspended
block in erase-suspend
mode.
1
1
0
1
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Section 7 ROM
Full status check
FMEBSF = 1
and
FMPRSF = 1
Yes
Command sequence error
No
Erasure/blank-checking status flag
FMEBSF = 1
Yes
Erasure error
or
blank checking error
Yes
Programming error
or
lock-bit programming error
No
Programming status flag
FMPRSF = 1
Full status check end
Command sequence error
Erasure error
Execute the clear-status command.
(Clear the status flag to 0).
Execute the clear-status command.
(Clear the status flag to 0).
Check that the command is input correctly.
Has the erase command been
re-executed three or less times?
The target block is unavailable.
Re-execute the erasure command.
Re-execute the erasure command.
Programming error
Lock-bit programming error
Execute the clear-status command.
(Clear the status flag to 0).
Execute the clear-status command.
(Clear the status flag to 0).
Specify the different address from the address
having caused an error as the
programming address.
Has the lock-bit programming
command been executed
1000 or less times in total?
Re-execute the erasure command.
The target block is unavailable.
Re-execute the lock-bit programming
command.
Figure 7.19 Full Status Checking Flowchart and Procedures of Handling Errors
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Section 7 ROM
(10) Example of Issuing Commands
Figures 7.20 and 7.21 show examples of issuing programming commands and erasure commands,
respectively. Figure 7.22 shows examples of issuing read-array commands.
Using word-length instructions to issue programming commands (FMWUS = 1)
Target address
for writing
Data
H'004000
H'12
H'004001
H'34
H'004002
H'56
H'004003
H'78
[Programming Example]
@MOV.W #H'4141,R0
@MOV.W #H'1234,R1
@MOV.W #H'5678,R2
@MOV.W R0, @H'00004000
@MOV.W R1, @H'00004000
@MOV.W R2, @H'00004000
; Programming command
; Writing of data
; Writing of data
; First command
; Second command
; Third command
Prefetching and other
Prefetching and other
internal processing
internal processing
Issuing of third Programming of flash
Issuing of second
Issuing of first
command
ROM starts
command
command
Internal address bus
Internal data bus
H'004000
H'004000
H'004000
H'4141
H'1234
H'5678
Using byte-length instructions to issue programming commands (FMWUS = 0)
Target address
for writing
Data
H'004000
H'12
H'004001
H'34
H'004002
H'56
H'004003
H'78
[Programming Example]
@MOV.B #H'41, R0L
@MOV.W #H'1234,R1
@MOV.W #H'5678,R2
@MOV.B R0L, @H'00004000
@MOV.B R1H, @H'00004000
@MOV.B R1L, @H'00004000
@MOV.B R2H, @H'00004000
@MOV.B R2L, @H'00004000
; Programming command
; Writing of data
; Writing of data
; First command
; Second command
; Third command
; Fourth command
; Fifth command
Prefetching and other
Prefetching and other
Prefetching and other Prefetching and other
internal processing
internal processing
internal processing
internal processing
Issuing of fourth
Issuing of fifth
Issuing of first
Issuing of second
Issuing of third
command
command
command
command
command
Internal address
bus
H'004000
H'004000
H'004000
H'004000
H'004000
Internal data bus
H'41
H'12
H'34
H'56
H'78
Figure 7.20 Examples of Issuing Programming Commands
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Programming
of flash ROM
starts
Section 7 ROM
Using word-length instructions to issue erasure commands (FMWUS = 1)
[Erasure Setting]
Erasure block = Data flash A
[Programming Example]
@MOV.W
@MOV.W
@MOV.W
@MOV.W
#H'2020,R0
#H'D0D0,R1
R0,@H'00F00000
R1,@H'00F00000
Prefetching and other
internal processing
Issuing of first
Issuing of second
command
command
Internal address bus
Internal data bus
H'F00000
H'F00000
H'2020
H'D0D0
; Erasure command
; Erasure command
; First command
; Second command
Programming of flash
ROM starts
Using byte-length instructions to issue erasure commands (FMWUS = 0)
[Erasure Setting]
Erasure block = Data flash A
[Programming Example]
@MOV.B
@MOV.B
@MOV.B
@MOV.B
#H'20, R0L
#H'D0, R0H
R0L,@H'00F00000
R0H,@H'00F00000
; Erasure command
; Erasure command
; First command
; Second command
Prefetching and other
internal processing
Issuing of second Programming of flash
Issuing of first
command
command
ROM starts
Internal address bus
Internal data bus
H'F00000
H'F00000
H'20
H'D0
Figure 7.21 Examples of Issuing Erasure Commands
Rev. 1.00 Oct. 03, 2008 Page 223 of 962
REJ09B0465-0100
Section 7 ROM
Using word-length instructions to issue read-array commands (FMWUS = 1)
[Read-Array Setting]
Address = Program-ROM area
[Programming Example]
; Read-array command
@MOV.W #H'FFFF, R0
@MOV.W R0, @H'00000000 ; First command
Issuing of first command
Address bus
Data bus
Reading can proceed.
H'000000
H'FFFF
Using byte-length instructions to issue read-array commands (FMWUS = 0)
[Read-Array Setting]
Address = Program-ROM area
[Programming Example]
; Read-array command
@MOV.B #H'FF, R0L
@MOV.B R0L,@H'00000000 ; First command
Issuing of first command
Address bus
Reading can proceed.
H'000000
Data bus
H'FF
Figure 7.22 Examples of Issuing Read-Array Commands
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REJ09B0465-0100
Section 7 ROM
7.7
Protection
Three modes are available to protect the flash memory against reading, programming, and erasing:
software protection, lock-bit protection, and protection to restrict access in programmer mode and
boot mode.
7.7.1
Software Protection
Software commands can be disabled by clearing the FMCMDEN bit in the flash memory control
register (FLMCR1) through software. In this state, no software commands are executed even if
input.
Data flash areas can be protected in block units by using the flash memory data flash protect
register (DFPR). Setting bits DFPR1 and DFPR0 in DFPR to 1 places all the data flash areas in
protect mode.
7.7.2
Lock-Bit Protection
The programming/erasure commands can be disabled by programming the lock bits using the
lock-bit programming command. In this state, the erasure/programming commands are not
executed even if input. This prevents flash memory from being erroneously erased or programmed
due to CPU runaway.
The protection function can be temporarily disabled by setting the FMLBD bit in FLMCR1 to 1.
To clear the lock bit, erase the specified block. Note that lock bits are unavailable in data flash
areas.
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Section 7 ROM
7.7.3
PROM Programmer Protection/Boot Mode Protection
PROM programmer protection/boot mode protection is enabled by writing the specified data to the
user ROM area shown in the table 7.12.
The protection function can be disabled by using a PROM programmer or on-board programmer
to delete the entire user ROM area.
Table 7.13 shows the specifications for PROM programmer protection and table 7.14 shows the
specifications of protection in boot mode.
Table 7.12 Address Range of the Protection Code in User ROM
H'000004 H'000005 H'000006 H'000007 H'000010 H'000011 H'000012 H'000013
PROM
programmer
Control
code
Boot mode
Not used
Authentication ID code (56 bits)
Table 7.13 Specifications for PROM Programmer Protection
Control code*
Protection State
Operation to be Carried Out
H'FF
PROM programmer protection
is disabled.
Possible operations; reading/programming/
erasing by PROM programmer.
Other than above PROM programmer protection
is enabled.
Note:
*
Possible operations; programming/erasing by
PROM programmer.
However, reading is not possible.
Used together with control code for boot mode protection.
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REJ09B0465-0100
Section 7 ROM
Table 7.14 Specifications for Boot Mode Protection
Control code* Protection State
Operation in Serial Connection
Other than
above
Protection is disabled.
Entire blocks are deleted.
H'45
ID authentication protection 1*2
Possible for reading/programming/erasing if
the ID was authenticated.
If the ID was not authenticated, entire blocks
are deleted.
H'52
ID authentication protection 2
Possible for reading/programming/erasing if
the ID was authenticated.
If the ID was not authenticated, authentication
is performed again.
ID authentication protection 2+*3
If control code is H'52 and the special code
(H'50, H'72, H'6F, H'74, H'65, H'63 and H'74)
is written to the authentication ID bytes,
processing for serial connections will not be
accepted.
Note:
7.8
1. Used together with the control code for the PROM programmer.
2. Re-authentication can be performed up to 3 times in case of error in the ID code.
3. Once this setting has been made, serial connections are not accepted unless a PROM
programmer is used to delete the setting.
Programmer Mode
In programmer mode, flash memory areas can be programmed/erased using a PROM programmer
via a socket adapter, just as a discrete flash memory can be. Use the PROM programmer that
supports the Renesas Technology microcomputer device type with the on-chip 128-kbyte flash
memory.
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Section 7 ROM
7.9
Usage Notes
(1)
Prohibited Instruction
In EW0 mode, the following instruction cannot be used because it refers to the data in the flash
memory area.
• TRAP
(2)
Interrupts
Table 7.15 shows interrupt handling in CPU reprogramming mode.
Table 7.15 Interrupt Handling in CPU Reprogramming Mode
Mode State
EW0
When Watchdog Timer Reset,
LVD Reset, Software Reset, or
When Interrupt Request is Pin Reset, Interrupt Request is
Received
Generated
During erasure command Interrupts can be handled if
interrupt vectors are located
During programming
in the RAM. For details, see
command
section 4.2.7, Interrupt
During lock-bit
vector offset register
programming command
(VOFR).
During blank checking
command
Immediately after a reset is
generated, a software command
is forcibly terminated, and flash
memory and LSI are reset.
Because of the forced
termination, it might be
impossible to read correct values
from the block or address for
which the software command
has been executed; execute
erasure again after restarting and
confirm that erasure is completed
successfully.
The watchdog timer does not
stop even during command
execution; initialize the timer
periodically.
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Section 7 ROM
Mode State
EW1
When Watchdog Timer Reset,
LVD Reset, Software Reset, or
When Interrupt Request is Pin Reset, Interrupt Request is
Received
Generated
During erasure command Erasure is given priority,
(erase-suspend function keeping the interrupt
not used)
request waiting. When
erasure is completed,
execution of the interrupt
processing is started.
Immediately after a reset is
generated, a software command
is forcibly terminated, and flash
memory and LSI are reset.
During erasure command After the transition time to
(erase-suspend function erase-suspend mode,
used)
erasure is suspended
starting execution of the
interrupt processing. When
the interrupt processing is
completed, setting the
FMSPREQ bit in FLMCR2
to 0 resumes erasure.
During programming
command
During lock-bit
programming command
During blank checking
command
(3)
A software command is
given priority, keeping the
interrupt request waiting.
When the software
command is completed,
execution of the interrupt
processing is started.
Because of the forced
termination, it might be
impossible to read correct values
from the block or address for
which the software command
has been executed; execute
erasure again after restarting and
confirm that erasure is completed
successfully.
Since the watchdog timer does
not stop even during command
execution, set the overflow time
of the watchdog timer longer
than the erasure/programming
execution time.
Method of Access
When writing values to the protected bits indicated below, start by writing 0 to the bit and then
write 1 to it or by writing 1 to the bit and then write 0 to it. Do not allow the generation of any
interrupt or any access to other I/O registers between the two operations. For writing, always use
the MOV instruction.
(a)
Bits that are set to 1 by writing 0 and then 1 consecutively
• FLMCR1: FMLBD and FMCMDEN bits
• FLMCR2: FMISPE and FMSPEN bits
(b)
Bits that are cleared to 0 by writing 1 and then 0 consecutively
• DFPR: DFPR1 and DFPR0 bits
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Section 7 ROM
The example below is of code for use when the FMCMDEN and FMLBD bits in FLMCR1 are to
be changed from 0 to 1.
MOV.B
@FLMCR1,R0L
:FLMCR1=H'04
R0L=H'04
R0H=H'xx
MOV.B
@FLMCR1,R0H
:FLMCR1=H'04
R0L=H'04
R0H=H'04
BSET
#0,R0H
:FLMCR1=H'04
R0L=H'04
R0H=H'05
BSET
#3,R0H
:FLMCR1=H'04
R0L=H'04
R0H=H'0D
MOV.B
R0L,@FLMCR1
:FLMCR1=H'04
R0L=H'04
R0H=H'0D
MOV.B
R0H,@FLMCR1
:FLMCR1=H'0D
R0L=H'04
R0H=H'0D
(4)
Reprogramming User ROM Area
When it is necessary to reprogram the block containing the reprogramming-control program, use
boot mode. This is because if the power supply voltage drops in EW0 mode while the block
containing the reprogramming-control program is being reprogrammed, the reprogrammingcontrol program cannot be correctly reprogrammed, and this might disable further reprogramming
of the flash memory. Only proceed with overwriting of the programming-control program after
securing ample stabilization time for the power supply.
(5)
Program
Do not program the already-programmed addresses.
(6)
LSI Mode Transition
During software command execution, do not cause a transition to standby mode or sleep mode.
(7)
Reset during Execution of Software Command in Flash Memory
Do not apply a pin reset, LVD reset, or watchdog timer reset during execution of the
programming, lock-bit programming, blank-checking, and erasure commands. If applied, the
currently executed command is forcibly terminated. In this case, execute the erasure command of
the specified block again and confirm that erasure is completed successfully.
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Section 8 RAM
Section 8 RAM
The H8S/20103, H8S/20203, and H8S/20223 Group LSIs have an on-chip high-speed static RAM.
The RAM is connected to the CPU via a 16-bit data bus, enabling the CPU to access both byte
data and word data in one state.
Product Classification
Flash memory version
64 pins
80 pins
RAM Size
RAM Address
H8S/20103
8 kbytes
H'FFDF80 to H'FFFF7F
H8S/20102
8 kbytes
H'FFDF80 to H'FFFF7F
H8S/20223
8 kbytes
H'FFDF80 to H'FFFF7F
H8S/20222
8 kbytes
H'FFDF80 to H'FFFF7F
H8S/20203
8 kbytes
H'FFDF80 to H'FFFF7F
H8S/20202
8 kbytes
H'FFDF80 to H'FFFF7F
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Section 8 RAM
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Section 9 Peripheral I/O Mapping Controller
Section 9 Peripheral I/O Mapping Controller
The peripheral function mapping controller (PMC) is composed of registers that are used to select
the functions of multiplexed pins. The multiplexed pins are divided into two groups: group 1 and
group 2. Group 1 consists of ports 1 to 3, 5, and 6, and group 2 consists of ports 8, 9*, and A.
Tables 9.1 and 9.2 list the functions of the multiplexed pins in each group.
Note: Port 9 is not available on the H8S/20103 group.
Table 9.1
Multiplexed Pin Functions (Ports 1, 2, 3, 5, and 6)
Group 1
Pin
Name
Function 1
Function 2
Port 1
Pm7
IRQ7 input
TXD_2 output TXD_3 output SCL/SSI
input/output
FTIOD1
ADTRG2
input/output input
Pm6
IRQ6 input
RXD_2 input
RXD_3 input
SDA/SCS
input/output
FTIOC1
ADTRG1
input/output input
Pm5
IRQ5 input
SCK3_2
input/output
SCK3_3
input/output
SSCK
input/output
FTIOB1
TRDOI_1
input/output input
Pm4
IRQ4 input
TRDOI_0
input
FTCI input*
SSO
input/output
FTIOA1
TRAIO
input/output input/output
Pm3
IRQ3 input
TRCOI input* FTIOD
TGIOB
input/output* input/output
FTIOD0
TRAO output
input/output
Pm2
IRQ2 input
TXD output
FTIOC
TGIOA
input/output* input/output
FTIOC0
TRBO output
input/output
Pm1
IRQ1 input
RXD input
FTIOB
TCLKB input
input/output*
FTIOB0
TRGB input
input/output
Pm0
IRQ0 input
SCK3
input/output
FTIOA
TCLKA input
input/output*
FTIOA0
TREO output
input/output
Port 1
Port 2
Port 3
Port 6
Port 2
Port 3
Port 5
Port 6
Initially mapped port
Function 3
Function 4
Port 5
Function 5
Function 6
None
[Legend] m = 1, 2, 3, 5 and 6
Note: The timer RC is not available on the H8S/20203 and H8S/20223 groups; therefore, the
function cannot be selected for these groups.
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Section 9 Peripheral I/O Mapping Controller
Table 9.2
Multiplexed Pin Functions (Ports 8, 9, and A)
Group 2
Pin
Name
Function 1 Function 2 Function 3 Function 4
Function 5*2 Function 6
Port 8
Pm7
IRQ7 input 
TXD output TREO
output
FTIOD3
input/output
TXD_3
output
Pm6
IRQ6 input 
RXD input
FTIOC3
input/output
RXD_3
input
Pm5
IRQ5 input 
SCK3
TRAIO
input/output input/output
FTIOB3
input/output
SCK3_3
input/output
Pm4
IRQ4 input 

TRGB input
FTIOA3
input/output

Pm3
IRQ3 input 

TRAO output FTIOD2
input/output

Pm2
IRQ2 input 


FTIOC2
input/output

Pm1
IRQ1 input 


FTIOB2
input/output

Pm0
IRQ0 input 


FTIOA2
input/output

None
None
Port 8
Port 9
None
Port 9
1
Port A*
Initially mapped
port
None
[Legend]
Note:
TRBO
output
n = 8, 9, and A
: Reserved
1. Port A is multiplexed with A/D converter analog input in the H8S/20223 group.
Therefore, the multiplexed functions cannot be selected for the port.
The PA3 to PA0 pins are multiplexed with A/D converter analog input in the H8S/20203
group. Therefore, the multiplexed functions cannot be selected for the port pins.
2. Function 5 cannot be selected for the H8S/20103 group.
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Section 9 Peripheral I/O Mapping Controller
9.1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Register Descriptions
Peripheral function mapping register write-protect register (PMCWPR)
Port 1 peripheral function mapping register 1 (PMCR11)
Port 1 peripheral function mapping register 2 (PMCR12)
Port 1 peripheral function mapping register 3 (PMCR13)
Port 1 peripheral function mapping register 4 (PMCR14)
Port 2 peripheral function mapping register 1 (PMCR21)
Port 2 peripheral function mapping register 2 (PMCR22)
Port 2 peripheral function mapping register 3 (PMCR23)
Port 2 peripheral function mapping register 4 (PMCR24)
Port 3 peripheral function mapping register 1 (PMCR31)
Port 3 peripheral function mapping register 2 (PMCR32)
Port 3 peripheral function mapping register 3 (PMCR33)
Port 3 peripheral function mapping register 4 (PMCR34)
Port 5 peripheral function mapping register 1 (PMCR51)
Port 5 peripheral function mapping register 2 (PMCR52)
Port 5 peripheral function mapping register 3 (PMCR53)
Port 5 peripheral function mapping register 4 (PMCR54)
Port 6 peripheral function mapping register 1 (PMCR61)
Port 6 peripheral function mapping register 2 (PMCR62)
Port 6 peripheral function mapping register 3 (PMCR63)
Port 6 peripheral function mapping register 4 (PMCR64)
Port 8 peripheral function mapping register 3 (PMCR83)
Port 8 peripheral function mapping register 4 (PMCR84)
Port 9 peripheral function mapping register 1 (PMCR91)*1
Port 9 peripheral function mapping register 2 (PMCR92)*1
Port 9 peripheral function mapping register 3 (PMCR93)*1
Port 9 peripheral function mapping register 4 (PMCR94)*1
Port A peripheral function mapping register 3 (PMCRA3)*2
Port A peripheral function mapping register 4 (PMCRA4)*2
Notes: 1. PMCR91 to PMCR94 are not available on the H8S/20103 group.
2. PMCRA3 and PMCRA4 are not available on the H8S/20223 group.
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Section 9 Peripheral I/O Mapping Controller
9.1.1
Peripheral Function Mapping Register Write-Protect Register (PMCWPR)
Address: H'FF0065
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
B0WI
PMCRWE






1
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
B0WI
Bit 6 write
protect
0: Writing to PMCRWE (bit 6 in this register) is
enabled.
W
1: Writing to the PMCRWE bit is disabled.
6
PMCRWE PMCR write
enable
0: Writing to PMCR is disabled.
5 to 0

These bits are always read as 0. The write value
should always be 0.
Reserved
R/W
1: Writing to PMCR is enabled.

Note: A MOV instruction should be used to rewrite this register.
• B0WI bit (Bit 6 write protect)
Only when the write value to this bit is 0, PMCRWE (bit 6 in this register) can be modified.
This bit is always read as 1.
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Section 9 Peripheral I/O Mapping Controller
9.1.2
Port Group 1
Peripheral Function Mapping Registers 1 to 4 (PMCRn1 to PMCRn4 (n = 1, 2, 3, 5,
and 6))
(1)
Port 1
(a)
Port 1 Peripheral Function Mapping Register 1 (PMCR11)
Address: H'FF0040
Bit:
b7
b6
0
b4
P11MD[2:0]

Value after reset:
b5
0
0
b3
b2
0
b0
P10MD[2:0]

1
b1
0
0
1
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is always read as 0. The write value should
always be 0.

000: Setting prohibited
R/W
6 to 4 P11MD[2:0] P11 function
select
001: IRQ1 input (initial value)
010: RXD input (SCI3_1)
011: FTIOB input/output (timer RC)*2
100: TCLKB input (timer RG)
101: FTIOB0 input/output (timer RD_0)
110: TRGB input (timer RB)
111: Setting prohibited
3

Reserved
2 to 0 P10MD[2:0] P10 function
select*1
This bit is always read as 0. The write value should
always be 0.

000: Setting prohibited
R/W
001: IRQ0 input (initial value)
010: SCK3 input/output (SCI3_1)
011: FTIOA input/output (timer RC)*2
100: TCLKA input (timer RG)
101: FTIOA0 input/output (timer RD_0)
110: TREO output (timer RE)
111: Setting prohibited
Notes: 1. For the H8S/20103 group, P10 is not provided and P10MD[2:0] are reserved. The initial
value is B'001. The write value should be B'001.
2. This function cannot be selected for the H8S/20203 and H8S/20223 groups.
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Section 9 Peripheral I/O Mapping Controller
(b)
Port 1 Peripheral Function Mapping Register 2 (PMCR12)
Address: H'FF0041
Bit:
b7
b6
0
b4
P13MD[2:0]

Value after reset:
b5
0
0
b3
b2
0
b0
P12MD[2:0]

1
b1
0
0
1
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is always read as 0. The write value should
always be 0.

000: Setting prohibited
R/W
6 to 4 P13MD[2:0] P13 function
select
001: IRQ3 input (initial value)
010: TRCOI input (timer RC)*
011: FTIOD input/output (timer RC)*
100: TGIOB input/output (timer RG)
101: FTIOD0 input/output (timer RD_0)
110: TRAO output (timer RA)
111: Setting prohibited
3

Reserved
2 to 0 P12MD[2:0] P12 function
select
This bit is always read as 0. The write value should
always be 0.

000: Setting prohibited
R/W
001: IRQ2 input (initial value)
010: TXD output (SCI3_1)
011: FTIOC input/output (timer RC)*
100: TGIOA input/output (timer RG)
101: FTIOC0 input/output (timer RD_0)
110: TRBO output (timer RB)
111: Setting prohibited
Note:
*
This function cannot be selected for the H8S/20203 and H8S/20223 groups.
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Section 9 Peripheral I/O Mapping Controller
(c)
Port 1 Peripheral Function Mapping Register 3 (PMCR13)
Address: H'FF0042
Bit:
b7
b6
0
b4
P15MD[2:0]

Value after reset:
b5
0
0
b3
b2
b0
P14MD[2:0]

1
b1
0
0
0
1
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is always read as 0. The write value should
always be 0.

6 to 4
P15MD[2:0] P15 function 000: Setting prohibited
select
001: IRQ5 input (initial value)
R/W
010: SCK3_2 input/output (SCI3_2)
011: SCK3_3 input/output (SCI3_3)
4
100: SSCK input/output* (SSU)
101: FTIOB1 input/output (timer RD_0)
110: TRDOI_1 input (timer RD_1)*
2
111: Setting prohibited
3

2 to 0
P14MD[2:0] P14 function 000: Setting prohibited
1
select*
001: IRQ4 input (initial value)
Reserved
This bit is always read as 0. The write value should
always be 0.

R/W
010: TRDOI_0 input (timer RD_0)
3
011: FTCI input (timer RC)*
4
100: SSO input/output* (SSU)
101: FTIOA1 input/output (timer RD_0)
110: TRAIO input/output (timer RA)
111: Setting prohibited
Notes: 1. For the H8S/20103 group, P14 is not provided and P14MD[2:0] are reserved. The initial
value is B'001. The write value should be B'001.
2. This function cannot be selected for the H8S/20103 group.
3. This function cannot be selected for the H8S/20203 and H8S/20223 groups.
4. If the SSCK output pin or the SSO output pin is set, the NMOS open-drain output
cannot be selected.
Rev. 1.00 Oct. 03, 2008 Page 239 of 962
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Section 9 Peripheral I/O Mapping Controller
(d)
Port 1 Peripheral Function Mapping Register 4 (PMCR14)
Address: H'FF0043
Bit:
b7
b6
0
b4
P17MD[2:0]

Value after reset:
b5
0
0
b3
b2
0
b0
P16MD[2:0]

1
b1
0
0
1
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is always read as 0. The write value should
always be 0.

000: Setting prohibited
R/W
6 to 4 P17MD[2:0] P17 function
select
001: IRQ7 input (initial value)
010: TXD_2 output (SCI3_2)
011: TXD_3 output (SCI3_3)
1
100: SSI/SCL input/output* (SSU/IIC2)
101: FTIOD1 input/output (timer RD_0)
110: ADTRG2 input (AD_2)
111: Setting prohibited
3

Reserved
2 to 0 P16MD[2:0] P16 function
select
This bit is always read as 0. The write value should
always be 0.

000: Setting prohibited
R/W
001: IRQ6 input (initial value)
010: RXD_2 input (SCI3_2)
011: RXD_3 input (SCI3_3)
1 2
100: SCS/SDA input/output* * (SSU/IIC2)
101: FTIOC1 input/output (timer RD_0)
110: ADTRG1 input (AD_1)
111: Setting prohibited
Note:
1. When the IICS/SSU is used as the IIC2 function, the SCL and SDA functions should be
allocated to the P56 and P57 pins because SCL and SDA require buffers dedicated for
2
IIC input/output. When the ICSU is used for the SSU function except * , there is no
restriction.
2. If the SCS output pin of the SSU is set, the NMOS open-drain output cannot be
selected.
Rev. 1.00 Oct. 03, 2008 Page 240 of 962
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Section 9 Peripheral I/O Mapping Controller
(2)
Port 2
(a)
Port 2 Peripheral Function Mapping Register 1 (PMCR21)
Address: H'FF0044
Bit:
b7
b6
Value after reset:
0
b5
b4
P21MD[2:0]

0
1
b3
b2
0
0
b1
b0
P20MD[2:0]

0
1
0
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is always read as 0. The write value
should always be 0.

000: Setting prohibited
R/W
6 to 4 P21MD[2:0] P21 function
select
001: IRQ1 input
010: RXD input (SCI3_1) (initial value)
011: FTIOB input/output (timer RC)*
100: TCLKB input (timer RG)
101: FTIOB0 input/output (timer RD_0)
110: TRGB input (timer RB)
111: Setting prohibited
3

Reserved
2 to 0 P20MD[2:0] P20 function
select
This bit is always read as 0. The write value
should always be 0.

000: Setting prohibited
R/W
001: IRQ0 input
010: SCK3 input/output (SCI3_1) (initial value)
011: FTIOA input/output (timer RC)*
100: TCLKA input (timer RG)
101: FTIOA0 input/output (timer RD_0)
110: TREO output (timer RE)
111: Setting prohibited
Note:
*
The timer RC is not available on the H8S/20203 and H8S/20223 groups. These bits are
reserved and the function cannot be selected for these groups.
Rev. 1.00 Oct. 03, 2008 Page 241 of 962
REJ09B0465-0100
Section 9 Peripheral I/O Mapping Controller
(b)
Port 2 Peripheral Function Mapping Register 2 (PMCR22)
Address: H'FF0043
Bit:
b7
b6
0
b4
P23MD[2:0]

Value after reset:
b5
0
1
b3
b2
0
b0
P22MD[2:0]

0
b1
0
1
0
Bit
Bit Name
Initial Value
Description
R/W
7

Reserved
This bit is always read as 0. The write value
should always be 0.

000: Setting prohibited
R/W
6 to 4 P23MD[2:0] P23 function
select
001: IRQ3 input
010: TRCOI input (timer RC) (initial value)
011: FTIOD input/output (timer RC)*
100: TGIOB input/output (timer RG)
101: FTIOD0 input/output (timer RD_0)
110: TRAO output (timer RA)
111: Setting prohibited
3

Reserved
2 to 0 P22MD[2:0] P22 function
select
This bit is always read as 0. The write value
should always be 0.

000: Setting prohibited
R/W
001: IRQ2 input
010: TXD output (SCI3_1) (initial value)
011: FTIOC input/output (timer RC)*
100: TGIOA input/output (timer RG)
101: FTIOC0 input/output (timer RD_0)
110: TRBO output (timer RB)
111: Setting prohibited
Note:
*
The timer RC is not available on the H8S/20203 and H8S/20223 groups. These bits are
reserved and the function cannot be selected for these groups.
Rev. 1.00 Oct. 03, 2008 Page 242 of 962
REJ09B0465-0100
Section 9 Peripheral I/O Mapping Controller
(c)
Port 2 Peripheral Function Mapping Register 3 (PMCR23)
Address: H'FF0046
Bit:
b7
b6
0
b4
P25MD[2:0]

Value after reset:
b5
0
1
b3
b2
b1
P24MD[2:0]

0
b0
0
0
1
0
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is always read as 0. The write value
should always be 0.

000: Setting prohibited
R/W
6 to 4 P25MD[2:0] P25 function
select
001: IRQ5 input
010: SCK3_2 input/output (SCI3_2) (initial value)
011: SCK3_3 input/output (SCI3_3)
3
100: SSCK input/output* (SSU)
101: FTIOB1 input/output (timer RD_0)
110: TRDOI_1 input (timer RD_1)*
1
111: Setting prohibited
3

Reserved
2 to 0 P24MD[2:0] P24 function
select
This bit is always read as 0. The write value
should always be 0.

000: Setting prohibited
R/W
001: IRQ4 input
010: TRDOI_0 input (timer RD_0) (initial value)
011: FTCI input (timer RC)*
2
3
100: SSO input/output* (SSU)
101: FTIOA1 input/output (timer RD_0)
110: TRAIO input/output (timer RA)
111: Setting prohibited
Notes: 1. This function cannot be selected for the H8S/20103 group.
2. This function cannot be selected for the H8S/20203 and H8S/20223 groups.
3. If the SSCK output pin or the SSO output pin is set, the NMOS open-drain output
cannot be selected.
Rev. 1.00 Oct. 03, 2008 Page 243 of 962
REJ09B0465-0100
Section 9 Peripheral I/O Mapping Controller
(d)
Port 2 Peripheral Function Mapping Register 4 (PMCR24)
Address: H'FF0047
Bit:
b7
b6
0
b4
P27MD[2:0]

Value after reset:
b5
0
1
b3
b2
0
b0
P26MD[2:0]

0
b1
0
1
0
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is always read as 0. The write value
should always be 0.

6 to 4
P27MD[2:0]
P27 function
select
000: Setting prohibited
R/W
001: IRQ7 input
010: TXD_2 output (SCI3_2) (initial value)
011: TXD_3 output (SCI3_3)
1
100: SSI/SCL input/output* (SSU/IIC2)
101: FTIOD1 input/output (timer RD_0)
110: ADTRG2 input (AD_2)
111: Setting prohibited
3

Reserved
This bit is always read as 0. The write value
should always be 0.

2 to 0
P26MD[2:0]
P26 function
select
000: Setting prohibited
R/W
001: IRQ6 input
010: RXD_2 input (SCI3_2) (initial value)
011: RXD_3 input (SCI3_3)
1 2
100: SCS/SDA input/output* * (SSU/IIC2)
101: FTIOC1 input/output (timer RD_0)
110: ADTRG1 input (AD_1)
111: Setting prohibited
Note:
1. When the IIC2/SSU is used as the IIC2 function, the SCL and SDA functions should be
allocated to the P56 and P57 pins because SCL and SDA require buffers dedicated for
2
IIC input/output. When the ICSU is used for the SSU function except * , there is no
restriction.
2. If the SCS output pin of the SSU is set, the NMOS open-drain output cannot be
selected.
Rev. 1.00 Oct. 03, 2008 Page 244 of 962
REJ09B0465-0100
Section 9 Peripheral I/O Mapping Controller
(3)
Port 3
(a)
Port 3 Peripheral Function Mapping Register 1 (PMCR31)
Address: H'FF0048
Bit:
b7
b6
Value after reset:
0
b5
b4
P31MD[2:0]

0
1
b3
b2
1
0
b1
b0
P32MD[2:0]

0
1
1
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is always read as 0. The write value should
always be 0.

000: Setting prohibited
R/W
6 to 4 P31MD[2:0] P31 function
select
001: IRQ1 input
010: RXD input (SCI3_1)
011: FTIOB input/output (timer RC)* (initial value)
100: TCLKB input (timer RG)
101: FTIOB0 input/output (timer RD_0)
110: TRGB input (timer RB)
111: Setting prohibited
3

Reserved
2 to 0 P30MD[2:0] P30 function
select
This bit is always read as 0. The write value should
always be 0.

000: Setting prohibited
R/W
001: IRQ0 input
010: SCK3 input/output (SCI3_1)
011: FTIOA input/output (timer RC)* (initial value)
100: TCLKA input (timer RG)
101: FTIOA0 input/output (timer RD_0)
110: TREO output (timer RE)
111: Setting prohibited
Note:
*
The timer RC is not available on the H8S/20203 and H8S/20223 groups. No function is
selected in the initial state for these groups.
Rev. 1.00 Oct. 03, 2008 Page 245 of 962
REJ09B0465-0100
Section 9 Peripheral I/O Mapping Controller
(b)
Port 3 Peripheral Function Mapping Register 2 (PMCR32)
Address: H'FF0049
Bit:
b7
b6
0
b4
P33MD[2:0]

Value after reset:
b5
0
1
b3
b2
0
b0
P32MD[2:0]

1
b1
0
1
1
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is always read as 0. The write value should
always be 0.

6 to 4 P33MD[2:0]
P33 function 000: Setting prohibited
select
001: IRQ3 input
R/W
010: TRCOI input (timer RC)*
011: FTIOD input/output (timer RC)* (initial value)
100: TGIOB input/output (timer RG)
101: FTIOD0 input/output (timer RD_0)
110: TRAO output (timer RA)
111: Setting prohibited
3

Reserved
2 to 0 P32MD[2:0]
This bit is always read as 0. The write value should
always be 0.
P32 function 000: Setting prohibited
select
001: IRQ2 input

R/W
010: TXD output (SCI3_1)
011: FTIOC input/output (timer RC)* (initial value)
100: TGIOA input/output (timer RG)
101: FTIOC0 input/output (timer RD_0)
110: TRBO output (timer RB)
111: Setting prohibited
Note:
*
The timer RC is not available on the H8S/20203 and H8S/20223 groups. No function is
selected in the initial state for these groups.
Rev. 1.00 Oct. 03, 2008 Page 246 of 962
REJ09B0465-0100
Section 9 Peripheral I/O Mapping Controller
(c)
Port 3 Peripheral Function Mapping Register 3 (PMCR33)
Address: H'FF004A
Bit:
b7
b6
0
b4
P35MD[2:0]

Value after reset:
b5
0
1
b3
b2
b1
P34MD[2:0]

1
0
b0
0
1
1
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is always read as 0. The write value
should always be 0.

6 to 4
P35MD[2:0] P35 function
select
000: Setting prohibited
R/W
001: IRQ5 input
010: SCK3_2 input/output (SCI3_2)
011: SCK3_3 input/output (SCI3_3) (initial value)
3
100: SSCK input/output* (SSU)
101: FTIOB1 input/output (timer RD_0)
110: TRDOI_1 input (timer RD_1)*
1
111: Setting prohibited
3

2 to 0
P34MD[2:0] P34 function
select
Reserved
This bit is always read as 0. The write value
should always be 0.

000: Setting prohibited
R/W
001: IRQ4 input
010: TRDOI_0 input (timer RD_0)
2
011: FTCI input (timer RC)* (initial value)
3
100: SSO input/output* (SSU)
101: FTIOA1 input/output (timer RD_0)
110: TRAIO input/output (timer RA)
111: Setting prohibited
Notes: 1. This function cannot be selected for the H8S/20103 group.
2. The timer RC is not available on the H8S/20203 and H8S/20223 groups. No function is
selected in the initial state for these groups.
3. If the SSCK output pin or the SSO output pin is set, the NMOS open-drain output
cannot be selected.
Rev. 1.00 Oct. 03, 2008 Page 247 of 962
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Section 9 Peripheral I/O Mapping Controller
(d)
Port 3 Peripheral Function Mapping Register 4 (PMCR34)
Address: H'FF004B
Bit:
b7
b6
0
b4
P37MD[2:0]

Value after reset:
b5
0
1
b3
b2
b0
P36MD[2:0]

1
b1
0
0
1
1
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is always read as 0. The write value
should always be 0.

6 to 4
P37MD[2:0] P37 function
select
000: Setting prohibited
R/W
001: IRQ7 input
010: TXD_2 output (SCI3_2)
011: TXD_3 output (SCI3_3) (initial value)
1
100: SSI/SCL input/output* (SSU/IIC2)
101: FTIOD1 input/output (timer RD_0)
110: ADTRG2 input (AD_2)*
2
111: Setting prohibited
3

2 to 0
P36MD[2:0] P36 function
select
Reserved
This bit is always read as 0. The write value
should always be 0.

000: Setting prohibited
R/W
001: IRQ6 input
010: RXD_2 input (SCI3_2)
011: RXD_3 input (SCI3_3) (initial value)
1 3
100: SCS/SDA input/output* * (SSU/IIC2)
101: FTIOC1 input/output (timer RD_0)
110: ADTRG1 input (AD_1)
111: Setting prohibited
Notes: 1. When the IIC2/SSU is used as the IIC2 function, the SCL and SDA functions should be
allocated to the P56 and P57 pins because SCL and SDA require buffers dedicated for
2
IIC input/output. When the ICSU is used for the SSU function except * , there is no
restriction.
2. This function cannot be selected for the H8S/20103 and H8S/20203 groups.
3. If the SCS output pin of the SSU is set, the NMOS open-drain output cannot be
selected.
Rev. 1.00 Oct. 03, 2008 Page 248 of 962
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Section 9 Peripheral I/O Mapping Controller
(4)
Port 5
(a)
Port 5 Peripheral Function Mapping Register 1 (PMCR51)
Address: H'FF0050
Bit:
b7
b6
Value after reset:
0
b5
b4
P51MD[2:0]

1
0
b3
b2
0
0
b1
b0
P50MD[2:0]

1
0
0
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is always read as 0. The write value
should always be 0.

6 to 4
P51MD[2:0] P51 function
select
000: Setting prohibited
R/W
001: IRQ1 input
010: RXD input (SCI3_1)
011: FTIOB input/output (timer RC)*
100: TCLKB input (timer RG) (initial value)
101: FTIOB0 input/output (timer RD_0)
110: TRGB input (timer RB)
111: Setting prohibited
3

2 to 0
P50MD[2:0] P50 function
select
Reserved
This bit is always read as 0. The write value
should always be 0.

000: Setting prohibited
R/W
001: IRQ0 input
010: SCK3 input/output (SCI3_1)
011: FTIOA input/output (timer RC)*
100: TCLKA input (timer RG) (initial value)
101: FTIOA0 input/output (timer RD_0)
110: TREO output (timer RE)
111: Setting prohibited
Note:
*
The timer RC is not available on the H8S/20203 and H8S/20223 groups. These bits are
reserved and the function cannot be selected for these groups.
Rev. 1.00 Oct. 03, 2008 Page 249 of 962
REJ09B0465-0100
Section 9 Peripheral I/O Mapping Controller
(b)
Port 5 Peripheral Function Mapping Register 2 (PMCR52)
Address: H'FF0051
Bit:
b7
b6
0
b4
P53MD[2:0]

Value after reset:
b5
1
0
b3
b2
0
b0
P52MD[2:0]

0
b1
1
0
0
Bit
Symbol
Bit Name
Description
7

Reserved
This bit is always read as 0. The write value should 
always be 0.
6 to 4 P53MD[2:0] P53 function
select
000: Setting prohibited
R/W
R/W
001: IRQ3 input
010: TRCOI input (timer RC)*
011: FTIOD input/output (timer RC)*
100: TGIOB input/output (timer RG) (initial value)
101: FTIOD0 input/output (timer RD_0)
110: TRAO output (timer RA)
111: Setting prohibited
3

Reserved
2 to 0 P52MD[2:0] P52 function
select
This bit is always read as 0. The write value should 
always be 0.
000: Setting prohibited
R/W
001: IRQ2 input
010: TXD output (SCI3_1)
011: FTIOC input/output (timer RC)*
100: TGIOA input/output (timer RG) (initial value)
101: FTIOC0 input/output (timer RD_0)
110: TRBO output (timer RB)
111: Setting prohibited
Note:
*
The timer RC is not available on the H8S/20203 and H8S/20223 groups. These bits are
reserved and the function cannot be selected for these groups.
Rev. 1.00 Oct. 03, 2008 Page 250 of 962
REJ09B0465-0100
Section 9 Peripheral I/O Mapping Controller
(c)
Port 5 Peripheral Function Mapping Register 3 (PMCR53)
Address: H'FF0052
Bit:
b7
b6
0
b4
P55MD[2:0]

Value after reset:
b5
1
0
b3
b2
b0
P54MD[2:0]

0
b1
0
1
0
0
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is always read as 0. The write value should 
always be 0.
6 to 4
P55MD[2:0]
P55 function
select
000: Setting prohibited
R/W
001: IRQ5 input
010: SCK3_2 input/output (SCI3_2)
011: SCK3_3 input/output (SCI3_3)
3
100: SSCK input/output* (SSU) (initial value)
101: FTIOB1 input/output (timer RD_0)
110: TRDOI_1 !Unexpected End of
1
Formulainput/output (timer RD_1)*
111: Setting prohibited
3

Reserved
This bit is always read as 0. The write value should 
always be 0.
2 to 0
P54MD[2:0]
P54 function
select
000: Setting prohibited
R/W
001: IRQ4 input
010: TRDOI_0 input (timer RD_0)
2
011: FTCI input (timer RC)*
3
100: SSO input/output* (SSU) (initial value)
101: FTIOA1 input/output (timer RD_0)
110: TRAIO input/output (timer RA)
111: Setting prohibited
Notes: 1. This function cannot be selected for the H8S/20103 group.
2. The timer RC is not available on the H8S/20203 and H8S/20223 groups. These bits are
reserved and the function cannot be selected for these groups.
3. If the NMOS open-drain output is selected for the SSCK output pin or the SSO output
pin, use the PMC to allocate that pin from port 5
Rev. 1.00 Oct. 03, 2008 Page 251 of 962
REJ09B0465-0100
Section 9 Peripheral I/O Mapping Controller
(d)
Port 5 Peripheral Function Mapping Register 4 (PMCR54)
Address: H'FF0053
Bit:
b7
b6
0
b4
P57MD[2:0]

Value after reset:
b5
1
0
b3
b2
0
b0
P56MD[2:0]

0
b1
1
0
0
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is always read as 0. The write value
should always be 0.

6 to 4
P57MD[2:0] P57 function
select
000: Setting prohibited
R/W
001: IRQ7 input
010: TXD_2 output (SCI3_2)
011: TXD_3 output (SCI3_3)
1
100: SSI/SCL input/output* (SSU/IIC2)
(initial value)
101: FTIOD1 input/output (timer RD_0)
110: ADTRG2 input (AD_2)
111: Setting prohibited
3

2 to 0
P56MD[2:0] P56 function
select
Reserved
This bit is always read as 0. The write value
should always be 0.

000: Setting prohibited
R/W
001: IRQ6 input
010: RXD_2 input (SCI3_2)
011: RXD_3 input (SCI3_3)
1 2
100: SCS/SDA input/output* * (SSU/IIC2)
(initial value)
101: FTIOC1 input/output (timer RD_0)
110: ADTRG1 input (AD_1)
111: Setting prohibited
Rev. 1.00 Oct. 03, 2008 Page 252 of 962
REJ09B0465-0100
Section 9 Peripheral I/O Mapping Controller
Note:
1. When the IIC2/SSU is used as the IIC2 function, the SCL and SDA functions should be
allocated to the P56 and P57 pins because SCL and SDA require buffers dedicated for
2
IIC input/output. When the ICSU is used for the SSU function except * , there is no
restriction.
The P56 and P57 pins have different characteristics from other pins. When these pins
are used as the SCL and SDA pins for the IIC2, they provide NMOS open drain output.
When the P56 and P57 pins are used for other output functions, they provide NMOS
push-pull output and characteristics of the high level output is different from that of the
CMOS output.
2. If the NMOS open-drain output is selected for the SCS output pin, use the PMC to
allocate that pin from port 5
Rev. 1.00 Oct. 03, 2008 Page 253 of 962
REJ09B0465-0100
Section 9 Peripheral I/O Mapping Controller
(5)
Port 6
(a)
Port 6 Peripheral Function Mapping Register 1 (PMCR61)
Address: H'FF0054
Bit:
b7
b6
Value after reset:
0
b5
b4
P61MD[2:0]

1
0
b3
b2
1
0
b1
b0
P60MD[2:0]

1
0
1
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is always read as 0. The write value
should always be 0.

6 to 4
P61MD[2:0] P61 function
select
000: Setting prohibited
R/W
001: IRQ1 input
010: RXD input (SCI3_1)
011: FTIOB input/output (timer RC)*
100: TCLKB input (timer RG)
101: FTIOB0 input/output (timer RD_0)
(initial value)
110: TRGB input (timer RB)
111: Setting prohibited
3

2 to 0
P60MD[2:0] P60 function
select
Reserved
This bit is always read as 0. The write value
should always be 0.

000: Setting prohibited
R/W
001: IRQ0 input
010: SCK3 input/output (SCI3_1)
011: FTIOA input/output (timer RC)*
100: TCLKA input (timer RG)
101: FTIOA0 input/output (timer RD_0)
(initial value)
110: TREO output (timer RE)
111: Setting prohibited
Note:
*
The timer RC is not available on the H8S/20203 and H8S/20223 groups. These bits are
reserved and the function cannot be selected for these groups.
Rev. 1.00 Oct. 03, 2008 Page 254 of 962
REJ09B0465-0100
Section 9 Peripheral I/O Mapping Controller
(b)
Port 6 Peripheral Function Mapping Register 2 (PMCR62)
Address: H'FF0055
Bit:
b7
b6
0
b4
P63MD[2:0]

Value after reset:
b5
1
0
b3
b2
0
b0
P62MD[2:0]

1
b1
1
0
1
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is always read as 0. The write value
should always be 0.

6 to 4
P63MD[2:0] P63 function
select
000: Setting prohibited
R/W
001: IRQ3 input
010: TRCOI input (timer RC)*
011: FTIOD input/output (timer RC)*
100: TGIOB input/output (timer RG)
101: FTIOD0 input/output (timer RD_0)
(initial value)
110: TRAO output (timer RA)
111: Setting prohibited
3

2 to 0
P62MD[2:0] P62 function
select
Reserved
This bit is always read as 0. The write value
should always be 0.

000: Setting prohibited
R/W
001: IRQ2 input
010: TXD output (SCI3_1)
011: FTIOC input/output (timer RC)*
100: TGIOA input/output (timer RG)
101: FTIOC0 input/output (timer RD_0)
(initial value)
110: TRBO output (timer RB)
111: Setting prohibited
Note:
*
The timer RC is not available on the H8S/20203 and H8S/20223 groups. These bits are
reserved and the function cannot be selected for these groups.
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Section 9 Peripheral I/O Mapping Controller
(c)
Port 6 Peripheral Function Mapping Register 3 (PMCR63)
Address: H'FF0056
Bit:
b7
b6
0
b4
P65MD[2:0]

Value after reset:
b5
1
0
b3
b2
b0
P64MD[2:0]

1
b1
0
1
0
1
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is always read as 0. The write value should 
always be 0.
6 to 4
P65MD[2:0]
P65 function
select
000: Setting prohibited
R/W
001: IRQ5 input
010: SCK3_2 input/output (SCI3_2)
011: SCK3_3 input/output (SCI3_3)
3
100: SSCK input/output* (SSU)
101: FTIOB1 input/output (timer RD_0)
(initial value)
110: TRDOI_1 input (timer RD_1)*1
111: Setting prohibited
3

Reserved
This bit is always read as 0. The write value should 
always be 0.
2 to 0
P64MD[2:0]
P64 function
select
000: Setting prohibited
R/W
001: IRQ4 input
010: TRDOI_0 input (timer RD_0)
2
011: FTCI input (timer RC)*
3
100: SSO input/output* (SSU)
101: FTIOA1 input/output (timer RD_0)
(initial value)
110: TRAIO input/output (timer RA)
111: Setting prohibited
Notes: 1. This function cannot be selected for the H8S/20103 group.
2. The timer RC is not available on the H8S/20203 and H8S/20223 groups. These bits are
reserved and the function cannot be selected for these groups.
3. If the SSCK output pin or the SSO output pin is set, the NMOS open-drain output
cannot be selected.
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Section 9 Peripheral I/O Mapping Controller
(d)
Port 6 Peripheral Function Mapping Register 4 (PMCR64)
Address: H'FF0057
Bit:
b7
b6
0
b4
P67MD[2:0]

Value after reset:
b5
1
0
b3
b2
0
b0
P66MD[2:0]

1
b1
1
0
1
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is always read as 0. The write value
should always be 0.

6 to 4
P67MD[2:0]
P67 function
select
000: Setting prohibited
R/W
001: IRQ7 input
010: TXD_2 output (SCI3_2)
011: TXD_3 output (SCI3_3)
1
100: SSI/SCL input/output* (SSU/IIC2)
101: FTIOD1 input/output (timer RD_0)
(initial value)
110: ADTRG2 input (AD_2) *2
111: Setting prohibited
3

Reserved
This bit is always read as 0. The write value
should always be 0.

2 to 0
P66MD[2:0]
P66 function
select
000: Setting prohibited
R/W
001: IRQ6 input
010: RXD_2 input (SCI3_2)
011: RXD_3 input (SCI3_3)
1 3
100: SCS/SDA input/output* * (SSU/IIC2)
101: FTIOC1 input/output (timer RD_0)
(initial value)
110: ADTRG1 input (AD_1)
111: Setting prohibited
Notes: 1. When the IIC2/SSU is used as the IIC2 function, the SCL and SDA functions should be
allocated to the P56 and P57 pins because SCL and SDA require buffers dedicated for
2
IIC input/output. When the ICSU is used for the SSU function except * , there is no
restriction.
2. This function cannot be selected for the H8S/20103 and H8S/20203 groups.
3. If the SCS output pin of the SSU is set, the NMOS open-drain output cannot be
selected.
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Section 9 Peripheral I/O Mapping Controller
9.1.3
Port Group 2
Peripheral Function Mapping Registers 1 to 4 (PMCRn1 to PMCRn4 (n = 8, 9, and
A)
(1)
Port 8
(a)
Port 8 Peripheral Function Mapping Register 3 (PMCR83)
Address: H'FF005E
Bit:
b7
b6
0
b4
P85MD[2:0]

Value after reset:
b5
1
0
0
b3
b2
b1
b0




0
1
0
0
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is always read as 0. The write value should
always be 0.

6 to 4
P85MD[2:0] P85 function 000: Setting prohibited
select
001: IRQ5 input
R/W
010: Setting prohibited
011: SCK3 input/output (SCI3_1)
100: TRAIO input/output (timer RA) (initial value)
101: FTIOB3 input/output (timer RD_1)*
110: SCK3_3 input/output (SCI3_3)
111: Setting prohibited
3

Reserved
This bit is always read as 0. The write value should
always be 0.

2 to 0

Reserved
This bit is always read as B'100. The write value
should always be B'100.

Note:
*
This function cannot be selected for the H8S/20103 group.
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Section 9 Peripheral I/O Mapping Controller
(b)
Port 8 Peripheral Function Mapping Register 4 (PMCR84)
Address: H'FF005F
Bit:
b7
b6
0
b4
P87MD[2:0]

Value after reset:
b5
1
0
b3
b2
0
b0
P86MD[2:0]

0
b1
1
0
0
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is always read as 0. The write value should
always be 0.

6 to 4
P87MD[2:0] P87 function
select
000: Setting prohibited
R/W
001: IRQ7 input
010: Setting prohibited
011: TXD output (SCI3_1)
100: TREO output (timer RE) (initial value)
101: FTIOD3 input/output (timer RD_1)*
110: TXD_3 output (SCI3_3)
111: Setting prohibited
3

2 to 0
P86MD[2:0] P86 function
select
Reserved
This bit is always read as 0. The write value should
always be 0.

000: Setting prohibited
R/W
001: IRQ6 input
010: Setting prohibited
011: RXD input (SCI3_1)
100: TRBO output (timer RB) (initial value)
101: FTIOC3 input/output (timer RD_1)*
110: RXD_3 input (SCI3_3)
111: Setting prohibited
Note:
*
This function cannot be selected for the H8S/20103 group.
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Section 9 Peripheral I/O Mapping Controller
(2)
Port 9
(a)
Port 9 Peripheral Function Mapping Register 1 (PMCR91)
Address: H'FF0060
Bit:
b7
b6
Value after reset:
0
b5
b4
P91MD[2:0]

1
0
b3
b2
1
0
b1
b0
P90MD[2:0]

1
0
1
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is always read as 0. The write value
should always be 0.

6 to 4
P91MD[2:0]
P91 function
select
000: Setting prohibited
R/W
001: IRQ1 input
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: FTIOB2 input/output (timer RD_1)
(initial value)
110: Setting prohibited
111: Setting prohibited
3

Reserved
This bit is always read as 0. The write value
should always be 0.

2 to 0
P90MD[2:0]
P90 function
select
000: Setting prohibited
R/W
001: IRQ0 input
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: FTIOA2 input/output (timer RD_1)
(initial value)
110: Setting prohibited
111: Setting prohibited
Note: PMCR91 is not available on the H8S/20103 group.
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Section 9 Peripheral I/O Mapping Controller
(b)
Port 9 Peripheral Function Mapping Register 2 (PMCR92)
Address: H'FF0061
Bit:
b7
b6
0
b4
P93MD[2:0]

Value after reset:
b5
1
0
b3
b2
0
b0
P92MD[2:0]

1
b1
1
0
1
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is always read as 0. The write value should 
always be 0.
6 to 4
P93MD[2:0] P93 function
select
000: Setting prohibited
R/W
001: IRQ3 input
010: Setting prohibited
011: Setting prohibited
100: TRAO output (timer RA)
101: FTIOD2 input/output (timer RD_1)
(initial value)
110: Setting prohibited
111: Setting prohibited
3

2 to 0
P92MD[2:0] P92 function
select
Reserved
This bit is always read as 0. The write value should 
always be 0.
000: Setting prohibited
R/W
001: IRQ2 input
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: FTIOC2 input/output (timer RD_1)
(initial value)
110: Setting prohibited
111: Setting prohibited
Note: PMCR92 is not available on the H8S/20103 group.
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Section 9 Peripheral I/O Mapping Controller
(c)
Port 9 Peripheral Function Mapping Register 3 (PMCR93)
Address: H'FF0062
Bit:
b7
b6
0
b4
P95MD[2:0]

Value after reset:
b5
1
0
b3
b2
0
b0
P94MD[2:0]

1
b1
1
0
1
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is always read as 0. The write value
should always be 0.

6 to 4
P95MD[2:0]
P95 function
select
000: Setting prohibited
R/W
001: IRQ5 input
010: Setting prohibited
011: SCK3 input/output (SCI3_1)
100: TRAIO input/output (timer RA)
101: FTIOB3 input/output (timer RD_1)
(initial value)
110: SCK3_3 input/output (SCI3_3)
111: Setting prohibited
3

Reserved
This bit is always read as 0. The write value
should always be 0.

2 to 0
P94MD[2:0]
P94 function
select
000: Setting prohibited
R/W
001: IRQ4 input
010: Setting prohibited
011: Setting prohibited
100: TRGB input (timer RB)
101: FTIOA3 input/output (timer RD_1)
(initial value)
110: Setting prohibited
111: Setting prohibited
Note: PMCR93 is not available on the H8S/20103 group.
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Section 9 Peripheral I/O Mapping Controller
(d)
Port 9 Peripheral Function Mapping Register 4 (PMCR94)
Address: H'FF0063
Bit:
b7
b6
0
b4
P97MD[2:0]

Value after reset:
b5
1
0
b3
b2
0
b0
P96MD[2:0]

1
b1
1
0
1
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is always read as 0. The write value
should always be 0.

6 to 4
P97MD[2:0] P97 function
select
000: Setting prohibited
R/W
001: IRQ7 input
010: Setting prohibited
011: TXD output (SCI3_1)
100: TREO output (timer RE)
101: FTIOD3 input/output (timer RD_1)
(initial value)
110: TXD_3 output (SCI3_3)
111: Setting prohibited
3

2 to 0
P96MD[2:0] P96 function
select
Reserved
This bit is always read as 0. The write value
should always be 0.

000: Setting prohibited
R/W
001: IRQ6 input
010: Setting prohibited
011: RXD input (SCI3_1)
100: TRBO output (timer RB)
101: FTIOC3 input/output (timer RD_1)
(initial value)
110: RXD_3 input (SCI3_3)
111: Setting prohibited
Note: PMCR94 is not available on the H8S/20103 group.
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Section 9 Peripheral I/O Mapping Controller
(3)
Port A
(a)
Port A Peripheral Function Mapping Register 3 (PMCRA3)
Address: H'FF0066
Bit:
b7
b6
Value after reset:
0
b5
b4
PA5MD[2:0]

0
0
b3
b2
0
0
b1
b0
PA4MD[2:0]

0
0
0
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is always read as 0. The write value
should always be 0.

6 to 4
PA5MD[2:0]
PA5 function
select
000: No function selected (initial value)
R/W
001: IRQ5 input
010: Setting prohibited
011: SCK3 input/output (SCI3_1)
100: TRAIO input/output (timer RA)
101: FTIOB3 input/output (timer RD_1)*
110: SCK3_3 input/output (SCI3_3)
111: Setting prohibited
3

Reserved
This bit is always read as 0. The write value
should always be 0.

2 to 0
PA4MD[2:0]
PA4 function
select
000: No function selected (initial value)
R/W
001: IRQ4 input
010: Setting prohibited
011: Setting prohibited
100: TRGB input (timer RB)
101: FTIOA3 input/output (timer RD_1)*
110: Setting prohibited
111: Setting prohibited
Note: PMCRA3 is not available on the H8S/20223 group.
* This function cannot be selected for the H8S/20103 group.
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Section 9 Peripheral I/O Mapping Controller
(b)
Port A Peripheral Function Mapping Register 4 (PMCRA4)
Address: H'FF0067
Bit:
b7
b6
0
b4
PA7MD[2:0]

Value after reset:
b5
0
0
b3
b2
0
b0
PA6MD[2:0]

0
b1
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is always read as 0. The write value
should always be 0.

6 to 4
PA7MD[2:0]
PA7 function
select
000: No function selected (initial value)
R/W
001: IRQ7 input
010: Setting prohibited
011: TXD output (SCI3_1)
100: TREO output (timer RE)
101: FTIOD3 input/output (timer RD_1)*
110: TXD_3 output (SCI3_3)
111: Setting prohibited
3

Reserved
This bit is always read as 0. The write value
should always be 0.

2 to 0
PA6MD[2:0]
PA6 function
select
000: No function selected (initial value)
R/W
001: IRQ6 input
010: Setting prohibited
011: RXD input (SCI3_1)
100: TRBO output (timer RB)
101: FTIOC3 input/output (timer RD_1)*
110: RXD_3 input (SCI3_3)
111: Setting prohibited
Note: PMCRA4 is not available on the H8S/20223 group.
* This function cannot be selected for the H8S/20103 group.
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Section 9 Peripheral I/O Mapping Controller
9.2
Usage Notes
9.2.1
Procedures for Setting Multiplexed Port Functions
Use the following procedures to set a function for a multiplexed port.
1.
2.
3.
4.
5.
Clear the relevant port mode register (PMR) bit to 0 to select the general input function.
Set PMCWPR to enable writing to the relevant peripheral function mapping register (PMCR).
Select a function using the peripheral function mapping register (PMCR).
Set the PMCRWE bit in PMCWPR to 0 to disable writing to PMCR.
Set the PMR bit to 1 as necessary to activate the selected multiplexed function.
9.2.2
Notes on Setting PMC Registers
1. A function of a multiplexed port should be set when the relevant PMR bit is 0. If a function is
set when PMR is 1, an unintended edge may be input for the input function or unintended
pulses may be output for the output function.
2. Only the functions that can be selected by PMCR should be set. If the other functions are set,
operation cannot be guaranteed.
3. The same function must not be assigned to multiple pins by the PMC.
4. Port A also has an analog input function for the A/D converter. When port A is used as analog
input, the relevant bit in PMRA should be set to 0 to select general I/O.
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Section 10 I/O Ports
Section 10 I/O Ports
The H8S/20103 group has fifty-five general I/O ports, and the H8S/20223 and H8S/20203 groups
each have sixty-nine general I/O ports. The general I/O ports are divided into three groups: the
digital I/O ports that can also be used as I/O pins of the on-chip peripheral modules or external
interrupt input pins, the ports that can also be used as analog input ports, and the ports that can
also be used as external oscillation pins. Although all the ports are set as general input ports
immediately after a reset, the pin functions can be selected by setting the appropriate register.
Pin functions of the digital I/O ports are selected by the peripheral function mapping controller
(PMC). For details, see section 9, Peripheral I/O Mapping Controller. All pins of general I/O ports
can be set as high-power ports. For the permissible total output current, see section 28, Electrical
Characteristics.
10.1
Port 1
Figure 10.1 shows the pin configuration of port 1.
H8S/20103 group
P17/IRQ7
P16/IRQ6
P15/IRQ5
P14/IRQ4
P13/IRQ3
P12/IRQ2
P11/IRQ1
P10/IRQ0
P17/IRQ7
P16/IRQ6
P15/IRQ5
Port 1
Port 1
H8S/20203 group
H8S/20223 group
P13/IRQ3
P12/IRQ2
P11/IRQ1
Note: Only the functions initially selected by PMCR are shown following the port pin names.
Figure 10.1 Port 1 Pin Configuration
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REJ09B0465-0100
Section 10 I/O Ports
Port 1 has the following registers.
•
•
•
•
•
Port mode register 1 (PMR1)
Port control register 1 (PCR1)
Port data register 1 (PDR1)
Port pull-up control register 1 (PUCR1)
Port drive control register 1 (PDVR1)
10.1.1
Port Mode Register 1 (PMR1)
Address: H'FF0000
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PMR17
PMR16
PMR15
PMR14
PMR13
PMR12
PMR11
PMR10
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PMR17
Port 17 mode
0: General I/O port
R/W
6
PMR16
Port 16 mode
R/W
5
PMR15
Port 15 mode
1: The function selected by the peripheral I/O
mapping controller (PMC).
4
PMR14
Port 14 mode
3
PMR13
Port 13 mode
2
PMR12
Port 12 mode
1
PMR11
Port 11 mode
R/W
In the H8S/20103 group, bits PMR14 and PMR10
are reserved. Only 0 should be written to these bits. R/W
0
PMR10
Port 10 mode
R/W
Rev. 1.00 Oct. 03, 2008 Page 268 of 962
REJ09B0465-0100
R/W
PMR1 is a register that selects the function of the
R/W
multiplexed pins: general I/O function or the function
R/W
selected by the PMC.
Section 10 I/O Ports
10.1.2
Port Control Register 1 (PCR1)
Address: H'FFFFF0
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
PCR17
PCR16
PCR15
PCR14
PCR13
PCR12
PCR11
PCR10
0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
PCR17
Port 17 control
R/W
6
PCR16
Port 16 control
0: When the corresponding pin is designated as a
general I/O port, the pin functions as an input
port.
5
PCR15
Port 15 control
4
PCR14
Port 14 control
3
PCR13
Port 13 control
2
PCR12
Port 12 control
1
PCR11
Port 11 control
0
PCR10
Port 10 control
1: When the corresponding pin is designated as a
general I/O port, the pin functions as an output
port.
R/W
R/W
R/W
R/W
When the corresponding pin is designated in PMR1 R/W
as a general I/O pin, setting a PCR bit to 1 makes
the corresponding pin an output port, while clearing R/W
the bit to 0 makes the pin an input port.
R/W
In the H8S/20103 group, bits PCR14 and PCR10
are reserved. Only 0 should be written to these bits.
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Section 10 I/O Ports
10.1.3
Port Data Register 1 (PDR1)
Address: H'FFFFE0
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PDR17
PDR16
PDR15
PDR14
PDR13
PDR12
PDR11
PDR10
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PDR17
Port 17 data
0: Low level
R/W
6
PDR16
Port 16 data
1: High level
R/W
5
PDR15
Port 15 data
4
PDR14
Port 14 data
3
PDR13
Port 13 data
2
PDR12
Port 12 data
1
PDR11
Port 11 data
0
PDR10
Port 10 data
PDR1 is a register that stores output data for port 1 R/W
pins. When PCR1 bits are set to 1, the values
R/W
stored in PDR1 are output.
R/W
When PDR1 is read while PCR1 bits are set to 1,
the values stored in PDR1 are read. If PDR1 is read R/W
while PCR1 bits are cleared to 0, the pin states are R/W
read regardless of the value stored in PDR1.
R/W
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Section 10 I/O Ports
10.1.4
Port Pull-Up Control Register 1 (PUCR1)
Address: H'FF0010
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PUCR17
PUCR16
PUCR15
PUCR14
PUCR13
PUCR12
PUCR11
PUCR10
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PUCR17
Port 17 pull-up
control
0: The pull-up MOS of corresponding pin is
disabled.
R/W
6
PUCR16
Port 16 pull-up
control
1: The pull-up MOS of corresponding pin is
enabled.
R/W
5
PUCR15
Port 15 pull-up
control
R/W
4
PUCR14
Port 14 pull-up
control
R/W
3
PUCR13
Port 13 pull-up
control
R/W
2
PUCR12
Port 12 pull-up
control
R/W
1
PUCR11
Port 11 pull-up
control
R/W
0
PUCR10
Port 10 pull-up
control
R/W
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Section 10 I/O Ports
10.1.5
Port Drive Control Register 1 (PDVR1)
Address: H'FF0030
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PDVR17
PDVR16
PDVR15
PDVR14
PDVR13
PDVR12
PDVR11
PDVR10
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PDVR17
Port 17 drive
control
0: Normal output
R/W
6
PDVR16
Port 16 drive
control
5
PDVR15
Port 15 drive
control
PDVR1 is a register that controls drive capability of R/W
the output pins in a bit unit.
In the H8S/20103 group, bits PVDR14 and PVDR10 R/W
4
PDVR14
Port 14 drive
control
R/W
3
PDVR13
Port 13 drive
control
R/W
2
PDVR12
Port 12 drive
control
R/W
1
PDVR11
Port 11 drive
control
R/W
0
PDVR10
Port 10 drive
control
R/W
Rev. 1.00 Oct. 03, 2008 Page 272 of 962
REJ09B0465-0100
1: High-current drive output
are reserved. Only 0 should be written to these bits.
Section 10 I/O Ports
10.2
Port 2
Figure 10.2 shows the pin configuration of port 2.
H8S/20103 group
P27/TXD_2
P26/RXD_2
P25/SCK3_2
P24/TRDOI
P23
P22/TXD
P21/RXD
P20/SCK3
P27/TXD_2
P26/RXD_2
P25/SCK3_2
P24/TRDOI
P23/TRCOI
P22/TXD
P21/RXD
P20/SCK3
Port 2
Port 2
H8S/20203 group
H8S/20223 group
Note: Only the functions initially selected by PMCR are shown following the port pin names.
Figure 10.2 Port 2 Pin Configuration
Port 2 has the following registers.
•
•
•
•
•
Port mode register 2 (PMR2)
Port control register 2 (PCR2)
Port data register 2 (PDR2)
Port pull-up control register 2 (PUCR2)
Port drive control register 2 (PDVR2)
Rev. 1.00 Oct. 03, 2008 Page 273 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.2.1
Port Mode Register 2 (PMR2)
Address: H'FF0001
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PMR27
PMR26
PMR25
PMR24
PMR23
PMR22
PMR21
PMR20
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PMR27
Port 27 mode
0: General I/O port
R/W
6
PMR26
Port 26 mode
R/W
5
PMR25
Port 25 mode
1: The function selected by the peripheral function
mapping controller (PMC).
4
PMR24
Port 24 mode
3
PMR23
Port 23 mode
R/W
PMR2 is a register that selects the function of the
R/W
multiplexed pins: general I/O function or the function
R/W
selected by the PMC.
2
PMR22
Port 22 mode
R/W
1
PMR21
Port 21 mode
R/W
0
PMR20
Port 20 mode
R/W
Rev. 1.00 Oct. 03, 2008 Page 274 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.2.2
Port Control Register 2 (PCR2)
Address: H'FFFFF1
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
PCR27
PCR26
PCR25
PCR24
PCR23
PCR22
PCR21
PCR20
0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
PCR27
Port 27 control
R/W
6
PCR26
Port 26 control
0: When the corresponding pin is designated as a
general I/O port, the pin functions as an input
port.
5
PCR25
Port 25 control
4
PCR24
Port 24 control
3
PCR23
Port 23 control
2
PCR22
Port 22 control
1
PCR21
Port 21 control
0
PCR20
Port 20 control
1: When the corresponding pin is designated as a
general I/O port, the pin functions as an output
port.
R/W
R/W
R/W
R/W
PCR2 is a register that selects inputs/outputs in bit R/W
units for pins to be used as general I/O ports of port
R/W
2.
R/W
• PCR27 bit to PCR20 bit (port 27 to 20 control)
When the corresponding pin is designated in PMR2 as a general I/O pin, setting a PCR2 bit to
1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an
input port.
Rev. 1.00 Oct. 03, 2008 Page 275 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.2.3
Port Data Register 2 (PDR2)
Address: H'FFFFE1
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PDR27
PDR26
PDR25
PDR24
PDR23
PDR22
PDR21
PDR20
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PDR27
Port 27 data
0: Low level
R/W
6
PDR26
Port 26 data
1: High level
R/W
5
PDR25
Port 25 data
4
PDR24
Port 24 data
3
PDR23
Port 23 data
2
PDR22
Port 22 data
1
PDR21
Port 21 data
0
PDR20
Port 20 data
PDR2 is a register that stores output data for port 2 R/W
pins. When PCR2 bits are set to 1, the values
R/W
stored in PDR2 are output.
R/W
When PDR2 is read while PCR2 bits are set to 1,
the values stored in PDR2 are read. If PDR2 is read R/W
while PCR2 bits are cleared to 0, the pin states are R/W
read regardless of the value stored in PDR2.
R/W
Rev. 1.00 Oct. 03, 2008 Page 276 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.2.4
Port Pull-Up Control Register 2 (PUCR2)
Address: H'FF0011
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PUCR27
PUCR26
PUCR25
PUCR24
PUCR23
PUCR22
PUCR21
PUCR20
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PUCR27
Port 27 pull-up
control
0: The pull-up MOS of corresponding pin is
disabled.
R/W
6
PUCR26
Port 26 pull-up
control
1: The pull-up MOS of corresponding pin is
enabled.
R/W
5
PUCR25
Port 25 pull-up
control
PUCR2 is a register that controls the pull-up MOS
in bit units of the pins set as the input ports.
R/W
4
PUCR24
Port 24 pull-up
control
R/W
3
PUCR23
Port 23 pull-up
control
R/W
2
PUCR22
Port 22 pull-up
control
R/W
1
PUCR21
Port 21 pull-up
control
R/W
0
PUCR20
Port 20 pull-up
control
R/W
• PUCR27 bit to PUCR20 bit (port 27 to 20 pull-up control)
This function is valid only for the pin set as general input, and for the input pin with a function
selected by the PMC.
Rev. 1.00 Oct. 03, 2008 Page 277 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.2.5
Port Drive Control Register 2 (PDVR2)
Address: H'FF0031
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PDVR27
PDVR26
PDVR25
PDVR24
PDVR23
PDVR22
PDVR21
PDVR20
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PDVR27
Port 27 drive
control
0: Normal output
R/W
6
PDVR26
Port 26 drive
control
5
PDVR25
Port 25 drive
control
PDVR2 is a register that controls drive capability of R/W
the output pins in a bit unit.
R/W
4
PDVR24
Port 24 drive
control
R/W
3
PDVR23
Port 23 drive
control
R/W
2
PDVR22
Port 22 drive
control
R/W
1
PDVR21
Port 21 drive
control
R/W
0
PDVR20
Port 20 drive
control
R/W
Rev. 1.00 Oct. 03, 2008 Page 278 of 962
REJ09B0465-0100
1: High-current drive output
Section 10 I/O Ports
10.3
Port 3
Figure 10.3 shows the pin configuration of port 3.
H8S/20103 group
P37/TXD_3
P36/RXD_3
P35/SCK3_3
P34
P33
P32
P31
P30
P37/TXD_3
P36/RXD_3
P35/SCK3_3
P34/FTCI
P33/FTIOD
P32/FTIOC
P31/FTIOB
P30/FTIOA
Port 3
Port 3
H8S/20203 group
H8S/20223 group
Note: Only the functions initially selected by PMCR are shown following the port pin names.
Figure 10.3 Port 3 Pin Configuration
Port 3 has the following registers.
•
•
•
•
•
Port mode register 3 (PMR3)
Port control register 3 (PCR3)
Port data register 3 (PDR3)
Port pull-up control register 3 (PUCR3)
Port drive control register 3 (PDVR3)
Rev. 1.00 Oct. 03, 2008 Page 279 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.3.1
Port Mode Register 3 (PMR3)
Address: H'FF0002
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PMR37
PMR36
PMR35
PMR34
PMR33
PMR32
PMR31
PMR30
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PMR37
Port 37 mode
0: General I/O port
R/W
6
PMR36
Port 36 mode
R/W
5
PMR35
Port 35 mode
1: The function selected by the peripheral function
mapping controller (PMC).
4
PMR34
Port 34 mode
3
PMR33
Port 33 mode
R/W
PMR3 is a register that selects the function of the
R/W
multiplexed pins: general I/O function or the function
R/W
selected by the PMC.
2
PMR32
Port 32 mode
R/W
1
PMR31
Port 31 mode
R/W
0
PMR30
Port 30 mode
R/W
Rev. 1.00 Oct. 03, 2008 Page 280 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.3.2
Port Control Register 3 (PCR3)
Address: H'FFFFF2
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
PCR37
PCR36
PCR35
PCR34
PCR33
PCR32
PCR31
PCR30
0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
PCR37
Port 37 control
R/W
6
PCR36
Port 36 control
0: When the corresponding pin is designated as a
general I/O port, the pin functions as an input
port.
5
PCR35
Port 35 control
4
PCR34
Port 34 control
3
PCR33
Port 33 control
2
PCR32
Port 32 control
1
PCR31
Port 31 control
0
PCR30
Port 30 control
1: When the corresponding pin is designated as a
general I/O port, the pin functions as an output
port.
R/W
R/W
R/W
R/W
PCR3 is a register that selects inputs/outputs in bit R/W
units for pins to be used as general I/O ports of port
R/W
3.
R/W
• PCR37 bit to PCR30 bit (port 37 to 30 control)
When the corresponding pin is designated in PMR3 as a general I/O pin, setting a PCR3 bit to
1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an
input port.
Rev. 1.00 Oct. 03, 2008 Page 281 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.3.3
Port Data Register 3 (PDR3)
Address: H'FFFFE2
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PDR37
PDR36
PDR35
PDR34
PDR33
PDR32
PDR31
PDR30
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PDR37
Port 37 data
0: Low level
R/W
6
PDR36
Port 36 data
1: High level
R/W
5
PDR35
Port 35 data
4
PDR34
Port 34 data
3
PDR33
Port 33 data
2
PDR32
Port 32 data
1
PDR31
Port 31 data
0
PDR30
Port 30 data
PDR3 is a register that stores output data for port 3 R/W
pins. When PCR3 bits are set to 1, the values
R/W
stored in PDR3 are output.
R/W
When PDR3 is read while PCR3 bits are set to 1,
the values stored in PDR3 are read. If PDR3 is read R/W
while PCR3 bits are cleared to 0, the pin states are R/W
read regardless of the value stored in PDR3.
R/W
Rev. 1.00 Oct. 03, 2008 Page 282 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.3.4
Port Pull-Up Control Register 3 (PUCR3)
Address: H'FF0012
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PUCR37
PUCR36
PUCR35
PUCR34
PUCR33
PUCR32
PUCR31
PUCR30
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PUCR37
Port 37 pull-up
control
0: The pull-up MOS of corresponding pin is
disabled.
R/W
6
PUCR36
Port 36 pull-up
control
1: The pull-up MOS of corresponding pin is
enabled.
R/W
5
PUCR35
Port 35 pull-up
control
PUCR3 is a register that controls the pull-up MOS
in bit units of the pins set as the input ports.
R/W
4
PUCR34
Port 34 pull-up
control
R/W
3
PUCR33
Port 33 pull-up
control
R/W
2
PUCR32
Port 32 pull-up
control
R/W
1
PUCR31
Port 31 pull-up
control
R/W
0
PUCR30
Port 30 pull-up
control
R/W
• PUCR37 bit to PUCR30 bit (port 37 to 30 pull-up control)
This function is valid only for the pin set as general input, and for the input pin with a function
selected by the PMC.
Rev. 1.00 Oct. 03, 2008 Page 283 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.3.5
Port Drive Control Register 3 (PDVR3)
Address: H'FF0032
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PDVR37
PDVR36
PDVR35
PDVR34
PDVR33
PDVR32
PDVR31
PDVR30
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PDVR37
Port 37 drive
control
0: Normal output
R/W
6
PDVR36
Port 36 drive
control
5
PDVR35
Port 35 drive
control
PDVR3 is a register that controls drive capability of R/W
the output pins in a bit unit.
R/W
4
PDVR34
Port 34 drive
control
R/W
3
PDVR33
Port 33 drive
control
R/W
2
PDVR32
Port 32 drive
control
R/W
1
PDVR31
Port 31 drive
control
R/W
0
PDVR30
Port 30 drive
control
R/W
Rev. 1.00 Oct. 03, 2008 Page 284 of 962
REJ09B0465-0100
1: High-current drive output
Section 10 I/O Ports
10.4
Port 5
Port 5
Figure 10.4 shows the pin configuration of port 5.
P57/SCL/SSI
P56/SDA/SCS
P55/SSCK
P54/SSO
P53/TGIOB
P52/TGIOA
P51/TCLKB
P50/TCLKA
Note: Only the functions initially selected by PMCR are shown following the port pin names.
Figure 10.4 Port 5 Pin Configuration
Port 5 has the following registers.
•
•
•
•
•
Port mode register 5 (PMR5)
Port control register 5 (PCR5)
Port data register 5 (PDR5)
Port pull-up control register 5 (PUCR5)
Port drive control register 5 (PDVR5)
Rev. 1.00 Oct. 03, 2008 Page 285 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.4.1
Port Mode Register 5 (PMR5)
Address: H'FF0004
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PMR57
PMR56
PMR55
PMR54
PMR53
PMR52
PMR51
PMR50
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PMR57
Port 57 mode
0: General I/O port
R/W
6
PMR56
Port 56 mode
R/W
5
PMR55
Port 55 mode
1: The function selected by the peripheral function
mapping controller (PMC).
4
PMR54
Port 54 mode
3
PMR53
Port 53 mode
R/W
PMR5 is a register that selects the function of the
R/W
multiplexed pins: general I/O function or the function
R/W
selected by the PMC.
2
PMR52
Port 52 mode
R/W
1
PMR51
Port 51 mode
R/W
0
PMR50
Port 50 mode
R/W
Rev. 1.00 Oct. 03, 2008 Page 286 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.4.2
Port Control Register 5 (PCR5)
Address: H'FFFFF4
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
PCR57
PCR56
PCR55
PCR54
PCR53
PCR52
PCR51
PCR50
0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
PCR57
Port 57 control
R/W
6
PCR56
Port 56 control
0: When the corresponding pin is designated as a
general I/O port, the pin functions as an input
port.
5
PCR55
Port 55 control
4
PCR54
Port 54 control
3
PCR53
Port 53 control
2
PCR52
Port 52 control
1
PCR51
Port 51 control
0
PCR50
Port 50 control
1: When the corresponding pin is designated as a
general I/O port, the pin functions as an output
port.
R/W
R/W
R/W
R/W
PCR5 is a register that selects inputs/outputs in bit R/W
units for pins to be used as general I/O ports of port
R/W
5.
R/W
• PCR57 bit to PCR50 bit (port 57 to 50 control)
When the corresponding pin is designated in PMR5 as a general I/O pin, setting a PCR5 bit to
1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an
input port.
Rev. 1.00 Oct. 03, 2008 Page 287 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.4.3
Port Data Register 5 (PDR5)
Address: H'FFFFE4
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PDR57
PDR56
PDR55
PDR54
PDR53
PDR52
PDR51
PDR50
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PDR57
Port 57 data
0: Low level
R/W
6
PDR56
Port 56 data
1: High level
R/W
5
PDR55
Port 55 data
4
PDR54
Port 54 data
3
PDR53
Port 53 data
2
PDR52
Port 52 data
1
PDR51
Port 51 data
0
PDR50
Port 50 data
PDR5 is a register that stores output data for port 5 R/W
pins. When PCR5 bits are set to 1, the values
R/W
stored in PDR5 are output.
R/W
When PDR5 is read while PCR5 bits are set to 1,
the values stored in PDR5 are read. If PDR5 is read R/W
while PCR5 bits are cleared to 0, the pin states are R/W
read regardless of the value stored in PDR5.
R/W
Rev. 1.00 Oct. 03, 2008 Page 288 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.4.4
Port Pull-Up Control Register 5 (PUCR5)
Address: H'FF0014
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
—
—
PUCR55
PUCR54
PUCR53
PUCR52
PUCR51
PUCR50
0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
6

Reserved
These bits are read as 0. The write value should be 
0.

5
PUCR55
Port 55 pull-up
control
0: The pull-up MOS of corresponding pin is
disabled.
R/W
4
PUCR54
Port 54 pull-up
control
1: The pull-up MOS of corresponding pin is
enabled.
R/W
3
PUCR53
Port 53 pull-up
control
PUCR5 is a register that controls the pull-up MOS
in bit units of the pins set as the input ports.
R/W
2
PUCR52
Port 52 pull-up
control
R/W
1
PUCR51
Port 51 pull-up
control
R/W
0
PUCR50
Port 50 pull-up
control
R/W
• PUCR55 bit to PUCR50 bit (port 55 to 50 pull-up control)
This function is valid only for the pin set as general input, and for the input pin with a function
selected by the PMC.
Rev. 1.00 Oct. 03, 2008 Page 289 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.4.5
Port Drive Control Register 5 (PDVR5)
Address: H'FF0034
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0


PDVR55
PDVR54
PDVR53
PDVR52
PDVR51
PDVR50
0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is read as 0. The write value should be 0.

6

Reserved
5
PDVR55
Port 55 drive
control
0: Normal output
4
PDVR54
Port 54 drive
control
3
PDVR53
Port 53 drive
control
PDVR5 is a register that controls drive capability of R/W
the output pins in a bit unit.
When pins P56 and P57 are set as general output, R/W
2
PDVR52
Port 52 drive
control
1
PDVR51
Port 51 drive
control
R/W
0
PDVR50
Port 50 drive
control
R/W

R/W
1: High-current drive output
they function as NMOS push-pull output and thus
drive capability cannot be selected for them.
R/W
Note: When pins P56 and P57 are set as general output, they function as NMOS push-pull output,
and have characteristics different from those of other CMOS outputs. When set as SDA and
SCL of IIC2, they function as NMOS open-drain output. For details, see section 28,
Electrical Characteristics.
Rev. 1.00 Oct. 03, 2008 Page 290 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.5
Port 6
Port 6
Figure 10.5 shows the pin configuration of port 6.
P67/FTIOD1
P66/FTIOC1
P65/FTIOB1
P64/FTIOA1
P63/FTIOD0
P62/FTIOC0
P61/FTIOB0
P60/FTIOA0
Note: Only the functions initially selected by PMCR are shown following the port pin names.
Figure 10.5 Port 6 Pin Configuration
Port 6 has the following registers.
•
•
•
•
•
Port mode register 6 (PMR6)
Port control register 6 (PCR6)
Port data register 6 (PDR6)
Port pull-up control register 6 (PUCR6)
Port drive control register 6 (PDVR6)
Rev. 1.00 Oct. 03, 2008 Page 291 of 962
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Section 10 I/O Ports
10.5.1
Port Mode Register 6 (PMR6)
Address: H'FF0005
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PMR67
PMR66
PMR65
PMR64
PMR63
PMR62
PMR61
PMR60
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PMR67
Port 67 mode
0: General I/O port
R/W
6
PMR66
Port 66 mode
R/W
5
PMR65
Port 65 mode
1: The function selected by the peripheral function
mapping controller (PMC).
4
PMR64
Port 64 mode
3
PMR63
Port 63 mode
R/W
PMR6 is a register that selects the function of the
R/W
multiplexed pins: general I/O function or the function
R/W
selected by the PMC.
2
PMR62
Port 62 mode
R/W
1
PMR61
Port 61 mode
R/W
0
PMR60
Port 60 mode
R/W
Rev. 1.00 Oct. 03, 2008 Page 292 of 962
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Section 10 I/O Ports
10.5.2
Port Control Register 6 (PCR6)
Address: H'FFFFF5
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
PCR67
PCR66
PCR65
PCR64
PCR63
PCR62
PCR61
PCR60
0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
PCR67
Port 67 control
R/W
6
PCR66
Port 66 control
0: When the corresponding pin is designated as a
general I/O port, the pin functions as an input
port.
5
PCR65
Port 65 control
4
PCR64
Port 64 control
3
PCR63
Port 63 control
2
PCR62
Port 62 control
1
PCR61
Port 61 control
0
PCR60
Port 60 control
1: When the corresponding pin is designated as a
general I/O port, the pin functions as an output
port.
R/W
R/W
R/W
R/W
PCR6 is a register that selects inputs/outputs in bit R/W
units for pins to be used as general I/O ports of port
R/W
6.
R/W
• PCR67 bit to PCR60 bit (port 67 to 60 control)
When the corresponding pin is designated in PMR6 as a general I/O pin, setting a PCR6 bit to
1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an
input port.
Rev. 1.00 Oct. 03, 2008 Page 293 of 962
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Section 10 I/O Ports
10.5.3
Port Data Register 6 (PDR6)
Address: H'FFFFE5
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PDR67
PDR66
PDR65
PDR64
PDR63
PDR62
PDR61
PDR60
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PDR67
Port 67 data
0: Low level
R/W
6
PDR66
Port 66 data
1: High level
R/W
5
PDR65
Port 65 data
4
PDR64
Port 64 data
3
PDR63
Port 63 data
2
PDR62
Port 62 data
1
PDR61
Port 61 data
0
PDR60
Port 60 data
PDR6 is a register that stores output data for port 6 R/W
pins. When PCR6 bits are set to 1, the values
R/W
stored in PDR6 are output.
R/W
When PDR6 is read while PCR6 bits are set to 1,
the values stored in PDR6 are read. If PDR6 is read R/W
while PCR6 bits are cleared to 0, the pin states are R/W
read regardless of the value stored in PDR6.
R/W
Rev. 1.00 Oct. 03, 2008 Page 294 of 962
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Section 10 I/O Ports
10.5.4
Port Pull-Up Control Register 6 (PUCR6)
Address: H'FF0015
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PUCR67
PUCR66
PUCR65
PUCR64
PUCR63
PUCR62
PUCR61
PUCR60
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PUCR67
Port 67 pull-up
control
0: The pull-up MOS of corresponding pin is
disabled.
R/W
6
PUCR66
Port 66 pull-up
control
1: The pull-up MOS of corresponding pin is
enabled.
R/W
5
PUCR65
Port 65 pull-up
control
PUCR6 is a register that controls the pull-up MOS
in bit units of the pins set as the input ports.
R/W
4
PUCR64
Port 64 pull-up
control
R/W
3
PUCR63
Port 63 pull-up
control
R/W
2
PUCR62
Port 62 pull-up
control
R/W
1
PUCR61
Port 61 pull-up
control
R/W
0
PUCR60
Port 60 pull-up
control
R/W
• PUCR67 bit to PUCR60 bit (port 67 to 60 pull-up control)
This function is valid only for the pin set as general input, and for the input pin with a function
selected by the PMC.
Rev. 1.00 Oct. 03, 2008 Page 295 of 962
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Section 10 I/O Ports
10.5.5
Port Drive Control Register 6 (PDVR6)
Address: H'FF0035
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PDVR67
PDVR66
PDVR65
PDVR64
PDVR63
PDVR62
PDVR61
PDVR60
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PDVR67
Port 67 drive
control
0: Normal output
R/W
6
PDVR66
Port 66 drive
control
5
PDVR65
Port 65 drive
control
PDVR6 is a register that controls drive capability of R/W
the output pins in a bit unit.
R/W
4
PDVR64
Port 64 drive
control
R/W
3
PDVR63
Port 63 drive
control
R/W
2
PDVR62
Port 62 drive
control
R/W
1
PDVR61
Port 61 drive
control
R/W
0
PDVR60
Port 60 drive
control
R/W
Rev. 1.00 Oct. 03, 2008 Page 296 of 962
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1: High-current drive output
Section 10 I/O Ports
10.6
Port 8
Port 8
Figure 10.6 shows the pin configuration of port 8.
P87/TREO
P86/TRBO
P85/TRAIO
Note: Only the functions initially selected by PMCR are shown following the port pin names.
Figure 10.6 Port 8 Pin Configuration
Port 8 has the following registers.
•
•
•
•
•
Port mode register 8 (PMR8)
Port control register 8 (PCR8)
Port data register 8 (PDR8)
Port pull-up control register 8 (PUCR8)
Port drive control register 8 (PDVR8)
Rev. 1.00 Oct. 03, 2008 Page 297 of 962
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Section 10 I/O Ports
10.6.1
Port Mode Register 8 (PMR8)
Address: H'FF0005
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PMR67
PMR66
PMR65
PMR64
PMR63
PMR62
PMR61
PMR60
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PMR87
Port 87 mode
0: General I/O port
R/W
6
PMR86
Port 86 mode
R/W
5
PMR85
Port 85 mode
1: The function selected by the peripheral function
mapping controller (PMC).
R/W
PMR8 is a register that selects the function of the
multiplexed pins: general I/O function or the function
selected by the PMC.
4 to 0 
Reserved
Rev. 1.00 Oct. 03, 2008 Page 298 of 962
REJ09B0465-0100
These bits are read as 0. The write value should be 
0.
Section 10 I/O Ports
10.6.2
Port Control Register 8 (PCR8)
Address: H'FFFFF7
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
PCR87
PCR86
PCR85





0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
PCR87
Port 87 control
6
PCR86
Port 86 control
5
PCR85
Port 85 control
0: When the corresponding pin is designated as a R/W
general I/O port, the pin functions as an input
R/W
port.
R/W
1: When the corresponding pin is designated as a
general I/O port, the pin functions as an output
port.
PCR8 is a register that selects inputs/outputs in bit
units for pins to be used as general I/O ports of
port 8.
4 to 0 
Reserved
These bits are read as 0. The write value should
be 0.

• PCR87 bit to PCR85 bit (port 87 to 85 control)
When the corresponding pin is designated in PMR8 as a general I/O pin, setting a PCR8 bit to
1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an
input port.
Rev. 1.00 Oct. 03, 2008 Page 299 of 962
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Section 10 I/O Ports
10.6.3
Port Data Register 8 (PDR8)
Address: H'FFFFE7
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PDR87
PDR86
PDR85





0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PDR87
Port 87 data
0: Low level
R/W
6
PDR86
Port 86 data
1: High level
R/W
5
PDR85
Port 85 data
PDR8 is a register that stores output data for port R/W
8 pins. When PCR8 bits are set to 1, the values
stored in PDR8 are output.
When PDR8 is read while PCR8 bits are set to 1,
the values stored in PDR8 are read. If PDR8 is
read while PCR8 bits are cleared to 0, the pin
states are read regardless of the value stored in
PDR8.
4 to 0 
Reserved
Rev. 1.00 Oct. 03, 2008 Page 300 of 962
REJ09B0465-0100
These bits are read as 0. The write value should
be 0.

Section 10 I/O Ports
10.6.4
Port Pull-Up Control Register 8 (PUCR8)
Address: H'FF0017
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PUCR87
PUCR86
PUCR85





0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PUCR87
Port 87 pull-up
control
0: The pull-up MOS of corresponding pin is
disabled.
R/W
6
PUCR86
Port 86 pull-up
control
1: The pull-up MOS of corresponding pin is
enabled.
R/W
5
PUCR85
Port 85 pull-up
control
PUCR8 is a register that controls the pull-up MOS R/W
in bit units of the pins set as the input ports.
Reserved
These bits are read as 0. The write value should
be 0.
4 to 0 

• PUCR87 bit to PUCR85 bit (port 87 to 85 pull-up control)
This function is valid only for the pin set as general input, and for the input pin with a function
selected by the PMC.
Rev. 1.00 Oct. 03, 2008 Page 301 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.6.5
Port Drive Control Register 8 (PDVR8)
Address: H'FF0037
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PDVR87
PDVR86
PDVR85





0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PDVR87
Port 87 drive
control
0: Normal output
R/W
6
PDVR86
Port 86 drive
control
5
PDVR85
Port 85 drive
control
PDVR8 is a register that controls drive capability of R/W
the output pins in a bit unit.
R/W
4 to 0 
10.6.6
Reserved
1: High-current drive output
These bits are read as 0. The write value should
be 0.
Notes on Using Port 8
When using on-chip debugger function, set port 8 as general I/O port using PMR8.
Rev. 1.00 Oct. 03, 2008 Page 302 of 962
REJ09B0465-0100

Section 10 I/O Ports
10.7
Port 9
Port 9
Figure 10.7 shows the pin configuration of port 9. Port 9 is not available on the H8S/20103 group.
P97/FTIOD3
P96/FTIOC3
P95/FTIOB3
P94/FTIOA3
P93/FTIOD2
P92/FTIOC2
P91/FTIOB2
P90/FTIOA2
Note: Only the functions initially selected by PMCR are shown following the port pin names.
Figure 10.7 Port 9 Pin Configuration
Port 9 has the following registers.
•
•
•
•
•
Port mode register 9 (PMR9)
Port control register 9 (PCR9)
Port data register 9 (PDR9)
Port pull-up control register 9 (PUCR9)
Port drive control register 9 (PDVR9)
Rev. 1.00 Oct. 03, 2008 Page 303 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.7.1
Port Mode Register 9 (PMR9)
Address: H'FF0008
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PMR97
PMR96
PMR95
PMR94
PMR93
PMR92
PMR91
PMR90
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PMR97
Port 97 mode
0: General I/O port
R/W
6
PMR96
Port 96 mode
R/W
5
PMR95
Port 95 mode
1: The function selected by the peripheral function
mapping controller (PMC).
4
PMR94
Port 94 mode
3
PMR93
Port 93 mode
R/W
PMR9 is a register that selects the function of the
R/W
multiplexed pins: general I/O function or the function
R/W
selected by the PMC.
2
PMR92
Port 92 mode
R/W
1
PMR91
Port 91 mode
R/W
0
PMR90
Port 90 mode
R/W
Rev. 1.00 Oct. 03, 2008 Page 304 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.7.2
Port Control Register 9 (PCR9)
Address: H'FFFFF8
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
PCR97
PCR96
PCR95
PCR94
PCR93
PCR92
PCR91
PCR90
0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
PCR97
Port 97 control
R/W
6
PCR96
Port 96 control
0: When the corresponding pin is designated as a
general I/O port, the pin functions as an input
port.
5
PCR95
Port 95 control
4
PCR94
Port 94 control
3
PCR93
Port 93 control
2
PCR92
Port 92 control
1
PCR91
Port 91 control
0
PCR90
Port 90 control
1: When the corresponding pin is designated as a
general I/O port, the pin functions as an output
port.
R/W
R/W
R/W
R/W
PCR9 is a register that selects inputs/outputs in bit R/W
units for pins to be used as general I/O ports of port
R/W
9.
R/W
• PCR97 bit to PCR90 bit (port 97 to 90 control)
When the corresponding pin is designated in PMR9 as a general I/O pin, setting a PCR9 bit to
1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an
input port.
Rev. 1.00 Oct. 03, 2008 Page 305 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.7.3
Port Data Register 9 (PDR9)
Address: H'FFFFE8
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PDR97
PDR96
PDR95
PDR94
PDR93
PDR92
PDR91
PDR90
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PDR97
Port 97 data
0: Low level
R/W
6
PDR96
Port 96 data
1: High level
R/W
5
PDR95
Port 95 data
4
PDR94
Port 94 data
3
PDR93
Port 93 data
2
PDR92
Port 92 data
1
PDR91
Port 91 data
0
PDR90
Port 90 data
PDR9 is a register that stores output data for port 9 R/W
pins. When PCR9 bits are set to 1, the values
R/W
stored in PDR9 are output.
R/W
When PDR9 is read while PCR9 bits are set to 1,
the values stored in PDR9 are read. If PDR9 is read R/W
while PCR9 bits are cleared to 0, the pin states are R/W
read regardless of the value stored in PDR9.
R/W
Rev. 1.00 Oct. 03, 2008 Page 306 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.7.4
Port Pull-Up Control Register 9 (PUCR9)
Address: H'FF0018
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PUCR97
PUCR96
PUCR95
PUCR94
PUCR93
PUCR92
PUCR91
PUCR90
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PUCR97
Port 97 pull-up
control
0: The pull-up MOS of corresponding pin is
disabled.
R/W
6
PUCR96
Port 96 pull-up
control
1: The pull-up MOS of corresponding pin is
enabled.
R/W
5
PUCR95
Port 95 pull-up
control
PUCR9 is a register that controls the pull-up MOS
in bit units of the pins set as the input ports.
R/W
4
PUCR94
Port 94 pull-up
control
R/W
3
PUCR93
Port 93 pull-up
control
R/W
2
PUCR92
Port 92 pull-up
control
R/W
1
PUCR91
Port 91 pull-up
control
R/W
0
PUCR90
Port 90 pull-up
control
R/W
• PUCR97 bit to PUCR90 bit (port 97 to 90 pull-up control)
This function is valid only for the pin set as general input, and for the input pin with a function
selected by the PMC.
Rev. 1.00 Oct. 03, 2008 Page 307 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.7.5
Port Drive Control Register 9 (PDVR9)
Address: H'FF0038
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PDVR97
PDVR96
PDVR95
PDVR94
PDVR93
PDVR92
PDVR91
PDVR90
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PDVR97
Port 97 drive
control
0: Normal output
R/W
6
PDVR96
Port 96 drive
control
5
PDVR95
Port 95 drive
control
PDVR9 is a register that controls drive capability of R/W
the output pins in a bit unit.
R/W
4
PDVR94
Port 94 drive
control
R/W
3
PDVR93
Port 93 drive
control
R/W
2
PDVR92
Port 92 drive
control
R/W
1
PDVR91
Port 91 drive
control
R/W
0
PDVR90
Port 90 drive
control
R/W
Rev. 1.00 Oct. 03, 2008 Page 308 of 962
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1: High-current drive output
Section 10 I/O Ports
10.8
Port A
Port A consists of general I/O pins that are also used as analog input pins for A/D converter unit 1
and unit 2 (only in the H8S/20223 group).
The functions of PA4 to PA7 can be selected with the peripheral function mapping register of the
PMC (except for the H8S/20223 group).
For selection of functions by the peripheral function mapping controller, see section 9, Peripheral
I/O Mapping Controller. Figure 10.8 shows the pin configuration of port A.
PA7/AN3_2
PA6/AN2_2
PA5/AN1_2
PA4/AN0_2
PA3/AN11
PA2/AN10
PA1/AN9
PA0/AN8
H8S/20103 group
PA7
PA6
PA5
PA4
PA3/AN11
PA2/AN10
PA1/AN9
PA0/AN8
Port A
H8S/20203 group
Port A
Port A
H8S/20223 group
PA7
PA6
PA5
PA4
Figure 10.8 Port A Pin Configuration
Port A has the following registers.
•
•
•
•
Port mode register A (PMRA)
Port control register A (PCRA)
Port data register A (PDRA)
Port pull-up control register A (PUCRA)
Rev. 1.00 Oct. 03, 2008 Page 309 of 962
REJ09B0465-0100
Section 10 I/O Ports
• H8S/20103 group
10.8.1
Port Mode Register A (PMRA)
Address: H'FF0009
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PMRA7
PMRA6
PMRA5
PMRA4

PMRA2


0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PMRA7
Port A7 mode
0: General I/O port
R/W
6
PMRA6
Port A6 mode
R/W
5
PMRA5
Port A5 mode
1: The function selected by the peripheral function
mapping controller (PMC).
4
PMRA4
Port A4 mode
3

Reserved
This bit is read as 0. The write value should be 0.

2
PMRA2
Port A2 mode
0: General I/O port
R/W
R/W
PMRA is a register that selects the function of the
R/W
port A multiplexed pins: general I/O function or the
function selected by the PMC. PMRA also provides
the bit to select the function of the PB0 pin.
1: AN0 input pin
1, 0

Reserved
These bits read as 0. The write value should be 0.

• PMRA7 bit to PMRA4 bit (port A7 to A4 mode)
These bits select the function of the multiplexed pins PA7 to PA4: general I/O function or the
function selected by the PMC.
• PMRA2 bit (port A2 mode)
This bit selects general I/O function or the analog input function for PB0.
Rev. 1.00 Oct. 03, 2008 Page 310 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.8.2
Port Control Register A (PCRA)
Address: H'FFFFF9
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
PCRA7
PCRA6
PCRA5
PCRA4




0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
PCRA7
6
PCRA6
5
PCRA5
4
PCRA4
Port A7 control 0: When the corresponding pin is designated as a
general I/O port, the pin functions as an input
Port A6 control
port.
Port A5 control
1: When the corresponding pin is designated as a
Port A4 control
general I/O port, the pin functions as an output
port.
R/W
R/W
R/W
R/W
PCRA is a register that selects inputs/outputs in bit
units for pins to be used as general I/O ports of port
A.
3 to 0 
Reserved
These bits are read as 0. The write value should be 
0.
• PCRA7 bit to PCRA4 bit (port A7 to A4 control)
When the corresponding pin is designated in PMRA as a general I/O pin, setting a PCRA bit to
1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an
input port.
Rev. 1.00 Oct. 03, 2008 Page 311 of 962
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Section 10 I/O Ports
10.8.3
Port Data Register A (PDRA)
Address: H'FFFFE9
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PDRA7
PDRA6
PDRA5
PDRA4




0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PDRA7
Port A7 data
0: Low level
R/W
6
PDRA6
Port A6 data
1: High level
R/W
5
PDRA5
Port A5 data
4
PDRA4
Port A4 data
PDRA is a register that stores output data for port A R/W
pins. When PCRA bits are set to 1, the values
R/W
stored in PDRA are output.
When PDRA is read while PCRA bits are set to 1,
the values stored in PDRA are read. If PDRA is
read while PCRA bits are cleared to 0, the pin
states are read regardless of the value stored in
PDRA.
3 to 0 
Reserved
Rev. 1.00 Oct. 03, 2008 Page 312 of 962
REJ09B0465-0100
These bits are read as 0. The write value should be 
0.
Section 10 I/O Ports
10.8.4
Port Pull-Up Control Register A (PUCRA)
Address: H'FF0019
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PUCRA7
PUCRA6
PUCRA5
PUCRA4




0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
7
PUCRA7*
Port A7 pull-up 0: The pull-up MOS of corresponding pin is
disabled.
control
R/W
6
PUCRA6*
Port A6 pull-up 1: The pull-up MOS of corresponding pin is not
enabled.
control
R/W
5
PUCRA5*
Port A5 pull-up PUCRA is a register that controls the pull-up MOS
in bit units of the pins set as the input ports.
control
R/W
4
PUCRA4*
Port A4 pull-up
control
R/W
3 to 0 
Note:
*
Reserved
Description
R/W
These bits are read as 0. The write value should be 
0.
When PA7 to PA4 are set as the analog input pin, clear the corresponding bits to 0.
• PUCRA7 bit to PUCRA4 bit (port A7 to A4 pull-up control)
This function is valid only for the pin set as general input, and for the input pin with a function
selected by the PMC.
Rev. 1.00 Oct. 03, 2008 Page 313 of 962
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Section 10 I/O Ports
• H8S/20203 group
10.8.5
Port Mode Register A (PMRA)
Address: H'FF0009
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PMRA7
PMRA6
PMRA5
PMRA4

PMRA2


0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PMRA7
Port A7 mode
0: General I/O port
R/W
6
PMRA6
Port A6 mode
R/W
5
PMRA5
Port A5 mode
1: The function selected by the peripheral function
mapping controller (PMC).
4
PMRA4
Port A4 mode
3

Reserved
2
PMRA2
Port A2 mode
PMRA is a register that selects the function of the
port A multiplexed pins: general I/O function or the
function selected by the PMC.
R/W
R/W
This bit is read as 0. The write value should be 0.

0: General I/O port
R/W
1: AN0 input pin
1, 0

Reserved
These bits are read as 0. The write value should be 
0.
• PMRA7 bit to PMRA4 bit (port A7 to A4 mode)
These bits select the function of the multiplexed pins PA7 to PA4: general I/O function or the
function selected by the PMC.
• PMRA2 bit (port A2 mode)
This bit selects general I/O function or the analog input function for PB0.
Rev. 1.00 Oct. 03, 2008 Page 314 of 962
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Section 10 I/O Ports
10.8.6
Port Control Register A (PCRA)
Address: H'FFFFF9
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
PCRA7
PCRA6
PCRA5
PCRA4
PCRA3
PCRA2
PCRA1
PCRA0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
PCRA7
6
PCRA6
5
PCRA5
4
PCRA4
3
PCRA3
Port A7 control 0: When the corresponding pin is designated as a
general I/O port, the pin functions as an input
Port A6 control
port.
Port A5 control
1: When the corresponding pin is designated as a
Port A4 control
general I/O port, the pin functions as an output
port.
Port A3 control
2
PCRA2
1
PCRA1
0
PCRA0
R/W
R/W
R/W
R/W
R/W
PCRA
is
a
register
that
selects
inputs/outputs
in
bit
Port A2 control
R/W
units for pins to be used as general I/O ports of port
Port A1 control A.
R/W
Port A0 control
R/W
• PCRA7 bit to PCRA0 bit (port A7 to A0 control)
When the corresponding pin is designated in PMRA as a general I/O pin, setting a PCRA bit to
1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an
input port.
Rev. 1.00 Oct. 03, 2008 Page 315 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.8.7
Port Data Register A (PDRA)
Address: H'FFFFE9
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PDRA7
PDRA6
PDRA5
PDRA4
PDRA3
PDRA2
PDRA1
PDRA0
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PDRA7
Port A7 data
0: Low level
R/W
6
PDRA6
Port A6 data
1: High level
R/W
5
PDRA5
Port A5 data
4
PDRA4
Port A4 data
3
PDRA3
Port A3 data
2
PDRA2
Port A2 data
1
PDRA1
Port A1 data
0
PDRA0
Port A0 data
PDRA is a register that stores output data for port A R/W
pins. When PCRA bits are set to 1, the values
R/W
stored in PDRA are output.
R/W
When PDRA is read while PCRA bits are set to 1,
R/W
the values stored in PDRA are read. If PDRA is
read while PCRA bits are cleared to 0, the pin
R/W
states are read regardless of the value stored in
R/W
PDRA.
When pins PA3 to PA0 are set as analog input
channels by ADCSR and ADCR of the A/D
converter, however, the corresponding PCRA bits
are always read as 1 even if they are cleared to 0.
Rev. 1.00 Oct. 03, 2008 Page 316 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.8.8
Port Pull-Up Control Register A (PUCRA)
Address: H'FF0019
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PUCRA7
PUCRA6
PUCRA5
PUCRA4
PUCRA3
PUCRA2
PUCRA1
PUCRA0
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
7
PUCRA7*
Port A7 pull-up 0: The pull-up MOS of corresponding pin is
disabled.
control
R/W
6
PUCRA6*
Port A6 pull-up 1: The pull-up MOS of corresponding pin is
enabled.
control
R/W
5
PUCRA5*
Port A5 pull-up PUCRA is a register that controls the pull-up MOS
in bit units of the pins set as the input ports.
control
R/W
4
PUCRA4*
Port A4 pull-up
control
R/W
3
PUCRA3*
Port A3 pull-up
control
R/W
2
PUCRA2*
Port A2 pull-up
control
R/W
1
PUCRA1*
Port A1 pull-up
control
R/W
0
PUCRA0*
Port A0 pull-up
control
R/W
Note:
*
Description
R/W
When PA7 to PA4 are set as the analog input pin, clear the corresponding bits to 0.
• PUCRA7 bit to PUCRA0 bit (port A7 to A0 pull-up control)
This function is valid only for the pin set as general input, and for the input pin with a function
selected by the PMC. However, this setting is invalid for the analog input pin.
Rev. 1.00 Oct. 03, 2008 Page 317 of 962
REJ09B0465-0100
Section 10 I/O Ports
• H8S/20223 group
10.8.9
Port Mode Register A (PMRA)
Address: H'FF0009
Bit:
Value after reset:
Bit
Symbol
b7
b6
b5
b4
b3
b2
b1
b0




PMRA3
PMRA2


0
0
0
0
0
0
0
0
Bit Name
Description
R/W
7 to 4 
Reserved
These bits are read as 0. The write value should
be 0.

3
Port A3 mode
0: General I/O port
R/W
PMRA3
1: AN0_2 input pin
2
PMRA2
Port A2 mode
0: General I/O port
R/W
1: AN0 input pin
1, 0

Reserved
These bits are read as 0. The write value should
be 0.

PMRA is a register that selects the function of the port A multiplexed pins: general I/O function or
the function selected by the PMC. PMRA also provides the bit to select the function of the PB0
pin.
• PMRA3 bit (port A3 mode)
This bit selects general I/O function or the function selected by the PMC.
• PMRA2 bit (port A2 mode)
This bit selects general I/O function or the analog input function for PB0.
Rev. 1.00 Oct. 03, 2008 Page 318 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.8.10 Port Control Register A (PCRA)
Address: H'FFFFF9
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
PCRA7
PCRA6
PCRA5
PCRA4
PCRA3
PCRA2
PCRA1
PCRA0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
PCRA7
6
PCRA6
5
PCRA5
4
PCRA4
3
PCRA3
Port A7 control 0: When the corresponding pin is designated as a
general I/O port, the pin functions as an input
Port A6 control
port.
Port A5 control
1: When the corresponding pin is designated as a
Port A4 control
general I/O port, the pin functions as an output
port.
Port A3 control
2
PCRA2
1
PCRA1
0
PCRA0
R/W
R/W
R/W
R/W
R/W
PCRA
is
a
register
that
selects
inputs/outputs
in
bit
Port A2 control
R/W
units for pins to be used as general I/O ports of port
Port A1 control A.
R/W
Port A0 control
R/W
• PCRA7 bit to PCRA0 bit (port A7 to A0 control)
When the corresponding pin is designated in PMRA as a general I/O pin, setting a PCRA bit to
1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an
input port.
Rev. 1.00 Oct. 03, 2008 Page 319 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.8.11 Port Data Register A (PDRA)
Address: H'FFFFE9
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PDRA7
PDRA6
PDRA5
PDRA4
PDRA3
PDRA2
PDRA1
PDRA0
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PDRA7
Port A7 data
0: Low level
R/W
6
PDRA6
Port A6 data
1: High level
R/W
5
PDRA5
Port A5 data
4
PDRA4
Port A4 data
3
PDRA3
Port A3 data
2
PDRA2
Port A2 data
1
PDRA1
Port A1 data
0
PDRA0
Port A0 data
PDRA is a register that stores output data for port A R/W
pins. When PCRA bits are set to 1, the values
R/W
stored in PDRA are output.
R/W
When PDRA is read while PCRA bits are set to 1,
R/W
the values stored in PDRA are read. If PDRA is
read while PCRA bits are cleared to 0, the pin
R/W
states are read regardless of the value stored in
R/W
PDRA.
Rev. 1.00 Oct. 03, 2008 Page 320 of 962
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Section 10 I/O Ports
10.8.12 Port Pull-Up Control Register A (PUCRA)
Address: H'FF0019
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PUCRA7
PUCRA6
PUCRA5
PUCRA4
PUCRA3
PUCRA2
PUCRA1
PUCRA0
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
7
PUCRA7*
Port A7 pull-up 0: The pull-up MOS of corresponding pin is
disabled.
control
R/W
6
PUCRA6*
Port A6 pull-up 1: The pull-up MOS of corresponding pin is
enabled.
control
R/W
5
PUCRA5*
Port A5 pull-up PUCRA is a register that controls the pull-up MOS
in bit units of the pins set as the input ports.
control
R/W
4
PUCRA4*
Port A4 pull-up
control
R/W
3
PUCRA3*
Port A3 pull-up
control
R/W
2
PUCRA2*
Port A2 pull-up
control
R/W
1
PUCRA1*
Port A1 pull-up
control
R/W
0
PUCRA0*
Port A0 pull-up
control
R/W
Note:
*
Description
R/W
When PA7 to PA0 are set as the analog input pin, clear the corresponding bits to 0.
• PUCRA7 bit to PUCRA0 bit (port A7 to A0 pull-up control)
This function is valid only for the pin set as general input, and for the input pin with a function
selected by the PMC. However, this setting is invalid for the analog input pin.
10.8.13 Notes on Using Port A
1. The PA4 pin is initially set as general I/O pin. If using this pin as the AN0_2 analog input pin
for the A/D converter unit 2 in the H8S/20223 group, set the PMRA3 bit in PMRA to 1.
2. In the H8S/20223 group, pins PA7 to PA4 can be used as the general I/O pins or analog input
pins. If using these pins as the general I/O pins, do not set bits CH3 to CH0 in ADCSR_2 of
the A/D converter unit 2 to set these pins as the analog input pins.
Rev. 1.00 Oct. 03, 2008 Page 321 of 962
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Section 10 I/O Ports
10.9
Port B
Port B
Port B consists of general I/O pins that are also used as analog input pins for the A/D converter
unit 1, or as analog output pins for the D/A converter. Figure 10.9 shows the pin configuration of
port B.
PB7/AN7/DA1
PB6/AN6/DA0
PB5/AN5
PB4/AN4
PB3/AN3
PB2/AN2
PB1/AN1
PB0/AN0
Figure 10.9 Port B Pin Configuration
Port B has the following registers.
• Port control register B (PCRB)
• Port data register B (PDRB)
• Port pull-up control register B (PUCRB)
Rev. 1.00 Oct. 03, 2008 Page 322 of 962
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Section 10 I/O Ports
10.9.1
Port Control Register B (PCRB)
Address: H'FFFFFA
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
PCRB7
PCRB6
PCRB5
PCRB4
PCRB3
PCRB2
PCRB1
PCRB0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
PCRB7
6
PCRB6
5
PCRB5
4
PCRB4
3
PCRB3
Port B7 control 0: When the corresponding pin is designated as a
general I/O port, the pin functions as an input
Port B6 control
port.
Port B5 control
1: When the corresponding pin is designated as a
Port B4 control
general I/O port, the pin functions as an output
port.
Port B3 control
2
PCRB2
1
PCRB1
0
PCRB0
R/W
R/W
R/W
R/W
R/W
PCRB
is
a
register
that
selects
inputs/outputs
in
bit
Port B2 control
R/W
units for pins to be used as general I/O ports of port
Port B1 control B.
R/W
Port B0 control
R/W
• PCRB7 bit to PCRB0 bit (port B7 to B0 control)
When the corresponding pin is designated in PMRB as a general I/O pin, setting a PCRB bit to
1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an
input port.
Rev. 1.00 Oct. 03, 2008 Page 323 of 962
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Section 10 I/O Ports
10.9.2
Port Data Register B (PDRB)
Address: H'FFFFEA
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PDRB7
PDRB6
PDRB5
PDRB4
PDRB3
PDRB2
PDRB1
PDRB0
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PDRB7
Port B7 data
0: Low level
R/W
6
PDRB6
Port B6 data
1: High level
R/W
5
PDRB5
Port B5 data
R/W
4
PDRB4
Port B4 data
3
PDRB3
Port B3 data
When the pins are set as analog input channels by
ADCSR and ADCR of the A/D converter, however,
the corresponding PCRB bits are always read as 1
even if they are cleared to 0.
2
PDRB2
Port B2 data
1
PDRB1
Port B1 data
0
PDRB0
Port B0 data
REJ09B0465-0100
R/W
Similarly, when pins PB6 and PB7 are set as analog R/W
output for the D/A converter by bit DAOE1 in DACR R/W
of the D/A converter, the corresponding PCRB bits
are always read as 1 even if they are cleared to 0. R/W
PDRB is a register that stores output data for port B pins.
Rev. 1.00 Oct. 03, 2008 Page 324 of 962
R/W
Section 10 I/O Ports
10.9.3
Port Pull-Up Control Register B (PUCRB)
Address: H'FF001A
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PUCRB7
PUCRB6
PUCRB5
PUCRB4
PUCRB3
PUCRB2
PUCRB1
PUCRB0
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PUCRB7
Port B7 pull-up 0: The pull-up MOS of corresponding pin is
disabled.
control
R/W
6
PUCRB6
Port B6 pull-up 1: The pull-up MOS of corresponding pin is
enabled.
control
R/W
5
PUCRB5
Port B5 pull-up PUCRB is a register that controls the pull-up MOS
in bit units of the pins set as the input ports.
control
R/W
4
PUCRB4
Port B4 pull-up
control
R/W
3
PUCRB3
Port B3 pull-up
control
R/W
2
PUCRB2
Port B2 pull-up
control
R/W
1
PUCRB1
Port B1 pull-up
control
R/W
0
PUCRB0
Port B0 pull-up
control
R/W
• PUCRB7 bit to PUCRB0 bit (port B7 to B0 pull-up control)
This function is valid only for the pin set as general input, and for the input pin with a function
selected by the PMC. However, this setting is invalid for the analog input pin.
10.9.4
Notes on Using Port B
1. The PB0 pin is initially set as general I/O pin. If using this pin as the analog input pin for the
A/D converter, set the PMRA2 bit in PMRA to 1.
2. Pins PB7 and PB6 can be used as analog input pins for the A/D converter or analog output pins
for the D/A converter. Do not set these pins as analog input pins and analog output pins at the
same time.
Rev. 1.00 Oct. 03, 2008 Page 325 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.10
Port J
Port J
Port J consists of pins PJ1 and PJ0. These pins can also be used as external oscillation pins and
clock output pin. Figure 10.10 shows the pin configuration of port J. In selection of the function of
these multiplexed pins, the PMRJ register setting is given priority.
PJ1/OSC2/CLKOUT
PJ0/OSC1
Figure 10.10 Port J Pin Configuration
Port J has the following registers.
•
•
•
•
Port mode register J (PMRJ)
Port control register J (PCRJ)
Port data register J (PDRJ)
Port pull-up control register J (PUCRJ)
Rev. 1.00 Oct. 03, 2008 Page 326 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.10.1 Port Mode Register J (PMRJ)
Address: H'FF000C
Bit:
Value after reset:
Bit
Symbol
7 to 2 
1, 0
Note:
b7
b6
b5
b4
b3
b2






0
0
0
0
0
0
b1
b0
PMRJ[1:0]
0
Bit Name
Description
R/W
Reserved
These bits are read as 0. The write value should be 0. 
PMRJ[1:0] Port J[1:0] mode Selects PJ1 and PJ0 pin functions.
*
0
R/W
PMRJ1
PMRJ0
PJ1 Pin
PJ0 Pin
0
0
PJ1 I/O
PJ0 I/O
0
1
PJ1 I/O
OSC1 input*
(external
clock input)
1
0
CLKOUT
PJ0 I/O
1
1
OSC2
OSC1
Set the PMRJ1 and PMRJ0 bits to 01 to input the external clock on the OSC1 pin. Do
not apply the external clock to the OSC1 pin while the PMRJ1 and PMRJ0 bits are set
to 11.
Rev. 1.00 Oct. 03, 2008 Page 327 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.10.2 Port Control Register J (PCRJ)
Address: H'FFFFFC
Bit:
Value after reset:
Bit
Symbol
b7
b6
b5
b4
b3
b2
b1
b0






PCRJ1
PCRJ0
0
0
0
0
0
0
0
0
Bit Name
Description
R/W
7 to 2 
Reserved
These bits are read as 0. The write value should
be 0.

1
PCRJ1
Port J1 control
R/W
0
PCRJ0
Port J0 control
0: When the corresponding pin is designated as a
general I/O port, the pin functions as an input
port.
R/W
1: When the corresponding pin is designated as a
general I/O port, the pin functions as an output
port.
PCRJ is a register that selects inputs/outputs in bit
units for pins to be used as general I/O ports of
port J.
• PCRJ1 bit and PCRJ0 bit (port J1 and J0 control)
When the general I/O port function is selected by PMRJ, setting a PCRJ bit to 1 makes the
corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
Rev. 1.00 Oct. 03, 2008 Page 328 of 962
REJ09B0465-0100
Section 10 I/O Ports
10.10.3 Port Data Register J (PDRJ)
Address: H'FFFFEC
Bit:
Value after reset:
Bit
Symbol
b7
b6
b5
b4
b3
b2
b1
b0






PDRJ1
PDRJ0
0
0
0
0
0
0
0
0
Bit Name
Description
R/W
7 to 2 
Reserved
These bits are read as 0. The write value should be 0. 
1
PDRJ1
Port J1 data
0: Low level
R/W
0
PDRJ0
Port J0 data
1: High level
R/W
PDRJ is a register that stores output data for port J
pins. When PCRJ bits are set to 1, the values stored in
PDRJ are output.
When PDRJ is read while PCRJ bits are set to 1, the
values stored in PDRJ are read. If PDRJ is read while
PCRJ bits are cleared to 0, the pin states are read
regardless of the value stored in PDRJ.
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Section 10 I/O Ports
10.10.4 Port Pull-Up Control Register J (PUCRJ)
Address: H'FF001C
Bit:
Value after reset:
Bit
Symbol
b7
b6
b5
b4
b3
b2
b1
b0






PUCRJ1
PUCRJ0
0
0
0
0
0
0
0
0
Bit Name
Description
R/W
7 to 2 
Reserved
These bits are read as 0. The write value should
be 0.

1
PUCRJ1
Port J1 pull-up
control
0: The pull-up MOS of corresponding pin is
disabled.
R/W
0
PUCRJ0
Port J0 pull-up
control
1: The pull-up MOS of corresponding pin is
enabled.
R/W
PUCRJ is a register that controls the pull-up MOS
in bit units of the pins set as the input ports.
• PUCRJ1 bit and PUCRJ0 bit (port J1 and J0 pull-up control)
This function is valid only for the pin set as general input, and for the input pin with a function
selected by the PMC.
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Section 11 Data Transfer Controller (DTC)
Section 11 Data Transfer Controller (DTC)
This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or
software to transfer data.
Figure 11.1 shows a block diagram of the DTC.
11.1
Features
• Transfer possible over any number of channels
• Three transfer modes
 Normal mode
One operation transfers one byte or one word of data.
Memory address is incremented or decremented by 1 or 2.
From 1 to 65,536 transfers can be specified.
 Repeat mode
One operation transfers one byte or one word of data.
Memory address is incremented or decremented by 1 or 2.
Once the specified number of transfers (1 to 256) has ended, the initial state is restored, and
transfer is repeated.
 Block transfer mode
One operation transfers specified one block of data.
The block size is 1 to 256 bytes or words.
From 1 to 65,536 transfers can be specified.
Either the transfer source or the transfer destination is designated as a block area.
• One activation source can trigger a number of data transfers (chain transfer)
• Direct specification of 16-Mbyte address space possible
• Activation by software is possible.
• Transfer can be set in byte or word units.
• A CPU interrupt can be requested for the interrupt that activated the DTC.
• Module standby mode can be set.
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Section 11 Data Transfer Controller (DTC)
The DTC's register information is stored in the on-chip RAM. A 32-bit bus connects the DTC to
the on-chip RAM, enabling 32-bit/1-state reading and writing of the DTC register information.
Internal address bus
CPU interrupt
request
On-chip
RAM
Internal data bus
Figure 11.1 Block Diagram of DTC
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Register information
MRA MRB
CRA
CRB
DAR
SAR
DTC
Control logic
DTC activation
request
Interrupt
request
DTVECR
DTCERA
to
DTCERH
Interrupt controller
Section 11 Data Transfer Controller (DTC)
11.2
Register Descriptions
DTC has the following registers.
•
•
•
•
•
•
DTC mode register A (MRA)
DTC mode register B (MRB)
DTC source address register (SAR)
DTC destination address register (DAR)
DTC transfer count register A (CRA)
DTC transfer count register B (CRB)
The above six registers cannot be directly accessed from the CPU. When the DTC activation
source is generated, the DTC reads from a set of register information that is stored in an on-chip
RAM to the corresponding DTC register information and transfers data. After the data transfer, it
writes a set of updated register information back to the RAM.
•
•
•
•
•
•
•
•
•
DTC enable register A (DTCERA)
DTC enable register B (DTCERB)
DTC enable register C (DTCERC)
DTC enable register D (DTCERD)
DTC enable register E (DTCERE)
DTC enable register F (DTCERF)
DTC enable register G (DTCERG)
DTC enable register H (DTCERH)
DTC vector register (DTVECR)
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Section 11 Data Transfer Controller (DTC)
11.2.1
DTC Mode Register A (MRA)
Address:

Bit:
b7
b6
b5
SM[1:0]
Value after reset:

b4
b3
DM[1:0]


b2
MD[1:0]



Bit
Symbol
Bit Name
7
SM[1:0]
Source
0×: SAR is fixed
address mode 10: SAR is incremented after a transfer
1 and 0
(by +1 when Sz = 0; by +2 when Sz = 1)
6
b1
b0
DTC
Sz


Description
R/W

11: SAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
5
DM[1:0]
4
Destination
0×: DAR is fixed
address mode 10: DAR is incremented after a transfer
1 and 0
(by +1 when Sz = 0; by +2 when Sz = 1)

11: DAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
3
MD[1:0]
2
DTC mode 1
and 0
00: Normal mode

01: Repeat mode
10: Block transfer mode
11: Setting prohibited
1
DTC
DTC transfer
mode select
0: Destination side is repeat area or block area.
0
Sz
DTC data
transfer size
0: Byte-size transfer
1: Source side is repeat area or block area.
1: Word-size transfer
Legend:
×:
Don't care
Rev. 1.00 Oct. 03, 2008 Page 334 of 962
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

Section 11 Data Transfer Controller (DTC)
MRA selects the DTC operating mode.
• SM[1:0] bits (source address mode 1 and 0)
These bits specify an SAR operation after data transfer.
• DM[1:0] bits (destination address mode 1 and 0)
These bits specify a DAR operation after data transfer.
• MD[1:0] bits (DTC mode 1 and 0)
These bits specify the DTC transfer mode.
• DTS bit (DTC transfer mode select)
This bit specifies whether the source side or the destination side is set to be a repeat area or
block area, in repeat mode or block transfer mode.
• Sz bit (DTC data transfer size)
This bit specifies the size of data to be transferred.
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Section 11 Data Transfer Controller (DTC)
11.2.2
DTC Mode Register B (MRB)
Address:

Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
CHNE
DISEL
CHNS













Bit
Symbol
Bit Name
Description
R/W
7
CHNE
DTC chain
transfer
enable
0: Disables chain transfer.

DTC interrupt
select
0: Generates an interrupt request to the CPU only
when the specified data transfer has been
completed.
6
DISEL
1: Enables chain transfer.

1: Generates an interrupt request to the CPU every
time after the DTC transfer has been completed.
5
CHNS
4 to 0 
Chain transfer 0: Performs chain transfer consecutively.

select
1: Performs chain transfer only when transfer counter
=0
Reserved
These bits have no effect on DTC operation. The
write value should be 0.

MRB selects the DTC operating mode.
• CHNE bit (DTC chain transfer enable)
When this bit is set to 1, a chain transfer will be performed. For details, see section 11.5.4,
Chain Transfer.
In the data transfer with CHNE set to 1, determination of the end of the specified number of
transfers, clearing of the activation source flag, and clearing of DTCER are not performed.
• DISEL bit (DTC interrupt select)
When this bit is set to 1, a CPU interrupt request is generated every time the DTC transfer is
performed (the interrupt source flags as the activation source are not cleared to 0 by the DTC).
When this bit is cleared to 0, a CPU interrupt request is generated at the time when the
specified number of data transfers ends (the interrupt source flags as the activation source is
cleared to 0 by the DTC).
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Section 11 Data Transfer Controller (DTC)
11.2.3
DTC Source Address Register (SAR)
Address: 
Bit:
Value after reset:
Bit:
Value after reset:
Bit:
Value after reset:
b23
b22
b21
b20
b19
b18
b17
b16
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16








b15
b14
b13
b12
b11
b10
b9
b8
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8








b7
b6
b5
b4
b3
b2
b1
b0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0








SAR designates the source address of data to be transferred by the DTC. For word-size transfer,
specify an even source address.
11.2.4
DTC Destination Address Register (DAR)
Address:
Bit:
Value after reset:
Bit:

b23
b22
b21
b20
b19
b18
b17
b16
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16








b15
b14
b13
b12
b11
b10
b9
b8
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Value after reset:








Bit:
b7
b6
b5
b4
b3
b2
b1
b0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0








Value after reset:
DAR designates the destination address of data to be transferred by the DTC. For word-size
transfer, specify an even destination address.
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Section 11 Data Transfer Controller (DTC)
11.2.5
DTC Transfer Count Register A (CRA)
Address: 
Bit:
Value after reset:
Bit:
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8








b7
b6
b5
b4
b3
b2
b1
b0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0








CRA designates the number of times that data is to be transferred by the DTC.
In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is
decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits
(CRAH) and the lower 8 bits (CRAL). In repeat mode, CRAH holds the number of transfers while
CRAL functions as an 8-bit transfer counter (1 to 256). In block transfer mode, CRAH holds the
size of blocks while CRAL functions as a block-size counter. CRAL is decremented by 1 every
time data is transferred, and the contents of CRAH are sent when the count value reaches H'00.
11.2.6
DTC Transfer Count Register B (CRB)
Address: 
Bit:
b15
b14
b13
b12
b11
b10
b9
b8
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Value after reset:








Bit:
b7
b6
b5
b4
b3
b2
b1
b0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0








Value after reset:
CRB is a 16-bit register that designates the number of times block data is to be transferred by the
DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is
decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
The CRB is not available in normal and repeat modes.
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Section 11 Data Transfer Controller (DTC)
11.2.7
DTC Enable Registers A to H (DTCERA to DTCERH)
Address: H'FF0534 to H'FF053B
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
DTCEn7
DTCEn6
DTCEn5
DTCEn4
DTCEn3
DTCEn2
DTCEn1
DTCEn0








Value after reset:
Bit
Symbol
Bit Name
7
DTCEn7
6
DTCEn6
DTC activation 0: A relevant interrupt source is not selected as a
enable
DTC activation source.
5
DTCEn5
4
DTCEn4
3
DTCEn3
2
DTCEn2
1
DTCEn1
0
DTCEn0
Description
R/W
1: A relevant interrupt source is selected as a DTC
activation source.
[Setting condition]
•
R/W
R/W
R/W
R/W
R/W
Setting this bit to 1 specifies a relevant interrupt
source to a DTC activation source.
R/W
R/W
[Clearing conditions]
•
When the DISEL bit in MRB is set to 1 and the
data transfer has ended.
•
When the specified number of data transfers has
ended.
R/W
These bits are not automatically cleared when the
DISEL bit is 0 and the specified number of data
transfers has not ended.
•
When 0 is written to DTCE after reading DTCE =
1.
Notes: n = A to H
DTCE bits with no corresponding interrupt are reserved. The write value should always be
0.
DTCER, which is comprised of DTCERA to DTCERH, is a register that specifies DTC activation
interrupt sources. The correspondence between interrupt sources and DTCE bits is shown in table
11.1. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all
interrupts are masked, multiple activation sources can be set at one time (only at the initial setting)
by writing data after executing a dummy read on the relevant register.
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Section 11 Data Transfer Controller (DTC)
Table 11.1 Correspondence between Interrupt Sources and DTCER
Bit
Register
7
DTCERA IRQ0
6
5
4
3
2
1
0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ7
IRQ5
IRQ6
DTCERB IADEND_1 IADCMP_1 IADEND_2 IADCMP_2 ELC1FP
1
1
*
*
ELC2FP
SCI3_1_RXI SCI3_1_TXI
DTCERC SCI3_2_RXI SCI3_2_TXI SCI3_3_RXI SCI3_3_TXI 


DTCERD IIC2/SSU_ IIC2/SSU_ 
RXI
TXI

ITCMA*
2
ITCMB*
2

2
ITCMC*
2
ITCMD*
DTCERE ITDMA0_0 ITDMB0_0 ITDMC0_0 ITDMD0_0 ITDMA0_1 ITDMB0_1 ITDMC0_1 ITDMD0_1
DTCERF ITDMA1_2 ITDMB1_2 ITDMC1_2 ITDMD1_2 ITDMA1_3 ITDMB1_3 ITDMC1_3 ITDMD1_3
3
3
3
3
3
3
3
3
*
*
*
*
*
*
*
*
DTCERG 


ITESC
ITEMI
ITEHR
ITEDY
ITEWK
DTCERH 



ITGMA
ITGMB


Notes: :
1.
2.
3.
Reserved bit
Supported only in the H8S/20223 group.
Supported only in the H8S/20103 group.
Not supported in the H8S/20103 group.
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Section 11 Data Transfer Controller (DTC)
11.2.8
DTC Vector Register (DTVECR)
Address:
H'FF053D
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
SWDTE
DTVEC6
DTVEC5
DTVEC4
DTVEC3
DTVEC2
DTVEC1
DTVEC0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
SWDTE
DTC software 0: Disables the DTC activation by software.
activation
1: Enables the DTC activation by software.
enable
Setting this bit to 1 activates DTC. Only 1 can be
written to this bit.
R/W
[Clearing conditions]
•
When the DISEL bit is 0 and the specified
number of data transfers has not ended.
•
When 0 is written to the DISEL bit after a
software-activated data transfer end interrupt
(SWDTEND) request has been sent to the CPU.
When the DISEL bit is 1 and data transfer has ended
or when the specified number of data transfers has
ended, this bit will not be cleared.
6
DTVEC6
5
DTVEC5
4
DTVEC4
3
DTVEC3
2
DTVEC2
1
DTVEC1
0
DTVEC0
R/W
DTC software These bits specify a vector number for DTC
activation
activation by software.
R/W
vector 6 to 0 These bits specify a vector number for DTC software
R/W
activation.
R/W
The vector address is expressed as H'0400 + (vector
R/W
number × 2). For example, when DTVEC6 to
DTVEC0 = H'10, the vector address is H'0420.
R/W
When the bit SWDTE is 0, these bits can be written.
R/W
DTVECR enables or disables DTC activation by software, and sets a vector number for the
software activation interrupt.
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Section 11 Data Transfer Controller (DTC)
11.3
Activation Sources
The DTC operates when activated by an interrupt request or by a write to DTVECR by software.
An interrupt request can be designated by the DTCER bit. At the end of a data transfer (or the last
consecutive transfer in the case of chain transfer), the activation source interrupt flag or
corresponding bit to DTCER is cleared. For example, the activation source flag, in the case of
SCI3_1_RXI, is the RDRF flag of SCI3_1.
When an interrupt has been designated a DTC activation source, existing CPU mask level and
interrupt controller priorities have no effect. If there is more than one activation source at the same
time, the DTC operates in accordance with the default priorities for the interrupt sources.
Table 11.2 shows a relationship between activation sources and DTCER clear conditions. Figure
11.2 shows a block diagram of DTC activation source control. For details, see section 4, Interrupt
Controller.
Table 11.2 Relationship between Activation Sources and DTCER Clearing
Activation Source
DISEL = 0 and Specified
Number of Transfers Has
Not Ended
DISEL = 1 or Specified
Number of Transfers Has
Ended
Activation by software
SWDTE bit is cleared to 0
•
SWDTE bit remains set to 1
•
Interrupt request to CPU
Activation by an interrupt
•
Corresponding DTCER bit
remains set to 1.
•
Corresponding DTCER bit is
cleared to 0.
•
Activation source flag is
cleared to 0.
•
Activation source flag
remains set to 1.
•
Interrupt that became the
activation source is
requested to the CPU.
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Section 11 Data Transfer Controller (DTC)
Source flag cleared
Clear
controller
Clear
DTCER
On-chip
peripheral
module
IRQ interrupt
DTVECR
Interrupt
request
Selection circuit
Select
Clear request
DTC
CPU
Interrupt controller
Interrupt mask
Figure 11.2 Block Diagram of DTC Activation Source Control
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Section 11 Data Transfer Controller (DTC)
11.4
Location of Register Information and DTC Vector Table
Locate the register information in the on-chip RAM. Register information should be located at the
address that is multiple of four. Locating the register information in address space is shown in
figure 11.3. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the
start address of the register information. In the case of chain transfer, register information should
be located in consecutive areas as shown in figure 11.3 and the register information start address
should be located at the corresponding vector address to the activation source. Figure 11.4 shows
correspondences between the DTC vector address and register information. The DTC reads the
start address of the register information from the vector address set for each activation source, and
then reads the register information from that start address.
When the DTC is activated by software, the vector address is obtained from: H'0400 +
(DTVECR[6:0] × 2). For example, if VOFR and DTVECR are H'0000 and H'18 respectively, the
vector address is H'0430.
The configuration of the vector address is a 2-byte unit. These two bytes specify the lower bits of
the start address. Variable vector addresses can be used by setting VOFR. For details on VOFR
settings, see section 4, Interrupt Controller.
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Section 11 Data Transfer Controller (DTC)
Lower addresses
0
Start address of
register information
1
2
MRA
SAR
MRB
DAR
3
Register information
CRB
CRA
Chain transfer
MRA
SAR
MRB
DAR
CRB
CRA
Register information
for second transfer
in case of chain
transfer
Four bytes
Figure 11.3 Locating DTC Register Information in Address Space
DTC vector
address
Start address of
register information
Register information
Chain transfer
Figure 11.4 Correspondence between DTC Vector Address and Register Information
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Section 11 Data Transfer Controller (DTC)
Table 11.3 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs
Origin of
Activation
Source
Activation Source
Software
Write to DTVECR
DTVECR H'0400 +

(DTVECR[6:0] × 2)
External pin
IRQ0
22
A/D converter
unit 1
A/D converter
unit 2*2
ELC
Vector
Number
1
Vector Address*
H'42C to H'42D
DTCE*
5
IRQ1
23
H'42E to H'42F
DTCEA6
IRQ2
24
H'430 to H'431
DTCEA5
IRQ3
25
H'432 to H'433
DTCEA4
IRQ4
26
H'434 to H'435
DTCEA3
IRQ5
27
H'436 to H'437
DTCEA2
IRQ6
28
H'438 to H'439
DTCEA1
IRQ7
29
H'43A to H'43B
DTCEA0
IADEND_1
(conversion completion)
30
H'43C to H'43D
DTCEB7
IADCMP_1
31
(compare condition match)
H'43E to H'43F
DTCEB6
IADEND_2
(conversion completion)
32
H'442 to H'443
DTCEB5
IADCMP_2
33
(compare condition match)
H'444 to H'445
DTCEB4
ELC1FP
35
(ELSR12 event occurrence)
H'446 to H'447
DTCEB3
ELC2FP
36
(ELSR30 event occurrence)
H'448 to H'449
DTCEB2
38
H'44C to H'44D
DTCEB1
SCI3_1 TXI
39
H'44E to H'44F
DTCEB0
SCI3 channel 2 SCI3_2 RXI
42
H'454 to H'455
DTCEC7
SCI3_2 TXI
43
H'456 to H'457
DTCEC6
SCI3 channel 3 SCI3_3 RXI
46
H'45C to H'45D
DTCEC5
SCI3_3 TXI
47
H'45E to H'45F
DTCEC4
IIC2/SSU_RXI
60
H'478 to H'479
DTCED7
IIC3/SSU_TXI
61
H'47A to H'47B
DTCED6
Rev. 1.00 Oct. 03, 2008 Page 346 of 962
REJ09B0465-0100
High
DTCEA7
SCI3 channel 1 SCI3_1 RXI
IIC2/SSU
Priority
Low
Section 11 Data Transfer Controller (DTC)
Origin of
Activation
Source
Timer RC*
3
Timer RD
unit 0
channel 0
Timer RD
unit 0
channel 1*4
Vector Vector
1
Number Address*
DTCE*
Priority
ITCMA
Input capture A/ compare
match A
71
H'48E to H'48F
DTCED3
High
ITCMB
Input capture B/ compare
match B
72
H'490 to H'491
DTCED2
ITCMC
Input capture C/ compare
match C
73
H'492 to H'493
DTCED1
ITCMD
Input capture D/ compare
match D
74
H'494 to H'495
DTCED0
ITDMA0_0
Input capture A/ compare
match A
76
H'498 to H'499
DTCEE7
ITDMB0_0
Input capture B/ compare
match B
77
H'49A to H'49B
DTCEE6
ITDMC0_0
Input capture C/ compare
match C
78
H'49C to H'49D
DTCEE5
ITDMD0_0
Input capture D/ compare
match D
79
H'49E to H'49F
DTCEE4
ITDMA0_1
Input capture A/ compare
match A
82
H'4A4 to H'4A5
DTCEE3
ITDMB0_1
Input capture B/ compare
match B
83
H'4A6 to H'4A7
DTCEE2
ITDMC0_1
Input capture C/ compare
match C
84
H'4A8 to H'4A9
DTCEE1
ITDMD0_1
Input capture D/ compare
match D
85
H'4AA to H'4AB
DTCEE0
Activation Source
5
Low
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Section 11 Data Transfer Controller (DTC)
Origin of
Activation
Source
Activation Source
Timer RD
unit 1
channel 2*4
Timer RD
unit 1
channel 3*4
Timer RE
Timer RG
Vector Vector
1
Number Address*
DTCE*
Priority
ITDMA1_2
Input capture A/ compare
match A
87
H'4AE to H'4AF
DTCEF7
High
ITDMB1_2
Input capture B/ compare
match B
88
H'4B0 to H'4B1
DTCEF6
ITDMC1_2
Input capture C/ compare
match C
89
H'4B2 to H'4B3
DTCEF5
ITDMD1_2
Input capture D/ compare
match D
90
H'4B4 to H'4B5
DTCEF4
ITDMA1_3
Input capture A/ compare
match A
93
H'4BA to H'4BB
DTCEF3
ITDMB1_3
Input capture B/ compare
match B
94
H'4BC to H'4BD DTCEF2
ITDMC1_3
Input capture C/ compare
match C
95
H'4BE to H'4BF
DTCEF1
ITDMD1_3
Input capture D/ compare
match D
96
H'4C0 to H'4C1
DTCEF0
ITESC
100
H'4C8 to H'4C9
DTCEG4
ITEMI
101
H'4CA to H'4CB DTCEG3
ITEHR
102
H'4CC to H'4CD DTCEG2
ITEDY
103
H'4CE to H'4CF DTCEG1
ITEWK
104
H'4D0 to H'4D1
ITGMA
Input capture A/ compare
match A
109
H'4DA to H'4DB DTCEH3
ITGMB
Input capture B/ compare
match B
110
H'4DC to H'4DD DTCEH2
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5
DTCEG0
Low
Section 11 Data Transfer Controller (DTC)
Notes: 1.
2.
3.
4.
5.
11.5
Vector address indicates the lower 11 bits of vector address when VOFR = H'0000.
Supported only in the H8S/20223 group and reserved in other products.
Supported only in the H8S/20103 group and reserved in other products.
Not supported in the H8S/20103 group and reserved in the H8S/20103 group.
DTCE bits with no corresponding interrupt are reserved. The write value should always
be 0.
Operation
The DTC stores register information in the on-chip RAM. When activated, the DTC reads register
information in the on-chip RAM and transfers data. After the data transfer, it writes updated
register information back to the on-chip RAM. Pre-storage of register information in the on-chip
RAM makes it possible to transfer data over any required number of channels. There are three
transfer modes: normal mode, repeat mode, and block transfer mode. Setting the CHNE bit to 1
allows a number of transfers with a single activation (chain transfer). Setting the CHNS bit to 1
enables chain transfer only when the transfer counter value is 0.
The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed according to the register information.
Figure 11.5 shows a flowchart of DTC operation, and table 11.4 summarizes the chain transfer
conditions (for performing the first and second transfers).
Rev. 1.00 Oct. 03, 2008 Page 349 of 962
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Section 11 Data Transfer Controller (DTC)
Start
Read DTC vector
Next transfer
Read register information
Data transfer
Write register information
CHNE = 1
Yes
No
CHNS = 0
Yes
Transfer counter = 0
or DISEL = 1
No
No
Yes
Transfer
counter = 0
Yes
No
DISEL = 1
Yes
No
Clear activation source flag
Clear DTCER
End
Interrupt exception
handling
Figure 11.5 Flowchart of DTC Operation
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Section 11 Data Transfer Controller (DTC)
Table 11.4 Chain Transfer Conditions
1st Transfer
2nd Transfer
CHNE CHNS DISEL CR
CHNE CHNS DISEL CR
DTC Transfer
0

0
Except 0 



Ends at 1st transfer
0

0
0




Ends at 1st transfer
0

1





Interrupt request to CPU
1
0


0

0
Except 0 Ends at 2nd transfer
0

0
0
Ends at 2nd transfer
0

1

Interrupt request to CPU
Ends at 1st transfer
1
1
0
Except 0 



1
1

0
0

0
Except 0 Ends at 2nd transfer
0

0
0
Ends at 2nd transfer
0

1

Interrupt request to CPU



Ends at 1st transfer
1
1
1
Except 0 
Interrupt request to CPU
11.5.1
Normal Mode
In normal mode, one operation transfers one byte or one word of data. Table 11.5 lists the register
function in normal mode. From 1 to 65,536 transfers can be specified. Once the specified number
of transfers has ended, a CPU interrupt can be requested.
Table 11.5 Register Function in Normal Mode
Name
Abbreviation
Function
DTC source address register
SAR
Designates transfer source address
DTC destination address register
DAR
Designates transfer destination address
DTC transfer count register A
CRA
Designates transfer count
DTC transfer count register B
CRB
Not used
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Section 11 Data Transfer Controller (DTC)
SAR
DAR
Transfer
Figure 11.6 Memory Mapping in Normal Mode
11.5.2
Repeat Mode
In repeat mode, one operation transfers one byte or one word of data. Table 11.6 lists the register
function in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of
transfers has ended, the initial state of the transfer counter and the address register specified as the
repeat area is restored, and transfer is repeated. In repeat mode, the transfer counter value does not
reach H'00, therefore CPU interrupts cannot be requested when DISEL = 0.
Table 11.6 Register Function in Repeat Mode
Name
Abbreviation
Function
DTC source address register
SAR
Designates transfer source address
DTC destination address register
DAR
Designates transfer destination address
DTC transfer count register AH
CRAH
Holds number of transfers
DTC transfer count register AL
CRAL
Designates transfer count
DTC transfer count register B
CRB
Not used
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Section 11 Data Transfer Controller (DTC)
SAR
or
DAR
DAR
or
SAR
Repeat area
Transfer
Figure 11.7 Memory Mapping in Repeat Mode
11.5.3
Block Transfer Mode
In block transfer mode, one operation transfers one block of data. Either the transfer source or the
transfer destination is designated as a block area. Table 11.7 lists the register function in block
transfer mode. The block size is 1 to 256. When the transfer of one block ends, the initial state of
the block size counter and the address register specified as the block area is restored. The other
address register is then incremented, decremented, or left fixed according to the register
information. From 1 to 65,536 transfers can be specified. Once the specified number of transfers
has ended, a CPU interrupt is requested.
Table 11.7 Register Function in Block Transfer Mode
Name
Abbreviation
Function
DTC source address register
SAR
Designates source address
DTC destination address register
DAR
Designates destination address
DTC transfer count register AH
CRAH
Holds block size
DTC transfer count register AL
CRAL
Designates block size count
DTC transfer count register B
CRB
Designates transfer count
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Section 11 Data Transfer Controller (DTC)
First block
SAR
or
DAR
Block area
Transfer
DAR
or
SAR
Nth block
Figure 11.8 Memory Mapping in Block Transfer Mode
11.5.4
Chain Transfer
Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed
consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB
can be set independently.
Figure 11.9 shows the operation of chain transfer. When activated, the DTC reads the register
information start address stored at the vector address, and then reads the first register information
at that start address. The CHNE bit in MRB is checked after the end of data transfer, if the value is
1, the next register information, which is located consecutively, is read and transfer is performed.
This operation is repeated until the end of data transfer of register information with CHNE = 0.
Setting both the CHNE bit and CHNS bit to 1 enables execution of chain transfer only when the
transfer counter value is 0.
In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the
end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt
source flag for the activation source is not affected.
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Section 11 Data Transfer Controller (DTC)
Source
Destination
Register information
CHNE=1
DTC vector
address
Start address of
register information
Register information
CHNE=0
Source
Destination
Figure 11.9 Operation of Chain Transfer
11.5.5
Interrupt Sources
An interrupt request is issued to the CPU when the DTC ends the specified number of data
transfers, or when the DTC ends a data transfer for which the DISEL bit was set to 1. In the case
of interrupt activation, the interrupt set as the activation source is generated. These interrupts to
the CPU are subject to CPU mask level and interrupt controller priority level control.
In the case of activation by software, a software activated data transfer end interrupt (SWDTEND)
is generated.
When the DISEL bit is 1 and one data transfer has ended or the specified number of transfers has
ended, the SWDTE bit is held at 1 and an SWDTEND interrupt is generated after data transfer
ends. The interrupt handling routine should clear the SWDTE bit to 0.
When the DTC is activated by software, an SWDTEND interrupt is not generated during a data
transfer wait or during data transfer even if the SWDTE bit is set to 1.
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Section 11 Data Transfer Controller (DTC)
11.5.6
Operation Timing
φ
DTC activation
request
DTC
request
Data transfer
Vector read
Address
Read Write
Transfer
information read
Transfer
information write
Figure 11.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode)
φ
DTC activation
request
DTC
request
Data transfer
Vector read
Read Write Read Write
Address
Transfer
information read
Transfer
information write
Figure 11.11 DTC Operation Timing (Example of Block Transfer Mode,
with Block Size of 2)
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Section 11 Data Transfer Controller (DTC)
φ
DTC activation
request
DTC
request
Data transfer
Data transfer
Read Write
Read Write
Vector read
Address
Transfer
information read
Transfer
information
write
Transfer
information
read
Transfer
information write
Figure 11.12 DTC Operation Timing (Example of Chain Transfer)
11.5.7
Number of DTC Execution States
Table 11.8 lists execution state for a single DTC data transfer, and table 11.9 shows the number of
states required for each execution status.
Table 11.8 DTC Execution State
Mode
Vector Read
I
Register
Information
Read/Write
J
Data Read
K
Data Write
L
Internal
Operations
M
Normal
1
6
1
1
3
Repeat
1
6
1
1
3
Block transfer
1
6
N
N
3
Legend:
N:
Block size (initial setting value of CRAH and CRAL)
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Section 11 Data Transfer Controller (DTC)
Table 11.9 Number of States Required for Each Execution Status
Object to be Accessed
OnChip
RAM
OnChip
ROM Internal I/O Register
Bus width
32
16
Access states
1
1
2
3
4
2
3
4
Execution
state
Vector read SI
1
1
2
3
4
2
3
4
Register information
read/write SJ
1







Byte data read SK
1
1
2
3
4
2
3
4
Word data read SK
1
1
4
6
8
2
3
4
Byte data write SL
1
1
2
3
4
2
3
4
Word data write SL
1
1
4
6
8
2
3
4
Internal operation SM
8
16
1
The number of execution states is calculated from the formula below. Note that Σ means the sum
of all transfers activated by one activation source (the number in which the CHNE bit is set to 1 +
1).
Number of execution states = I · SI + Σ (J · SJ + K · SK + L · SL) + M · SM
For example, when the DTC vector address table is located in on-chip ROM and data is
transferred from the on-chip ROM to an internal I/O register (two-state access) in normal mode,
the time required for the DTC operation is 13 states. The time from activation to the end of the
data write is 10 states.
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Section 11 Data Transfer Controller (DTC)
11.6
Procedures for Using DTC
11.6.1
Activation by Interrupt
The procedure for using the DTC with interrupt activation is as follows:
1.
2.
3.
4.
Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.
Set the start address of the register information in the DTC vector address.
Set the corresponding bit in DTCER to 1.
Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC
is activated when an interrupt used as an activation source is generated.
5. After the end of one data transfer, or after the specified number of data transfers have ended,
the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue
transferring data, set the DTCE bit to 1.
11.6.2
Activation by Software
The procedure for using the DTC with software activation is as follows:
1.
2.
3.
4.
5.
6.
Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.
Set the start address of the register information in the DTC vector address.
Check that the SWDTE bit is 0.
Write 1 to the SWDTE bit and the vector number to DTVECR.
Check the vector number written to DTVECR.
After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested,
the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit
to 1. When the DISEL bit is 1, or after the specified number of data transfers has ended, the
SWDTE bit is held at 1 and a CPU interrupt is requested. Clear the SWDTE bit to 0 by an
interrupt processing routine.
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Section 11 Data Transfer Controller (DTC)
11.7
Examples of Use of the DTC
11.7.1
Normal Mode
An example is shown in which the DTC is used to receive 128 bytes of data via the SCI3.
1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 =
1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have
any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the
RDR address in SCI3 of SAR, the start address of the RAM area where the data is stored in
DAR, and 128 (H'0080) in CRA. CRB can be set to any value.
2. Set the start address of the register information at the DTC vector address.
3. Set the corresponding bit in DTCER to 1.
4. Set the SCI3 to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the
reception complete (RXI) interrupt. Since the generation of a receive error during the SCI
reception operation will disable subsequent reception, the CPU should be enabled to accept
receive error interrupts.
5. Each time reception of one byte of data ends on the SCI3, the RDRF flag in SSR is set to 1, an
RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR
to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is
automatically cleared to 0.
6. When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the
DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt
handling routine should perform termination processing.
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Section 11 Data Transfer Controller (DTC)
11.7.2
Chain Transfer when Transfer Counter = 0
By executing the second data transfer, and performing re-setting of the first data transfer, only
when the counter value is 0, 256 or more repeat transfers can be performed.
An example is shown in which a 128-kbyte input buffer is configured. The input buffer is assumed
to have been set to start at lower address H'0000. Figure 11.13 shows overview of the chain
transfer when the counter value is 0.
1. For the first transfer, set the normal mode for input data. Set fixed transfer source address
(G/A, etc.), CRA = H'0000 (65,536 times), and CHNE = 1, CHNS = 1, and DISEL = 0.
2. Prepare the upper 8-bit addresses of the start addresses for each of the 65,536 transfer start
addresses for the first data transfer in a separate area (in ROM, etc.). For example, if the input
buffer comprises H'200000 to H'21FFFF, prepare H'21 and H'20.
3. For the second transfer, set repeat mode (with the source side as the repeat area) for re-setting
the transfer destination address for the first data transfer. Use the upper 8 bits of DAR in the
first register information area as the transfer destination. Set CHNE = DISEL = 0. If the above
input buffer is specified as H'200000 to H'21FFFF, set the transfer counter to 2.
4. Execute the first data transfer 65,536 times by means of interrupts. When the transfer counter
for the first data transfer reaches 0, the second data transfer is started. Set the upper 8 bits of
the transfer source address for the first data transfer to H'21. The lower 16 bits of the transfer
destination address of the first data transfer and the transfer counter are H'0000.
5. Next, execute the first data transfer the 65,536 times specified for the first data transfer by
interrupts. When the transfer counter for the first data transfer reaches 0, the second data
transfer is started. Set the upper 8 bits of the transfer source address for the first data transfer to
H'20. The lower 16 bits of the transfer destination address of the first data transfer is H'0000.
6. Steps 4 and 5 are repeated endlessly. As repeat mode is specified for the second data transfer,
an interrupt request is not sent to the CPU.
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Section 11 Data Transfer Controller (DTC)
Input circuit
Input buffer
First data
transfer register
information
Chain transfer
(counter = 0)
Second data
transfer register
information
Upper 8 bits
of DAR
Figure 11.13 Chain Transfer when Counter = 0
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Section 11 Data Transfer Controller (DTC)
11.7.3
Software Activation
An example is shown in which the DTC is used to transfer a block of 128 bytes of data by
software activation. The transfer source address is H'1000 and the destination address is H'2000.
The vector number is H'60, so the vector address is H'04C0.
1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination
address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz =
0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE =
0). Set the transfer source address (H'1000) in SAR, the transfer destination address (H'2000)
in DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB.
2. Set the start address of the register information at the DTC vector address (H'04C0).
3. Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated
by software.
4. Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0.
5. Read DTVECR again and check that H'60 is set to the vector number. If it is not, this indicates
that the write has failed. This is because an interrupt occurred between steps 3 and 4 and led to
a different software activation. To activate this transfer, go back to step 3.
6. If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred.
7. After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear
the SWDTE bit to 0 and perform other wrap-up processing.
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Section 11 Data Transfer Controller (DTC)
11.8
Usage Notes
11.8.1
Module Standby Mode Setting
DTC operation can be disabled or enabled using the module standby control register. The initial
value is for DTC operation to be disabled. When the DTC is used, cancel module standby mode.
Register access is disabled in module standby mode. Module standby mode cannot be set while
the DTC is activated. For details, see section 6, Power-Down Modes.
11.8.2
DTCE Bit Setting
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts
are disabled, multiple activation sources can be set at one time (only at the initial setting) by
writing data after executing a dummy read on the relevant register.
11.8.3
DTC Activation by SCI3, IIC2/SSU and A/D Converter Interrupt Sources
Interrupts and activation sources of the SCI3, IIC2/SSU, and A/D converter are cleared when the
DTC reads or writes the prescribed register. Therefore, when the DTC is activated by an interrupt
or activation source, the interrupt or activation source will be retained if a read/write of the
relevant register is not included in the last chained data transfer.
The above operation is performed regardless of the DISEL bit setting.
Rev. 1.00 Oct. 03, 2008 Page 364 of 962
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Section 12 Event Link Controller
Section 12 Event Link Controller
The event link controller (ELC) connects the events generated by the various peripheral modules
to different modules. This function allows direct cooperation between the modules without CPU
intervention. A block diagram of the ELC is shown in figure 12.1.
12.1
Overview
• Fifty-nine event signals can be directly connected to modules.
• The operation of timer modules can be selected when an event is input to the timer module.
• Events can be connected to ports 3 and 6.
Single port-pin: An event link can be set for a single specific pin of a port.
Port group: An event link can be set for a specific group of bits within an 8-bit port.
In addition, in the specified single pin or group within a port, an event is generated by a change
in the value of the linked signals.
• Four channels of events can be generated in arbitrary setting interval using the eventgeneration timer.
Rev. 1.00 Oct. 03, 2008 Page 365 of 962
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Section 12 Event Link Controller
ELCR
Event control
Peripheral modules
Timer event
input control
Peripheral timer
modules
ELSR0 to ELSR31
ELOPA
ELOPB
ELOPC
PGR1, PGR2
PGC1, PGC2
Port event
input/output control
Port 3 or port 6
PDBF1, PDBF2
PEL0 to PEL3
ELTMCR
Event-generation
timer
Event signal 1
ELTMSA
Event signal 2
ELTMSB
Event signal 3
Event signal 4
ELTMDR
ELTMCNT
Figure 12.1 Block Diagram of Event Link Controller
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Section 12 Event Link Controller
12.2
Register Descriptions
The ELC has the following registers.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Event link control register (ELCR)
Event link setting registers 0 to 32 (ELSR0 to ELSR32)
Event link option setting register A (ELOPA)
Event link option setting register B (ELOPB)
Event link option setting register C (ELOPC)
Port-group setting registers 1 and 2 (PGR1, PGR2)
Port-group control registers 1 and 2 (PGC1, PGC2)
Port buffer registers 1 and 2 (PDBF1 and PDBF2)
Event link port setting registers 0 to 3 (PEL0 to PEL3)
Event-generation timer control register (ELTMCR)
Event-generation timer interval setting register A (ELTMSA)
Event-generation timer interval setting register B (ELTMSB)
Event-generation timer delay selection register (ELTMDR)
ELC timer counter (ELTMCNT)
12.2.1
Event Link Control Register (ELCR)
Address: H'FF06BC
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
ELCON







0
1
1
1
1
1
1
1
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
ELCON
All event link
enable
0: Linkage of all the events are disabled.
R/W
Reserved
These bits are read as 1. The write value should be
1.
6 to 0 
1: Linkage of all the events are enabled.

ELCR controls the operation of the event link controller (ELC) collectively.
Rev. 1.00 Oct. 03, 2008 Page 367 of 962
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Section 12 Event Link Controller
12.2.2
Event Link Setting Registers 0 to 32 (ELSR0 to ELSR32)
Address:
H'FF0680 to H'FF0684, H'FF0688, H'FF068A to H'FF068C, H'FF068E, H'FF068F, H'FF0692, H'FF0693,
H'FF0695 to H'FF0698, H'FF069D to H'FF06A0
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
ELSn7
ELSn6
ELSn5
ELSn4
ELSn3
ELSn2
ELSn1
ELSn0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
ELSn7
Event link
select n7
00000000: Linkage of the event is disabled.
R/W
0000001 to 01100001: Set the number specific to the
event signal to be linked.
R/W
6
ELSn6
Event link
select n6
5
ELSn5
Event link
select n5
R/W
4
ELSn4
Event link
select n4
R/W
3
ELSn3
Event link
select n3
R/W
2
ELSn2
Event link
select n2
R/W
1
ELSn1
Event link
select n1
R/W
0
ELSn0
Event link
select n0
R/W
Other than the above: Setting prohibited.
[Legend]
n:
0 to 32 (except 5 to 7, 9, 13, 16, 17, 20, and 25 to 28)
Each of ELSR0 to ELSR32 specifies an event signal to be linked for the peripheral module. Table
12.1 shows the correspondence between ELSR0 to ELSR31 and the peripheral modules. Table
12.2 shows the correspondence between the event signal names and the numbers specific to the
signals.
Rev. 1.00 Oct. 03, 2008 Page 368 of 962
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Section 12 Event Link Controller
Table 12.1 Correspondence between ELSR and Peripheral Modules
Register Name
Peripheral Module (Functions)
ELSR0
Timer RA
ELSR1
Timer RB
1
ELSR2*
Timer RC
ELSR3
Timer RD_0 channel 0
ELSR4
Timer RD_0 channel 1
ELSR8
Timer RG
ELSR10
AD converter unit 1
2
ELSR11*
AD converter unit 2
ELSR12
Interrupts 1
ELSR14
Output port-group 2
ELSR15
Output port-group 3
ELSR18
Input port-group 2
ELSR19
Input port-group 3
ELSR21
Single-port 1
ELSR22
Single-port 2
ELSR23
Single-port 3
ELSR24
Single-port 4
ELSR29
Clock oscillator
ELSR30
Interrupts 2
ELSR31
DA converter channel 0
ELSR32
DA converter channel 1
Note:
1. Supported only in the H8S/20103 group.
2. Supported only in the H8S/20223 group.
Rev. 1.00 Oct. 03, 2008 Page 369 of 962
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Section 12 Event Link Controller
Table 12.2 Correspondence between Event Signal Names and ELSn Bit Values
ELSn7 to ELSn0 Bit Value
(Signal Number)
Name of Event Signal to Set ELSR
00000001 (H'01)
Timer RA underflow
00000010 (H'02)
Timer RB underflow
00000011 (H'03)*
1
Timer RC overflow
00000100 (H'04)*
1
Timer RC compare-match A
00000101 (H'05)*
1
Timer RC compare-match B
00000110 (H'06)*
1
Timer RC compare-match C
00000111 (H'07)*
1
Timer RC compare-match D
00001000 (H'08)
Timer RD_0 channel 0 overflow
00001001 (H'09)
Timer RD_0 channel 0 compare-match A
00001010 (H'0A)
Timer RD_0 channel 0 compare-match B
00001011 (H'0B)
Timer RD_0 channel 0 compare-match C
00001100 (H'0C)
Timer RD_0 channel 0 compare-match D
00001101 (H'0D)
Timer RD_0 channel 1 overflow
00001110 (H'0E)
Timer RD_0 channel 1 underflow
00001111 (H'0F)
Timer RD_0 channel 1 compare-match A
00010000 (H'10)
Timer RD_0 channel 1 compare-match B
00010001 (H'11)
Timer RD_0 channel 1 compare-match C
00010010 (H'12)
Timer RD_0 channel 1 compare-match D
00100001 (H'21)
Timer RG overflow
00100010 (H'22)
Timer RG underflow
00100011 (H'23)
Timer RG compare-match A
00100100 (H'24)
Timer RG compare-match B
00101001 (H'29)
AD conversion end in AD converter unit 1
00101010 (H'2A)*2
AD conversion end in AD converter unit 2
00101100 (H'2C)
Input edge detection on input port-group 1
00101101 (H'2D)
Input edge detection on input port-group 2
00101111 (H'2F)
Input edge detection on single input port 1
00110000 (H'30)
Input edge detection on single input port 2
00110001 (H'31)
Input edge detection on single input port 3
00110010 (H'32)
Input edge detection on single input port 4
00110111 (H'37)
Voltage-drop detection in LVD
Rev. 1.00 Oct. 03, 2008 Page 370 of 962
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Section 12 Event Link Controller
ELSn7 to ELSn0 Bit Value
(Signal Number)
Name of Event Signal to Set ELSR
00111000 (H'38)
Voltage-drop reset detection in LVD
00111001 (H'39)
CPG backup start
00111010 (H'3A)
WDT increment
00111011 (H'3B)
WDT reset
00111100 (H'3C)
Timer RE interval (week, day, hour, minute, or second)
00111101 (H'3D)
DTC transfer end
00111110 (H'3E)
Transmit-buffer empty in IIC2/SSU
00111111 (H'3F)
Transmit end in IIC2/SSU
01000000 (H'40)
Receive-buffer full in IIC2/SSU
01000001 (H'41)
Stop-condition detection in IIC2/SSU
01000010 (H'42)
Arbitration loss/overrun error in IIC2/SSU
01000011 (H'43)
NACK detection/conflict error in IIC2/SSU
01001010 (H'4A)
SCI3_1 transmit-buffer empty
01001011 (H'4B)
SCI3_1 transmit end
01001100 (H'4C)
SCI3_1 receive-buffer full
01001101 (H'4D)
SCI3_1 transfer error
01001110 (H'4E)
SCI3_2 transmit-buffer empty
01001111 (H'4F)
SCI3_2 transmit end
01010000 (H'50)
SCI3_2 receive-buffer full
01010001 (H'51)
SCI3_2 transfer error
01010010 (H'52)
SCI3_3 transmit-buffer empty
01010011 (H'53)
SCI3_3 transmit end
01010100 (H'54)
SCI3_3 receive-buffer full
01010101 (H'55)
SCI3_3 transfer error
01011110 (H'5E)
Timer ELC event 0
01011111 (H'5F)
Timer ELC event 1
01100000 (H'60)
Timer ELC event 2
01100001 (H'61)
Timer ELC event 3
Other than the above: Setting prohibited
Note:
1. Selected for the H8S/20103 group.
2. Selected for the H8S/20223 group.
Rev. 1.00 Oct. 03, 2008 Page 371 of 962
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Section 12 Event Link Controller
12.2.3
Event Link Option Setting Register A (ELOPA)
Address: H'FF06B5
Bit:
b7
b6
b5
TMRAM[2:1]
Value after reset:
1
b4
b3
TMRBM[2:1]
1
1
1
b2
b1
TMRCM[2:1]
1
b0
TMRD1M[2:1]
1
1
1
Bit
Symbol
Bit Name
Description
R/W
7
TMRAM
[2:1]
Timer RA
operation
select
00: Timer starts counting.
R/W
6
01: Timer counts events.
10: Setting prohibited.
11: Events disabled.
5
4
TMRBM
[2:1]
Timer RB
operation
select
00: Timer starts counting.
R/W
01: Timer counts events.
10: Setting prohibited.
11: Events disabled.
3
2
TMRCM
[2:1]*1
Timer RC
operation
select
00: Timer starts counting.
R/W
01: Timer counts events.
2
10: Timer performs input-capture operation.*
11: Events disabled.
1
0
TMRD1M
[2:1]
Timer RD_0
channel 0
operation
select
00: Timer starts counting.
R/W
01: Timer counts events.
3
10: Timer performs input-capture operation.*
11: Events disabled.
Note:
1. Selected only for the H8S/20103 group and reserved in other products. When writing,
b'11 should be written.
2. The TRCCNT value is captured by GRD.
3. The TRDCNT_0 value is captured by GRD_0.
ELOPA determines the operation of timer RA, timer RB, timer RC, and timer RD_0 when an
event is input to the timer.
Rev. 1.00 Oct. 03, 2008 Page 372 of 962
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Section 12 Event Link Controller
12.2.4
Event Link Option Setting Register B (ELOPB)
Address: H'FF06B6
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
TMRD2M[2:1]






1
1
1
1
1
1
1
1
Bit
Symbol
Bit Name
7, 6
TMRD2M Timer RD_0
[2:1]
channel 1
operation select
Description
R/W
00: Timer starts counting.
R/W
01: Timer counts events.
10: Timer performs input-capture operation.*
11: Events disabled.
5 to 0 
Note:
Reserved
These bits are read as 1. The write value should be 1. 
The TRDCNT_1 value is captured by GRD_1.
*
ELOPB determines the operation of timer RD_0 when an event is input to the timer.
12.2.5
Event Link Option Setting Register C (ELOPC)
Address: H'FF06B7
Bit:
b7
b6
TMRGM[2:1]
Value after reset:
1
1
b5
b4
b3
b2
b1
b0






1
1
1
1
1
1
Bit
Symbol
Bit Name
Description
R/W
7, 6
TMRGM
[2:1]
Timer RG
00: Timer starts counting.
operation select 01: Timer counts events.
R/W
10: Timer performs input-capture operation.*
11: Events disabled.
5 to 0 
Note:
*
Reserved
These bits are read as 1. The write value should be 1.

The TRGCNT value is captured by GRB.
ELOPC determines the operation of timer RG when an event is input to the timer.
Rev. 1.00 Oct. 03, 2008 Page 373 of 962
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Section 12 Event Link Controller
12.2.6
Port-Group Setting Registers 1 and 2 (PGR1 and PGR2)
Address:
H'FF06A2, H'FF06A3
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PGRn7
PGRn6
PGRn5
PGRn4
PGRn3
PGRn2
PGRn1
PGRn0
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PGRn7
Port-group
setting n7
0: The port bit is not specified as the member of the
same group.
R/W
6
PGRn6
Port-group
setting n6
1: The port bit is specified as the member of the
same group.
R/W
5
PGRn5
Port-group
setting n5
R/W
4
PGRn4
Port-group
setting n4
R/W
3
PGRn3
Port-group
setting n3
R/W
2
PGRn2
Port-group
setting n2
R/W
1
PGRn1
Port-group
setting n1
R/W
0
PGRn0
Port-group
setting n0
R/W
[Legend]
n:
1 or 2
PGR specifies each port bit in the same 8-bit I/O port as the member of a group. One to eight port
bits can be specified as the members of the same group as required. The correspondence between
PGR and ports is shown in table 12.3.
Rev. 1.00 Oct. 03, 2008 Page 374 of 962
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Section 12 Event Link Controller
12.2.7
Port-Group Control Registers 1 and 2 (PGC1 and PGC2)
Address:
H'FF06A6, H'FF06A7
Bit:
b7
b6

Value after reset:
1
b5
b4
PGCOn[2:0]
0
0
0
b3
b2

PGCOVEn
1
0
b0
b1
PGCIn[1:0]
0
0
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is read as 1. The write value should be 1.

000: 0 is output when the event is input.
R/W
6 to 4 PGCOn[2:0] Port group
operation
select
001: 1 is output when the event is input.
010: The toggled (inverted) value is output when the
event is input.
011: The buffer value is output when the event is
input.
1XX: The bit value is sifted out in the group (from
MSB to LSB) when the event is input.
3

Reserved
This bit is read as 1. The write value should be 1.

2
PGCOVEn
PDBF
overwrite
0: Overwriting PDBF is disabled.
R/W
Event output
edge select
00: Event is generated upon detection of the rising
edge of the external input signal.
1, 0
PGCIn[1:0]
1: Overwriting PDBF is enabled.
R/W
01: Event is generated upon detection of the falling
edge of the external input signal.
1X: Event is generated upon detection of both the
rising and falling edge of the external input
signal.
[Legend]
n:
1 or 2
X:
Don't care.
For the output port-group, PGC specifies the form of outputting the signal externally via the port
when the event signal is input. For the input port-group, PGC enables/disables overwriting of
PDBF and specifies the conditions of event generation (edge of the externally input signal).
The correspondence between PGR and ports is shown in table 12.3.
Rev. 1.00 Oct. 03, 2008 Page 375 of 962
REJ09B0465-0100
Section 12 Event Link Controller
12.2.8
Port Buffer Registers 1 and 2 (PDBF1 and PDBF2)
Address:
H'FF06AA, H'FF06AB
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
PDBFn7
PDBFn6
PDBFn5
PDBFn4
PDBFn3
PDBFn2
PDBFn1
PDBFn0
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
PDBFn7
6
PDBFn6
5
PDBFn5
4
PDBFn4
Port buffer n7 Data is transferred between PDR and PDBF when
Port buffer n6 an event is input. Write access to the bit specified as
a member of the input port-group by the CPU is
Port buffer n5 invalid. For details, see section 12.3, Operation.
Port buffer n4
3
PDBFn3
Port buffer n3
R/W
2
PDBFn2
Port buffer n2
R/W
1
PDBFn1
Port buffer n1
R/W
0
PDBFn0
Port buffer n0
R/W
R/W
R/W
R/W
R/W
[Legend]
n:
1, 2
PDBF is an 8-bit readable/writable register used in combination with PGR. For PDBF operations,
see section 12.3, Operation. The correspondence of PPBF and PDR is shown in table 12.3.
Table 12.3 Registers Related to Port-Groups and Corresponding Port Numbers
Port Group Setting
Register (PGR)
Port Group Control
Register (PGC)
Port Buffer Register
(PDBF)
Port Number
PGR1
PGC1
PDBF1
Port 3
PGR2
PGC2
PDBF2
Port 6
Rev. 1.00 Oct. 03, 2008 Page 376 of 962
REJ09B0465-0100
Section 12 Event Link Controller
12.2.9
Event Link Port Setting Registers 0 to 3 (PEL0 to PEL3)
Address: H'FF06AD to H'FF06B0
Bit:
b7
b6

Value after reset:
1
b5
b4
PSMn[1:0]
0
b3
b2
PSPn[4:3]
0
0
b1
b0
PSPn[2:0]
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is read as 1. The write value should be 1.

6
PSMn[1:0]
Event link
specification
•
R/W
5
For the output port, data to be output from the
port is specified.
00: 0 is output when the event is input.
01: 1 is output when the event is input.
1X: The toggled (inverted) value is output when
the event is input.
•
For the input port, the edge on which the event is
to be output is specified.
00: Event is output upon detection of the rising
edge.
01: Event is output upon detection of the falling
edge.
1X: Event is output upon detection of both the
rising and falling edge.
4
PSPn[4:3]
3
Port number
specification
00: Do not set this value.
R/W
01: Port 3 (corresponding to PGR1)
10: Port 6 (corresponding to PGR2)
11: Do not set this value.
2
PSPn2
1
PSPn1
0
PSPn0
Bit number
specification
A bit number in an 8-bit port is specified.
R/W
R/W
R/W
[Legend]
n:
0 to 3
X:
Don't care.
PEL specifies the 1-bit port (hereinafter referred to as a single-port) to which an event is to be
linked, the port operation upon the event signal input, and the conditions of event generation. With
this LSI, a total of four bits in either port 3 or port 6 (8-bit ports) can be specified as single-ports.
Rev. 1.00 Oct. 03, 2008 Page 377 of 962
REJ09B0465-0100
Section 12 Event Link Controller
12.2.10 Event-Generation Timer Control Register (ELTMCR)
Address: H'FF06B8
Bit:
b7
b6
b5
b4
TMRSTR



0
1
1
1
Value after reset:
b3
b2
0
0
b1
b0
CLSRS[3:0]
0
0
Bit
Symbol
Bit Name
Description
R/W
7
TMRSTR
Timer count start
0: Counter is stopped.
R/W
1: Counter is incremented.
6 to 4 
Reserved
These bits are read as 1. The write value should 
be 1.
3 to 0 CLSRS[3:0] Clock source (φELC) 0000: φ
select
0001: φ/2
0010: φ/4
0011: φ/8
0100: φ/16
0101: φ/32
0110: φ/64
0111: φ/128
1000: φ/256
1001: φ/512
1010: φ/1024
1011: φ/2048
1100: φ/4096
1101: φ/8192
1110: Reserved (Counter is stopped.)
1111: Reserved (Counter is stopped.)
Note: Be sure to stop the counter before changing the clock source.
ELTMCR controls the ELTMCNT operation and selects the clock source.
Rev. 1.00 Oct. 03, 2008 Page 378 of 962
REJ09B0465-0100
R/W
Section 12 Event Link Controller
12.2.11 Event-Generation Timer Interval Setting Register A (ELTMSA)
Address: H'FF06B9
Bit:
b7
b6
b5
b4
b3
C1CLS[3:0]
Value after reset:
Bit
Symbol
1
0
Bit Name
0
b2
b1
b0
0
0
C0CLS[3:0]
0
1
0
Description
R/W
7 to 4 C1CLS[3:0] Channel 1
0000: Clock source φELC/1
event0001: Clock source φELC/2
generation
interval select 0010: Clock source φELC/4
0011: Clock source φELC/8
R/W
0100: Clock source φELC/16
0101: Clock source φELC/32
0110: Clock source φELC/64
0111: Clock source φELC/128
1000: Clock source φELC/256 (initial value)
1001: Clock source φELC/512
1010: Clock source φELC/1024
1011: Clock source φELC/2048
1100: Clock source φELC/4096
1101: Clock source φELC/8192
1110: Clock source φELC/16384
1111: Clock source φELC/32768
Rev. 1.00 Oct. 03, 2008 Page 379 of 962
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Section 12 Event Link Controller
Bit
Symbol
Bit Name
3 to 0 C0CLS[3:0] Channel 0
eventgeneration
interval select
Description
R/W
0000: Clock source φELC/1
R/W
0001: Clock source φELC/2
0010: Clock source φELC/4
0011: Clock source φELC/8
0100: Clock source φELC/16
0101: Clock source φELC/32
0110: Clock source φELC/64
0111: Clock source φELC/128
1000: Clock source φELC/256 (initial value)
1001: Clock source φELC/512
1010: Clock source φELC/1024
1011: Clock source φELC/2048
1100: Clock source φELC/4096
1101: Clock source φELC/8192
1110: Clock source φELC/16384
1111: Clock source φELC/32768
Note: Do not set B'0000 when the clock source is set to φs.
ELTMSA determines the event-generation interval for channels 0 and 1, and sets the division ratio
for the clock source specified by ELTMCR.
Rev. 1.00 Oct. 03, 2008 Page 380 of 962
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Section 12 Event Link Controller
12.2.12 Event-Generation Timer Interval Setting Register B (ELTMSB)
Address: H'FF06BA
Bit:
b7
b6
b5
b4
b3
C3CLS[3:0]
Value after reset:
Bit
Symbol
1
0
Bit Name
7 to 4 C3CLS[3:0] Channel 3
eventgeneration
interval select
0
b2
b1
b0
0
0
C2CLS[3:0]
0
1
0
Description
R/W
0000: Clock source φELC/1
R/W
0001: Clock source φELC/2
0010: Clock source φELC/4
0011: Clock source φELC/8
0100: Clock source φELC/16
0101: Clock source φELC/32
0110: Clock source φELC/64
0111: Clock source φELC/128
1000: Clock source φELC/256 (initial value)
1001: Clock source φELC/512
1010: Clock source φELC/1024
1011: Clock source φELC/2048
1100: Clock source φELC/4096
1101: Clock source φELC/8192
1110: Clock source φELC/16384
1111: Clock source φELC/32768
Rev. 1.00 Oct. 03, 2008 Page 381 of 962
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Section 12 Event Link Controller
Bit
Symbol
Bit Name
3 to 0 C2CLS[3:0] Channel 2
eventgeneration
interval select
Description
R/W
0000: Clock source φELC/1
R/W
0001: Clock source φELC/2
0010: Clock source φELC/4
0011: Clock source φELC/8
0100: Clock source φELC/16
0101: Clock source φELC/32
0110: Clock source φELC/64
0111: Clock source φELC/128
1000: Clock source φELC/256 (initial value)
1001: Clock source φELC/512
1010: Clock source φELC/1024
1011: Clock source φELC/2048
1100: Clock source φELC/4096
1101: Clock source φELC/8192
1110: Clock source φELC/16384
1111: Clock source φELC/32768
Note: Do not set B'0000 when the clock source is set to φs.
ELTMSB determines the event-generation interval for channels 2 and 3, and sets the division ratio
for the clock source specified by ELTMCR.
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Section 12 Event Link Controller
12.2.13 Event-Generation Timer Delay Selection Register (ELTMDR)
Address: H'FF06BB
Bit:
b7
b6
b5
C3DLY[1:0]
Value after reset:
0
b4
b3
C2DLY[1:0]
0
Bit
Symbol
Bit Name
7, 6
C3DLY[1:0] Channel 3
delay select
0
b2
b1
C1DLY[1:0]
0
0
b0
C0DLY[1:0]
0
0
0
Description
R/W
00: No delay
R/W
01: 1 clock cycle
10: 2 clock cycles
11: 3 clock cycles
5, 4
C2DLY[1:0] Channel 2
delay select
00: No delay
R/W
01: 1 clock cycle
10: 2 clock cycles
11: 3 clock cycles
3, 2
C1DLY[1:0] Channel 1
delay select
00: No delay
R/W
01: 1 clock cycle
10: 2 clock cycles
11: 3 clock cycles
1, 0
C0DLY[1:0] Channel 0
delay select
00: No delay
R/W
01: 1 clock cycle
10: 2 clock cycles
11: 3 clock cycles
Note: There is no delay when the event-generation interval is set to clock source φ/1.
ELTMDR determines the necessary delay time, which is the time from the specified eventgeneration timing (= interval) to the actual generation timing of the event in terms of the cycles of
the selected clock source.
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Section 12 Event Link Controller
12.2.14 ELC Timer Counter (ELTMCNT)
Address: H'FF06C0
Bit:
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ELTMCNT is a 16-bit readable/writable up-counter. To select the input clock signal to be supplied
to the counter, use the CLSRS[3:0] bits in ELTMCR. ELTMCNT cannot be accessed in 8-bit
units; it must always be accessed in 16-bit units. The initial value of ELTMCNT is H'0000.
To set the event-generation interval to the time from starting of the timer to generation of the first
event, set the counter to 0.
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Section 12 Event Link Controller
12.3
Operation
12.3.1
Relation between Interrupt Processing and Event Linking
The modules incorporated in this LSI are provided with the interrupt request status flags and the
bits to enable/disable these interrupt requests. When an interrupt request is generated in a module,
the corresponding interrupt request status flag is set. If the corresponding interrupt request is
enabled then, the interrupt requested is issued to the CPU.
In contrast, the ELC uses interrupt requests (hereinafter referred to as events) generated in
modules as event signals that directly activate other modules. This means that the event signal can
be used whether or not the interrupt signal is enabled. Figure 12.2 shows the relation between the
interrupt processing and ELC.
Module
External pin
Interrupt request
(event)
Port
ELC
Module 1
Module n
Interrupt control
circuit
Status flag
CPU
Interrupt enable control
Figure 12.2 Relation between Interrupt Processing and ELC
12.3.2
Event Linkage
When an event has been set as a trigger in the event-link setting registers (ELSR0 to ELSR32) and
then occurs, that event is linked with the corresponding module (activate the module). Only one
type of event can be connected with one module. When a module is to be activated by the eventlink controller, the operation of the module must be set up in advance. Table 12.4 lists the
operations of modules when an event is input.
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Section 12 Event Link Controller
Table 12.4 Operations of Modules when Event is Input
Module
Operations when Event is Input
Timer RA
Timer RB
Each timer operates differently depending on the setting of the relevant
event link option setting register as below.
Timer RC
•
Starts counting when an event signal is input.
Timer RD
•
Counts the input events.
Timer RG
•
Performs input-capture operation when an event is input. (except timer
RA and timer RB)
A/D converter
Starts A/D conversion when an event signal is input.
D/A converter
Starts D/A conversion when an event signal is input.
Output ports
The value of PDR (port
data register) changes
when an event signal is
input. (The value of the
signal to be output from
the relevant external pin
changes.)
Input ports
Port-groups
The port-group operates
differently depending on the
settings as below.
•
Changes the PDR value
to the specified value.
•
Transfers the PDBF
values to the PDR.
•
Shifts out the bit value.
Single-ports
Changes the PDR value to
the specified value.
When the signal value of
the input pin changes.
Port-groups
Generates an event.
When an event is input
Port-groups
Transfers the signal value
of the external pin to PDBF.
Single-ports
Event connection is
impossible.
Single-ports
Clock oscillator
Switches the clock source to the low-speed on-chip oscillator operation.
Interrupt controller
Issues an interrupt request to the CPU, and the DTC starts to transfer data.
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Section 12 Event Link Controller
12.3.3
Operation of Peripheral Timer Modules When Event is Input
Three different operations are performed depending on the ELOP settings when an event is input.
• Counting-Start Operation
When an event is input, the timer starts counting, which sets the count start bit* in each timer
control register to 1. An event that is input while the count start bit is 1 is invalid.
• Event-Counter Operation
Event-input is selected as the timer clock source and the timer counts events.
• Input-Capture Operation
When an event is input, the timer performs input-capture operation.
Note: * See the descriptions on the bit in the relevant timer section.
12.3.4
Operation of A/D and D/A Converters When Event is Input
The A/D and D/A converter start A/D and D/A conversion, respectively, which sets the start bits*
in the A/D control register and the output enable bits* in the D/A control register to 1.
Note: * See the descriptions on the bit in the A/D and D/A converter sections.
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Section 12 Event Link Controller
12.3.5
Port Operation upon Event Input and Event Generation
The port operation to be performed upon event input to the port can be set and the operation
causing the port to generate an event can be set.
(1)
Single-Ports and Port-Groups
There are two event link modes: event link to single-ports and event link to port-groups. In the
former mode, events can be connected to single-ports in an 8-bit port. In the latter mode, events
can be connected to port-groups consisting of any two or more bits in the same 8-bit port.
A single-port can be set by specifying any one bit in the port* to which an event can be connected
using the PEL register. A port-group can be set by specifying any two or more bits in the port* to
which an event can be connected using the PGR register. One input port-group and one output
port-group can be set in the same port.
If the port bit is specified as both a single-port and a member of a port-group, both functions are
effective when the relevant port is input, whereas only the group-port function is effective when
the relevant port is output.
The input or output direction of ports can be selected using the PCR register. PCR should be set so
that all the bits in the same port-group should have the same direction.
Note: Port 3 and port 6
(2)
Event Generation by Input Single-Ports
An input single-port generates an event when the signal value of the external pin connected to the
relevant port changes. The event-generation condition is specified using the PEL0 to PEL3
registers. An example of operation is shown in figure 12.3.
(3)
Output Single-Port Operation upon Event Input
When an event is input to an output single-port, the PDR value of the relevant port changes. The
specific change of the PDR value is specified using the PEL0 to PEL3 registers. Thus, the change
of the PDR value changes the signal value of the external pin connected to the relevant port. An
example of operation is shown in figure 12.3.
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Section 12 Event Link Controller
(4)
Input Port-Group Operation upon Event Input and Event Generation
An input port-group generates an event when the signal value of any one of the external pins
connected to the relevant port-group changes. The event-generation condition is specified using
the PGC1 and PGC2 registers. When an event is input to an input port-group, the signal value of
the external pin upon event input is transferred to PDBF. In this case, only the values of the bits
specified as members of the input port-group are transferred. An example of operation is shown in
figure 12.4.
(5)
Output Port-Group Operation upon Event Input
When an event is input to an output port-group, the PDR values change to the values according to
the PGC1 or PGC2 settings. An example of operation is shown in figure 12.5.
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Section 12 Event Link Controller
Example of Operation for Single-Port Input
Port 3
External pin
Port 37
On-chip module
Event link
Port 36
Port 35
Port 34
Example of Operation for Single-Port Output
Port 33
On-chip module
Event link
Port 32
Port 31
Port 30
Port to which event is
connected
Figure 12.3 Event Linkage related to Single-Ports
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Section 12 Event Link Controller
PDBF
External signal
PDBF
0
0
0
0
P37
P36
0
0
P35
0
0
P34
0
1
P33
0
0
P32
0
1
P31
0
0
P30
P30 to P33 are specified
as an input port-group.
Event signal
Figure 12.4 Event Linkage related to Input Port-Groups
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Section 12 Event Link Controller
(6)
Operation of Port Buffer Registers
(a)
Input Port-Groups
When an event is input to an input port-group, the signal value of the external pin of the bit
specified as the members of the input port-group is transferred to PDBF. If another event is input
to the input port-group in this state, the current PDR value is transferred or not depending on the
PGCOVE bit setting in PGC as described below.
• PGCOVE = 0 (overwriting PDBF is disabled)
If the PDBF value that has been transferred upon the latest event input has already been read
by the CPU (or transferred by the DTC), the signal value of the external pin is transferred to
PDBF. If not read, the signal value of the external pin is not transferred and the input event is
invalid.
• PGCOVE = 1 (overwriting PDBF is enabled)
When another event is input to an input port-group, the signal value of the external pin is
transferred to PDBF.
(b)
Output Port-Groups
If an output port-group is specified so that it should output the PDBF value, the PDBF value is
transferred to PDR when an event is input to the output port-group. In this case, only the values of
the bits specified as the members of the output port-group are transferred
If an output port-group is specified so that it should shift out the bit values in the group (PGCO
bits = 1xx in PGC), the PDBF data is transferred to PDR, and then the PDR value is shifted bit by
bit from MSB to LSB. The initial value to be output to the port-group should be provided in
PDBF.
Examples of operation are shown in figures 12.5 and 12.6.
(7)
Restrictions on Writing to PDR or PDBF by CPU
When the ELCON bit in ELCR is set to 1, write access to the following registers is invalid.
• If bits are specified as members of the input port-group and the event-linkage is set for the
port-group, write access to the relevant bits in PDBF by the CPU is invalid.
• If port bits are specified as members of the output port-group, write access to the relevant bits
in PDR by the CPU is invalid.
• If a port bit is specified as an output single-port and the event-linkage is set (by ELSR) for the
port, write access to the relevant bit in PDR by the CPU is invalid.
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Section 12 Event Link Controller
External signal
PDBF
PDR
PDBF
PDR
P33
1
0
1
1
Port
P33
P32
0
0
0
0
P32
P31
1
0
1
1
P31
P30
0
0
0
0
P30
Event signal
Note: P30 to P33 are specified as an output port-group.
Figure 12.5 Event Linkage related to Output Port-Groups
P33
P32
P31
P30
PDBF
PDR
1
0
0
PDR
PDR
PDR
PDR
1
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
P33
P32
P31
P30
Event signal
Note: P30 to P33 are specified as an output port-group.
Figure 12.6 Bit-Shifting Operation of Output Port-Groups
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Section 12 Event Link Controller
12.3.6
Event-Generation Timer
The event-generation timer can generate an event at specified interval. The generated event can be
connected to another module. The features of the timer are given below.
• The interval can be generated using the 16-bit free-running counter.
• The delay time (of 0 to 3 counter clock cycles) can be set, which is the time from the set eventgeneration timing (= interval) to actual generation of the event.
• Four-channel event output is available (figure 12.8).
ELTMCR
Internal data bus
ELTMSA
ELTMSB
ELTMDR
φELC
32768 cycles
ELTMCNT
One cycle
Internal clock
(φ/8192 to φ)
Output delay
circuit 0
ELC timer event 0
Channel 1
Output delay
circuit 1
ELC timer event 1
Channel 2
Output delay
circuit 2
ELC timer event 2
Channel 3
Output delay
circuit 3
ELC timer event 3
Channel 0
Figure 12.7 Block Diagram of Event-Generation Timer
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Section 12 Event Link Controller
φELC
ELTMDR
φELC/one cycle
C
C
Q
D
Latch
C
Q
D
Latch
Q
D
Latch
φELC/32768 cycles
ELC timer event n
(n = 0 to 3)
Channel × selectable frequency
(16 counter cycles)
Event output x
Delay time can be specified using ELTMDR.
Figure 12.8 Operation of Event-Generation Timer
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Section 12 Event Link Controller
12.3.7
Procedure for Linking Events
The following describes the procedure for linking events.
1. Set the operation of the module to which an event is to be linked.
2. To the ELSRn register corresponding to the module to which an event signal is to be linked,
set the number of the event signal.
3. If events are to be linked to timers, set the ELOPA to ELOPC registers corresponding to the
timers as required.
4. Set the ELCON bit in ELCR to 1, which enables linkage of all the events.
5. Set the operation of the module from which an event is output, and start the module. This
allows the event output from the module to start the module to which an event is linked as
specified.
6. To stop event linkage of some independent modules, set B'00000000 to the ELSn7 to ELSn0
bits in the ELSRn corresponding to the modules. To stop linkage of all the events, clear the
ELCON bit in ELCR to 0.
If events are linked to ports, set the registers corresponding to the ports as below.
 PDR: Set the initial values of the output ports.
 PCR: Set the I/O direction of the ports.
 PGR: If ports are used as a port-group, set the ports (in bit units) to be grouped.
 PGC: Set the operation of the port-group.
 PEL: If ports are used as single-ports, set the ports, the operation of the ports when an
event is input, and the condition when an event is generated.
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Section 13 Timer RA
Section 13 Timer RA
The timer RA is an 8-bit reload timer with a prescaler. The prescaler and the timer are comprised
of a reload register and a counter, respectively.
13.1
Overview
• Operating mode: 5 modes
Timer mode: Counts internal count sources.
Pulse output mode: Counts internal count sources and produces a toggle output in timer
underflow.
Event counter mode: Counts external events.
Pulse width measurement mode: Measures the pulse width of external pulses.
Pulse cycle measurement mode: Measures the pulse cycle of external pulses.
• Selection of nine count sources
φ, φ/2, φ/8, φ/32, φ/64, φ/128, φ40, φsub, or an external event input to the TRAIO pin.
• An interrupt generated on an underflow of the counter
Data bus
TCK[2:0]
Pulse width measurement mode TRAPRE
Pulse cycle measurement mode
Reload
Timer mode
TCKCUT
register
Pulse output mode
TSTART
φ
φ/8
φ40
φ/2
φsub
φ/32
φ/64
φ/128
TRATR
Reload
register
Underflow signal
Counter
Counter
Timer RA
interrupt
Event count mode
Pulse width measurement mode
Pulse cycle measurement mode
TRAIO pin
Digital
filter
Polarity
switching
Count control
circuit
Measurement-complete signal
Pulse output mode
TOPCR
TIPF[1:0]
TEGSEL
Q
Toggle flipflop
CK
Q
CLR
Write to TRAMR register
Write 1 to TSTOP bit
TOENA
TRAO pin
Figure 13.1 Block Diagram of Timer RA
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Section 13 Timer RA
Table 13.1 shows the timer RA input/output pins.
Table 13.1 Pin Configuration
Name
Abbreviation
I/O
Function
Timer RA input/output
TRAIO
I/O
External event input and pulse input/output
Timer RA output
TRAO
Output
Inverted pulse output of TRAIO output
13.2
Register Descriptions
The timer RA has the following registers:
•
•
•
•
•
•
Timer RA control register (TRACR)
Timer RA I/O control register (TRAIOC)
Timer RA mode register (TRAMR)
Timer RA prescaler register (TRAPRE)
Timer RA timer register (TRATR)
Timer RA interrupt request status register (TRAIR)
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Section 13 Timer RA
13.2.1
Timer RA Control Register (TRACR)
Address: H'FF06F0
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0


TUNDF
TEDGF

TSTOP
TCSTF
TSTART
0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
7, 6

Reserved
These bits are read as 0. The write valued should be 0. 
5
TUNDF
[Setting condition]
Timer RA
underflow flag • When timer RA underflows from H'00 to H'FF.
[Clearing condition]
4
TEDGF
[Setting condition]
Valid edge
R/W
detection flag • When the pulse width measurement is completed
with TSTART in TRACR = 1, in pulse width
measurement mode.
• When the timer RA prescaler underflows at the
second time after a valid edge of the measurement
pulse is input, in pulse cycle measurement mode.
[Clearing condition]
•
•
R/W
R/W
When 0 is written to this bit*
When 0 is written to this bit*
3

Reserved
This bit is read as 0. The write value should be 0.

2
TSTOP
Timer RA
count forced
stop
0: Timer RA counting is continued.
R/W
1: Timer RA counting is forcedly stopped.
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Section 13 Timer RA
Bit
Symbol
Bit Name
Description
R/W
1
TCSTF
Timer RA
count status
flag
0: Timer RA counting has been stopped.
R
1: Timer RA counting is in progress.
[Setting condition]
•
When 1 is written to TSTART and counting is
started.
• The start of counting after ELOPA of the event link
controller is selected counting by timer RA, the
specified event is occurred, and the TSTART bit is
set to 1.
[Clearing condition]
•
•
0
Note:
TSTART
Timer RA
count start
When 0 is written to TSTART and counting is
stopped.
When 1 is written to TSTOP and counting is
stopped.
0: Timer RA counting is stopped.
R/W
1: Timer RA counting is started.
1. A MOV instruction should be used to write 0 to this register.
2. The timer RA registers should not be accessed until the TCSIF bit changes after the
TSTART bit is set, apart from TRACR which can be read at any time during timer
operation.
TRACR controls the timer RA counter and indicates the timer RA state.
• TSTOP bit (timer RA count forced stop)
Setting this bit to 1 initializes the counter of the timer and the prescaler, bits TSTART and
TCSTF, and timer outputs. This bit is always read as 0.
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Section 13 Timer RA
13.2.2
Timer RA I/O Control Register (TRAIOC)
Address: H'FF06F1
Bit:
b7
b6
b5
TIOGT[1:0]
Value after reset:
0
b4
TIPF[1:0]
0
Bit
Symbol
Bit Name
7, 6
TIOGT[1:0] TRAIO event
input control
0
0
b3
b2
b1
b0
TIOSEL
TOENA
TOPCR
TEDGSEL
0
0
0
0
Description
R/W
00: Input control is not performed. (Events are always R/W
enabled.)
01: Input control is performed. (Events are enabled
when IRQ2 input is high.)
10: Setting prohibited
11: Setting prohibited
5, 4
TIPF[1:0]
TRAIO input
filter select
00: No filter operation
R/W
01: Filtered (Sampled at φ)
10: Filtered (Sampled at φ/8)
11: Filtered (Sampled at φ/32)
These bits should be set to B'00 in timer mode and
pulse output mode.
3
2
TIOSEL
TOENA
TRAIO input
select
0: Input from the TRAIO pin
TRAO output
enable
0: TRAO outputs are disabled.
R/W
1: Input from the LIN
R/W
1: TRAO outputs are enabled.
This bit should be set to 0 except in event counter
mode and pulse output mode.
1
TOPCR
TRAIO output
control
0: TRAIO outputs are enabled.
R/W
1: TRAIO outputs are disabled.
This bit should be set to 0 except in pulse output
mode.
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Section 13 Timer RA
Bit
Symbol
Bit Name
Description
0
TEDGSEL
Input/output
•
polarity switch
•
Timer mode
R/W
R/W
This bit should be set to 0.
Pulse output mode
0: The initial value of TRAIO output is set at a high
level.
1: The initial value of TRAIO output is set at a low
level.
•
Event count mode
0: Counter incremented at the TRAIO input rising
edge. The initial value of TRAIO output is set at a
low level.
1: Counter incremented at the TRAIO input falling
edge. The initial value of TRAIO output is set at
a high level.
•
Pulse width measurement mode
0: Measures the low-level width of TRAIO input.
1: Measures the high-level width of TRAIO input.
•
Pulse cycle measurement mode
0: Measures from the rising edge of the
measurement pulse to the next rising edge.
1: Measures from the falling edge of the
measurement pulse to the next falling edge.
Note: When TCSTF = 1, do not rewrite this register.
• TIOGT1 bit and TIOGT0 bit (TRAIO event input control 1 and 0)
These bits control input events in event counter mode.
• TIPF1 bit and TIPF0 bit (TRAIO input filter select 1 and 0)
If filtered operation is selected, the input is determined when the same value is sampled three
times in succession from the TRAIO pin.
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Section 13 Timer RA
13.2.3
Timer RA Mode Register (TRAMR)
Address: H'FF06F2
Bit:
b7
b6
0
b4
0
0
b3
b2

TCK[2:0]
TCKCUT
Value after reset:
b5
0
0
b1
b0
TMOD[2:0]
0
0
Bit
Symbol
Bit Name
7
TCKCUT
R/W
6 to 4
TCK[2:0]*2
Timer RA count 0: Count source is supplied.
source cutoff
1: Count source is cut off.
Timer RA count 000: φ
source select
001: φ/8
010: φ/40
011: φ/2
100: φsub
101: φ/32
110: φ/64
111: φ/128
3

Reserved

2 to 0
TMOD[2:0]
000: Timer mode
Timer RA
operating mode 001: Pulse output mode
select
010: Event count mode
011: Pulse width measurement mode
100: Pulse cycle measurement mode
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Note:
•
Description
0
R/W
R/W
This bit is read as 0. The write value should be 0.
R/W
1. The counting should be stopped (when both the TSTART and TCSTF bits in TRACR
are 0) when this register is modified.
2. If the internal φ/40 clock is selected, the high-speed on-chip oscillator must be
operating. As long as the internal φ40 clock is selected, do not stop the high-speed onchip oscillator.
TCK2 bit and TCK0 bit (timer RA count source select)
A count source is selected if the mode is not the event count mode.
• TMOD2 bit to TMOD0 bit (timer RA operating mode select)
Writing to TRAMR initializes the output level.
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Section 13 Timer RA
13.2.4
Timer RA Interrupt Enable Status Register (TRAIR)
Address: H'FF06F5
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
TRAIE
TRAIF






0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
7
TRAIE
Timer RA
0: Timer RA interrupt requests are disabled.
interrupt
1: Timer RA interrupt requests are enabled.
request enable
R/W
6
TRAIF
Timer RA
interrupt
request flag
R/W
[Setting condition]
•
When the timer RA underflows.
•
When the input pulse measurement is completed in
pulse width measurement mode.
•
When the timer RA prescaler underflows at the
second time after a valid edge of measurement
pulse is input, in pulse cycle measurement mode.
R/W
[Clearing condition]
5 to 0

Reserved
•
When 1 is read from the bit and then 0 is written to.
•
When the DTC is activated by a TRAIF interrupt,
and the DISEL bit in MRB of the DTC is 0.
This bit is read as 0. The write value should be 0.
Rev. 1.00 Oct. 03, 2008 Page 404 of 962
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
Section 13 Timer RA
13.2.5
Timer RA Prescaler Register (TRAPRE)
Address: H'FF06F3
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
Value after reset:
1
1
1
1
1
1
1
1
TRAPRE consists of a reload register and an 8-bit counter, each with an initial value of H'FF.
If a down-count is performed using the count source selected with TRAMR and an underflow
occurs, the value of the reload register is loaded to the counter. The underflow becomes a count
source for TRATR.
The reload register and the counter are assigned to the same address. On write, a value is written
to the reload register, and on read, a counter value is read. During a write to TRAPRE the load
timing from the reload register to the counter differs between counting in progress and counting
stopped. Writing to TRAPRE when counting is stopped causes the data to be written to both the
reload register and the counter. Writing to TRAPRE during counting causes the new value to be
written to the reload register after four cycles of count source, and to be loaded to the counter in
synchronization with the next count source.
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Section 13 Timer RA
13.2.6
Timer RA Timer Register (TRATR)
Address: H'FF06F4
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
Value after reset:
1
1
1
1
1
1
1
1
TRATR consists of a reload register and an 8-bit counter, each with an initial value of H'FF.
TRATR performs a down-count of the prescaler underflows. When an underflow occurs in
TRATR, the value of the reload register is loaded to the counter and a timer RA interrupt request
is generated at the same time.
The reload register and the counter are assigned to the same address. On write, a value is written
to the reload register, and on read, a counter value is read. However, on read in pulse cycle
measurement mode, a value in the read buffer is read. During a write to TRATR the load timing
from the reload register to the counter differs between counting in progress and counting stopped.
Writing to TRATR when counting is stopped causes the data to be written to both the reload
register and the counter. Writing to TRATR during counting causes the new value to be written to
the reload register in synchronization with an underflow of the prescaler first after four counts of
the count source, and to be loaded to the counter in synchronization with the next underflow of the
prescaler.
TRAPRE and TRATR should not be set to H'00 at the same time.
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Section 13 Timer RA
13.3
Operation
13.3.1
Operations Common to Various Modes
(1)
Starting and Stopping Operation
Writing the value 1 to the TSTART bit in TRACR starts counting in a set operating mode; writing
the value 0 to the TSTART bit stops the counting. The prescaler counts down in the counter clock
cycle to be input into the prescaler. The timer counts down using the underflow of the prescaler as
a count source.
(2)
Forced Termination of Operation
Writing 1 to the TSTOP bit in TRACR stops the counting forcibly. When the counting is stopped,
the timer counter, the prescaler counter, and any associated flags are initialized while the reload
registers of the prescaler and the timer counter are retained.
(3)
Interrupt Request
An interrupt request is generated on the underflow of the timer RA counter.
(4)
Reading and Writing Count Value
Reading registers TRAPRE and TRATR reads count values from each register. If a write is
performed to TRAPRE or TRATR when the counting is stopped, a specified value is written to
both the reload register and the counter.
If a write is performed to the TRAPRE register during counting, first a set value is written to the
reload register in synchronization with the count source after four cycles of count source, and the
set value is then transferred to the prescaler counter in synchronization with the next count source.
If a write is performed to the TRATR register, a set value is written to the reload register in
synchronization with the underflow of the prescaler, and the set value is transferred to the timer
counter in synchronization the next underflow of the prescaler. For this reason, if a write is
performed to TRAPRE or TRATR during counting, the value of the counter is not updated
immediately after the execution of the write command. Figure 13.2 shows an example operation
where a count value is rewritten when the timer RA is counting.
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Section 13 Timer RA
Write H'01 to TRAPRE and
H'25 to TRATR by a program
Count source
After a write, reload register is written to
after four counts of count source.
Reload register for
timer RA prescaler
Counter for
H'06
timer RA prescaler
Previous value
H'05
H'04
H'03
New value (H'01)
H'02
H'01
Reloaded at the
second count
source
Reloaded on
underflow
H'01
H'01
H'00
H'00
H'01
H'00
H'01
H'00
Reload register is written to
at the first underflow after a write.
Reload register
for timer RA
Previous value
New value (H'25)
Reloaded at the second underflow
Timer RA counter
H'03
H'25
H'24
TRAIF in TRAIR "0"
IR bit does not change until an underflow occurs with
the new value.
Figure 13.2 Rewriting Count Value When Timer RA Counting is in Progress
13.3.2
Timer Mode
This mode counts internal clocks as a count source. Setting the TMOD[2:0] bits in TRAMR to
B'000 activates the timer mode operation. A count source is selected in terms of the TCK[2:0] bits
in TRAMR.
13.3.3
Pulse Output Mode
This mode counts internal clocks as a count source, and toggle-outputs pulses from the TRAIO pin
each time the counter underflows. Setting the TMOD[2:0] bits in TRAMR to B'001 activates pulse
the output mode operation. A count source is selected using the TCK[2:0] bits in TRAMR. The
initial output value of the pin is set using the TEDGSEL bit in TRAIOC. By setting the TOENA
bit in TRAIOC, a reverse output can be output from the TRAO pin to the TRAIO pin.
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Section 13 Timer RA
13.3.4
Event Counter Mode
This mode counts external events that are input from the TRAIO pin as a count source. Setting the
TMOD[2:0] bits in TRAMR to B'010 activates the event-counter mode operation. By setting the
TEDGSEL bit in TRAIOC, it is possible to specify whether counting is to be performed on the
rising or falling edge of an input event from the TRAIO pin. Also, by setting the TIOGT[1:0] bits
in TRAIOC, a function enables external event input when the IRQ2 pin is at a high level. Setting
the TIPF[1:0] bits in TRAIOC allows applying a filter to external event input. Similar to the pulse
output operation mode, a toggle can be output from the TRAO pin in synchronization with an
underflow of the timer counter. In event counter mode, even if 1 is written to the TSTART bit, the
value of the TCSTF bit will not become 1 unless the corresponding event signal is input. If the
event signal is input while TCSTF = 0, the counter value will be the number of times the event has
occurred minus 3. If the event signal is input while TCSTF=1, the number time the event has
occurred = counter value.
13.3.5
Pulse Width Measurement Mode
This mode measures the pulse width of external signals that are input from the TRAIO pin. Setting
the TMOD[2:0] bits in TRAMR to B'011 activates the pulse width measurement mode operation.
A count source is selected in terms of the TCK[2:0] bits in TRAMR. The TEDGSEL bit in
TRAIOC can be used to specify whether the low-level width or the high-level width of input
pulses is to be measured. Setting the TIPF[1:0] bits in TRAIOC allows applying a filter to external
pulse input. Figure 13.3 shows an operation example of pulse width measurement mode.
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Section 13 Timer RA
0 = Contents of TRATR (upper) and TRAPRE (lower) registers
Counter value (hexadecimal)
H'FFFF
Start measurement.
Underflow
n
Measurement is stopped.
Measurement is stopped.
Start
H'0000
Start
Set to 1 by a program.
TSTART in TRACR "1"
"0"
Measurement pulse
(TRAIO pin input)
"1"
"0"
Set to 0 by a program.
TRAIF in TRAIC
"1"
"0"
Set to 0 by a program.
TEDGF in TRACR
"1"
"0"
Set to 0 by a program.
TUNDF in TRACR
"1"
"0"
When a high level is specified for measuring the pulse width (TEDGSEL = 1).
Figure 13.3 Operation Example of Pulse Width Measurement Mode
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Section 13 Timer RA
13.3.6
Pulse Cycle Measurement Mode
This mode measures the cycle of external pulses that are input from the TRAIO pin. Setting the
TMOD[2:0] bits in TRAMR to B'100 activates the pulse cycle measurement operation. The
TEDGSEL in TRAIOC can be used to specify whether the period from the falling edge to another
falling edge of the input pulse of the TRAIO pin is to be measured or the period from the rising
edge to another rising edge is to be measured. Setting the TIPF[1:0] bits in TRAIOC also enables
to apply a filter to external pulse input. Count sources are selected using the TCK[2:0] bits in
TRAMR.
After the start of timer counting, each time a valid input edge is input from the TRAIO pin, a value
is transferred from the counter of the timer RA to the read buffer in synchronization with the
underflow of the timer RA prescaler. The value in the read buffer is retained until the timer RA
register is read. Also, after a value is transferred to the read buffer, a value is transferred from the
reload register to the counter in synchronization with the next underflow of the timer RA
prescaler. Reading of the read buffer should not be performed until the TEDGF bit in TRACR is
set to 1. An interrupt request is generated either when the TEDGF bit in TRACR is set to 1 or
when the timer RA counter underflows.
For pulse input to the TRAIO pin, pulses with a cycle greater than double the cycle of the timer
RA prescaler should be input. Also, input pulses for which the high pulse width and the low pulse
width are greater than the cycle of the timer RA prescaler. If pulses with a short cycle are input,
the input is ignored in some cases.
Figure 13.4 shows an operation example of pulse cycle measurement mode.
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Section 13 Timer RA
13.3.7
Operation through an Event Link
Using the event link controller (ELC), timer RA can be made to operate in the following ways in
relation to events occurring in other modules.
(1)
Starting Counter Operation
The start of counting operations by timer RA can be selected by the ELOPA register of the ELC.
When the event specified in ELSR0 occurs, the TSTART bit in the TRACR is set to 1, which
starts counting by timer RA. However, if the specified event occurs when the TCSTF flag has
already been set to 1, that event is not effective.
(2)
Counting Events
The counting of events by timer RA can be selected by the ELOPA register of the ELC. When the
event specified in ELSR0 occurs, event-counter operation proceeds with that event as the source to
drive counting, regardless of the setting in TRAMR. When event-counter operation is to be
employed, set the TSTART bit in TRACR to 1 beforehand. When the value of the counter is read,
the value read out is the actual number of input events minus three.
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Section 13 Timer RA
Timer RA prescaler
underflow signal
Set to 1 by a program.
TSTART in TRACR
"1"
"0"
Start counting
Measurement pulse
(TRAIO pin input)
"1"
"0"
TRA reload
TRATR content
TRA reload
H'0F H'0E H'0D H'0F H'0E H'0D H'0C H'0B H'0A H'09 H'0F H'0E H'0D
H'01 H'00 H'0F H'0E
Underflow
Retained
Read buffer content *1
H'0F H'0E
Retained
H'0D
H'0B H'0A
H'09
H'0D
H'01 H'00 H'0F H'0E
TRA read (*3)
*2
*2
TEDGF in TRACR
"1"
"0"
Set to 0 by a program.
*4
*6
TRAIF in TRAIR
"1"
"0"
Set to 0 by a program.
TUNDF in TRACR
*5
"1"
"0"
Set to 0 by a program.
Measurement condition: The initial value of TRATR is H'0F and the width from the rising edge to the next rising edge
of measurement pulse is measured (TEDGSEL = 0).
Notes: 1. When TRATR is read in pulse cycle measurement mode, the value in the read buffer can be read.
2. The TEDGF bit in TRACR is set to 1 (valid edge exists) on the second underflow of the timer RA
prescaler after a valid edge of the measurement pulses is input.
3. TRATR should be read between the TEDGF bit setting to 1 (valid edge exists) and the next
valid edge input.
The value in the read buffer is retained until TRATR is read. Therefore, if the value is not read
before the next valid edge input, the measurement result of the previous cycle remains.
4. The MOV instruction should be used to write 0 to the TEDGF bit in TRACR using a program.
Here, 1 should be written to the TUNDF bit .
5. The MOV instruction should be used to write 0 to the TUNDF bit in TRACR using a program.
Here, 1 should be written to the TEDGF bit.
6. If an underflow of timer RA and reloading of timer RA by valid edge input occur at the same time,
both the TUNDF and TEDGF bits are set to 1. In this case, the effectiveness of the TUNDF bit should
be determined according to the read buffer contents.
Figure 13.4 Operation Example of Pulse Cycle Measurement Mode
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Section 13 Timer RA
13.4
Usage Notes
1. The prescaler and timer are read out per byte inside the microcomputer even when they are
read out in 16-byte unit. Therefore, the timer value can be updated while those two registers
are read out.
2. The TEDGF and TUNDF bits in TRACR used in pulse width and pulse cycle measurement
modes assume the value 0 when 0 is written by a program and do not change if 1 is written. If
one flag is set to 0 by a program, use the MOV instruction to write 1 to the other flag. In this
manner, unintended flag changes can be prevented.
3. When a transition is made to pulse width or pulse cycle measurement mode from another
mode, the TEDGF and TUNDF bits are undefined. Timer RA counting should be started by
writing 0 to the TEDGF and TUNDF bits.
4. In some cases, the TEDGF bit becomes 1 on the first timer RA prescaler underflow signal that
is generated after the start of counting.
5. When using the pulse cycle measurement mode, set the TEDGF bit to 0 by allowing a length
of time 2 cycles or greater of the timer RA prescaler after the counting process is started.
6. After 1 is written to the TSTART bit when counting is stopped, the TCSTF bit remains 0 for
the number of cycle of count source. Registers associated with the timer RA except the
TRACR for reading should not be accessed until the TCSTF bit becomes 1. Counting starts
from a valid edge of the first count source after the TCSTF bit becomes 1.
After 0 is written to the TSTART bit when counting is in progress, the TCSTF bit remains 1
for the number of cycle of count source. Registers associated with the timer RA except the
TRACR for reading should not be accessed until the TCSTF bit becomes 0. Counting stops
when the TCSTF bit becomes 0.
7. When writing successively to TRAPRE during counting (TCSTF=1), allow a minimum write
interval of 4 cycles of count source.
8. When writing successively to TRATR during counting (TCSTF=1), allow a minimum write
interval of 4 cycles of count source underflow.
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Section 14 Timer RB
Section 14 Timer RB
The timer RB is an 8-bit reload timer with an 8-bit prescaler. The prescaler and the timer are each
comprised of a reload register and a counter. The timer RB has two reload registers: timer RB
primary register and timer RB secondary register.
14.1
Overview
• Four operating modes
Timer mode: Counts either internal count sources or timer RA underflows.
Programmable waveform generation mode: Outputs any pulse widths continuously.
Programmable one-shot generation mode: Outputs one-shot pulses.
Programmable wait one-shot generation mode: Outputs delayed one-shot pulses.
• Selection of eight count sources
φ, φ/2, φ/4, φ/8, φ/32, φ/64, φ/128, or an underflow of timer RA
• An interrupt generated on an underflow of the timer RB counter
Data bus
Timer counter
Prescaler
φ
φ8
TCK[2:0]
bits
TRBPRE
TRBSC
TRBPR
TCKCUT bit
Timer RA underflow
φ2
φ4
φ32
φ64
φ128
Timer RB interrupt
Counter
Counter
TMOD[1:0] = B'10 or B'11
TSTART bit
TOSST bit
Polarity
select
Digital
filter
TRGB pin
INOSEG bit
TOPL
TMOD[1:0] bits
TOCNT
TRBO pin
INOSTG bit
Q Toggle flipflop
CK
Q
CLR
Write to TSTOP
except in timer mode
Figure 14.1 Block Diagram of Timer RB
Rev. 1.00 Oct. 03, 2008 Page 415 of 962
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Section 14 Timer RB
Table 14.1 shows the timer RB input/output pins.
Table 14.1 Pin Configuration
Name
I/O
Function
TRGB
Input
External trigger input
TRBO
Output
Successive pulse output or one-shot pulse output
14.2
Register Descriptions
The timer RB has the following registers:
•
•
•
•
•
•
•
•
Timer RB control register (TRBCR)
Timer RB one-shot control register (TRBOCR)
Timer RB I/O control register (TRBIOC)
Timer RB mode register (TRBMR)
Timer RB interrupt request status register (TRBIR)
Timer RB prescaler register (TRBPRE)
Timer RB secondary register (TRBSC)
Timer RB primary register (TRBPR)
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Section 14 Timer RB
14.2.1
Timer RB Control Register (TRBCR)
Address: H'FFFFA0
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0





TSTOP
TCSTF
TSTART
0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7 to 3

Reserved
These bits are read as 0. The write value should
be 0.

2
TSTOP
Count forced stop
0: Timer RB counting is continued.
R/W
1: Timer RB counting is forcedly stopped.
1
TCSTF
Count status flag
0: Timer RB counting is stopped.
R
1: Timer RB counting is in progress.
[Setting conditions]
•
•
When 1 is written to TSTART and counting is
started.
The start of counting after ELOPA of the event
link controller is selected counting by timer
RB, the specified event is occurred, and the
TATRT bit is set to 1.
[Clearing conditions]
•
•
0
TSTART
Count start
When 0 is written to TSTART and counting is
stopped.
When 1 is written to TSTOP and counting is
stopped.
0: Timer RB counting is stopped.
R/W
1: Timer RB counting is started.
Notes: 1. A MOV instruction should be used to write to this register.
2. The timer RB registers should not be accessed until the TCSTF bit changes after the
TSTART bit is set, apart from TRBCR which can be read at any time during timer
operation.
• TSTOP bit (count forced stop)
Setting this bit to 1 stops counting forcibly. At this time, the counter of the timer RB prescaler
and the timer RB counter are initialized. Also, bits TSTART and TCSTF in TRBCR, bits
TOSSTF, TOSSP, TOSST in TRBOCR, and TRBO outputs are initialized. The reload register
of the prescaler and the timer RB counter are hold. This bit is always read as 0.
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Section 14 Timer RB
14.2.2
Timer RB One-Shot Control Register (TRBOCR)
Address: H'FFFFA1
Bit:
b7
b6
b5
b4
b3
b2
b1
b0





TOSSTF
TOSSP
TOSST
0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7 to 3

Reserved
These bits are read as 0. The write value should be 0. 
2
TOSSTF
One-shot
status flag
0: Timer RB one-shot function has been stopped.
R
1: Timer RB one-shot function is active (including wait
time).
[Setting conditions]
•
When 1 is written to the TOSST bit.
•
When trigger inputs to the TRGB pin are enabled.
[Clearing conditions]
•
When 1 is written to the TOSSP bit.
•
When 0 is written to the TSTART bit in TRBCR.
•
When 1 is written to the TSTOP bit in TRBCR.
[In programmable one-shot generation mode]
•
When the timer counter reaches H'00 and the
reloading is performed.
[In programmable wait on-shot generation mode]
When the counter value reaches H'00 during the
secondary counting and the reloading is performed.
1
TOSSP*1
0
2
One-shot stop 0: Timer RB counting is not stopped.
R/W
1: Timer RB counting is stopped.
TOSST*
One-shot start 0: Timer RB counting is stopped.
1: Timer RB counting is started.
Note:
1. The TOSSP bit should be modified to 1 when the TOSSTF bit is 1.
2. The TOSST bit should be modified to 1 when the TOSSTF bit is 1.
Rev. 1.00 Oct. 03, 2008 Page 418 of 962
REJ09B0465-0100
R/W
Section 14 Timer RB
• TOSSP bit (one-shot stop)
Writing 1 to this bit stops the timer counting. This bit is always read as 0
• TOSST bit (one-shot start)
In programmable one-shot generation mode or programmable wait one-shot generation mode,
writing 1 to this bit starts the timer counting and one-shot pulse output in synchronization with
the count source. This bit is always read as 0.
14.2.3
Timer RB I/O Control Register (TRBIOC)
Address: H'FFFFA2
Bit:
b7
b6


0
0
Value after reset:
b5
b4
TIPF[1:0]
0
0
b3
b2
b1
b0
INOSEG
INOSTG
TOCNT
TOPL
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7, 6

Reserved
These bits are read as 0. The write value should
be 0.

5, 4
TIPF[1:0]
TRGB input filter
select
00: No filter operation
R/W
01: Filtered (Sampled at φ)
10: Filtered (Sampled at φ/8)
11: Filtered (Sampled at φ/32)
These bits should be set to B'00 for timer mode or
pulse output mode.
3
INOSEG
One-shot trigger
polarity select
0: Triggered at a falling edge.
R/W
2
INOSTG
One-shot trigger
control
0: The one-shot trigger function for the TRGB pin
is disabled.
1: Triggered at a rising edge.
R/W
1: The one-shot trigger function for TRGB pin is
enabled.
1
TOCNT
Timer RB output
switch
0: Waveform is output from timer RB.
R/W
1: Waveform output is disabled.
Rev. 1.00 Oct. 03, 2008 Page 419 of 962
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Section 14 Timer RB
Bit
Symbol
Bit Name
Description
R/W
0
TOPL
Timer RB output
level select
Programmable Waveform Generation Mode
R/W
0: A high-level signal is output in primary period, a
low-level signal in secondary period and a lowlevel signal when the timer stops.
1: A low-level signal is output in primary period, a
high-level signal in secondary period, and a
high-level signal when the timer stops.
Programmable one-shot generation mode
0: A high-level signal is output for one-shot pulse
output and a low-level signal when the timer
stops.
1: A low-level signal is output for one-shot pulse
output and a high-level signal when the timer
stops.
Programmable wait one-shot generation mode
0: A high-level signal is output for one-shot pulse
output and a low-level signal during the wait time
or the time when the timer stops.
1: A low-level signal is output for one-shot pulse
output and a high-level signal during the wait
time or the time when the timer stops.
This bit should be 0 in timer mode.
• INOSEG bit (one-shot trigger polarity select)
Selects an edge for the one-shot trigger signal input from the TRGB pin in programmable oneshot generation mode or programmable wait one-shot generation mode. This bit should be 0 in
timer mode or programmable waveform generation mode.
• INOSTG bit (one-shot trigger control)
Enables or disables one-shot trigger signal input from the TRGB pin. This bit should be 0 in
timer mode or programmable waveform generation mode.
• TOCNT bit (timer RB output switch)
For TRBO output state or output change conditions in each mode, see section 14.3.6, TOCNT
Settings and Pin State Update Conditions.
• TOPL bit (timer RB output level select)
This bit should be 0 in timer mode.
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Section 14 Timer RB
14.2.4
Timer RB Mode Register (TRBMR)
Address: H'FFFFA3
Bit:
b7
b6
TCKCUT
0
Value after reset:
Bit
7
0
Symbol
TCKCUT*
1
1
6 to 4 TCK[2:0]*
b5
b4
TCK[2:0]
0
0
b3
b2
TWRC

0
0
b1
b0
TMOD[1:0]
0
0
Bit Name
Description
R/W
Count source
cutoff
0: Timer RB clock source is supplied.
R/W
Count source
select
000: φ
1: Timer RB clock source is cut off.
R/W
001: φ/8
010: Underflow of timer RA
011: φ/2
100: φ4
101: φ/32
110: φ/64
111: φ/128
3
TWRC
Write control
0: Both the reload register and counter are written to.
1: Only the reload register is written to.
2
1, 0

Reserved
2
TMOD[1:0]* Operating
mode select
This bit is read as 0. The write value should be 0.

00: Timer mode
R/W
01: Programmable waveform generation mode
10: Programmable one-shot generation mode
11: Programmable wait one-shot generation mode
Notes: 1. A count source should not be switched or cut off during counting. The count source
should be switched or cut off when both the TSTART and TCSTF bits in TRBCR are 0
(when the timer counting is stopped).
2. An operating mode should be selected when the counting is stopped (when both the
TSTART and TCSTF bits in TRBCR are 0).
• TWRC bit (write control)
Controls the timing when the counter reflects the value of the reload register. This bit should
be 1 except in timer mode.
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Section 14 Timer RB
14.2.5
Timer RB Interrupt Enable Status Register (TRBIR)
Address: H'FFFFA7
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
TRBIE
TRBIF






0
0
0
0
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
TRBIE
Interrupt enable
0: Timer RB interrupt requests are disabled.
R/W
1: Timer RB interrupt requests are enabled.
6
TRBIF
Interrupt request flag [Setting conditions]
R/W
Timer mode
•
When the timer RA underflows.
Programmable waveform generation mode
•
A half cycle of the count source after the
counter underflow in the secondary period
Programmable one-shot generation mode.
•
A half cycle of the count source after the
counter underflow
Programmable wait one-shot generation mode
•
A half cycle of the counter source after the
counter underflow in the secondary period
[Clearing conditions]
5 to 0

Reserved
Rev. 1.00 Oct. 03, 2008 Page 422 of 962
REJ09B0465-0100
•
When 1 is read from the bit and then 0 is
written to.
•
When the DTC is activated by a TRBAIF
interrupt, and the DISEL bit in MRB of the DTC
is 0.
These bits are read as 0. The write value should
be 0.

Section 14 Timer RB
14.2.6
Timer RB Prescaler Register (TRBPRE)
Address: H'FFFFA4
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
Value after reset:
1
1
1
1
1
1
1
1
TRBPRE is a reload register for the timer RB prescaler. The timer RB prescaler consists of a
reload register and an 8-bit counter.
If a down-count is performed using the count source selected on TRBMR and an underflow
occurs, the value of the reload register is loaded to the counter. The underflow becomes a count
source for TRBTR.
TRBPRE and the counter are assigned to the same address. On write, a value is written to the
reload register, and on read, a counter value is read. During a write to TRBPRE, the load timing
from the reload register to the counter differs between counting in progress and counting stopped
by the setting of the TWRC bit in TRBMR. For details, see descriptions of each operating mode.
The initial values of TRBPRE and the counter are H'FF.
14.2.7
Timer RB Secondary Register (TRBSC)
Address: H'FFFFA5
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
Value after reset:
1
1
1
1
1
1
1
1
TRBSC is an 8-bit write-only register that sets the secondary period for the timer RB counter. This
register is used only in programmable waveform generation mode and programmable wait oneshot generation mode. This register is not used in timer mode or programmable one-shot
generation mode.
When TRBSC is written to in any operating mode where TRBSC is used, both the TRBSC and
TRBPR should be written to in this order. Even if only TRBSC is to be modified, TRBPR should
also be set to the previous value. The initial value is H'FF.
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Section 14 Timer RB
14.2.8
Timer RB Primary Register (TRBPR)
Address: H'FFFFA6
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
Value after reset:
1
1
1
1
1
1
1
1
TRBPR is an 8-bit reload register that sets the cycle or primary period for the timer RB counter.
The timer RB counter consists of two registers, primary and secondary registers, and a counter.
The primary register and counter are assigned to the same address. On write to TRBPR, a value is
written to the reload register, and on read from TRBPR, a counter value is read.
During a write to TRBPR the load timing from the reload register to the counter differs between
counting in progress and counting stopped. For details, see descriptions of each operating mode.
The initial values of TRBPR and the counter are H'FF.
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Section 14 Timer RB
14.3
Operation
14.3.1
Timer Mode
The internal clock pulses or timer RA underflows are counted as a count source in timer mode.
When an underflow occurs on the timer RB counter, the value of TRBPR is reloaded and counting
is continued. TRBOCR and TRBSC are not used in timer mode. A count source is selected with
the TCK[2:0] bits in TRBMR.
(1)
Starting and Stopping Operation
Writing the value 1 to the TSTART bit in TRBCR starts counting; writing the value 0 to the
TSTART bit stops the counting.
(2)
Forced Termination of Operation
Writing 1 to the TSTOP bit in TRBCR stops the counting forcedly. When the counting is forcedly
stopped, the timer RB counter, the prescaler counter, and any associated flags are initialized.
(3)
Interrupt Request
An interrupt request is generated on the underflow of the timer RB counter.
(4)
Reading and Writing Count Value
Reading TRBPRE and TRBTR reads count values from each register.
If a write is performed to TRBPRE or TRBTR when the counting is stopped, a specified value is
written to both the reload register and the counter.
If a write is performed to TRBPRE during counting when TWRC in TRBMR is 0, first a set value
is written to the reload register, and the set value is then transferred to the prescaler counter in
synchronization with the count source. If a write is performed to TRBPR, a set value is written to
the reload register in synchronization with the underflow of the prescaler after four cycles of the
count source of the prescaler, and the set value is transferred to the timer counter in
synchronization with the next underflow of the prescaler.
For this reason, if a write is performed to TRBPRE or TRBPR during counting when TWRC is 1,
the value is written only to the reload register. Loading to the counter is performed in
synchronization with the underflow of the prescaler or timer counter.
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Section 14 Timer RB
14.3.2
Programmable Waveform Generation Mode
This mode alternately reloads and counts values of TRBPR and TRBSC, and produces toggle
output from the TRBO pin each time the counter underflows. At the start of counting, this mode
counts beginning with the value assigned to TRBPR. TRBOCR is not used when programmable
waveform generation mode is used.
(1)
Starting and Stopping Operation
Writing the value 1 to the TSTART bit in TRBCR starts counting; writing the value 0 to the
TSTART bit stops the counting.
(2)
Forced Termination of Operation
Writing 1 to the TSTOP bit in TRBCR stops the counting forcedly. When the counting is forcedly
stopped, the timer RB counter, the prescaler counter, and any associated flags are initialized.
(3)
Interrupt Request
An interrupt request is generated on the underflow of the timer RB counter during the secondary
period counting.
(4)
Reading and Writing Count Value
Reading TRBPRE and TRBTR reads count values from each register.
If a write is performed to TRBPRE, TRBPR, or TRBSC when counting is stopped, set values are
written to both the reload register and the counter.
If a write is performed to TRBPRE, TRBPR, or TRBSC when counting is in progress, data is
written only to the respective reload registers. The output of a waveform reflects a set value
beginning with the next primary period after data is written to TRBPR.
However, if writing to TRBSC or TRBPR proceeds when the value of the counter is H'00,
updating of the waveform will be suspended for one cycle.
Rev. 1.00 Oct. 03, 2008 Page 426 of 962
REJ09B0465-0100
Section 14 Timer RB
Figure 14.2 shows an operation example of the timer RB in programmable waveform generation
mode.
Set to 1 by a program.
TSTART in TRBCR
"1"
"0"
Count source
Timer RB prescaler
underflow signal
Timer RB
secondary reload
Timer RB counter
H'01
H'00
H'02
Timer RB
primary reload
H'01
H'00
H'01
H'00
H'02
Set to 0 by a program.
TRBIF in TRBIR
"1"
"0"
Set to 0 by a program
TOPL in TRBIOC
"1"
"0"
Waveform output is started. Waveform output is inverted.
Waveform output is started
"1"
TRBO pin output
"0"
Primary period
Secondary period
Primary period
Conditions for the above operation:
TRBPRE=H'01, TRBPR=H'01, TRBSC=H'02
TOCNT = 0 in TRBIOC (Timer RB waveform is output from the TRBO pin.)
Figure 14.2 Operation in Programmable Waveform Generation Mode
Rev. 1.00 Oct. 03, 2008 Page 427 of 962
REJ09B0465-0100
Section 14 Timer RB
14.3.3
Programmable One-Shot Generation Mode
This mode outputs one-shot pulses from the TRBO pin, based on either program or external
trigger input. When a trigger is generated, beginning with that point in time the timer operates
only once for any length of time specified in TRBPR. TRBSC is not used in this mode. In this
mode, TRBPRE or TRBPR should not be set to H'00.
(1)
Starting and Stopping Operation
The counting is started when 1 is written to the TOSST bit in TRBOCR or a valid trigger signal is
input to the TRGB pin after the TSTART bit in TRBCR is set to 1 and the TCSTF flag is set to 1.
For a trigger input, the pulse must be longer than one cycle of the clock source for counting.
The counting is stopped when reloading is performed with an underflow of the counter, when 1 is
written to the TOSSP bit in TRBOCR, or when 0 is written to the TSTART bit in TRBCR.
(2)
Forced Termination of Operation
Writing 1 to the TSTOP bit in TRBCR stops the counting forcedly. When the counting is forcedly
stopped, the timer RB counter, the prescaler counter, and any associated flags are initialized.
(3)
Interrupt Request
An interrupt request is generated on the underflow of the timer RB counter.
(4)
Reading and Writing Count Value
Reading TRBPRE and TRBTR reads count values from each register.
If a write is performed to TRBPRE or TRBPR when counting is stopped, set values are written to
both the reload register and the counter.
If a write is performed to TRBPRE or TRBPR during counting, data is written only to the
respective reload registers. The value written to TRBPRE takes effect in synchronization with the
underflow of the prescaler. The value written to TRBPR takes effect during the next one-shot
pulse.
Figure 14.3 shows an operation example of the timer RB in programmable one-shot generation
mode.
Rev. 1.00 Oct. 03, 2008 Page 428 of 962
REJ09B0465-0100
Section 14 Timer RB
Set to 1 by a program.
"1"
TSTART
in TRBCR
"0"
Write 1 to TOSST in
TRBOCR.
Change to 0 at the
end of counting.
Change to 1 by the
TRGB pin input trigger.
TOSSTF
in TRBOCR
TRGB pin
Count source
Timer RB prescaler
underflow signal
Start of counting
Timer RB counter
H'01
Timer RB primary
reload
H'00
Start of counting
H'01
Timer RB primary
reload
H'00
H'01
Set to 0 by a program.
TRBIF in TRBIOC
"1"
"0"
Set to 0 by a program.
TOPL in TRBIOC "1"
"0"
Start of waveform output
End of waveform output
Start of waveform output
End of waveform output
"1"
TRBO pin
"0"
Conditions for the above operation:
TRBPRE = H'01, TRBPR=H'01
TOPL = 0 and TOCNT = 0 in TRBIOC
INOSTG = 1 (TRBG pin one-shot trigger function is enabled)
INOSEG = 1 (Rising edge trigger)
Figure 14.3 Operation in Programmable One-Shot Generation Mode
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REJ09B0465-0100
Section 14 Timer RB
14.3.4
Programmable Wait One-Shot Generation Mode
This mode outputs one-shot pulses from the TRBO pin after a fixed amount of time based on
either program or external trigger input. When a trigger is generated, beginning with that point in
time, pulses are output only once for any length of time set in TRBSC, after any length of time set
in TRBPR.
(1)
Starting and Stopping Operation
The counting is started when 1 is written to the TOSST bit in TRBOCR or a valid trigger signal is
input to the TRGB pin after the TSTART bit in TRBCR is set to 1 and the TCSTF flag is set to 1.
For a trigger input, the pulse must be longer than one cycle of the clock source for counting.
The counting is stopped when reloading is performed with an underflow of the timer RB counter
during the secondary period counting , when 1 is written to the TOSSP bit in TRBOCR, or when 0
is written to the TSTART bit in TRBMR.
(2)
Forced Termination of Operation
Writing 1 to the TSTOP bit in TRBCR stops the counting forcedly. When the counting is forcedly
stopped, the timer RB counter, the prescaler counter, and any associated flags are initialized.
(3)
Interrupt Request
An interrupt request is generated on the underflow of the timer RB counter during the secondary
period counting.
(4)
Reading and Writing Count Value
Reading TRBPRE and TRBTR reads count values from each register.
If a write is performed to TRBPRE, TRBPR, or TRBSC when counting is stopped, set values are
written to both the reload register and the counter.
If a write is performed to TRBPRE, TRBPR, or TRBSC during counting, data is written only to
the respective reload registers. The value written to TRBPRE takes effect in synchronization with
the underflow of the prescaler. The value written to TRBPR takes effect during the next one-shot
pulse.
After writing to TRBSC and TRBPR when TCSTF = 1 or TOSSTF = 0, if a write is successively
performed to TRBSC and then to TRBPR, allow an interval of 5 cycles of the clock source for
counting before writing 1 to the TOSST bit.
In this mode, TRBPRE or TRBPR should not be set to H'00.
Rev. 1.00 Oct. 03, 2008 Page 430 of 962
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Section 14 Timer RB
Figure 14.4 shows an operation example of the timer RB in programmable wait one-shot
generation mode.
Set to 1 by a program.
TSTART in
TRBCR
"1"
"0"
Change to 1 by writing 1 to TOSST in
TRBOCR or by the TRGB pin input trigger.
TOSSTF in
TRBOCR
Change to 0 at the
end of counting.
"1"
"0"
TRGB input pin
Count source
Timer RB prescaler
underflow signal
Start of counting Timer RB secondary
reload
Timer RB counter
H'01
H'00
H'04
Timer RB primary
reload
H'03
H'02
H'01
H'00
01h
Set to 0 by a program.
TRBIF in TRBIR
"1"
"0"
Set to 0 by a program.
TOPL in TRBIOC
"1"
"0"
Start of waiting
Start of waveform output
End of waveform output
"1"
TRBO pin output
"0"
Conditions for the above operation:
TRBPRE = H'01, TRBPR = H'01, TRBSC = H'04
INOSTG = 1 (TRGB one-shot trigger function is enabled.)
INOSEG = 1 (Rising edge trigger)
Figure 14.4 Operation in Programmable Wait One-Shot Generation Mode
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REJ09B0465-0100
Section 14 Timer RB
14.3.5
Timing at Which Values Take Effect in Prescaler or Counter Depending on TWRC
Bit
Depending on the value assigned to the TWRC bit in TRBMR, the timing at which the value
written to TRBPRE, TRBPR, or TRBSC during timer operation takes effect in the counter can
vary.
If TWRC is set to 1 and value is written only to the register, the counter value is updated between
cycles, thus preventing the occurrence of fractional cycles. In modes other than the timer mode,
TWRC should be set to 1.
Figure 14.5 shows operation examples on the prescaler and the counter when the value of TWRC
is 0 and 1.
If TCSTF is 1, even when TWRC is cleared to 0, any transfer to the prescaler or the counter is
performed in synchronization with the count source; therefore, the counter value is not updated
immediately after the execution of a write instruction.
Rev. 1.00 Oct. 03, 2008 Page 432 of 962
REJ09B0465-0100
Section 14 Timer RB
(1) TWRC=0
Write H'01 to TRBPRE and
H'25 to TRBPR by program.
Count source
After a writing, data are written to the reload register
after 4 cycles of the source for counting have elapsed.
Reload register of
timer RB prescaler
Previous value
Counter of
timer RB prescaler H'06
New value (H'01)
Reloaded at
the second
count source
H'05
H'04
H'03
H'02
H'01
H'01
Reloaded on
underflow
H'00 H'01
Underflow of
timer RB prescaler
H'00 H'01
H'00
H'01 H'00
Reload register is written to
at the first underflow after a write.
TRBPR
Previous value
New value (H'25)
Reloaded at the second underflow
of prescaler
Counter of timer RB
H'25
H'03
H'24
(2) TWRC=1
Write H'01 to TRBPRE and
H'25 to TRBPR by program.
Count source
After a writing, data are written to the reload register
after 4 cycles of the source for counting have elapsed.
Reload register of
timer RB prescaler
Counter of
H'06
timer RB prescaler
H'05
H'04
H'03
Underflow of
timer RB prescaler
TRBPR
New value (H'01)
Previous value
Reloaded on
underflow
Reloaded at the second
count source
H'02
H'01
H'00
H'01
H'00
H'01
H'00
H'01
H'00
H'01
H'00
Reload register is written to
at the first underflow after a write.
Previous value
New value (H'25)
Reloaded at
underflow
of prescaler
Counter of timer RB
H'03
H'02
H'01
H'00
H'25
Figure 14.5 TWRC Settings and Operation of Prescaler and Counter
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REJ09B0465-0100
Section 14 Timer RB
14.3.6
TOCNT Settings and Pin State Update Conditions
Depending on the TOCNT bit in TRBIOC and the corresponding bit in PMR, the user can select
whether the pin is used as a general I/O port or as a specific timer waveform output. In the case of
timer mode, however, the pin operates as a general I/O port, irrespective of TOCNT bit settings.
When the TOCNT bit is rewritten, the pin state is not updated immediately; the change takes
effect when either of the following conditions occurs:
Pin state update conditions:
• When the TSTART bit in TRBCR is changed from 0 to 1
• When TRBPR is reloaded to the counter
Rev. 1.00 Oct. 03, 2008 Page 434 of 962
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Section 14 Timer RB
14.3.7
Operation through an Event Link
Using the event link controller (ELC), timer RB can be made to operate in the following ways in
relation to events occurring in other modules.
(1)
Starting Counter Operation
The start of counting operations by timer RB can be selected by the ELOPA register of the ELC.
When the event specified in ELSR1 occurs, the TSTART bit in the TRBCR is set to 1, which
starts counting by timer RB. However, if the specified event occurs when the TCSTF flag has
already been set to 1, that event is not effective.
(2)
Counting Events
The counting of events by timer RB can be selected by the ELOPA register of the ELC. When the
event specified in ELSR1 occurs, event counter operation proceeds with that event as the source to
drive counting, regardless of the setting in TRBMR. When event-counter operation is to be
employed, set the TSTART bit in TRBCR to 1 beforehand. When the value of the counter is read,
the value read out is the actual number of input events minus three.
14.4
Interrupt Request
This module provides a timer RB interrupt enable bit (the TRBIE bit in TRBIR) and a timer RB
interrupt request flag (the TRBIF bit in TRBIR). An interrupt request is issued to the CPU when
the TRBIE bit is set to 1 while the TRBIF bit is 1, or when the TRBIE bit changes from 0 to 1
while the TRBIF bit is 1. Since the condition under which the TRBIF bit is set varies with
operation modes, see the explanation on the TRBIF bit and the description of the various operation
modes.
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Section 14 Timer RB
14.5
Usage Notes
1. In programmable one-shot generation mode and programmable wait one-shot generation
mode, if the counting is stopped by clearing the TSTART bit in TRBCR to 0, the timer counter
holds a count value, and then stops.
2. After 1 is written to the TSTART bit when the counting is stopped, the TCSTF bit remains 0
for the number of cycles of the count source. The timer RB related registers*, with the
exception of the TRBCR for reading should not be accessed until the TCSTF bit is set to 1.
After 0 is written to the TSTART bit during counting, the TCSTF bit remains 1 for the number
of cycles of the count source. The timer RB related registers*, with the exception of the
TRBCR for reading should not be accessed until the TCSTF bit is cleared to 0.
Note: Timer RB-related registers refer to registers TRBCR, TRBOCR, TRBIOC, TRBMR,
TRBPRE, TRBSC, and TRBPR.
3. TRBPRE and TRBPR should not be set to H'00 at the same time.
4. When rewriting the bits TRBPRE, TRBPR, and TRBSC at TSTART = 0, set TSTART to 1
after the passage of at least φ2-cycle of the system clock.
5. When TSTART = 1 or TCSTF = 1, TRBIOC, or TRBMR should not be rewritten.
6. When writing 1 to the TOSST bit, read the TCSTF bit and write by verifying the value 1.
7. In programmable waveform generation mode or programmable wait one-shot mode, make sure
another write to TRBSC does not occur between writing to TRBPR and reloading to the
counter.
8. When writing successively to TRBPRE during counting (TCSTF=1), allow a minimum write
interval of 4 cycles of count source.
9. When writing successively to TRBPR and TRBSC during counting (TCSTF=1), allow a
minimum write interval of 4 cycles of count source.
10. When 1 is written to the TOSST or TOSSP bit in TRBOCR, the value of the TOSSTF bit
changes accordingly after 1 to 2 cycles of the source for counting. If 1 is written to the TOSSP
bit during the period between the TOSST bit having been set to 1 and the value of the TOSSTF
bit becoming 1, the value of the TOSSTF bit will become 0 in some cases and 1 in others,
depending on the internal state. In the same way, if 1 is written to the TOSST bit during the
period between the TOSSP bit having been set to 1 and the value of the TOSSTF bit becoming
0, whether the value of the TOSSTF bit will become 0 or 1 is not defined.
Rev. 1.00 Oct. 03, 2008 Page 436 of 962
REJ09B0465-0100
Section 15 Timer RC
Section 15 Timer RC
Timer RC is a 16-bit timer having output compare and input capture functions. Timer RC can
count external events and output pulses with a desired duty cycle using the compare match
function between the timer counter and four general registers. Thus, it can be applied to various
systems.
Note: Timer RC is not supported in H8S/20223 and H8S/20203 groups.
15.1
Features
• Selection of seven counter clock sources
Six internal clocks (φ, φ/2, φ/4, φ/8, φ/32, and φ40) and an external clock (for counting external
events)
• Capability to process up to four pulse outputs or four pulse inputs
• Four general registers
Can be used as output compare or input capture registers independently
Can be used as buffer registers for the output compare or input capture registers
• Timer inputs and outputs
 Timer mode
Output compare function (Selection of 0 output, 1 output, or toggle output)
Input capture function (Rising edge, falling edge, or both edges can be detected.)
Counter clearing function (Counter cycle can be set.)
 PWM mode
Generates up to three-phase PWM output.
 PWM2 mode
Generates pulses with a desired period and duty cycle.
• Any initial timer output value can be set
• Five interrupt sources
Four compare match/input capture interrupts and an overflow interrupt.
Rev. 1.00 Oct. 03, 2008 Page 437 of 962
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Section 15 Timer RC
Table 15.1 summarizes the timer RC functions, and figure 15.1 shows a block diagram of timer
RC.
Table 15.1 Timer RC Functions
Input/Output Pins
Item
Counter
FTIOA
Count clock
Internal clocks: φ, φ/2, φ/4, φ/8, φ/32, and φ40
External clock: FTCI
General registers
(output compare/input
capture registers)
Period
GRA
specified in
GRA
GRB
GRC (buffer
register for
GRA in
buffer mode)
GRD (buffer
register for
GRB in
buffer mode)
Counter clearing function
GRA input
capture/
compare
match



GRA input
capture/
compare
match
FTIOB
FTIOC
FTIOD
TGRC input 



Initial output value
setting function

Yes
Yes
Yes
Yes
Buffer function

Yes
Yes


0 output

Yes
Yes
Yes
Yes
1 output

Yes
Yes
Yes
Yes
Toggle
output

Yes
Yes
Yes
Yes
Input capture function

Yes
Yes
Yes
Yes
PWM mode


Yes
Yes
Yes
PWM2 mode


Yes


Interrupt sources
Overflow
Compare
match/input
capture
Compare
match/input
capture
Compare
match/input
capture
Compare
match/input
capture
Compare
match output
Rev. 1.00 Oct. 03, 2008 Page 438 of 962
REJ09B0465-0100
Section 15 Timer RC
Internal clock: φ
φ/2
φ/4
φ/8
φ/32
φ40
External clock: FTCI
FTIOA/TRGC
Clock selection
FTIOB
Control logic
FTIOC
FTIOD
Comparator
TRCOI
OVF
IMFA
IMFB
IMFC
Internal data bus
Bus interface
TRCADCR
TRCDF
TRCOER
TRCIOR1
TRCIOR0
TRCSR
TRCIER
TRCCR2
TRCCR1
TRCMR
GRD
GRC
GRB
GRA
TRCCNT
IMFD
Figure 15.1 Timer RC Block Diagram
Table 15.2 summarizes the timer RC pins.
Table 15.2 Pin Configuration
Pin Name
Input/
Output
Function
FTCI
Input
External clock input pin
FTIOA/TRGC
I/O
Output pin for GRA output compare/input pin for GRA input capture/
external trigger input pin (TRGC)
FTIOB
I/O
Output pin for GRB output compare/input pin for GRB input capture/
PWM output pin in PWM mode
FTIOC
I/O
Output pin for GRC output compare/input pin for GRC input capture/
PWM output pin in PWM mode
FTIOD
I/O
Output pin for GRD output compare/input pin for GRD input capture/
PWM output pin in PWM mode
TRCOI
Input
Input pin for timer output disabling signal
Rev. 1.00 Oct. 03, 2008 Page 439 of 962
REJ09B0465-0100
Section 15 Timer RC
15.2
Register Descriptions
The timer RC has the following registers.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Timer RC mode register (TRCMR)
Timer RC control register 1 (TRCCR1)
Timer RC control register 2 (TRCCR2)
Timer RC interrupt enable register (TRCIER)
Timer RC status register (TRCSR)
Timer RC I/O control register 0 (TRCIOR0)
Timer RC I/O control register 1 (TRCIOR1)
Timer RC output enable register (TRCOER)
Timer RC digital filtering function select register (TRCDF)
Timer RC A/D conversion start trigger control register (TRCADCR)
Timer RC counter (TRCCNT)
General register A (GRA)
General register B (GRB)
General register C (GRC)
General register D (GRD)
Rev. 1.00 Oct. 03, 2008 Page 440 of 962
REJ09B0465-0100
Section 15 Timer RC
15.2.1
Timer RC Mode Register (TRCMR)
Address: H'FFFF8A
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
CTS

BUFEB
BUFEA
PWM2
PWMD
PWMC
PWMB
0
1
0
0
1
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
CTS
Counter start
0: TRCCNT stops counting.
R/W
1: TRCCNT starts counting.
[Setting conditions]
•
When 1 is written in CTS
•
When the specified event is occurred after
ELOPA of the event link controller is selected
counting by timer RC.
[Clearing conditions]
•
When 0 is written in CTS
•
In PWM2 mode, when the CSTP bit in TRCCR2
is set to 1 and a compare match signal is
generated.
6

Reserved
This bit is read as 1. The write value should be 1.

5
BUFEB
Buffer
operation B
0: GRD functions as an input capture/output
compare register
R/W
1: GRD functions as the buffer register for GRB
4
BUFEA
Buffer
operation A
0: GRC functions as an input capture/output
compare register
R/W
1: GRC functions as the buffer register for GRA
3
PWM2
PWM2 mode
0: Timer RC functions in PWM2 mode.
R/W
The following settings are invalid: TRCIOR0,
TRCIOR1, and the PWMB, PWMC, and PWMD
bits in TRCMR.
1: Timer RC functions in timer mode or PWM mode.
The following settings are valid: TRCIOR0,
TRCIOR1, and the PWMB, PWMC, and PWMD
bits in TRCMR.
Rev. 1.00 Oct. 03, 2008 Page 441 of 962
REJ09B0465-0100
Section 15 Timer RC
Bit
Symbol
Bit Name
Description
R/W
2
PWMD
PWM mode D Selects the output mode of the FTIOD pin.
R/W
0: Functions in timer mode
1: Functions in PWM mode
1
PWMC
PWM mode C Selects the output mode of the FTIOC pin.
R/W
0: Functions in timer mode
1: Functions in PWM mode
0
PWMB
PWM mode B Selects the output mode of the FTIOB pin.
R/W
0: Functions in timer mode
1: Functions in PWM mode
15.2.2
Timer RC Control Register 1 (TRCCR1)
Address: H'FFFF8B
Bit:
b7
b6
CCLR
Value after reset:
0
b5
b4
CKS[2:0]
0
0
0
b3
b2
b1
b0
TOD
TOC
TOB
TOA
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
CCLR
Counter clear 0: TRCCNT functions as a free-running counter.
R/W
1: The TRCCNT value is cleared by
input capture A/compare match A.
6 to 4
CKS[2:0]*3
Clock select
2 to 0
Select the source of the clock input to TRCCNT.
000: TRCCNT counts the internal clock φ.
001: TRCCNT counts the internal clock φ/2.
010: TRCCNT counts the internal clock φ/4.
011: TRCCNT counts the internal clock φ/8.
100: TRCCNT counts the internal clock φ/32.
101: TRCCNT counts the rising edge of the
external event (FTCI).
110: TRCCNT counts the internal clock φ40.*
1
111: Reserved (setting prohibited)
Rev. 1.00 Oct. 03, 2008 Page 442 of 962
REJ09B0465-0100
R/W
Section 15 Timer RC
Bit
Symbol
Bit Name
Description
R/W
2
3
TOD
Timer output 0: Output value is 0* .
level setting D 1: Output value is 1*2.
R/W
2
TOC
Timer output 0: Output value is 0*2.
level setting C 1: Output value is 1*2.
R/W
1
TOB
Timer output 0: Output value is 0*2.
level setting B 1: Output value is 1*2.
R/W
0
TOA
Timer output 0: Output value is 0*2.
level setting A 1: Output value is 1*2.
R/W
Notes: 1. If the internal φ/40 clock is selected, the high-speed on-chip oscillator must be
operating. As long as the internal φ40 clock is selected, do not stop the high-speed onchip oscillator. Restrictions on access to registers are applied when the internal φ/40
clock is selected. For details, see 6 in section 15.5, Usage Notes. 6.
2. The change of the setting is immediately reflected in the output value.
3. When the counter clock is switched over, the counter should be halted.
• TOD bit (timer output level setting D)
Sets the output value of the FTIOD pin until the first compare match D is generated. In PWM
mode, controls the output polarity of the FTIOD pin.
• TOC bit (timer output level setting C)
Sets the output value of the FTIOC pin until the first compare match C is generated. In PWM
mode, controls the output polarity of the FTIOC pin.
• TOB bit (timer output level setting B)
Sets the output value of the FTIOB pin until the first compare match B is generated. In PWM
mode, controls the output polarity of the FTIOB pin.
• TOA bit (timer output level setting A)
Sets the output value of the FTIOA pin until the first compare match A is generated. In PWM
mode, controls the output polarity of the FTIOA pin.
Rev. 1.00 Oct. 03, 2008 Page 443 of 962
REJ09B0465-0100
Section 15 Timer RC
15.2.3
Timer RC Control Register 2 (TRCCR2)
Address: H'FFFF90
Bit:
b7
TCEG[1:0]
Value after reset:
0
b5
b4
b3
b2
b1
b0
CSTP


POLD
POLC
POLB
0
1
1
0
0
0
b6
0
Bit
Symbol
Bit Name
7, 6
TCEG[1:0] TRGC input edge
select
Description
R/W
00: A trigger input on TRGC is disabled.
R/W
01: The rising edge is selected.
10: The falling edge is selected.
11: Both edges are selected.
5
CSTP
Count stop
0: TRCCNT counting up continues.
R/W
1: TRCCNT counting up is halted.
4, 3

Reserved
These bits are read as 1. The write value should
be 1.

2
POLD
PWM mode output
level control D
0: The TRCIOD output is active low.
R/W
1
POLC
PWM mode output
level control C
0: The TRCIOC output is active low.
PWM mode output
level control B
0: The TRCIOB output is active low.
0
POLB
1: The TRCIOD output is active high.
R/W
1: The TRCIOC output is active high.
R/W
1: The TRCIOB output is active high.
• TCEG[1:0] bits (TRGC input edge select)
These bits select the input edge of the TRGC signal. This function is only enabled when the
PWM2 bit in TRCMR is set to 0.
• CSTP bit (count stop)
Specifies whether TRCCNT counting up is halted by the compare match A signal. This
function is enabled in all operating modes. To resume counting after counting has been
stopped on a compare match, set the CTS bit in the timer RC mode register (TRCMR) to 1.
Rev. 1.00 Oct. 03, 2008 Page 444 of 962
REJ09B0465-0100
Section 15 Timer RC
15.2.4
Timer RC Interrupt Enable Register (TRCIER)
Address: H'FFFF8C
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
OVIE



IMIED
IMIEC
IMIEB
IMIEA
0
1
1
1
0
0
0
0
Value after reset:
Bit
Symbol
Bit Name
Description
R/W
7
OVIE
Timer overflow 0: An interrupt (FOVI) requested by the OVF flag in R/W
interrupt
TRCSR is disabled.
enable
1: An interrupt (FOVI) requested by the OVF flag in
TRCSR is enabled.
6 to 4

Reserved
3
IMIED
Input capture/ 0: An interrupt (IMID) requested by the IMFD flag in R/W
compare
TRCSR is disabled.
match interrupt 1: An interrupt (IMID) requested by the IMFD flag in
enable D
TRCSR is enabled.
2
IMIEC
Input capture/ 0: An interrupt (IMIC) requested by the IMFC flag in R/W
compare
TRCSR is disabled.
match interrupt 1: An interrupt (IMIC) requested by the IMFC flag in
enable C
TRCSR is enabled.
1
IMIEB
Input capture/ 0: An interrupt (IMIB) requested by the IMFB flag in R/W
compare
TRCSR is disabled.
match interrupt 1: An interrupt (IMIB) requested by the IMFB flag in
enable B
TRCSR is enabled.
0
IMIEA
Input capture/ 0: An interrupt (IMIA) requested by the IMFA flag in R/W
compare
TRCSR is disabled.
match interrupt 1: An interrupt (IMIA) requested by the IMFA flag in
enable A
TRCSR is enabled.
These bits are read as 1. The write value should be 
1.
Rev. 1.00 Oct. 03, 2008 Page 445 of 962
REJ09B0465-0100
Section 15 Timer RC
15.2.5
Timer RC Status Register (TRCSR)
Address: H'FFFF8D
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
OVF



IMFD
IMFC
IMFB
IMFA
Value after reset:
0
1
1
1
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
OVF
Timer overflow flag 0: TRCCNT has not overflowed.
R/W
1: TRCCNT has overflowed.
[Setting condition]
•
When TRCCNT overflows from H'FFFF to
H'0000.
[Clearing condition]
•
Read OVF when OVF = 1, then write 0 in OVF.
6 to 4

Reserved
These bits are read as 1. The write value should
be 1.

3
IMFD
Input capture/
compare match
flag D
[Setting conditions]
R/W
•
TRCCNT = GRD when GRD functions as an
output compare register.
•
The TRCCNT value is transferred to GRD by
an input capture signal when GRD functions as
an input capture register.
•
TRCCNT = GRD when the PWMD bit is set to
1 or the PWM2 bit to 0 in TRCMR.
[Clearing conditions]
Rev. 1.00 Oct. 03, 2008 Page 446 of 962
REJ09B0465-0100
•
Read IMFD when IMFD = 1, then write 0 in
IMFD.
•
The DTC is activated by an IMFD interrupt and
the DISEL bit in MRB of DTC is 0.
Section 15 Timer RC
Bit
Symbol
Bit Name
Description
R/W
2
IMFC
Input capture/
compare match
flag C
[Setting conditions]
R/W
•
TRCCNT = GRC when GRC functions as an
output compare register.
•
The TRCCNT value is transferred to GRC by
an input capture signal when GRC functions as
an input capture register.
•
TRCCNT = GRC when the PWMC bit is set to
1 or the PWM2 bit to 0 in TRCMR.
[Clearing conditions]
1
IMFB
Input capture/
compare match
flag B
•
Read IMFC when IMFC = 1, then write 0 in
IMFC.
•
The DTC is activated by an IMFC interrupt
when the DISEL bit in MRB of DTC is 0.
[Setting conditions]
R/W
•
TRCCNT = GRB when GRB functions as an
output compare register.
•
The TRCCNT value is transferred to GRB by
an input capture signal when GRB functions as
an input capture register.
•
TRCCNT = GRB when the PWMB bit is set to
1 or the PWM2 bit to 0 in TRCMR.
[Clearing conditions]
•
Read IMFB when IMFB = 1, then write 0 in
IMFB.
•
The DTC is activated by an IMFB interrupt
when the DISEL bit in MRB of DTC is 0.
Rev. 1.00 Oct. 03, 2008 Page 447 of 962
REJ09B0465-0100
Section 15 Timer RC
Bit
Symbol
Bit Name
Description
R/W
0
IMFA
Input capture/
compare match
flag A
[Setting conditions]
R/W
•
TRCCNT = GRA when GRA functions as an
output compare register.
•
The TRCCNT value is transferred to GRA by
an input capture signal when GRA functions as
an input capture register.
[Clearing condition]
•
Read IMFA when IMFA = 1, then write 0 in
IMFA.
The DTC is activated by an IMFA interrupt when
the DISEL bit in MRB of DTC is 0.
Rev. 1.00 Oct. 03, 2008 Page 448 of 962
REJ09B0465-0100
Section 15 Timer RC
15.2.6
Timer RC I/O Control Register 0 (TRCIOR0)
Address: H'FFFF8E
Bit:
Value after reset:
b7
b6

IOB2
1
0
b5
b4
IOB[1:0]
0
0
b3
b2

IOA2
1
0
b1
b0
IOA[1:0]
0
0
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is read as 1. The write value should be 1.

6
IOB2
I/O control B2 Selects the GRB function.
R/W
0: GRB functions as an output compare register
1: GRB functions as an input capture register
5, 4
IOB[1:0]
I/O control B1 When IOB2 = 0,
and B0
00: No output on compare match
R/W
01: 0 output to the FTIOB pin on compare match of
GRB
10: 1 output to the FTIOB pin on compare match of
GRB
11: Toggle output to the FTIOB pin on compare
match of GRB
When IOB2 = 1,
00: Input capture to GRB at rising edge at the FTIOB
pin
01: Input capture to GRB at falling edge at the FTIOB
pin
1X: Input capture to GRB at rising and falling edges
of the FTIOB pin
3

Reserved
2
IOA2
I/O control A2 Selects the GRA function.
This bit is read as 1. The write value should be 1.

R/W
0: GRA functions as an output compare register
1: GRA functions as an input capture register
Rev. 1.00 Oct. 03, 2008 Page 449 of 962
REJ09B0465-0100
Section 15 Timer RC
Bit
Symbol
Bit Name
Description
1, 0
IOA[1:0]
I/O control A1 When IOA2 = 0,
and A0
00: No output on compare match
R/W
R/W
01: 0 output to the FTIOA pin on compare match of
GRA
10: 1 output to the FTIOA pin on compare match of
GRA
11: Toggle output to the FTIOA pin on compare
match of GRA
When IOA2 = 1,
00: Input capture to GRA at rising edge of the FTIOA
pin
01: Input capture to GRA at falling edge of the FTIOA
pin
1X: Input capture to GRA at rising and falling edges
of the FTIOA pin
[Legend]
X:
Don't care.
Notes: 1. When a GR register functions as a buffer register for a paired GR register, the settings
in the IOA2 and IOB2 bits in TRCIOR0 and the IOC2 and IOD2 bits in TRCIOR1 of both
registers should be the same.
2. The setting of TRCIOR is invalid in PWM mode and PWM2 mode.
TRCIOR0 selects the functions of GRA and GRB, and specifies the functions of the FTIOA and
FTIOB pins.
Rev. 1.00 Oct. 03, 2008 Page 450 of 962
REJ09B0465-0100
Section 15 Timer RC
15.2.7
Timer RC I/O Control Register 1 (TRCIOR1)
Address: H'FFFF8F
Bit:
Value after reset:
b7
b6
IOD3
IOD2
1
0
b5
b4
IOD[1:0]
0
0
b3
b2
IOC3
IOC2
1
0
Bit
Symbol
Bit Name
7
IOD3
I/O control D3 0: GRD is used as GR for the FTIOB pin
b1
b0
IOC[1:0]
0
Description
0
R/W

1: GRD is used as GR for the FTIOD pin
6
IOD2
I/O control D2 0: GRD functions as an output compare register
R/W
1: GRD functions as an input capture register
5, 4
IOD[1:0]
I/O control D1 When IOD3 = 0,
and D0
00: No output on compare match
R/W
01: 0 output to the FTIOB pin on compare match of
GRD
10: 1 output to the FTIOB pin on compare match of
GRD
11: Toggle output to the FTIOB pin on compare
match of GRD
When IOD3 = 1 and IOD2 = 0,
00: No output on compare match
01: 0 output to the FTIOD pin on compare match of
GRD
10: 1 output to the FTIOD pin on compare match of
GRD
11: Toggle output to the FTIOD pin on compare
match of GRD
When IOD3 = 1 and IOD2 = 1,
00: Input capture to GRD at rising edge of the FTIOD
pin
01: Input capture to GRD at falling edge of the
FTIOD pin
1X: Input capture to GRD at rising and falling edges
of the FTIOD pin
Rev. 1.00 Oct. 03, 2008 Page 451 of 962
REJ09B0465-0100
Section 15 Timer RC
Bit
Symbol
Bit Name
Description
R/W
3
IOC3
I/O control C3
0: GRC is used as GR for the FTIOA pin
R/W
1: GRC is used as GR for the FTIOC pin
2
IOC2
I/O control C2
0: GRC functions as an output compare register
R/W
1: GRC functions as an input capture register
1, 0
IOC[1:0]
I/O control C1
and C0
When IOC3 = 0,
R/W
00: No output on compare match
01: 0 output to the FTIOA pin on compare match of
GRC
10: 1 output to the FTIOA pin on compare match of
GRC
11: Toggle output to the FTIOA pin on compare
match of GRC
When IOC3 = 1 and IOC2 = 0,
00: No output on compare match
01: 0 output to the FTIOC pin on compare match of
GRC
10: 1 output to the FTIOC pin on compare match of
GRC
11: Toggle output to the FTIOC pin on compare
match of GRC
When IOC3 = 1 and IOC2 = 1,
00: Input capture to GRC at rising edge of the
FTIOC pin
01: Input capture to GRC at falling edge of the
FTIOC pin
1X: Input capture to GRC at rising and falling
edges of the FTIOC pin
[Legend]
X: Don't care.
Notes: 1. When a GR register functions as a buffer register for a paired GR register, the settings
in the IOA2 and IOB2 bits in TRCIOR0 and the IOC2 and IOD2 bits in TRCIOR1 of both
registers should be the same.
2. The setting of TRCIOR1 is invalid in PWM mode and PWM2 mode.
Rev. 1.00 Oct. 03, 2008 Page 452 of 962
REJ09B0465-0100
Section 15 Timer RC
15.2.8
Timer RC Output Enable Register (TRCOER)
Address: H'FFFF92
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
PTO



ED
EC
EB
EA
0
1
1
1
1
1
1
1
Bit
Symbol Bit Name
Description
7
PTO
0: The ED, EC, EB and EA bits are not set to 1 by R/W
the low level input of the TRCOI signal.
Timer output
disabled mode
R/W
1: The ED, EC, EB and EA bits are set to 1 by the
low level input of the TRCOI signal.
6 to 4

Reserved
These bits are read as 1. The write value should
be 1.

3
ED
Master enable D
0: The FTIOD output is enabled according to the
TRCMR and TRCIOR1 settings
R/W
1: The FTIOD output is disabled regardless of the
TRCMR and TRCIOR1 settings.
2
EC
Master enable C
0: The FTIOC output is enabled according to the
TRCMR and TRCIOR1 settings.
R/W
1: The FTIOC output is disabled regardless of the
TRCMR and TRCIOR1 settings.
1
EB
Master enable B
0: The FTIOB output is enabled according to the
TRCMR and TRCIOR0 settings
R/W
1: The FTIOB output is disabled regardless of the
TRCMR and TRCIOR0 settings.
0
EA
Master enable A
0: The FTIOA output is enabled according to the
TRCIOR0 settings
R/W
1: The FTIOA output is disabled regardless of the
TRCIOR0 settings.
TRCOER enables or disables the timer outputs. When setting the PTO bit to 1 and driving the
TRCOI signal low, the ED, EC, EB and EA bits are set to 1 and timer RC outputs are disabled.
Rev. 1.00 Oct. 03, 2008 Page 453 of 962
REJ09B0465-0100
Section 15 Timer RC
15.2.9
Timer RC Digital Filtering Function Select Register (TRCDF)
Address: H'FFFF91
Bit:
b7
b6
DFCK[1:0]
Value after reset:
0
0
b5
b4
b3
b2
b1
b0

DFTRG
DFD
DFC
DFB
DFA
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
7, 6
DFCK[1:0]
Digital filter clock These bits select the clock to be used by the
select
digital filter.
R/W
R/W
00: φ/32
01: φ/8
10: φ
11: Clock specified by bits CKS2 to CKS0 in
TRCCR1
5

Reserved
This bit is read as 0. The write value should be 0.

4
DFTRG
Digital filter
function trigger
pin
0: Disables the digital filter for the TRGC pin
R/W
Digital filter
function D
0: Disables the digital filter for the FTIOD pin
Digital filter
function C
0: Disables the digital filter for the FTIOC pin
3
2
DFD
DFC
1: Enables the digital filter for the TRGC pin
R/W
1: Enables the digital filter for the FTIOD pin
R/W
1: Enables the digital filter for the FTIOC pin
1
DFB
Digital filter
function B
0: Disables the digital filter for the FTIOB pin
0
DFA
Digital filter
function A
0: Disables the digital filter for the FTIOA pin
R/W
1: Enables the digital filter for the FTIOB pin
R/W
1: Enables the digital filter for the FTIOA pin
Note: The setting in this register is valid on the corresponding pin when the FTIOA to FTIOD
inputs are enabled by TRCIOR0 and TRCIOR1 and the TRGC input is selected by bits
TCEG1 and TCEG0 in TRCCR2.
Rev. 1.00 Oct. 03, 2008 Page 454 of 962
REJ09B0465-0100
Section 15 Timer RC
15.2.10 Timer RC A/D Conversion Start Trigger Control Register (TRCADCR)
Address: H'FFFF93
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0




ADTRGAE
ADTRGBE
ADTRGCE
ADTRGDE
1
1
1
1
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7 to 4

Reserved
These bits are read as 1. The write value should
be 1.

3
ADTRGAE A/D conversion
start trigger A
enable
0: A/D conversion start trigger is not generated by R/W
compare match of GRA
ADTRGBE A/D conversion
start trigger B
enable
0: A/D conversion start trigger is not generated by R/W
compare match of GRB
ADTRGCE A/D conversion
start trigger C
enable
0: A/D conversion start trigger is not generated by R/W
compare match of GRC
ADTRGDE A/D conversion
start trigger D
enable
0: A/D conversion start trigger is not generated by R/W
compare match of GRD
2
1
0
1: A/D conversion start trigger is generated by
compare match of GRA
1: A/D conversion start trigger is generated by
compare match of GRB
1: A/D conversion start trigger is generated by
compare match of GRC
1: A/D conversion start trigger is generated by
compare match of GRD
TRCADCR selects the trigger source to start A/D conversion. A/D conversion start trigger is
generated by a corresponding compare match.
Rev. 1.00 Oct. 03, 2008 Page 455 of 962
REJ09B0465-0100
Section 15 Timer RC
15.2.11 Timer RC Counter (TRCCNT)
Address: H'FFFF80
Bit:
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TRCCNT is a 16-bit readable/writable up-counter. The input clock is selected by bits CKS2 to
CKS0 in TRCCR1. TRCCNT can be cleared to H'0000 through a compare match of GRA by
setting the CCLR bit in TRCCR1 to 1. When TRCCNT overflows from H'FFFF to H'0000, the
OVF flag in TRCSR is set to 1. If the OVIE bit in TRCIER is set to 1 at this time, an interrupt
request is generated. TRCCNT must always be read from or written to in units of 16 bits; 8-bit
accesses are not allowed. The initial value of TRCCNT is H'0000.
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Section 15 Timer RC
15.2.12 General Registers A, B, C, and D (GRA, GRB, GRC, and GRD)
GRA
Address: H'FFFF82
Bit:
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GRB
Address: H'FFFF84
Bit:
Value after reset:
GRC
Address: H'FFFF86
Bit:
Value after reset:
GRD
Address: H'FFFF88
Bit:
Value after reset:
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Section 15 Timer RC
Each general register is a 16-bit readable/writable register that can function as either an outputcompare register or an input-capture register. The function is selected by settings in TRCIOR0 and
TRCIOR1.
When a general register is used as an input-compare register, its value is constantly compared with
the TRCCNT value. When the two values match (a compare match), the corresponding flag (the
IMFA, IMFB, IMFC, or IMFD bit) in TRCSR is set to 1. An interrupt request is generated at this
time, when the IMIEA, IMIEB, IMIEC, or IMIED bit in TRCIER is set to 1. A compare match
output can be selected in TRCIOR.
When a general register is used as an input-capture register, an external input-capture signal is
detected and the current TRCCNT value is stored in the general register. The corresponding flag
(the IMFA, IMFB, IMFC, or IMFD bit) in TRCSR is set to 1. If the corresponding interruptenable bit (the IMIEA, IMIEB, IMIEC, or IMIED bit) in TRIER is set to 1 at this time, an
interrupt request is generated. The edge of the input-capture signal is selected in TRCIOR.
GRC and GRD can be used as buffer registers of GRA and GRB, respectively, by setting BUFEA
and BUFEB in TRCMR.
For example, when GRA is set as an output-compare register and GRC is set as the buffer register
for GRA, the value in the buffer register GRC is sent to GRA whenever compare match A is
generated.
When GRA is set as an input-capture register and GRC is set as the buffer register for GRA, the
value in TRCCNT is transferred to GRA and the value in the buffer register GRA is transferred to
GRC whenever an input capture is generated.
GRA to GRD must be written or read in 16-bit units; 8-bit access is not allowed. GRA to GRD are
initialized to H'FFFF by a reset.
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Section 15 Timer RC
15.3
Operation
Timer RC has the following operating modes.
• Timer mode operation
Enables output compare and input capture functions by setting the IOA2 to IOA0 and IOB2 to
IOB0 bits in TRCIOR0 and the IOC3 to IOC0 and IOD3 to IOD0 bits in TRCIOR1.
• PWM mode operation
Enables PWM mode operation by setting the PWMD, PWMC, and PWMB bits in TRCMR.
• PWM2 mode operation
Enables PWM2 mode operation by setting the PWM2 bit in TRCMR.
The FTIOA to FTIOD pins indicate the timer output mode by each register setting. Set 1 to the
PMCR and PMR bits corresponding to the pins selected by the PMC.
Table 15.3 FTIOA Pin Functions
Register
Name
TRCOER
Bit Name
EA
PWM2
IOA2 to
IOA0
Setting
values
0
1
001, 01X
Timer mode waveform output (output compare
function)
X
1
1XX
Timer mode (input capture function)
X
1
000
General input port (when PCR = 0 on the
corresponding pin)
TRCMR
TRCIOR0
Other than above
Function
Setting prohibited
[Legend]
X:
Don't care.
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Section 15 Timer RC
Table 15.4 FTIOB Pin Functions
Register
Name
TRCOER
Bit Name
EB
PWM2
PWMB
IOB2 to
IOB0
Function
Setting
values
0
0
X
XXX
PWM2 mode waveform output
0
1
1
XXX
PWM mode waveform output
0
1
0
001, 01X
Timer mode waveform output (output
compare function)
X
1
0
1XX
Timer mode (input capture function)
X
1
0
000
General input port (when PCR = 0 on
the corresponding pin)
TRCMR
TRCIOR0
Other than above
Setting prohibited
[Legend]
X:
Don't care.
Table 15.5 FTIOC Pin Functions
Register
Name
TRCOER
Bit Name
EC
PWM2
PWMC
IOC2 to
IOC0
Function
Setting
values
0
1
1
XXX
PWM mode waveform output
0
1
0
001, 01X
Timer mode waveform output (output
compare function)
X
1
0
1XX
Timer mode (input capture function)
X
1
0
000
General input port (when PCR = 0 on
the corresponding pin)
TRCMR
Other than above
[Legend]
X:
Don't care.
Rev. 1.00 Oct. 03, 2008 Page 460 of 962
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TRCIOR1
Setting prohibited
Section 15 Timer RC
Table 15.6 FTIOD Pin Functions
Register
Name
TRCOER
Bit Name
ED
PWM2
PWMD
IOD2 to
IOD0
Function
Setting
values
0
1
1
XXX
PWM mode waveform output
0
1
0
001, 01X
Timer mode waveform output (output
compare function)
TRCMR
TRCIOR1
X
1
0
1XX
Timer mode (input capture function)
X
1
0
000
General input port (when PCR = 0 on
the corresponding pin)
Other than above
Setting prohibited
[Legend]
X:
Don't care.
15.3.1
Timer Mode Operation
TRCCNT performs free-running or periodic counting operations. After a reset, TRCCNT is set as
a free-running counter. When the CTS bit in TRCMR is set to 1, TRCCNT starts counting. When
the TRCCNT value overflows from H'FFFF to H'0000, the OVF flag in TRCSR is set to 1. If the
OVIE in TRCIER is set to 1, an interrupt request is generated. Figure 15.2 shows an example of
free-running counting.
TRCCNT
H'FFFF
H'0000
Time
CTS bit
Flag cleared
by software
OVF
Figure 15.2 Free-Running Counter Operation
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Section 15 Timer RC
Periodic counting operation can be performed when GRA is set as an output compare register and
the CCLR bit in TRCCR1 is set to 1. When the counter value matches GRA, TRCCNT is cleared
to H'0000, and the IMFA flag in TRCSR is set to 1. If the corresponding IMIEA bit in TRCIER is
set to 1, an interrupt request is generated. TRCCNT continues counting from H'0000. Figure 15.3
shows an example of periodic counting.
TRCCNT
GRA
H'0000
Time
CTS bit
Flag cleared
by software
IMFA
Figure 15.3 Periodic Counter Operation
By setting a general register as an output compare register, the specified level of a signal can be
output on the FTIOA, FTIOB, FTIOC, or FTIOD pin on compare match A, B, C, or D. The output
level can be selected from 0, 1, or toggle. Figure 15.4 shows an example of TRCCNT functioning
as a free-running counter. In this example, 1 is output on compare match A and 0 is output on
compare match B. When the signal level is already at the selected output level, it is not changed
on a compare match.
TRCCNT
H'FFFF
GRA
GRB
Time
H'0000
FTIOA
FTIOB
No change
No change
No change
No change
Figure 15.4 0 and 1 Output Example (TOA = 0, TOB = 1)
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Section 15 Timer RC
Figure 15.5 shows an example of toggled output when TRCCNT functions as a free-running
counter, and the toggled output is selected for both compare matches A and B.
TRCCNT
H'FFFF
GRA
GRB
Time
H'0000
FTIOA
Output toggled
FTIOB
Output toggled
Figure 15.5 Toggle Output Example (TOA = 0, TOB = 1)
Figure 15.6 shows another example of toggled output when TRCCNT functions as a periodic
counter on both compare matches A and B.
TRCCNT
Counter cleared by compare match of GRA
H'FFFF
GRA
GRB
H'0000
Time
FTIOA
Output
toggled
FTIOB
Output
toggled
Figure 15.6 Toggle Output Example (TOA = 0, TOB = 1)
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Section 15 Timer RC
The TRCCNT value can be captured into a general register (GRA, GRB, GRC, or GRD) when
signal levels are changed on an input-capture pin (FTIOA, FTIOB, FTIOC, or FTIOD) by
specifying the general register as an input capture register. The capture timing can be selected
from the rising, falling, or both edges. By using the input-capture function, the width or cycle of a
pulse can be measured. Figure 15.7 shows an example of an input capture when both edges of the
FTIOA signal and the falling edge of the FTIOB signal are selected as capture timings. TRCCNT
functions as a free-running counter.
TRCCNT
H'FFFF
H'F000
H'AA55
H'55AA
H'1000
H'0000
Time
FTIOA
GRA
H'1000
H'F000
FTIOB
GRB
H'AA55
Figure 15.7 Input Capture Operating Example
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H'55AA
Section 15 Timer RC
Figure 15.8 shows an example of buffer operation when GRA is set as an input-capture register
and GRC is set as the buffer register for GRA. TRCCNT functions as a free-running counter and
is captured at both rising and falling edges of the FTIOA signal. Due to the buffer operation, the
GRA value is transferred to GRC on an input-capture A and the TRCCNT value is stored in GRA.
TRCCNT
H'FFFF
H'DA91
H'5480
H'0245
H'0000
Time
FTIOA
GRA
GRC
H'0245
H'5480
H'DA91
H'0245
H'5480
Figure 15.8 Buffer Operation Example (Input Capture)
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Section 15 Timer RC
15.3.2
PWM Mode Operation
In PWM mode, PWM waveforms are generated by using GRA as the cycle register and GRB,
GRC, and GRD as duty cycle registers. PWM waveforms are output from the FTIOB, FTIOC, and
FTIOD pins. Up to three-phase PWM waveforms can be output. In PWM mode, a general register
functions as an output compare register automatically. The initial output level of each pin depends
on the settings in TRCCR1 and TRCCR2. Table 15.7 shows an example of the initial output level
of the FTIOB pin.
Table 15.7 Initial Output Level of FTIOB Pin
Bit TOB (TRCCR1)
Bit POLB (TRCCR2)
Initial Output Level
0
0
1
0
1
0
1
0
0
1
1
1
The output level of each pin is determined by the value of the corresponding PWM mode output
level control bit (POLB, POLC, or POLD) in TRCCR2. When POLB is 0, the FTIOB output pin is
set to 0 on compare match B, and set to 1 on compare match A, whereas when POLB is 1, the
FTIOB output pin is set to 1 on compare match B, and set to 0 on compare match A. When an
output pin is set to PWM mode, the settings in TRCIOR0 and TRCIOR1 are ignored. If the same
value is set in the cycle register and duty cycle register, output levels are not changed when a
compare match occurs.
Figure 15.9 shows an example of operation in PWM mode. The output signals go 1 and TRCCNT
is cleared on compare match A, and the output signals go 0 on compare match B, C, and D.
Rev. 1.00 Oct. 03, 2008 Page 466 of 962
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Section 15 Timer RC
TRCCNT
Counter cleared by compare match A
GRA
GRB
GRC
GRD
H'0000
Time
FTIOB
FTIOC
FTIOD
Figure 15.9 PWM Mode Example (1)
Figure 15.10 shows another example of operation in PWM mode. The output signals go 0 and
TRCCNT is cleared on compare match A, and the output signals go 1 on compare match B, C, and
D.
TRCCNT
Counter cleared by compare match A
GRA
GRB
GRC
GRD
H'0000
Time
FTIOB
FTIOC
FTIOD
Figure 15.10 PWM Mode Example (2)
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Section 15 Timer RC
Figure 15.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and
GRD is set as the buffer register for GRB. TRCCNT is cleared on compare match A, and the
FTIOB pin outputs 1 on compare match B and 0 on compare match A.
Due to the buffer operation, the FTIOB output levels are changed and the value of buffer register
GRD is transferred to GRB whenever compare match B occurs. This procedure is repeated every
time compare match B occurs.
TRCCNT value
GRA
GRB
H'0520
H'0450
H'0200
Time
H'0000
GRD
GRB
H'0200
H'0450
H'0200
H'0520
H'0450
H'0520
FTIOB
Figure 15.11 Buffer Operation Example (Output Compare)
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Section 15 Timer RC
Figures 15.12 and 15.13 show examples of the output of PWM waveforms with duty cycles of 0%
and 100%.
TRCCNT
GRB changed
GRA
GRB
GRB changed
H'0000
Time
Duty cycle 0%
FTIOB
TRCCNT
GRB changed
Output levels of FTIOB are not changed when compare
matches of cycle register and duty cycle register occur
simultaneously.
GRA
GRB changed
GRB changed
GRB
H'0000
Time
Duty cycle 100%
FTIOB
Output levels of FTIOB are not changed when compare
matches of cycle register and duty cycle register occur
simultaneously.
TRCCNT
GRB changed
GRA
GRB changed
GRB changed
GRB
H'0000
FTIOB
Time
Duty cycle 100%
Duty cycle 0%
Figure 15.12 PWM Mode Example (Initial Output Set to 0)
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Section 15 Timer RC
TRCCNT
GRB changed
GRA
GRB
GRB changed
H'0000
Time
Duty cycle 100%
FTIOB
TRCCNT
GRB changed
Output levels of FTIOB are not changed when compare
matches of cycle register and duty cycle register occur
simultaneously.
GRA
GRB changed
GRB changed
GRB
H'0000
Time
Duty cycle 0%
FTIOB
Output levels of FTIOB are not changed when compare
matches of cycle register and duty cycle register occur
simultaneously.
TRCCNT
GRB changed
GRA
GRB changed
GRB changed
GRB
H'0000
Time
Duty cycle 0%
FTIOB
Duty cycle 100%
Figure 15.13 PWM Mode Example (Initial Output Set to 1)
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Section 15 Timer RC
15.3.3
PWM2 Mode Operation
In PWM2 mode, waveforms are output on the FTIOB pin when a compare match occurs on GRB
or GRC. GRD functions as a buffer register for GRB by setting the BUFEB bit in TRCMR to 1.
The output level of the FTIOB signal is specified by the TOB bit in TRCCR1. When TOB = 0, 1
is output on a compare match of GRC and 0 is output on a compare match of GRB. When TOB =
1, 0 is output on a compare match of GRC and 1 is output on a compare match of GRB.
Table 15.8 shows the correspondence between the pin configuration and GR registers and figure
15.14 is a block diagram in PWM2 mode.
Figures 15.15 and 15.16 show the GRD and GRB buffer operating timing in PWM2 mode.
In PWM2 mode, the value of GRD is transferred to GRB on a compare match of GRA and the
counter is cleared. Note, however, that the counter is only cleared when the CCLR bit in TRCCR1
is set to 1. Moreover, when the trigger input is enabled by the TCEG1 and TCEG0 bits in
TRCCR2, the value of GRD is transferred to GRB by the trigger signal and the counter is cleared.
The input/output pins of timers which do not operate in PWM2 mode are only used as general I/O
ports.
Table 15.8 Pin Configuration in PWM2 Mode and GR Registers
Pin Name
Input/Output
Compare Match Register
Buffer Register
FTIOA
I/O
Port*/TRGC
Port*/TRGC
FTIOB
Output
GRB
GRD
GRC

FTIOC
I/O
Port*
Port*
FTIOD
I/O
Port*
Port*
Note:
*
When the port functions, clear the PMR bit on the corresponding pin to 0.
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Section 15 Timer RC
Trigger signal
FTIOA/TRGC
Counter clear
signal
Input
control
TRCCNT
Compare match signal
Comparator
GRA
Comparator
GRB
Comparator
GRC
Compare match signal
FTIOB
Output
control
Compare match signal
Figure 15.14 Block Diagram in PWM2 Mode
φ
TRCCNT
L
GRA
L
GRD
M
GRB
N
H'0000
M
Compare
match signal
Figure 15.15 GRD and GRB Buffer Operating Timing in PWM2 Mode (1)
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GRD
Section 15 Timer RC
φ
TRCCNT
N
GRA
L
GRD
M
GRB
N
N+1
H'0000
M
Counter clear
signal by trigger
input
Figure 15.16 GRD and GRB Buffer Operating Timing in PWM2 Mode (2)
In PWM2 mode, a pulse with arbitrary pulse width and delay time to the TRGC input can be
output from the FTIOB pin
Figures 15.17 and 15.18 show these examples in PWM2 mode. In these examples, the falling edge
of the TRGC input is selected by TRCCR2 (setting the TCEG1 bit to 1 and clearing the TCEG0
bit to 0), TRCCNT continues counting-up on compare match A of GRA (clearing the CSTP bit in
TRCCR2 to 0), and GRD is set as the buffer register (setting the BUFEB bit in TRCMR to 1). The
initial value of the output signal is set to either 0 or 1 by TRCCR1 (clearing the TOB bit to 0 or
setting the TOB bit to 1), TRCCNT is cleared on compare match A (setting the CCLR bit in
TRCCR1 to 1), and the waveform is output from the FTIOB pin (clearing the PWM2 bit in
TRCMR to 0).
When the TOB bit in TRCCR1 is cleared to 0 with the PWM2 mode function, the input edge is
ignored while the FTIOB pin is driven high. Whereas, when the TOB bit is set to 1, the input edge
is ignored while the FTIOB pin is driven low. The transfer from GRD to GRB is carried out on a
compare match of GRA and the TRGC input. However, if the TRGC input is canceled due to the
change of the FTIOB level, the transfer from GRD to GRB is not carried out.
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Section 15 Timer RC
The value of TRCCNT
H'FFFF
GRA
GRB
GRC
H'0000
Time
FTIOA/TRGC
FTIOB
(Output transformation
when TOB = 0)
When TOB = 0, the trigger input is ignored
while the FTIOB pin is driven high, whereas
when TOB = 1, the trigger input is ignored
while the FTIOB pin is driven low
FTIOB
(Output transformation
when TOB = 1)
GRD
A
GRB
B
D
C
A
B
C
D
Figure 15.17 Example (1) of TRGC Synchronous Operation in PWM2 Mode
The value of TRCCNT
H'FFFF
GRA
GRB
GRC
H'0000
Time
CTS
Data written from
the CPU to GRD
High
FTIOA/TRGC
FTIOB
(Output transformation
when TOB = 0)
FTIOB
(Output transformation
when TOB = 1)
GRD
GRB
A
B
A
C
B
A
A
A
Data copied from
GRD to GRB
Figure 15.18 Example (2) of TRGC Synchronous Operation in PWM2 Mode
The following is an example of stopping operation of the counter in PWM2 mode. When the
CSTP bit in TRCCR2 is set to 1 and the CCLR bit in TRCCR1 is set to 1, TRCCNT is cleared to
H'0000 on a compare match with GRA and stops counting. Moreover, TRCCNT is forcibly
stopped and cleared to the initial value when the CTS bit in TRCMR is cleared to 0. Figure 15.19
shows such an example when the TOB bit in TRCCR1 is cleared to 0 and set to 1.
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Section 15 Timer RC
The value of TRCCNT
H'FFFF
GRA
GRB
GRC
H'0000
Time
CTS
High
FTIOA/TRGC
FTIOB
(Output transformation
when TOB = 0)
FTIOB
(Output transformation
when TOB = 1)
Figure 15.19 Example of Stopping Operation of the Counter in PWM2 Mode
The following is an example of output operation of the one-shot pulse waveform in PWM2 mode.
When the TRGC input is disabled by TRCCR2 (clearing the TCEG1 and TCEG0 bits to 0),
TRCCNT is set to stop counting-up on compare match A with GRA (setting the CSTP bit in
TRCCR2 to 1), TRCCNT is cleared on compare match A (setting the CCRL bit in TRCCR1 to 1),
and the initial value of the output signal is set to 0 by TRCCR1 (clearing the TOB bit to 0),
TRCCNT starts counting when the CTS bit in TRCMR is set to 1. Then, TRCCNT is cleared to
H'0000 on a compare match with GRA and stops counting, and the one-shot pulse waveform is
output. Figure 15.20 shows such an example.
The value of TRCCNT
H'FFFF
GRA
GRB
GRC
H'0000
Time
CTS
High
FTIOA/TRGC
FTIOB
Figure 15.20 Example (1) of Output Operation of One-Shot Pulse Waveform
in PWM2 Mode
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Section 15 Timer RC
The following is an example of operation when TRCCNT starts counting by the TRGC input and
the one-shot pulse waveform is output in PWM2 mode. When the falling edge of the TRGC input
is selected by TRCCR2 (setting the TCEG1 bit to 1 and clearing the TCEG0 bit to 0), TRCCNT is
set to counting-up on compare match A with GRA (setting the CSTP bit in TRCCR2 to 1),
TRCCNT is cleared on compare match A (setting the CCRL bit in TRCCR1 to 1), and the initial
value of the output signal is set to 0 by TRCCR1 (clearing the TOB bit to 0), TRCCNT starts
counting at the falling edge of FTIOA/TRGC after the CTS bit in TRCMR has been set to 1. Then,
TRCCNT is cleared to H'0000 on a compare match with GRA and stops counting, and the oneshot pulse waveform is output. Figure 15.21 shows such an example.
The value of TRCCNT
H'FFFF
GRA
GRB
GRC
H'0000
Time
CTS
High
FTIOA/TRGC
FTIOB
Figure 15.21 Example (2) of Output Operation of One-Shot Pulse Waveform
in PWM2 Mode
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Section 15 Timer RC
15.3.4
Digital Filtering Function for Input Capture Inputs
Input signals on the FTIOA to FIOD and TRGC pin can be input via the digital filters. The digital
filter includes three latches connected in series and a match detector circuit. The input signals on
the FTIOA to FTIOD or TRGC pins are using on the sampling clock specified by the DFCK1 and
DFCK0 bits in TRCDF. When outputs of the three latches match, the match detector circuit
outputs the signal level of the input. Otherwise, the output remains unchanged. That is, when a
pulse width is equal to or greater than three sampling clock cycles, the pulse is input as a signal.
When a pulse width is less than three sampling clock cycles, the pulse is considered as noise to be
removed.
CKS2 to
CKS0
φ/32
φ/8
φ
φ40
φ/32
FTCI
φ/8
φ/4
φ/2
φ
FTIOA to FTIOD
and TRGC
input signals
DFCK1 and
DFCK0
Sampling clock
C
C
C
D
Q
Latch
D
Q
D
Latch
Latch
C
Q
Q
D
Latch
DFTRG and
DFA to DFD
IOA[1:0] to
IOD[1:0]
Selecter
Edge
detecting
circuit
Match
detector
circuit
φ, φ40
C
D
Q
Latch
Cycle of a clock specified
by CKS2 to CKS0
or DFCK1 and DFCK0
Sampling clock
FTIOA to FTIOD
or TRGC
input signal
Digital-filtered signal
Signal propagation delay:
5 sampling clocks
Signal change is not output unless
signal levels match three times.
Figure 15.22 Block Diagram of Digital Filter
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Section 15 Timer RC
15.3.5
A/D Conversion Start Trigger Setting Function
Timer RC can generate the A/D conversion start trigger signal on compare matches A, B, C, and
D by setting the timer RC A/D conversion start trigger control register (TRCADCR). Figure 15.23
shows an example where the A/D conversion start trigger signal is set to be output on compare
matches B and C.
GRA
GRB
GRC
H'0000
A/D conversion start
trigger is generated.
ADTRG
Figure 15.23 Example of Compare Match
In buffer operation, a buffer register cannot be used to generate the A/D conversion start trigger.
Moreover, GRC cannot serve as a buffer register for GRA in PWM2 mode. Table 15.9 shows the
A/D conversion start trigger source in each operating mode.
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Section 15 Timer RC
Table 15.9 A/D Conversion Start Trigger Generation in Each Operating Mode
A/D Conversion Start Trigger Generation
Operating Mode
Input capture
Compare match
PWM mode
PWM2 mode
Buffer Operation
GRA
GRB
GRC
GRD
Enabled
×
×
×
×
Disabled
×
×
×
×
Enabled
O
O
×
×
Disabled
O
O
O
O
Enabled
O
O
×
×
Disabled
O
O
O
O
Enabled
O
O
O
×
Disabled
O
O
O
O
[Legend]
O:
The A/D conversion start trigger signal is generated.
×:
The A/D conversion start trigger signal is not generated.
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Section 15 Timer RC
15.3.6
Function of Changing Output Pins for GR
With the settings of bits IOC3 and IOD3 in TRCIOR1, pins for outputs of compare match signals
for GRC and GRD can be changed from the FTIOC and FTIOD pins to the FTIOA and FTIOB
pins. This means that the compare match A signal with the compare match C signal can be output
on the FTIOA pin. The compare match B with the compare match D signal can be output on the
FTIOB pin. Figure 15.24 is a block diagram of this function. Channel 0 and channel 1 can be set
independently.
TRCCNT
Compare match signal
FTIOA
Output
control
Comparator
GRA
Comparator
GRC
Comparator
GRB
Comparator
GRD
Compare match signal
FTIOC
Output
control
Compare match signal
FTIOB
Output
control
Compare match signal
FTIOD
Output
control
Figure 15.24 Block Diagram of Output Pins for GR
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Section 15 Timer RC
Figure 15.25 is an example when non-overlapped pulses are output on pins FTIOA and FTIOB. In
this example, TRCCNT functions as a periodic counter which is cleared on compare match A (bit
CCLR in TRCCR1 is set to 1), an output signal is toggled on compare match A (bits IOA2 to
IOA0 in TRCIOR0 are set to B'011), the output signal on the FTIOA pin is toggled on compare
match C (GRC) (bits IOC3 to IOC0 in TRCIOR1are set to B'0X11), an output signal is toggled on
compare match B (GRB) (bits IOB2 to IOB0 in TRCIOR0 are set to B'011), and the output signal
on the FTIOB pin is toggled on compare match D (GRD) (bits IOD3 to IOD0 in TRCIOR1 are set
to B'0X11). The cycle of the pulse is arbitrary.
TRCCNT
Counter cleared by compare match of GRA
H'FFFF
GRA
GRC
GRB
GRD
H'0000
Time
FTIOA
FTIOB
Figure 15.25 Example of Non-Overlapped Pulses Output on Pins FTIOA and FTIOB
(TRCCNT Used)
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Section 15 Timer RC
15.3.7
Operation through an Event Link
Using the event link controller (ELC), timer RC can be made to operate in the following ways in
relation to events occurring in other modules.
(1)
Staring Counter Operation
The start of counting operations by timer RC can be selected by ELOPA of the ELC. When the
event specified by ELSR2 occur, the CTS bit in TRCMR is set to 1, which stars counting by timer
RC. However, if the specified event occurs when the CTS bit has already been set to 1, the event
is not effective.
(2)
Counting Event
The counting of events by timer RC can be selected by ELOPA of the ELC. When the event
specified in ELSR2 occurs, event counter operation proceeds with that event as the source to drive
counting, regardless of the setting of the CKS[2:0] bits in TRCCR1. When the value of the counter
is read, the value read out is the actual number of input events.
(3)
Input Capture
Input capture operation of timer RC can be selected by ELOPA of the ELC. When the event
specified in ELSR2 occurs, GRD captures the value of TRCCNT. When input capture operation
initiated by an event link is in use, set the IOD[3:0] bits = b'1101 in TRCIOR1 of timer RC, set the
CTS bit in TRCMR to 1, and then start the counter. Since input on the FTIOD pin becomes valid
at the same time, fix the input to the FTIOD pin or take other measures such as not allocating the
FTIOD pin to the port in the PMC, etc.
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Section 15 Timer RC
15.4
Operation Timing
15.4.1
TRCCNT Counting Timing
Figure 15.26 shows the TRCCNT count timing when the internal clock source is selected. Figure
15.27 shows the timing when the external clock source is selected.
φ
Internal clock
Rising edge
TRCCNT input
clock
TRCCNT
N
N+1
N+2
Figure 15.26 Count Timing for Internal Clock Source
φ
External clock
Rising edge
Rising edge
TRCCNT
input clock
TRCCNT
N
N+1
N+2
Figure 15.27 Count Timing for External Clock Source
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Section 15 Timer RC
15.4.2
Output Compare Output Timing
The compare match signal is generated in the last state in which TRCCNT and GR match (when
TRCCNT changes from the matching value to the next value). When the compare match signal is
generated, the output value selected in TRCIOR is output on the compare match output pin
(FTIOA, FTIOB, FTIOC, or FTIOD).
When TRCCNT matches GR, the compare match signal is generated only after the next counter
clock pulse is input.
Figure 15.28 shows the output compare timing.
φ
TRCCNT input
clock
TRCCNT
N
GRA to GRD
N
N+1
Compare
match signal
FTIOA to FTIOD
Figure 15.28 Output Compare Output Timing
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Section 15 Timer RC
15.4.3
Input Capture Timing
Input capture on the rising edge, falling edge, or both edges can be selected through settings in
TRCIOR0 and TRCIOR1. Figure 15.29 shows the timing when the falling edge is selected.
φ
Input capture
input
Input capture
signal
N
N-1
TRCCNT
N+1
N+2
N
GRA to GRD
Figure 15.29 Input Capture Input Signal Timing
15.4.4
Timing of Counter Clearing by Compare Match
Figure 15.30 shows the timing when the counter is cleared by compare match A. When the GRA
value is N, the counter counts from 0 to N, and its cycle is N + 1.
φ
Compare
match signal
TRCCNT
N
GRA
N
H'0000
Figure 15.30 Timing of Counter Clearing by Compare Match
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Section 15 Timer RC
15.4.5
Buffer Operation Timing
Figures 15.31 and 15.32 show the buffer operation timing.
φ
Compare
match signal
N
TRCCNT
GRC, GRD
N+1
M
GRA, GRB
M
Figure 15.31 Buffer Operation Timing (Compare Match)
φ
Input capture
signal
N
TRCCNT
GRA, GRB
M
GRC, GRD
N+1
N
N+1
M
N
Figure 15.32 Buffer Operation Timing (Input Capture)
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Section 15 Timer RC
15.4.6
Timing of IMFA to IMFD Flag Setting at Compare Match
If a general register (GRA, GRB, GRC, or GRD) matches TRCCNT, the corresponding IMFA to
IMFD flag which is used as output compare register is set to 1.
The compare match signal is generated in the last state in which the values match (when TRCCNT
is updated from the matching count to the next count). Therefore, when TRCCNT matches a
general register (GRA, GRB, GRC, or GRD), the compare match signal is generated only after the
next TRCCNT clock pulse is input.
Figure 15.33 shows the timing of the IMFA to IMFD flag setting at compare match.
φ
TRCCNT input
clock
TRCCNT
N
GRA to GRD
N
N+1
Compare match
signal
IMFA to IMFD
Figure 15.33 Timing of IMFA to IMFD Flag Setting at Compare Match
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Section 15 Timer RC
15.4.7
Timing of IMFA to IMFD Setting at Input Capture
The corresponding IMFA, IMFB, IMFC, or IMFD flag which functions as a general register is set
to 1 when an input capture occurs. Figure 15.34 shows the timing of the IMFA to IMFD flag
setting at input capture.
φ
Input capture
signal
TRCCNT
N
GRA to GRD
N
IMFA to IMFD
Figure 15.34 Timing of IMFA to IMFD Flag Setting at Input Capture
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Section 15 Timer RC
15.4.8
Timing of Status Flag Clearing
When the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag
is cleared. Figure 15.35 shows the status flag clearing timing.
TRCSR write cycle
T1
T2
φ
Address
TRCSR address
Write signal
IMFA to IMFD
Figure 15.35 Timing of Status Flag Clearing by CPU
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Section 15 Timer RC
15.4.9
Timing of A/D Conversion Start Trigger Generation on Compare Match
Figure 15.36 shows the timing of the A/D conversion start trigger generation on compare match.
φ
TRCCNT input
TRCCNT
N
GR
N
N+1
Compare match
signal
A/D conversion
trigger signal
Figure 15.36 Timing of A/D Conversion Start Trigger Generation on Compare Match
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Section 15 Timer RC
15.5
Usage Notes
The following types of contention or operation can occur in timer RC operation.
1. When the digital filtering function for input is not in use, the pulse width of the input clock
signal and the input capture signal must be at least three system clock (φ) cycles when the
CKS2 to CKS0 bits in TRCCR1 = B'0XX or B'10X, and at least 3 × φ40 cycles for B'110;
shorter pulses will not be detected correctly.
2. Writing to registers is performed in the T2 state of a TRCCNT write cycle.
If counter clear signal occurs in the T2 state of a TRCCNT write cycle, clearing of the counter
takes priority and the write is not performed, as shown in figure 15.37. If the TRCCNT write
cycle contends with the TRCCNT counting-up, writing takes precedence.
3. TRCCNT may erroneously count up depends on the timing of switching internal clocks. The
count clock is generated by detecting the rising edge of the divided system clock (φ) when the
internal clock is selected. If clocks are switched as shown in figure 15.38, the change from the
low level of the previous clock to the high level of the new clock is considered as the rising
edge. In this case, TRCCNT counts up the clock erroneously.
4. If timer RC enters the module standby mode while an interrupt is being requested, the interrupt
request cannot be cleared. Before entering the module standby mode, disable interrupt
requests.
TRCCNT write cycle
T2
T1
φ
TRCCNT address
Address
Write signal
Counter clear
signal
TRCCNT
N
H'0000
Figure 15.37 Contention between TRCCNT Write and Clear
Rev. 1.00 Oct. 03, 2008 Page 491 of 962
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Section 15 Timer RC
Previous clock
New clock
Counter clock
TRCCNT
N+1
N
N+2
N+3
The rising edge may occur depending on the timing
of changing bits CKS2 to CKS0. In this case, TRCCNT
counts up.
Figure 15.38 Internal Clock Switching and TRCCNT Operation
5. The TOA to TOD bits in TRCCR1 decide the output value of the FTIO pin until the first
compare match occurs. Once a compare match occurs and this compare match changes the
values of FTIOA to FTIOD output, the values of the FTIOA to FTIOD pin output and the
values read from the TOA to TOD bits may differ. Moreover, when the writing to TRCCR1
and the generation of the compare match A to D occur at the same timing, the writing to
TRCCR1 has the priority. Thus, output change due to the compare match is not reflected to the
FTIOA to FTIOD pins. Therefore, when bit manipulation instruction is used to write to
TRCCR1, the values of the FTIOA to FTIOD pin output may result in an unexpected result.
When TRCCR1 is to be written to while compare match is operating, stop the counter once
before accessing to TRCCR1, read the port H state to reflect the values of FTIOA to FTIOD
output, to TOA to TOD, and then restart the counter. Figure 15.39 shows an example when the
compare match and the bit manipulation instruction to TRCCR1 occur at the same timing.
Rev. 1.00 Oct. 03, 2008 Page 492 of 962
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Section 15 Timer RC
TRCCR1 has been set to H'06. Compare match B and compare match C are used. The FTIOB pin output 1,
and is set to the toggle output or the 0 output on compare match B.
When the TOC bit is cleared (the FTIOC signal is low) by execution of BCLR #2,@TRCCR1 and compare
match B occurs at the same timing as shown below, writing H'02 to TRCCR1 has priority and the FTIOB
signal is not driven low on compare match B; the FTIOB signal remains high.
Bit
TRCCR1
Setting
7
6
5
4
CCLR
CKS2
CKS1
CKS0
0
0
0
0
3
TOD
0
2
1
0
TOC
TOB
TOA
1
1
0
BCLR #2,@TRCCR1
(1) TRCCR1 is read as H'06.
(2) TRCCR1 is modified from H'06 to H'02.
(3) H'02 is written to TRCCR1.
φ
TRCCR1
write signal
Compare match B
signal
FTIOB pin
Remains high because the writing 1 to TOB has priority
Expected
output
Figure 15.39 When Compare Match and Bit Manipulation Instruction to TRCCR1
Occur at the Same Timing
Rev. 1.00 Oct. 03, 2008 Page 493 of 962
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Section 15 Timer RC
6. When the internal φ40 clock is selected as the counter source (the CKS[2:0] bits in TRCCR1 =
B'110), if any register of timer RC is to be read immediately after writing to another register in
a given module, proceed with reading after having executed one NOP instruction.
Write to TRCMR.
Execute NOP.
Read TRCCNT.
Figure 15.40 Example of Flow for Reading Immediately after Writing to a Register
Rev. 1.00 Oct. 03, 2008 Page 494 of 962
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Section 16 Timer RD
Section 16 Timer RD
This LSI has two units of 16-bit timers (timer RD_0 and timer RD_1), each of which has two
channels. Table 16.1 lists the timer RD functions, table 16.2 lists the channel configuration of
timer RD, and figure 16.1 is a block diagram of the entire timer RD. Block diagrams of channels 0
and 1 are shown in figures 16.2 and 16.3.
Timer RD_0 has the same functions as timer RD_1. Therefore, the unit number (_0 or _1) is not
explicitly mentioned in this section unless otherwise noted.
16.1
Features
• Capability to process up to eight inputs/outputs
• Eight general registers (GR): four registers for each channel
Independently assignable output compare or input capture functions
• Selection of seven counter clock sources: six internal clocks (φ, φ/2, φ/4, φ/8, φ/32, and φ40M)
and an external clock
• Seven selectable operating modes
 Timer mode
Output compare function (Selection of 0 output, 1 output, or toggle output)
Input capture function (Rising edge, falling edge, or both edges)
 Synchronous operation
Timer counters_0 and _1 (TRDCNT_0 and TRDCNT_1) can be written simultaneously.
Simultaneous clearing by compare match or input capture is possible.
 PWM mode
Up to six-phase PWM output can be provided with desired duty ratio.
 PWM3 mode
One-phase PWM output for non-overlapped normal and counter phases
 Reset synchronous PWM mode
Three-phase PWM output for normal and counter phases
 Complementary PWM mode
Three-phase PWM output for non-overlapped normal and counter phases
The A/D conversion start trigger can be set for PWM cycles.
 Buffer operation
The input capture register can be consisted of double buffers.
The output compare register can automatically be modified.
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Section 16 Timer RD
• High-speed access by the internal 16-bit bus
16-bit TRDCNT and GR registers can be accessed in high speed by a 16-bit bus interface
• Any initial timer output value can be set
• Output of the timer is disabled by external trigger
• Eleven interrupt sources
Four compare match/input capture interrupts and an overflow interrupt are available for each
channel. An underflow interrupt can be set for channel 1.
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Section 16 Timer RD
Table 16.1 Timer RD Functions (One Unit)
Item
Channel 0
Channel 1
Count clock
Internal clocks: φ, φ/2, φ/4, φ/8, φ/32, φ40M
External clock: FTIOA0 (TCLK)
General registers
(output compare/input
capture registers)
GRA_0, GRB_0, GRC_0, GRD_0 GRA_1, GRB_1, GRC_1, GRD_1
Buffer register
GRC_0, GRD_0
GRC_1, GRD_1
I/O pins
FTIOA0, FTIOB0, FTIOC0,
FTIOD0
FTIOA1, FTIOB1, FTIOC1,
FTIOD1
Counter clearing function
Compare match/input capture of
GRA_0, GRB_0, GRC_0, or
GRD_0
Compare match/input capture of
GRA_1, GRB_1, GRC_1, or
GRD_1
Compare
match output
0 output
Yes
Yes
1 output
Yes
Yes
Toggle
output
Yes
Yes
Input capture function
Yes
Yes
Synchronous operation
Yes
Yes
PWM mode
Yes
Yes
PWM3 mode
Yes
Yes
Reset synchronous PWM
mode
Yes
Yes
Complementary PWM
mode
Yes
Yes
Buffer function
Yes
Yes
Interrupt sources
Compare match/
input capture A0 to D0
Overflow
Compare match/
input capture A1 to D1
Overflow
Underflow
Rev. 1.00 Oct. 03, 2008 Page 497 of 962
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Section 16 Timer RD
Table 16.2 Channel Configuration of Timer RD
Unit
Channel
Pin
Timer RD_0
0
FTIOA0
(Unit 0)
FTIOB0
FTIOC0
FTIOD0
1
FTIOA1
FTIOB1
FTIOC1
FTIOD1
Timer RD_1
Shared by channels 0 and 1
TRDOI_0
2
FTIOA2
(Unit 1)
FTIOB2
FTIOC2
FTIOD2
3
FTIOA3
FTIOB3
FTIOC3
FTIOD3
Shared by channels 2 and 3
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TRDOI_1
Section 16 Timer RD
TRDOI_0
Channel 0
Interrupt request signal
ITDMA0
ITDMB0
ITDMC0
ITDMD0
ITDOV0
ITDUD0
FTIOA0
FTIOB0
FTIOC0
FTIOD0
Control logic
FTIOA1
Channel 1
Interrupt request signal
ITDMA1
ITDMB1
ITDMC1
ITDMD1
ITDOV1
FTIOB1
FTIOC1
FTIOD1
φ, φ/2,
φ/4, φ/8,
φ/32, φ40
ADTRG
TRDSTR TRDMDR TRDOER2
Channel 0
timer
Channel 1
timer
TRDPMR TRDFCR TRDADCR
TRDOER1 TRDOCR
Module data bus
Figure 16.1 Timer RD (One Unit) Block Diagram
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Section 16 Timer RD
FTIOA0
φ, φ/2,
φ/4, φ/8,
FTIOB0
FTIOC0
FTIOD0
Clock select
φ/32, φ40
Control logic
ITDMA0
ITDMB0
ITDMC0
ITDMD0
ITDOV0
ITDUD0
Comparator
Module data bus
Figure 16.2 Timer RD (Channel 0) Block Diagram
Rev. 1.00 Oct. 03, 2008 Page 500 of 962
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TRDDF_0
POCR_0
TRDIER_0
TRDSR_0
TRDIORC_0
TRDIORA_0
TRDCR_0
GRD_0
GRC_0
GRB_0
GRA_0
TRDCNT_0
TRDOI_0
Section 16 Timer RD
FTIOA1
φ, φ/2,
φ/4, φ/8,
FTIOB1
FTIOC1
FTIOD1
Clock select
φ/32, φ40
Control logic
ITDMA1
ITDMB1
ITDMC1
ITDMD1
ITDOV1
Comparator
TRDDF_1
POCR_1
TRDIER_1
TRDSR_1
TRDIORC_1
TRDIORA_1
TRDCR_1
GRD_1
GRC_1
GRB_1
GRA_1
TRDCNT_1
TRDOI_0
Module data bus
Figure 16.3 Timer RD (Channel 1) Block Diagram
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Section 16 Timer RD
Table 16.3 summarizes the timer RD pins.
Table 16.3 Pin Configuration (One Unit)
Pin Name
Input/Output
Function
FTIOA0
I/O
GRA_0 output compare output, GRA_0 input capture input, or
external clock input (TCLK)
FTIOB0
I/O
GRB_0 output compare output, GRB_0 input capture input, or
PWM output
FTIOC0
I/O
GRC_0 output compare output, GRC_0 input capture input, or
PWM synchronous output (in reset synchronous PWM and
complementary PWM modes)
FTIOD0
I/O
GRD_0 output compare output, GRD_0 input capture input, or
PWM output
FTIOA1
I/O
GRA_1 output compare output, GRA_1 input capture input, or
PWM output (in reset synchronous PWM and complementary
PWM modes)
FTIOB1
I/O
GRB_1 output compare output, GRB_1 input capture input, or
PWM output
FTIOC1
I/O
GRC_1 output compare output, GRC_1 input capture input, or
PWM output
FTIOD1
I/O
GRD_1 output compare output, GRD_1 input capture input, or
PWM output
TRDOI_0
Input
Input pin for timer output disabling signal
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Section 16 Timer RD
16.2
Register Descriptions
Timer RD has the following registers.
Common
•
•
•
•
•
•
•
•
Timer RD start register (TRDSTR)
Timer RD mode register (TRDMDR)
Timer RD PWM mode register (TRDPMR)
Timer RD function control register (TRDFCR)
Timer RD output master enable register 1 (TRDOER1)
Timer RD output master enable register 2 (TRDOER2)
Timer RD output control register (TRDOCR)
Timer RD A/D conversion start trigger control register (TRDADCR)
Channel 0
•
•
•
•
•
•
•
•
•
•
•
•
Timer RD control register_0 (TRDCR_0)
Timer RD I/O control register A_0 (TRDIORA_0)
Timer RD I/O control register C_0 (TRDIORC_0)
Timer RD status register_0 (TRDSR_0)
Timer RD interrupt enable register_0 (TRDIER_0)
PWM mode output level control register_0 (POCR_0)
Timer RD digital filtering function select register_0 (TRDDF_0)
Timer RD counter_0 (TRDCNT_0)
General register A_0 (GRA_0)
General register B_0 (GRB_0)
General register C_0 (GRC_0)
General register D_0 (GRD_0)
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Section 16 Timer RD
Channel 1
•
•
•
•
•
•
•
•
•
•
•
•
Timer RD control register_1 (TRDCR_1)
Timer RD I/O control register A_1 (TRDIORA_1)
Timer RD I/O control register C_1 (TRDIORC_1)
Timer RD status register_1 (TRDSR_1)
Timer RD interrupt enable register_1 (TRDIER_1)
PWM mode output level control register_1 (POCR_1)
Timer RD digital filtering function select register_1 (TRDDF_1)
Timer RD counter_1 (TRDCNT_1)
General register A_1 (GRA_1)
General register B_1 (GRB_1)
General register C_1 (GRC_1)
General register D_1 (GRD_1)
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Section 16 Timer RD
16.2.1
Timer RD Start Register (TRDSTR)
Address: H'FFFFD2
Bit:
b7
b6
b5
b4
b3
b2
b1
b0




CSTPN1
CSTPN0
STR1
STR0
Value after reset:
1
1
1
1
1
1
0
0
Bit
Bit Name
Description
R/W
7 to 4 
Reserved
These bits are read as 1. The write value should
be 1.

3
Channel 1 counter 0: Counting is stopped on a compare match of
stop
TRDCNT_1 and GRA_1
Symbol
CSTPN1
R/W
1: Counting is continued on a compare match of
TRDCNT_1 and GRA_1
Set this bit to 1 to restart counting after the
counting has been stopped on a compare match.
2
CSTPN0
Channel 0 counter 0: Counting is stopped on a compare match of
stop
TRDCNT_0 and GRA_0
R/W
1: Counting is continued on a compare match of
TRDCNT_0 and GRA_0
Set this bit to 1 to restart counting after the
counting has been stopped on a compare match.
1
STR1
Channel 1 counter 0: TRDCNT_1 stops counting.
start
1: TRDCNT_1 starts counting.
R/W
[Setting conditions]
•
When 1 is written in STR1
•
When the specified event is occurred after
ELOPB of the event link controller is selected
counting by timer RD_0 for channel 1.
[Clearing conditions]
•
When 0 is written in STR1 while CSTPN1 = 1
•
When the compare match A1 signal is
generated while CSTPN1 = 0
Rev. 1.00 Oct. 03, 2008 Page 505 of 962
REJ09B0465-0100
Section 16 Timer RD
Bit
Symbol
Bit Name
Description
0
STR0
Channel 0 counter 0: TRDCNT_0 stops counting.
start
1: TRDCNT_0 starts counting.
[Setting conditions]
•
When 1 is written in STR0
•
When the specified event is occurred after
ELOPA of the event link controller is selected
counting by timer RD_0 for channel 0.
[Clearing conditions]
•
When 0 is written in STR0 while CSTPN0 = 1
•
When the compare match A1 signal is
generated while CSTPN0 = 0
Note: Use a MOV instruction to modify this register.
Rev. 1.00 Oct. 03, 2008 Page 506 of 962
REJ09B0465-0100
R/W
R/W
Section 16 Timer RD
16.2.2
Timer RD Mode Register (TRDMDR)
Address: H'FFFFD3
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
BFD1
BFC1
BFD0
BFC0



SYNC
0
0
0
0
1
1
1
0
Bit
Symbol
Bit Name
Description
R/W
7
BFD1
Buffer
operation D1
0: GRD_1 operates normally
R/W
Buffer
operation C1
0: GRC_1 operates normally
Buffer
operation D0
0: GRD_0 operates normally
Buffer
operation C0
0: GRC_0 operates normally
3 to 1 
Reserved
These bits are read as 1. The write value should be
1.
0
Timer
0: TRDCNT_1 and TRDCNT_0 operate as
synchronization
independent timer counters
6
5
4
BFC1
BFD0
BFC0
SYNC
1: GRB_1 and GRD_1 are used together for buffer
operation
R/W
1: GRA_1 and GRC_1 are used together for buffer
operation
R/W
1: GRB_0 and GRD_0 are used together for buffer
operation
R/W
1: GRA_0 and GRC_0 are used together for buffer
operation

R/W
1: TRDCNT_1 and TRDCNT_0 operate
synchronously
TRDCNT_1 and TRDCNT_0 can be pre-set or
cleared synchronously.
Rev. 1.00 Oct. 03, 2008 Page 507 of 962
REJ09B0465-0100
Section 16 Timer RD
16.2.3
Timer RD PWM Mode Register (TRDPMR)
Address: H'FFFFD4
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0

PWMD1
PWMC1
PWMB1

PWMD0
PWMC0
PWMB0
1
0
0
0
1
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is read as 1. The write value should be 1.

6
PWMD1
PWM mode
D1
0: FTIOD1 operates normally
R/W
5
PWMC1
PWM mode
C1
0: FTIOC1 operates normally
PWM mode
B1
0: FTIOB1 operates normally
4
PWMB1
1: FTIOD1 operates in PWM mode
R/W
1: FTIOC1 operates in PWM mode
R/W
1: FTIOB1 operates in PWM mode
3

Reserved
This bit is read as 1. The write value should be 1.

2
PWMD0
PWM mode
D0
0: FTIOD0 operates normally
R/W
PWM mode
C0
0: FTIOC0 operates normally
PWM mode
B0
0: FTIOB0 operates normally
1
0
PWMC0
PWMB0
1: FTIOD0 operates in PWM mode
1: FTIOC0 operates in PWM mode
1: FTIOB0 operates in PWM mode
Rev. 1.00 Oct. 03, 2008 Page 508 of 962
REJ09B0465-0100
R/W
R/W
Section 16 Timer RD
16.2.4
Timer RD Function Control Register (TRDFCR)
Address: H'FFFFD5
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
PWM3
STCLK
ADEG
ADTRG
OLS1
OLS0
1
0
0
0
0
0
Bit
Symbol
Bit Name
Description
7
PWM3
PWM3 mode
select
0: PWM3 mode is selected
b0
b1
CMD[1:0]
0
0
R/W
1: PWM3 mode is not selected*
R/W
1
6
STCLK
External clock 0: External clock input is disabled
input select
1: External clock input is enabled
R/W
5
ADEG
A/D trigger
edge select
R/W
0: The A/D trigger signal is asserted when
TRDCNT_0 matches GRA_0 in complementary
PWM mode
1: The A/D trigger signal is asserted when
TRDCNT_1 underflows in complementary PWM
mode
4
ADTRG
External
0: A/D trigger for PWM cycles is disabled in
trigger disable
complementary PWM mode
R/W
1: A/D trigger for PWM cycles is enabled in
complementary PWM mode*2
3
2
OLS1
OLS0
Output level
select 1
0: Initial output is high and the active level is low.
Output level
select 0
0: Initial output is high and the active level is low.
R/W
1: Initial output is low and the active level is high.
R/W
1: Initial output is low and the active level is high.
Rev. 1.00 Oct. 03, 2008 Page 509 of 962
REJ09B0465-0100
Section 16 Timer RD
Bit
Symbol
Bit Name
Description
1, 0
CMD[1:0]
Combination 00: Channel 0 and channel 1 operate normally
mode 1 and 0 01: Channel 0 and channel 1 are used together to
operate in reset synchronous PWM mode
R/W
R/W
10: Channel 0 and channel 1 are used together to
operate in complementary PWM mode
(transferred when TRDCNT_0 matches GRA_0)
11: Channel 0 and channel 1 are used together to
operate in complementary PWM mode
(transferred when TRDCNT_1 underflows)
Note: When the reset synchronous PWM mode or
complementary PWM mode is selected by
these bits, this setting has the priority to the
settings for PWM mode by each bit in
TRDPMR. Stop TRDCNT_0 and TRDCNT_1
before making settings for reset synchronous
PWM mode or complementary PWM mode.
Notes: 1. This bit is valid when both bits CMD1 and CMD0 are cleared to 0. When PWM3 mode
is selected, TRDPMR, TRDIORA, and TRDIORC are invalid.
2. The A/D converter registers should be set so that A/D conversion is started by an
external trigger.
• OLS1 bit (output level select 1)
This bit selects the output level for counter phase in reset synchronous PWM mode and
complementary PWM mode.
• OLS0 bit (output level select 0)
This bit selects the output level for normal phase in reset synchronous PWM mode and
complementary PWM mode.
Rev. 1.00 Oct. 03, 2008 Page 510 of 962
REJ09B0465-0100
Section 16 Timer RD
TRDCNT_0
TRDCNT_1
Normal
phase
Normal
phase
Active level
Counter
phase
Counter
phase
Initial
output
Active level
Initial
output
Active level
Active level
Reset synchronous PWM mode
Note:
Complementary PWM mode
Write H'00 to TRDOCR to start initial outputs after stopping the counter.
Figure 16.4 Example of Outputs in Reset Synchronous PWM Mode
and Complementary PWM Mode
16.2.5
Timer RD Output Master Enable Register 1 (TRDOER1)
Address: H'FFFFD6
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
ED1
EC1
EB1
EA1
ED0
EC0
EB0
EA0
1
1
1
1
1
1
1
1
Bit
Symbol
Bit Name
Description
R/W
7
ED1
Master enable 0: FTIOD1 pin output is enabled according to the
D1
TRDPMR, TRDFCR, and TRDIORC_1 settings
R/W
1: FTIOD1 pin output is disabled regardless of the
TRDMR, TRDFCR, and TRDIORC_1 settings
(FTIOD1 pin is operated as an I/O port).
6
EC1
Master enable 0: FTIOC1 pin output is enabled according to the
C1
TRDPMR, TRDFCR, and TRDIORC_1 settings
R/W
1: FTIOC1 pin output is disabled regardless of the
TRDPMR, TRDFCR, and TRDIORC_1 settings
(FTIOC1 pin is operated as an I/O port).
Rev. 1.00 Oct. 03, 2008 Page 511 of 962
REJ09B0465-0100
Section 16 Timer RD
Bit
Symbol
Bit Name
Description
5
EB1
Master enable 0: FTIOB1 pin output is enabled according to the
B1
TRDPMR, TRDFCR, and TRDIORA_1 settings
R/W
R/W
1: FTIOB1 pin output is disabled regardless of the
TRDPMR, TRDFCR, and TRDIORA_1 settings
(FTIOB1 pin is operated as an I/O port).
4
EA1
Master enable 0: FTIOA1 pin output is enabled according to the
A1
TRDPMR, TRDFCR, and TRDIORA_1 settings
R/W
1: FTIOA1 pin output is disabled regardless of the
TRDPMR, TRDFCR, and TRDIORA_1 settings
(FTIOA1 pin is operated as an I/O port).
3
ED0
Master enable 0: FTIOD0 pin output is enabled according to the
D0
TRDPMR, TRDFCR, and TRDIORC_0 settings
R/W
1: FTIOD0 pin output is disabled regardless of the
TRDPMR, TRDFCR, and TRDIORC_0 settings
(FTIOD0 pin is operated as an I/O port).
2
EC0
Master enable 0: FTIOC0 pin output is enabled according to the
C0
TRDPMR, TRDFCR, and TRDIORC_0 settings
R/W
1: FTIOC0 pin output is disabled regardless of the
TRDPMR, TRDFCR, and TRDIORC_0 settings
(FTIOC0 pin is operated as an I/O port).
1
EB0
Master enable 0: FTIOB0 pin output is enabled according to the
B0
TRDPMR, TRDFCR, and TRDIORA_0 settings
R/W
1: FTIOB0 pin output is disabled regardless of the
TRDPMR, TRDFCR, and TRDIORA_0 settings
(FTIOB0 pin is operated as an I/O port).
0
EA0
Master enable 0: FTIOA0 pin output is enabled according to the
A0
TRDPMR, TRDFCR, and TRDIORA_0 settings
R/W
1: FTIOA0 pin output is disabled regardless of the
TRDPMR, TRDFCR, and TRDIORA_0 settings
(FTIOA0 pin is operated as an I/O port).
TRDOER1 enables/disables the outputs for channel 0 and channel 1. When TRDOI is selected for
inputs, if a low level signal is input to TRDOI, the bits in TRDOER1 are set to 1 to disable the
output for timer RD.
Rev. 1.00 Oct. 03, 2008 Page 512 of 962
REJ09B0465-0100
Section 16 Timer RD
16.2.6
Timer RD Output Master Enable Register 2 (TRDOER2)
Address: H'FFFFD7
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
PTO







0
1
1
1
1
1
1
1
Bit
Symbol
Bit Name
Description
R/W
7
PTO
Timer output 0: The corresponding bit in TRDOER1 is not set to 1 R/W
disabled mode
when the low level is input to the TRDOI pin
1: The corresponding bit in TRDOER1 is set to 1
when the low level is input to the TRDOI pin
6 to 0 
16.2.7
Reserved
These bits are read as 1. The write value should be
1.

Timer RD Output Control Register (TRDOCR)
Address: H'FFFFD8
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
TOD1
TOC1
TOB1
TOA1
TOD0
TOC0
TOB0
TOA0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
TOD1
Output level
select D1
0: 0 output at the FTIOD1 pin*
R/W
Output level
select C1
0: 0 output at the FTIOC1 pin*
Output Level
Select B1
0: 0 output at the FTIOB1 pin*
Output level
select A1
0: 0 output at the FTIOA1 pin*
Output level
select D0
0: 0 output at the FTIOD0 pin*
6
5
4
3
TOC1
TOB1
TOA1
TOD0
1: 1 output at the FTIOD1 pin*
R/W
1: 1 output at the FTIOC1 pin*
R/W
1: 1 output at the FTIOB1 pin*
R/W
1: 1 output at the FTIOA1 pin*
R/W
1: 1 output at the FTIOD0 pin*
Rev. 1.00 Oct. 03, 2008 Page 513 of 962
REJ09B0465-0100
Section 16 Timer RD
Bit
Symbol
Bit Name
Description
R/W
2
TOC0
Output level
select C0
0: 0 output at the FTIOC0 pin*
R/W
Output level
select B0
•
1
TOB0
1: 1 output at the FTIOC0 pin*
In modes other than PWM3 mode
R/W
0: 0 output at the FTIOB0 pin*
1: 1 output at the FTIOB0 pin*
•
In PWM3 mode
0: 1 output at the FTIOB0 pin on GRB_1
compare match and 0 output at the FTIOB0 pin
on GRB_0 compare match
1: 0 output at the FTIOB0 pin on GRB_1
compare match and 1 output at the FTIOB0 pin
on GRB_0 compare match
0
TOA0
Output level
select A0
•
In modes other than PWM3 mode
R/W
0: 0 output at the FTIOA0 pin*
1: 1 output at the FTIOA0 pin*
•
In PWM3 mode
0: 1 output at the FTIOB0 pin on GRA_1
compare match and 0 output at the FTIOB0 pin
on GRA_0 compare match
1: 0 output at the FTIOB0 pin on GRA_1
compare match and 1 output at the FTIOB0 pin
on GRA_0 compare match
Note:
*
The change of the setting is immediately reflected in the output value.
TRDOCR selects the initial outputs before the first occurrence of a compare match. Note that bits
OLS1 and OLS0 in TRDFCR set these initial outputs in reset synchronous PWM mode and
complementary PWM mode.
In PWM3 mode, TRDOCR selects the output level of the FTIOA0 and FTIOB0 pins.
Rev. 1.00 Oct. 03, 2008 Page 514 of 962
REJ09B0465-0100
Section 16 Timer RD
16.2.8
Timer RD A/D Conversion Start Trigger Control Register (TRDADCR)
Address: H'FFFFD9
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
ADTRGD1E ADTRGC1E ADTRGB1E TDTRGA1E ADTRGD0E ADTRGC0E ADTRGB0E ADTRGA0E
Value after reset:
Bit
Symbol
7
6
0
0
Bit Name
0
0
0
0
0
0
Description
R/W
ADTRGD1E A/D
conversion
start trigger
D1 enable
0: A/D conversion start trigger is not generated by
compare match of GRD_1
R/W
ADTRGC1E A/D
conversion
start trigger
C1 enable
0: A/D conversion start trigger is not generated by
compare match of GRC_1
1: A/D conversion start trigger is generated by
compare match of GRD_1
R/W
1: A/D conversion start trigger is generated by
compare match of GRC_1
5
ADTRGB1E A/D
0: A/D conversion start trigger is not generated by
conversion
compare match of GRB_1
start trigger B1 1: A/D conversion start trigger is generated by
enable
compare match of GRB_1
R/W
4
ADTRGA1E A/D
0: A/D conversion start trigger is not generated by
conversion
compare match of GRA_1
start trigger A1 1: A/D conversion start trigger is generated by
enable
compare match of GRA_1
R/W
3
ADTRGD0E A/D
conversion
start trigger
D0 enable
0: A/D conversion start trigger is not generated by
compare match of GRD_0
R/W
ADTRGC0E A/D
conversion
start trigger
C0 enable
0: A/D conversion start trigger is not generated by
compare match of GRC_0
2
1
1: A/D conversion start trigger is generated by
compare match of GRD_0
R/W
1: A/D conversion start trigger is generated by
compare match of GRC_0
ADTRGB0E A/D
0: A/D conversion start trigger is not generated by
conversion
compare match of GRB_0
start trigger B0 1: A/D conversion start trigger is generated by
enable
compare match of GRB_0
R/W
Rev. 1.00 Oct. 03, 2008 Page 515 of 962
REJ09B0465-0100
Section 16 Timer RD
Bit
Symbol
Bit Name
Description
R/W
0
ADTRGA0E A/D
0: A/D conversion start trigger is not generated by
conversion
compare match of GRA_0
start trigger A0 1: A/D conversion start trigger is generated by
enable
compare match of GRA_0
R/W
TRDADCR selects the trigger source to start A/D conversion. A/D conversion start trigger is
generated by a corresponding compare match.
16.2.9
Timer RD Counter (TRDCNT)
Address: H'FFFFB0, H'FFFFBA
Bit: b15
Value after reset:
0
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Timer RD has two TRDCNT counters (TRDCNT_0 and TRDCNT_1), one for each channel. The
TRDCNT counters are 16-bit readable/writable registers that increment/decrement according to
input clocks. Input clocks can be selected by bits TPSC2 to TPSC0 in TRDCR. TRDCNT_0 and
TRDCNT_1 increment/decrement in complementary PWM mode while they only increment in
other modes.
The TRDCNT counters are initialized to H'0000 by compare matches with corresponding GRA,
GRB, GRC, or GRD, or input captures to GRA, GRB, GRC, or GRD (counter clearing function).
When the TRDCNT counters overflow, an OVF flag in TRDSR for the corresponding channel is
set to 1. When TRDCNT_1 underflows, an UDF flag in TRDSR is set to 1. The TRDCNT
counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit.
Rev. 1.00 Oct. 03, 2008 Page 516 of 962
REJ09B0465-0100
Section 16 Timer RD
16.2.10 General Registers A, B, C, and D (GRA, GRB, GRC, and GRD)
GRA
Address: H'FFFFB2, H'FFFFBC
Bit:
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GRB
Address: H'FFFFB4, H'FFFFBE
Bit:
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GRC
Address: H'FFFFB6, H'FFFFC0
Bit:
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GRD
Address: H'FFFFB8, H'FFFFC2
Bit:
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rev. 1.00 Oct. 03, 2008 Page 517 of 962
REJ09B0465-0100
Section 16 Timer RD
GR are 16-bit registers. Timer RD has eight general registers (GR), four for each channel. The GR
registers are dual function 16-bit readable/writable registers, functioning as either output compare
or input capture registers. Functions can be switched by TRDIORA and TRDIORC.
The values in GR and TRDCNT are constantly compared with each other when the GR registers
are used as output compare registers. When the both values match, the IMFA to IMFD flags in
TRDSR are set to 1. Compare match outputs can be selected by TRDIORA and TRDIORC.
When the GR registers are used as input capture registers, the TRDCNT value is stored after
detecting external signals. At this point, IMFA to IMFD flags in the corresponding TRDSR are set
to 1. Detection edges for input capture signals can be selected by TRDIORA and TRDIORC.
When PWM mode, complementary PWM mode, or reset synchronous PWM mode is selected, the
values in TRDIORA and TRDIORC are ignored. Upon reset, the GR registers are set as output
compare registers (no output) and initialized to H'FFFF. The GR registers cannot be accessed in 8bit units; they must always be accessed as a 16-bit unit.
Rev. 1.00 Oct. 03, 2008 Page 518 of 962
REJ09B0465-0100
Section 16 Timer RD
16.2.11 Timer RD Control Register (TRDCR)
Address: H'FFFFCA, H'FFFFD1
Bit:
b7
Value after reset:
0
b6
b5
b4
0
0
CCLR[2:0]
Bit
Symbol
7 to 5 CCLR[2:0]
0
b3
b2
0
0
CKEG[1:0]
b1
b0
TPSC[2:0]
0
0
Bit Name
Description
R/W
Counter clear
2 to 0
000: Disables TRDCNT clearing
R/W
001: Clears TRDCNT by GRA compare match/input
1
capture*
010: Clears TRDCNT by GRB compare match/input
1
capture*
011: Synchronization clear; Clears TRDCNT in
synchronous with counter clearing of the other
2
channel's timer*
100: Disables TRDCNT clearing
101: Clears TRDCNT by GRC compare match/input
1
capture*
110: Clears TRDCNT by GRD compare match/input
1
capture*
111: Synchronization clear; Clears TRDCNT in
synchronous with counter clearing of the other
channel's timer*2
4, 3
CKEG[1:0]
Clock edge
1 and 0
00: Count at rising edge
R/W
01: Count at falling edge
1X: Count at both edges
Rev. 1.00 Oct. 03, 2008 Page 519 of 962
REJ09B0465-0100
Section 16 Timer RD
Bit
Symbol
2 to 0 TPSC[2:0]
*3*4
Bit Name
Description
Time
000: Internal clock: count by φ
prescaler 2 to 001: Internal clock: count by φ/2
0
010: Internal clock: count by φ/4
R/W
R/W
011: Internal clock: count by φ/8
100: Internal clock: count by φ/32
101: External clock: count by FTIOA0 (TCLK) pin
input
110: Internal clock: count by φ40M
111: Reserved (setting prohibited)
[Legend]
X:
Don't care
Notes: 1. When GR functions as an output compare register, TRDCNT is cleared by compare
match. When GR functions as input capture, TRDCNT is cleared by input capture.
2. Synchronous operation is set by TRDMDR.
3. If the internal φ/40 clock is selected, the high-speed on-chip oscillator must be
operating. As long as the internal φ40 clock is selected, do not stop the high-speed onchip oscillator. When the counter clock is switched over, the counter should be halted.
4. When the internal φ40 clock is selected, restrictions on access to registers are applied.
For details, see section 16.5, Usage Notes. (11) Restrictions on Access to Registers
when Internal φ40 Clock is Selected as Counter Clock.
TRDCR selects a TRDCNT counter clock, an edge when an external clock is selected, and counter
clearing sources. Timer RD has a total of two TRDCR registers, one for each channel.
Rev. 1.00 Oct. 03, 2008 Page 520 of 962
REJ09B0465-0100
Section 16 Timer RD
16.2.12 Timer RD I/O Control Registers (TRDIORA and TRDIORC)
TRDIORA
Address: H'FFFFC5, H'FFFFCC
Bit:
Value after reset:
b7
b6

IOB2
1
0
b5
b4
IOB[1:0]
0
0
b3
b2

IOA2
1
0
0
b1
b0
b1
IOA[1:0]
0
TRDIORC
Address: H'FFFFD6, H'FFFFCD
Bit:
Value after reset:
b7
b6
IOD3
IOD2
2
0
b5
b4
IOD[1:0]
0
b3
b2
IOC3
IOC2
1
0
0
b0
IOC[1:0]
0
0
• TRDIORA
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is read as 1. The write value should be 1.

6
IOB2
I/O control B2 Selects the GRB function.
R/W
0: GRB functions as an output compare register
1: GRB functions as an input capture register
5, 4
IOB[1:0]
I/O control B1 When IOB2 = 0,
and B0
00: No output at compare match
R/W
01: 0 output to the FTIOB pin at GRB compare
match
10: 1 output to the FTIOB pin at GRB compare
match
11: Output toggles to the FTIOB pin at GRB compare
match
When IOB2 = 1,
00: Input capture to GRB at rising edge at the FTIOB
pin
01: Input capture to GRB at falling edge at the FTIOB
pin
1X: Input capture to GRB at rising and falling edges
at the FTIOB pin
Rev. 1.00 Oct. 03, 2008 Page 521 of 962
REJ09B0465-0100
Section 16 Timer RD
Bit
Symbol
Bit Name
Description
R/W
3

Reserved
This bit is read as 1. The write value should be 1.

2
IOA2
I/O control A2 Selects the GRA function.
R/W
0: GRA functions as an output compare register
1: GRA functions as an input capture register
1, 0
IOA[1:0]
I/O control A1 When IOA2 = 0,
and A0
00: No output at compare match
R/W
01: 0 output to the FTIOA pin at GRA compare
match
10: 1 output to the FTIOA pin at GRA compare
match
11: Output toggles to the FTIOA pin at GRA compare
match
When IOA2 = 1,
00: Input capture to GRA at rising edge at the FTIOA
pin
01: Input capture to GRA at falling edge at the FTIOA
pin
1X: Input capture to GRA at rising and falling edges
at the FTIOA pin
[Legend]
X:
Don't care.
Notes: 1. When a GR register functions as a buffer register for a paired GR register, the settings
in the IOA2 and IOB2 bits in TRDIORA and the IOC2 and IOD2 bits in TRDIORC of
both registers should be the same. The IOA3 bit exists only in TRDIORA_0.
2. In PWM mode, PWM3 mode, complementary PWM mode, and reset synchronous
PWM mode, the settings of TRDIORA are invalid.
TRDIORA selects whether GRA or GRB is used as an output compare register or an input capture
register. When an output compare register is selected, the output setting is selected. When an input
capture register is selected, an input edge of an input capture signal is selected. TRDIORA also
selects the function of FTIOA or FTIOB pin.
Rev. 1.00 Oct. 03, 2008 Page 522 of 962
REJ09B0465-0100
Section 16 Timer RD
• TRDIORC
Bit
Symbol
Bit Name
Description
R/W
7
IOD3
I/O control D3 Specifies GRD to be used as GR for the FTIOB or
FTIOD pin.
R/W
0: GRD is used as GR for the FTIOB pin
1: GRD is used as GR for the FTIOD pin
6
IOD2
I/O control D2 Selects the GRD function.
R/W
0: GRD functions as an output compare register
1: GRD functions as an input capture register
5, 4
IOD[1:0]
I/O control D1 When IOD3 = 0,
and D0
00: No output at compare match
R/W
01: 0 output to the FTIOB pin at GRD compare
match
10: 1 output to the FTIOB pin at GRD compare
match
11: Output toggles to the FTIOB pin at GRD compare
match
When IOD3 = 1 and IOD2 = 0,
00: No output at compare match
01: 0 output to the FTIOD pin at GRD compare
match
10: 1 output to the FTIOD pin at GRD compare
match
11: Output toggles to the FTIOD pin at GRD
compare match
When IOD3 = 1 and IOD2 = 1,
00: Input capture to GRD at rising edge at the FTIOD
pin
01: Input capture to GRD at falling edge at the
FTIOD pin
1X: Input capture to GRD at rising and falling edges
at the FTIOD pin
3
IOC3
I/O control C3 Specifies GRC to be used as GR for the FTIOA or
FTIOC pin.
R/W
0: GRC is used as GR for the FTIOA pin
1: GRC is used as GR for the FTIOC pin
Rev. 1.00 Oct. 03, 2008 Page 523 of 962
REJ09B0465-0100
Section 16 Timer RD
Bit
Symbol
Bit Name
Description
2
IOC2
I/O control C2 Selects the GRC function.
R/W
R/W
0: GRC functions as an output compare register
1: GRC functions as an input capture register
1, 0
IOC[1:0]
I/O control C1 When IOC3 = 0,
and C0
00: No output at compare match
R/W
01: 0 output to the FTIOA pin at GRC compare
match
10: 1 output to the FTIOA pin at GRC compare
match
11: Output toggles to the FTIOA pin at GRC compare
match
When IOC3 = 1 and IOC2 = 0,
00: No output at compare match
01: 0 output to the FTIOC pin at GRC compare
match
10: 1 output to the FTIOC pin at GRC compare
match
11: Output toggles to the FTIOC pin at GRC
compare match
When IOC3 = 1 and IOC2 = 1,
00: Input capture to GRC at rising edge at the FTIOC
pin
01: Input capture to GRC at falling edge at the
FTIOC pin
1X: Input capture to GRC at rising and falling edges
at the FTIOC pin
[Legend]
X:
Don't care.
Notes: 1. When a GR register functions as a buffer register for a paired GR register, the settings
in the IOA2 and IOB2 bits in TRDIORA and the IOC2 and IOD2 bits in TRDIORC of
both registers should be the same.
2. In PWM mode, PWM3 mode, complementary PWM mode, and reset synchronous
PWM mode, the settings of TRDIORC are invalid.
TRDIORC selects whether GRC or GRD is used as an output compare register or an input capture
register. When an output compare register is selected, the output setting is selected. When an input
capture register is selected, an input edge of an input capture signal is selected. TRDIORC also
selects the function of the FTIOA to FTIOD pins.
Rev. 1.00 Oct. 03, 2008 Page 524 of 962
REJ09B0465-0100
Section 16 Timer RD
16.2.13 Timer RD Status Register (TRDSR)
Address: H'FFFFC7, H'FFFFCE
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0


UDF
OVF
IMFD
IMFC
IMFB
IMFA
1
1
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7, 6

Reserved
These bits are read as 1. The write value should be
1.

5
UDF*
Underflow flag 0: TRDCNT_1 has not underflowed.
R/W
1: TRDCNT_1 has underflowed.
[Setting condition]
• When TRDCNT underflows
[Clearing condition]
•
4
OVF
Overflow flag
When 0 is written to UDF after reading UDF = 1
0: TRDCNT has not overflowed.
R/W
1: TRDCNT has overflowed.
[Setting condition]
• When TRDCNT value is underflowed
[Clearing condition]
When 0 is written to OVF after reading OVF = 1
3
IMFD
Input capture/ [Setting conditions]
compare
• When TRDCNT = GRD and GRD is functioning
match flag D
as output compare register
• When TRDCNT = GRD while the FTIOD pin
operates in PWM mode
• When TRDCNT = GRD in PWM3 mode, reset
synchronous PWM mode, or complementary
PWM mode
• When TRDCNT value is transferred to GRD by
input capture signal and GRD is functioning as
input capture register
[Clearing conditions]
•
When the DTC is activated by an IMFD interrupt
and the DISEL bit in MRB of the DTC is 0
•
When 0 is written to IMFD after reading IMFD = 1
R/W
Rev. 1.00 Oct. 03, 2008 Page 525 of 962
REJ09B0465-0100
Section 16 Timer RD
Bit
Symbol
Bit Name
Description
2
IMFC
Input capture/ [Setting conditions]
compare
• When TRDCNT = GRC and GRC is functioning
match flag C
as output compare register
•
When TRDCNT = GRC while the FTIOC pin
operates in PWM mode
•
When TRDCNT = GRC in PWM3 mode, reset
synchronous PWM mode, or complementary
PWM mode
•
When TRDCNT value is transferred to GRC by
input capture signal and GRC is functioning as
input capture register
R/W
R/W
[Clearing conditions]
1
IMFB
•
When the DTC is activated by an IMFC interrupt
and the DISEL bit in MRB of the DTC is 0
•
When 0 is written to IMFC after reading IMFC = 1
Input capture/ [Setting conditions]
compare
• When TRDCNT = GRB and GRB is functioning
match flag B
as output compare register
•
When TRDCNT = GRB while the FTIOB pin
operates in PWM mode
•
When TRDCNT = GRB in PWM mode, PWM3
mode, reset synchronous PWM mode, or
complementary PWM mode (in reset
synchronous PWM mode, however, while
TRDCNT_0 = GRB_1 and TRDCNT_0 = GRB_0)
•
When TRDCNT value is transferred to GRB by
input capture signal and GRB is functioning as
input capture register
[Clearing conditions]
•
When the DTC is activated by an IMFB interrupt
and the DISEL bit in MRB of the DTC is 0
•
When 0 is written to IMFB after reading IMFB = 1
Rev. 1.00 Oct. 03, 2008 Page 526 of 962
REJ09B0465-0100
R/W
Section 16 Timer RD
Bit
Symbol
Bit Name
Description
R/W
0
IMFA
Input capture/ [Setting conditions]
compare
• When TRDCNT = GRA and GRA is functioning
match flag A
as output compare register
•
When TRDCNT = GRA in PWM mode, PWM3
mode, reset synchronous PWM mode, or
complementary PWM mode (in reset
synchronous PWM mode, however, while
TRDCNT_0 = GRA_1 and TRDCNT_0 = GRA_0)
•
When TRDCNT value is transferred to GRA by
input capture signal and GRA is functioning as
input capture register
R/W
[Clearing conditions]
Note:
*
•
When the DTC is activated by an IMFA interrupt
and the DISEL bit in MRB of the DTC is 0
•
When 0 is written to IMFA after reading IMFA = 1
Bit 5 is not the UDF flag in TRDSR_0. It is a reserved bit. It is always read as 1.
TRDSR is each interrupt request flag of the timer RD. If an interrupt is enabled by a
corresponding bit in TRDIER, TRDSR requests an interrupt for the CPU. Timer RD has two
TRDSR registers, one for each channel.
Rev. 1.00 Oct. 03, 2008 Page 527 of 962
REJ09B0465-0100
Section 16 Timer RD
16.2.14 Timer RD Interrupt Enable Register (TRDIER)
Address: H'FFFFC8, H'FFFFCF
Bit:
Value after reset:
Bit
Symbol
b7
b6
b5
b4
b3
b2
b1
b0



OVIE
IMIED
IMIEC
IMIEB
IMIEA
1
1
1
0
0
0
0
0
Bit Name
Description
R/W
7 to 5 
Reserved
These bits are read as 1. The write value should be 1.

4
Overflow interrupt 0: Interrupt requests (OVI) by OVF or UDF flag are
enable
disabled.
OVIE
R/W
1: Interrupt requests (OVI) by OVF or UDF flag are
enabled.
3
IMIED
Input capture/
0: Interrupt requests (IMID) by IMFD flag are disabled. R/W
compare match
1: Interrupt requests (IMID) by IMFD flag are enabled.
interrupt enable D
2
IMIEC
Input capture/
0: Interrupt requests (IMIC) by IMFC flag are disabled. R/W
compare match
1: Interrupt requests (IMIC) by IMFC flag are enabled.
interrupt enable C
1
IMIEB
Input capture/
0: Interrupt requests (IMIB) by IMFB flag are disabled.
compare match
1: Interrupt requests (IMIB) by IMFB flag are enabled.
interrupt enable B
R/W
0
IMIEA
Input capture/
0: Interrupt requests (IMIA) by IMFA flag are disabled.
compare match
1: Interrupt requests (IMIA) by IMFA flag are enabled.
interrupt enable A
R/W
Timer RD has two TRDIER registers, one for each channel.
Rev. 1.00 Oct. 03, 2008 Page 528 of 962
REJ09B0465-0100
Section 16 Timer RD
16.2.15 PWM Mode Output Level Control Register (POCR)
Address: H'FFFFC9, H'FFFFD0
Bit:
b7
b6
b5
b4
b3
b2
b1
b0





POLD
POLC
POLB
Value after reset:
1
1
1
1
1
0
0
0
Bit
Bit Name
Description
R/W
7 to 3 
Reserved
These bits are read as 1. The write value should
be 1.

2
PWM mode output
level control D
0: The output level of FTIOD is active low.
R/W
PWM mode output
level control C
0: The output level of FTIOC is active low.
PWM mode output
level control B
0: The output level of FTIOB is active low.
1
0
Symbol
POLD
POLC
POLB
1: The output level of FTIOD is active high.
R/W
1: The output level of FTIOC is active high.
R/W
1: The output level of FTIOB is active high.
Timer RD has two POCR registers, one for each channel.
Rev. 1.00 Oct. 03, 2008 Page 529 of 962
REJ09B0465-0100
Section 16 Timer RD
16.2.16 Timer RD Digital Filtering Function Select Register (TRDDF)
Address: H'FFFFCA, H'FFFFD1
Bit:
b7
Value after reset:
0
b6
DFCK[1:0]
0
b5
b4
b3
b2
b1
b0


DFD
DFC
DFB
DFA
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7, 6
DFCK[1:0]
Digital filter clock
select
00: φ/32
R/W
01: φ/8
10: φ
11: Clock specified by bits TPSC2 to TPSC0 in
TRDCR
5, 4

Reserved
These bits are read as 0. The write value should
be 0.

3
DFD
Digital filter
function D
0: Disables the digital filter for the FTIOD pin
R/W
Digital filter
function C
0: Disables the digital filter for the FTIOC pin
Digital filter
function B
0: Disables the digital filter for the FTIOB pin
Digital filter
function A
0: Disables the digital filter for the FTIOA pin
2
1
0
DFC
DFB
DFA
1: Enables the digital filter for the FTIOD pin
R/W
1: Enables the digital filter for the FTIOC pin
R/W
1: Enables the digital filter for the FTIOB pin
R/W
1: Enables the digital filter for the FTIOA pin
Note: The setting in this register is valid on the corresponding pin when the FTIOA to FTIOD
inputs are enabled by TRDIORA and TRDIORC.
Timer RD has two TRDDF registers, one for each channel.
Rev. 1.00 Oct. 03, 2008 Page 530 of 962
REJ09B0465-0100
Section 16 Timer RD
16.2.17 Interface with CPU
(1)
16-Bit Register
TRDCNT and GR are 16-bit registers. Reading/writing in a 16-bit unit is enabled but disabled in
an 8-bit unit since the data bus with the CPU is 16-bit width. These registers must always be
accessed in a 16-bit unit. Figure 16.5 shows an example of accessing the 16-bit registers.
Internal data bus
H
C
P
L
Module data bus
Bus interface
U
TRDCNTH
TRDCNTL
Figure 16.5 Accessing Operation of 16-Bit Register (between CPU and TRDCNT (16 bits))
(2)
8-Bit Register
Registers other than TRDCNT and GR are 8-bit registers that are connected internally with the
CPU in an 8-bit width. Figure 16.6 shows an example of accessing the 8-bit registers.
Internal data bus
H
C
P
L
Module data bus
Bus interface
U
TRDSTR
Figure 16.6 Accessing Operation of 8-Bit Register (between CPU and TRDSTR (8 bits))
Rev. 1.00 Oct. 03, 2008 Page 531 of 962
REJ09B0465-0100
Section 16 Timer RD
16.3
Operation
Timer RD has the following operating modes.
• Timer mode operation
Enables output compare and input capture functions by setting the IOA2 to IOA0 and IOB2 to
IOB0 bits in TRDIORA and the IOC3 to IOC0 and IOD3 to IOD0 bits in TRDIORC
• PWM mode operation
Enables PWM mode operation by setting TRDPMR
• PWM3 mode operation
Enables PWM3 mode operation by setting the PWM3 bit in TRDFCR
• Reset synchronous PWM mode operation
Enables reset synchronous PWM mode operation by setting the CMD1 and CMD0 bits in
TRDFCR
• Complementary PWM mode operation
Enables complementary PWM mode operation by setting the CMD1 and CMD0 bits in
TRDFCR
The following tables show the operating modes of the FTIOA0 to FTIOD0 and FTIOA1 to
FTIOD1 pins set by the appropriate bits in the registers mentioned above. Set 1 to the PMR bits
corresponding to the pins allocated by the PMC.
Rev. 1.00 Oct. 03, 2008 Page 532 of 962
REJ09B0465-0100
Section 16 Timer RD
• FTIOA0 pin
Register
Name
TRDOER1
Bit Name
EA0
STCLK
CMD1,
CMD0
PWM3
IOA2 to
IOA0
Setting
values
0
0
00
0
XXX
PWM3 mode waveform
output
0
0
00
1
001, 01X
Timer mode waveform
output (output compare
function)
X
0
00
1
1XX
Timer mode (input capture
function)
X
0
00
1
000
General input port (when
the corresponding pin PCR
= 0)
X
1
XX
X
0XX
External clock input
TRDFCR
TRDIORA
Other than above
Function
Setting prohibited
Rev. 1.00 Oct. 03, 2008 Page 533 of 962
REJ09B0465-0100
Section 16 Timer RD
• FTIOB0 pin
Register
Name
TRDOER1
Bit Name
EB0
CMD1,
CMD0
Setting
values
0
TRDFCR
TRDPMR
TRDIORA
PWM3
PWMB0
IOB2 to
IOB0
10, 11
X
X
XXX
Complementary PWM
mode waveform output
0
01
X
X
XXX
Reset synchronous
PWM mode waveform
output
0
00
0
X
XXX
PWM3 mode waveform
output
0
00
1
1
XXX
PWM mode waveform
output
0
00
1
0
001, 01X
Timer mode waveform
output (output compare
function)
X
00
1
0
1XX
Timer mode (input
capture function)
X
00
1
0
000
General input port (when
the corresponding pin
PCR = 0)
Other than above
Rev. 1.00 Oct. 03, 2008 Page 534 of 962
REJ09B0465-0100
Function
Setting prohibited
Section 16 Timer RD
• FTIOC0 pin
Register
Name
TRDOER1
Bit Name
EC0
CMD1,
CMD0
Setting
values
0
TRDFCR
TRDPMR
TRDIORC
PWM3
PWMC0
IOC2 to
IOC0
10, 11
X
X
XXX
Complementary PWM
mode waveform output
0
01
X
X
XXX
Reset synchronous
PWM mode waveform
output
0
00
1
1
XXX
PWM mode waveform
out
0
00
1
0
001, 01X
Timer mode waveform
output (output compare
function)
X
00
1
0
1XX
Timer mode (input
capture function)
X
00
1
0
000
General input port (when
the corresponding pin
PCR = 0)
Other than above
Function
Setting prohibited
Rev. 1.00 Oct. 03, 2008 Page 535 of 962
REJ09B0465-0100
Section 16 Timer RD
• FTIOD0 pin
Register
Name
TRDOER1
Bit Name
ED0
CMD1,
CMD0
Setting
values
0
TRDFCR
TRDPMR
TRDIORC
PWM3
PWMD0
IOD2 to
IOD0
10, 11
X
X
XXX
Complementary PWM
mode waveform output
0
01
X
X
XXX
Reset synchronous
PWM mode waveform
output
0
00
1
1
XXX
PWM mode waveform
out
0
00
1
0
001, 01X
Timer mode waveform
output (output compare
function)
X
00
1
0
1XX
Timer mode (input
capture function)
X
00
1
0
000
General input port (when
the corresponding pin
PCR = 0)
Other than above
Rev. 1.00 Oct. 03, 2008 Page 536 of 962
REJ09B0465-0100
Function
Setting prohibited
Section 16 Timer RD
• FTIOA1 pin
Register
Name
TRDOER1
Bit Name
EA1
CMD1,
CMD0
PWM3
IOA2 to
IOA0
Setting
values
0
10, 11
X
XXX
Complementary PWM mode waveform
output
0
01
X
XXX
Reset synchronous PWM mode
waveform output
0
00
1
001, 01X
Timer mode waveform output (output
compare function)
X
00
1
1XX
Timer mode (input capture function)
X
00
1
000
General input port (when the
corresponding pin PCR = 0)
TRDFCR
Other than above
TRDIORA
Function
Setting prohibited
Rev. 1.00 Oct. 03, 2008 Page 537 of 962
REJ09B0465-0100
Section 16 Timer RD
• FTIOB1 pin
Register
Name
TRDOER1
Bit Name
EB1
CMD1,
CMD0
Setting
values
0
TRDFCR
TRDPMR
TRDIORA
PWM3
PWMB1
IOB2 to
IOB0
10, 11
X
X
XXX
Complementary PWM
mode waveform output
0
01
X
X
XXX
Reset synchronous PWM
mode waveform output
0
00
1
1
XXX
PWM mode waveform out
0
00
1
0
001, 01X
Timer mode waveform
output (output compare
function)
X
00
1
0
1XX
Timer mode (input capture
function)
X
00
1
0
000
General input port (when
the corresponding pin
PCR = 0)
Other than above
Rev. 1.00 Oct. 03, 2008 Page 538 of 962
REJ09B0465-0100
Function
Setting prohibited
Section 16 Timer RD
• FTIOC1 pin
Register
Name
TRDOER1
Bit Name
EC1
CMD1,
CMD0
Setting
values
0
TRDFCR
TRDPMR
TRDIORC
PWM3
PWMC1
IOC2 to
IOC0
10, 11
X
X
XXX
Complementary PWM
mode waveform output
0
01
X
X
XXX
Reset synchronous PWM
mode waveform output
0
00
1
1
XXX
PWM mode waveform out
0
00
1
0
001, 01X
Timer mode waveform
output (output compare
function)
X
00
1
0
1XX
Timer mode (input capture
function)
X
00
1
0
000
General input port (when
the corresponding pin
PCR = 0)
Other than above
Function
Setting prohibited
Rev. 1.00 Oct. 03, 2008 Page 539 of 962
REJ09B0465-0100
Section 16 Timer RD
• FTIOD1 pin
Register
Name
TRDOER1
Bit Name
ED1
CMD1,
CMD0
Setting
values
0
TRDFCR
TRDPMR
TRDIORC
PWM3
PWMD1
IOD2 to
IOD0
10, 11
X
X
XXX
Complementary PWM
mode waveform output
0
01
X
X
XXX
Reset synchronous PWM
mode waveform output
0
00
1
1
XXX
PWM mode waveform out
0
00
1
0
001, 01X
Timer mode waveform
output (output compare
function)
X
00
1
0
1XX
Timer mode (input capture
function)
X
00
1
0
000
General input port (when
the corresponding pin
PCR = 0)
Other than above
Rev. 1.00 Oct. 03, 2008 Page 540 of 962
REJ09B0465-0100
Function
Setting prohibited
Section 16 Timer RD
16.3.1
Counter Operation
When one of bits STR0 and STR1 in TRDSTR is set to 1, the TRDCNT counter for the
corresponding channel begins counting. TRDCNT can operate as a free-running counter, periodic
counter, for example. Figure 16.7 shows an example of the counter operation setting procedure.
[1]
Operation selection
Select counter clock
[1]
[2]
Periodic counter
Free-running counter
[3]
Select counter clearing source
[2]
Select output compare register
[3]
Set period
[4]
Start count operation
[5]
[4]
[5]
Select the counter clock with bits
TPSC2 to TPSC0 in TRDCR. When
an external clock is selected, select
the external clock edge with bits
CKEG1 and CKEG0 in TRDCR.
For periodic counter operation, select
the TRDCNT clearing source with bits
CCLR2 to CCLR0 in TRDCR.
Designate the general register
selected in [2] as an output compare
register by means of TRDIOR.
Set the periodic counter cycle in the
general register selected in [2].
Set the STR bit in TRDSTR to 1 to
start the counter operation.
Figure 16.7 Example of Counter Operation Setting Procedure
Rev. 1.00 Oct. 03, 2008 Page 541 of 962
REJ09B0465-0100
Section 16 Timer RD
(1)
Free-Running Count Operation and Periodic Count Operation
Immediately after a reset, the TRDCNT counters for channels 0 and 1 are all designated as freerunning counters. When the relevant bit in TRDSTR is set to 1, the corresponding TRDCNT
counter starts an increment operation as a free-running counter. When TRDCNT overflows, the
OVF flag in TRDSR is set to 1. If the value of the OVIE bit in the corresponding TRDIER is 1 at
this point, timer RD requests an interrupt. After overflow, TRDCNT starts an increment operation
again from H'0000.
Figure 16.8 illustrates free-running counter operation.
TRDCNT value
H'FFFF
H'0000
Time
STR0,
STR1
OVF
Figure 16.8 Free-Running Counter Operation
When compare match is selected as the TRDCNT clearing source, the TRDCNT counter for the
relevant channel performs periodic count operation. The GR registers for setting the period are
designated as output compare registers, and counter clearing by compare match is selected by
means of bits CCLR1 and CCLR0 in TRDCR. After the settings have been made, TRDCNT starts
an increment operation as a periodic counter when the corresponding bit in TRDSTR is set to 1.
When the count value matches the value in GR, the IMFA, IMFB, IMFC, or IMFD flag in TRDSR
is set to 1 and TRDCNT is cleared to H'0000. If the value of the corresponding IMIEA, IMIEB,
IMIEC, or IMIED bit in TRDIER is 1 at this point, timer RD requests an interrupt. After a
compare match, TRDCNT starts an increment operation again from H'0000.
Rev. 1.00 Oct. 03, 2008 Page 542 of 962
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Section 16 Timer RD
Figure 16.9 illustrates periodic counter operation.
TRDCNT value
Counter cleared by GR compare match
GR value
H'0000
Time
STR
IMF
Figure 16.9 Periodic Counter Operation
(2)
TRDCNT Count Timing
• Internal clock operation
A system clock (φ), four types of clocks (φ/2, φ/4, φ/8, or φ/32) that are generated by dividing
the system clock, or on-chip oscillator clock (φ40M) can be selected by bits TPSC2 to TPSC0
in TRDCR.
Figure 16.10 illustrates this timing.
φ
Internal clock
TRDCNT input
TRDCNT
N -1
N+1
N
Figure 16.10 Count Timing in Internal Clock Operation
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Section 16 Timer RD
• External clock operation
An external clock input pin (TCLK) can be selected by bits TPSC2 to TPSC0 in TRDCR, and
a detection edge can be selected by bits CKEG1 and CKEG0. To detect an external clock, the
rising edge, falling edge, or both edges can be selected.
Figure 16.11 illustrates the detection timing of the rising and falling edges.
φ
External clock
input pin
TRDCNT input
TRDCNT
N-1
N
N+1
Figure 16.11 Count Timing in External Clock Operation (Both Edges Detected)
16.3.2
Waveform Output by Compare Match
Timer RD can perform 0, 1, or toggle output from the corresponding FTIOA, FTIOB, FTIOC, or
FTIOD output pin using compare match A, B, C, or D.
Figure 16.12 shows an example of the setting procedure for waveform output by compare match.
Output selection
Select waveform output mode
[1]
Set output timing
[2]
Enable waveform output
[3]
[1]
[2]
[3]
Start count operation
[4]
[4]
Select 0 output, 1 output, or toggle
output as a compare much output, by
means of TRDIOR. The initial values set
in TRDOCR are output unit the first
compare match occurs.
Set the timing for compare match
generation in GRA/GRB/GRC/GRD.
Enable or disable the timer output by
TRDOER1.
Set the STR bit in TRDSTR to 1 to start
the TRDCNT count operation.
<Waveform output>
Figure 16.12 Example of Setting Procedure for Waveform Output by Compare Match
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Section 16 Timer RD
(1)
Examples of Waveform Output Operation
Figure 16.13 shows an example of 0 output/1 output.
In this example, TRDCNT has been designated as a free-running counter, and settings have been
made such that 0 is output by compare match A, and 1 is output by compare match B. When the
set level and the pin level coincide, the pin level does not change.
TRDCNT value
H'FFFF
Time
H'0000
FTIOB
FTIOA
No change
No change
No change
No change
Figure 16.13 Example of 0 Output/1 Output Operation
Figure 16.14 shows an example of toggle output.
In this example, TRDCNT has been designated as a periodic counter (with counter clearing on
compare match B), and settings have been made such that the output is toggled by both compare
match A and compare match B.
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Section 16 Timer RD
TRDCNT value
GRB
GRA
Time
H'0000
FTIOB
Toggle output
FTIOA
Toggle output
Figure 16.14 Example of Toggle Output Operation
(2)
Output Compare Timing
The compare match signal is generated in the last state in which TRDCNT and GR match (when
TRDCNT changes from the matching value to the next value). When the compare match signal is
generated, the output value selected in TRDIOR is output at the compare match output pin
(FTIOA, FTIOB, FTIOC, or FTIOD). When TRDCNT matches GR, the compare match signal is
generated only after the next TRDCNT input clock pulse is input.
Figure 16.15 shows an example of the output compare timing.
φ
TRDCNT input
TRDCNT
N
GR
N
N+1
Compare match
signal
FTIOA to FTIOD
Figure 16.15 Output Compare Timing
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Section 16 Timer RD
16.3.3
Input Capture Function
The TRDCNT value can be transferred to GR on detection of the input edge of the input
capture/output compare pin (FTIOA, FTIOB, FTIOC, or FTIOD). Rising edge, falling edge, or
both edges can be selected as the detected edge. When the input capture function is used, the pulse
width or period can be measured.
Figure 16.16 shows an example of the input capture operation setting procedure.
Input selection
Select input edge of
input capture
[1]
Start counter operation
[2]
[1]
[2]
Designate GR as an input capture register
by means of TRDIOR, and select rising
edge, falling edge, or both edges as the
input edge of the input capture signal.
Set the STR bit in TRDSTR to 1 to start the
TRDCNT counter operation.
<Input capture operation>
Figure 16.16 Example of Input Capture Operation Setting Procedure
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REJ09B0465-0100
Section 16 Timer RD
(1)
Example of Input Capture Operation
Figure 16.17 shows an example of input capture operation.
In this example, both rising and falling edges have been selected as the FTIOA pin input capture
input edge, the falling edge has been selected as the FTIOB pin input capture input edge, and
counter clearing by GRB input capture has been designated for TRDCNT.
Counter cleared by FTIOB input (falling edge)
TRDCNT value
H'0180
H'0160
H'0005
H'0000
Time
FTIOB
FTIOA
H'0005
GRA
GRB
H'0160
H'0180
Figure 16.17 Example of Input Capture Operation
Rev. 1.00 Oct. 03, 2008 Page 548 of 962
REJ09B0465-0100
Section 16 Timer RD
(2)
Input Capture Signal Timing
Input capture on the rising edge, falling edge, or both edges can be selected through settings in
TRDIOR. Figure 16.18 shows the timing when the rising edge is selected.
φ
Input capture input
Input capture signal
TRDCNT
N
GR
N
Figure 16.18 Input Capture Signal Timing
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Section 16 Timer RD
16.3.4
Synchronous Operation
In synchronous operation, the values in a number of TRDCNT counters can be rewritten
simultaneously (synchronous presetting). Also, a number of TRDCNT counters can be cleared
simultaneously by making the appropriate setting in TRDCR (synchronous clearing). Synchronous
operation enables GR to be increased with respect to a single time base.
Figure 16.19 shows an example of the synchronous operation setting procedure.
Synchronous operation
selection
Set synchronous
operation
[1]
Synchronous clearing
Synchronous presetting
Set TRDCNT
[2]
Clearing
source generation
channel?
No
Yes
<Synchronous presetting>
[1]
[2]
[3]
[4]
[5]
Select counter
clearing source
[3]
Select counter
clearing source
[4]
Start counter operation
[5]
Start counter operation
[5]
<Counter clearing>
<Synchronous clearing>
Set the SYNC bits in TRDMDR to 1.
When a value is written to either of the TRDCNT counters, the same value is simultaneously written to the other
TRDCNT counter.
Set bits CCLR1 and CCLR0 in TRDCR to specify counter clearing by compare match/input capture.
Set bits CCLR1 and CCLR0 in TRDCR to designate synchronous clearing for the counter clearing source.
Set the STR bit in TRDSTR to 1 to start the count operation.
Figure 16.19 Example of Synchronous Operation Setting Procedure
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Section 16 Timer RD
Figure 16.20 shows an example of synchronous operation. In this example, synchronous operation
has been selected, FTIOB0 and FTIOB1 have been designated for PWM mode, GRA_0 compare
match has been set as the channel 0 counter clearing source, and synchronous clearing has been set
for the channel 1 counter clearing source. The same input clock has been set for the channel 0 and
channel 1 counter input clocks. Two-phase PWM waveforms are output from pins FTIOB0 and
FTIOB1. At this time, synchronous presetting and synchronous operation by GRA_0 compare
match are performed by TRDCNT counters.
For details on PWM mode, see section 16.3.5, PWM Mode.
TRDCNT values
Synchronous clearing by GRA_0 compare match
GRA_0
GRA_1
GRB_0
GRB_1
H'0000
Time
FTIOB0
FTIOB1
Figure 16.20 Example of Synchronous Operation
16.3.5
PWM Mode
In PWM mode, PWM waveforms are output from the FTIOB, FTIOC, and FTIOD output pins
with GRA as a cycle register and GRB, GRC, and GRD as duty registers. The initial output level
of the corresponding pin depends on the setting values of TRDOCR and POCR. Table 16.4 shows
an example of the initial output level of the FTIOB0 pin.
The output level is determined by the POLB to POLD bits corresponding to POCR. When POLB
is 0, the FTIOB output pin is set to 0 by compare match B and set to 1 by compare match A. When
POLB is 1, the FTIOB output pin is set to 1 by compare match B and cleared to 0 by compare
match A. In PWM mode, maximum 6-phase PWM outputs are possible.
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Section 16 Timer RD
Figure 16.21 shows an example of the PWM mode setting procedure.
Table 16.4 Initial Output Level of FTIOB0 Pin
TOB0
POLB
Initial Output Level
0
0
1
0
1
0
1
0
0
1
1
1
PWM mode
Select counter clock
[1]
Select counter clearing source
[2]
Set PWM mode
[3]
Set initial output level
[4]
Select output level
[5]
Set GR
Enable waveform output
Start counter operation
[1]
Select the counter clock with bits TPSC2 to
TOSC0 in TRDCR. When an external clock
is selected, select the external clock edge
with bits CKEG1 and CKEG0 in TRDCR.
[2]
Use bits CCLR2 to CCLR0 in TRDCR to
select the counter clearing source.
[3]
Select the PWM mode with bits PWMB0 to
PWMD0 and PWMB1 to PWMD1 in
TRDPMR.
[4]
Set the initial output value with bits TOB0 to
TOD0 and TOB1 to TOD1 in TRDOCR.
[5]
Set the output level with bits POLB to POLD
in POCR.
[6]
Set the cycle in GRA, and set the duty in the
other GR.
[7]
Enable or disable the timer output by
TRDOER1.
[8]
Set the STR bit in TRDSTR to 1 and start the
counter operation.
[6]
[7]
[8]
<PWM mode>
Figure 16.21 Example of PWM Mode Setting Procedure
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Section 16 Timer RD
Figure 16.22 shows an example of operation in PWM mode. The output signals go to 1 and
TRDCNT is reset at compare match A, and the output signals go to 0 at compare match B, C, and
D (TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 0).
TRDCNT value
Counter cleared by GRA compare match
GRA
GRB
GRC
GRD
H'0000
Time
FTIOB
FTIOC
FTIOD
Figure 16.22 Example of PWM Mode Operation (1)
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Section 16 Timer RD
Figure 16.23 shows another example of operation in PWM mode. The output signals go to 0 and
TRDCNT is reset at compare match A, and the output signals go to 1 at compare match B, C, and
D (TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 1).
TRDCNT value
Counter cleared by GRA compare match
GRA
GRB
GRC
GRD
H'0000
Time
FTIOB
FTIOC
FTIOD
Figure 16.23 Example of PWM Mode Operation (2)
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Section 16 Timer RD
Figures 16.24 (when TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 0) and 16.25 (when
TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 1) show examples of the output of PWM
waveforms with duty cycles of 0% and 100% in PWM mode.
TRDCNT value
GRB rewritten
GRA
GRB
GRB rewritten
Time
H'0000
0% duty
FTIOB
TRDCNT value
GRB rewritten
When cycle register and duty register compare matches
occur simultaneously, duty register compare match has
priority.
GRA
GRB rewritten
GRB
rewritten
GRB
H'0000
Time
FTIOB
100% duty
When cycle register and duty register compare matches
occur simultaneously, duty register compare match has
priority.
TRDCNT value
GRB rewritten
GRB rewritten
GRA
GRB rewritten
GRB
H'0000
FTIOB
Time
100% duty
0% duty
Figure 16.24 Example of PWM Mode Operation (3)
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Section 16 Timer RD
TRDCNT value
GRB rewritten
GRA
GRB
rewritten
GRB
H'0000
Time
FTIOB
0% duty
TRDCNT value
GRB rewritten
When cycle register and duty register compare matches
occur simultaneously, duty register compare match has
priority.
GRA
GRB rewritten
GRB
rewritten
GRB
Time
H'0000
100% duty
FTIOB
TRDCNT value
GRB rewritten
When cycle register and duty register compare matches
occur simultaneously, duty register compare match has
priority.
GRB rewritten
GRA
GRB rewritten
GRB
Time
H'0000
100% duty
FTIOB
0% duty
Figure 16.25 Example of PWM Mode Operation (4)
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Section 16 Timer RD
16.3.6
Reset Synchronous PWM Mode
Three normal- and counter-phase PWM waveforms are output by combining channels 0 and 1 that
one of changing points of waveforms will be common.
In reset synchronous PWM mode, the FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1 pins become
PWM-output pins automatically. TRDCNT_0 performs an increment operation. Tables 16.5 and
16.6 show the PWM-output pins used and the register settings, respectively.
Figure 16.29 shows the example of reset synchronous PWM mode setting procedure.
Table 16.5 Output Pins in Reset Synchronous PWM Mode
Channel
Pin Name
Input/Output
Pin Function
0
FTIOC0
Output
Toggle output in synchronous with PWM cycle
0
FTIOB0
Output
PWM output 1
0
FTIOD0
Output
PWM output 1 (counter-phase waveform of PWM
output 1)
1
FTIOA1
Output
PWM output 2
1
FTIOC1
Output
PWM output 2 (counter-phase waveform of PWM
output 2)
1
FTIOB1
Output
PWM output 3
1
FTIOD1
Output
PWM output 3 (counter-phase waveform of PWM
output 3)
Table 16.6 Register Settings in Reset Synchronous PWM Mode
Register
Description
TRDCNT_0
Initial setting of H'0000
TRDCNT_1
Not used (independently operates)
GRA_0
Sets counter cycle of TRDCNT_0
GRB_0
Set a changing point of the PWM waveform output from pins FTIOB0 and
FTIOD0.
GRA_1
Set a changing point of the PWM waveform output from pins FTIOA1 and
FTIOC1.
GRB_1
Set a changing point of the PWM waveform output from pins FTIOB1 and
FTIOD1.
Rev. 1.00 Oct. 03, 2008 Page 557 of 962
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Section 16 Timer RD
[1] Clear bit STR0 in TRDSTR to 0 and stop the
counter operation of TRDCNT_0. Set reset
synchronous PWM mode after TRDCNT_0
stops.
Reset synchronous PWM mode
Stop counter operation
[1]
Select counter clock
[2]
Select counter clearing source
[3]
Set reset synchronous PWM mode
[4]
Set TRDCNT
[5]
Set GR
[3] Use bits CCLR2 to CCLR0 in TRDCR to
select counter clearing source GRA_0.
[4] Select the reset synchronous PWM mode
with bits CMD1 and CMD0 in TRDFCR.
FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1
become PWM output pins automatically.
[5] Set TRDCNT_0 as H'0000. TRDCNT_1
does not need to be set.
[6]
Enable waveform output
[7]
Start counter operation
[8]
<Reset synchronous PWM mode>
[2] Select the counter clock with bits TPSC2 to
TPSC0 in TRDCR. When an external clock
is selected, select the external clock edge
with bits CKEG1 and CKEG0 in TRDCR.
[6] GRA_0 is a cycle register. Set a cycle for
GRA_0. Set the changing point timing of the
PWM output waveform for GRB_0, GRA_1,
and GRB_1.
[7] Enable or disable the timer output by
TRDOER1.
[8] Set the STR bit in TRDSTR to 1 and start
the counter operation.
Figure 16.26 Example of Reset Synchronous PWM Mode Setting Procedure
Rev. 1.00 Oct. 03, 2008 Page 558 of 962
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Section 16 Timer RD
Figures 16.27 and 16.28 show examples of operation in reset synchronous PWM mode.
TRDCNT value
Counter cleared by GRA compare match
GRA_0
GRB_0
GRA_1
GRB_1
H'0000
Time
FTIOB0
FTIOD0
FTIOA1
FTIOC1
FTIOB1
FTIOD1
FTIOC0
Figure 16.27 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 1)
Rev. 1.00 Oct. 03, 2008 Page 559 of 962
REJ09B0465-0100
Section 16 Timer RD
TRDCNT value
Counter cleared by GRA compare match
GRA_0
GRB_0
GRA_1
GRB_1
H'0000
Time
FTIOB0
FTIOD0
FTIOA1
FTIOC1
FTIOB1
FTIOD1
FTIOC0
Figure 16.28 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 0)
In reset synchronous PWM mode, TRDCNT_0 and TRDCNT_1 perform increment and
independent operations, respectively. However, GRA_1 and GRB_1 are separated from
TRDCNT_1. When a compare match occurs between TRDCNT_0 and GRA_0, a counter is
cleared and an increment operation is restarted from H'0000.
The PWM pin outputs 0 or 1 whenever a compare match between GRB_0, GRA_1, GRB_1 and
TRDCNT_0 or counter clearing occur.
For details on operations when reset synchronous PWM mode and buffer operation are
simultaneously set, see section 16.3.9, Buffer Operation.
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Section 16 Timer RD
16.3.7
Complementary PWM Mode
Three PWM waveforms for non-overlapped normal and counter phases are output by combining
channels 0 and 1.
In complementary PWM mode, the FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1 pins become
PWM-output pins automatically. TRDCNT_0 and TRDCNT_1 perform an increment or
decrement operation. Tables 16.7 and 16.8 show the output pins and register settings in
complementary PWM mode, respectively.
Figure 16.29 shows the example of complementary PWM mode setting procedure.
Table 16.7 Output Pins in Complementary PWM Mode
Channel
Pin Name
Input/Output
Pin Function
0
FTIOC0
Output
Toggle output in synchronous with PWM cycle
0
FTIOB0
Output
PWM output 1
0
FTIOD0
Output
PWM output 1 (counter-phase waveform nonoverlapped with PWM output 1)
1
FTIOA1
Output
PWM output 2
1
FTIOC1
Output
PWM output 2 (counter-phase waveform nonoverlapped with PWM output 2)
1
FTIOB1
Output
PWM output 3
1
FTIOD1
Output
PWM output 3 (counter-phase waveform nonoverlapped with PWM output 3)
Table 16.8 Register Settings in Complementary PWM Mode
Register
Description
TRDCNT_0
Initial setting of non-overlapped periods (non-overlapped periods are differences
with TRDCNT_1)
TRDCNT_1
Initial setting of H'0000
GRA_0
Sets (upper limit value – 1) of TRDCNT_0
GRB_0
Set a changing point of the PWM waveform output from pins FTIOB0 and
FTIOD0.
GRA_1
Set a changing point of the PWM waveform output from pins FTIOA1 and
FTIOC1.
GRB_1
Set a changing point of the PWM waveform output from pins FTIOB1 and
FTIOD1.
Rev. 1.00 Oct. 03, 2008 Page 561 of 962
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Section 16 Timer RD
[1]
Complementary PWM mode
Stop counter operation
[1]
[2]
Select counter clock
[2]
Set complementary
PWM mode
[3]
Set TCNT
[4]
Set GR
[5]
[3]
[4]
Enable waveform output
[6]
Start counter operation
[7]
[5]
<Complementary PWM mode>
[6]
[7]
Note:
Clear bits STR0 and STR1 in TRDSTR
to 0, and stop the counter operation of
TRDCNT_0. Stop TRDCNT_0 and
TRDCNT_1 and set complementary
PWM mode.
Use bits TPSC2 to TPSC0 in TRDCR to
select the same counter clock for
channels 0 and 1. When an external
clock is selected, select the edge of the
external clock by bits CKEG1 and
CKEG0 in TRDCR. Set bits CCLR2 to
CCLR0 in TRDCR so that the counter is
not cleared.
Use bits CMD1 and CMD0 in TRDFCR
to set complementary PWM mode.
FTIOB0 to FTIOD0 and FTIOA1 to
FTIOD1 automatically become PWM
output pins.
TRDCNT_1 must be H'0000. Set a nonoverlapped period to TRDCNT_0.
GRA_0 is a cycle register. Set the cycle
to GRA_0. Set the timing to change the
PWM output waveform to GRB_0,
GRA_1, and GRB_1. The settings must
be set so that a compare match occurs
on TRDCNT_0 and TRDCNT_1. T ≤ X
(X: Initial value in GRB_0, GRA_1, or
GRB_1).
Use TRDOER1 to enable or disable the
timer output.
Set the STR0 and STR1 bits in TRDSTR
to 1 to start the count operation.
To modify the settings for the complementary PWM mode, clear settings other
than those for the mode. After that, repeat setting from step [1].
Figure 16.29 Example of Complementary PWM Mode Setting Procedure
(1)
Canceling Procedure of Complementary PWM Mode
Figure 16.30 shows the complementary PWM mode canceling procedure.
Complementary PWM mode
[1]
Stop counter operation
[1]
Cancel complementary
PWM mode
[2]
[2]
Clear bit CMD1 in TRDFCR to 0, and set
channels 0 and 1 to normal operation.
After setting channels 0 and 1 to normal
operation, clear bits STR0 and STR1 in
TRDSTR to 0 and stop TRDCNT_0 and
TRDCNT_1.
<Normal operation>
Figure 16.30 Canceling Procedure of Complementary PWM Mode
Rev. 1.00 Oct. 03, 2008 Page 562 of 962
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Section 16 Timer RD
(2)
Examples of Complementary PWM Mode Operation
Figure 16.31 shows an example of complementary PWM mode operation. In complementary
PWM mode, TRDCNT_0 and TRDCNT_1 perform an increment or decrement operation. When
TRDCNT_0 and GRA_0 are compared and their contents match, the counter is decremented. And
when TRDCNT_1 underflows, the counter is incremented. In GRA_0, GRA_1, and GRB_1,
compare match is carried out in the order of TRDCNT_0 → TRDCNT_1 → TRDCNT_1 →
TRDCNT_0 and PWM waveform is output, during one cycle of an up/down counter. In this mode,
the initial setting will be TRDCNT_0 > TRDCNT_1.
TRDCNT values
TRDCNT_0 and GRA_0 are compared and their contents match
GRA_0
GRB_0
GRA_1
GRB_1
H'0000
Time
FTIOB0
FTIOD0
FTIOA1
FTIOC1
FTIOB1
FTIOD1
FTIOC0
Figure 16.31 Example of Complementary PWM Mode Operation (1)
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Section 16 Timer RD
Figure 16.32 shows an example of PWM waveform output with 0% duty and 100% duty in
complementary PWM mode (for one phase).
In this figure, GRB_0 is set to a value equal to or greater than GRA_0 and H'0000. The waveform
with a duty cycle of 0% and 100% can be output. When buffer operation is used together, the duty
cycles can easily be changed, including the above settings, during operation. For details on buffer
operation, see section 16.3.9, Buffer Operation.
TRDCNT values
GRA_0
GRB_0
H'0000
Time
FTIOB0
FTIOD0
0% duty
(a) When duty is 0%
TRDCNT values
GRA_0
GRB_0
H'0000
Time
FTIOB0
FTIOD0
100% duty
(b) When duty is 100%
Figure 16.32 Example of Complementary PWM Mode Operation (2)
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Section 16 Timer RD
In complementary PWM mode, when the counter switches from up-counter to down-counter or
vice versa, TRDCNT_0 and TRDCNT_1 overshoots or undershoots, respectively. In this case, the
conditions to set the IMFA flag in channel 0 and the UDF flag in channel 1 differ from usual
settings. Also, the transfer conditions in buffer operation differ from usual settings. Such timings
are shown in figures 16.33 and 16.34.
TRDCNT
N
N-1
GRA_0
N+1
N
N-1
N
IMFA
Set to 1.
Flag is not set.
Buffer transfer
signal
GR
Transferred
to buffer
Not transferred
to buffer
Figure 16.33 Timing of Overshooting
TRDCNT
H'0001
H'0000
H'FFFF
H'0000
H'0001
UDF
Set to 1.
Flag is not set.
OVF
Buffer transfer
signal
GR
Transferred
to buffer
Not transferred
to buffer
Figure 16.34 Timing of Undershooting
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Section 16 Timer RD
When the counter is incremented or decremented, the IMFA flag of channel 0 is set to 1, and when
the register is underflowed, the UDF flag of channel 0 is set to 1. After buffer operation has been
designated for GR, the value in the buffer registers is transferred to GR when the counter is
incremented by compare match A0 or when TRDCNT_1 is underflowed. In complementary PWM
mode, the OVF flag is not set to 1 at the timing that the counter value changes from H'FFFF to
H'0000 as shown in figure 16.34.
(3)
Setting GR Value in Complementary PWM Mode
To set the general register (GR) or modify GR during operation in complementary PWM mode,
see the following notes.
1. Initial value
 H'0000 to T – 1 (T: Initial value of TRDCNT_0) must not be set for the initial value.
 GRA_0 – (T – 1) or more must not be set for the initial value.
 When using buffer operation, the same values must be set in the buffer registers and
corresponding general registers.
2. Modifying the setting value
 Use the buffer operation to change the GR value. If the GR value is changed by writing to
it directly, the intended waveform may not be output.
 Do not change settings of GRA_0 during operation.
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Section 16 Timer RD
16.3.8
PWM3 Mode Operation
In PWM3 mode, single-phase PWM waveforms can be output using TRDCNT_0. The waveform
does not overlap its counter-phase waveform.
When the PWM3 mode is selected, the FTIOA0 and FTIOB0 pins are automatically set to output
pins for the PWM function using TRDCNT_0 regardless of the TRDPMR value. The waveform is
output on a GRA_0, GRA_1, GRB_0, or GRB_1 compare match according to bits TOA0 and
TOB0 in TRDOCR regardless of the TRDIORA and TRDIORC settings.
• When TOA0 = 0, 1 is output on a compare match of GRA_1 and 0 is output on a compare
match of GRA_0 on the FTIOA0 pin.
• When TOA0 = 1, 0 is output on a compare match of GRA_1 and 1 is output on a compare
match of GRA_0 on the FTIOA0 pin.
• When TOB0 = 0, 1 is output on a compare match of GRB_1 and 0 is output on a compare
match of GRB_0 on the FTIOB0 pin.
• When TOB0 = 1, 0 is output on a compare match of GRB_1 and 1 is output on a compare
match of GRB_0 on the FTIOB0 pin.
Table 16.9 lists the correspondence between pin functions and GR registers, figure 16.35 shows a
block diagram in PWM3 mode, and figure 16.36 shows a flowchart of setting in PWM3 mode.
When the buffer operation is used, set TRDMDR. The timer input/output pins, which are not used
in PWM3 mode, can be used as general port pins. When the buffer operation is not set, since GRC
or GRD is not used, a compare match interrupt can be generated when GRC or GRD matches with
TRDCNT_1.
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Section 16 Timer RD
Table 16.9 Pin Configuration in PWM3 Mode and GR Registers
Channel
Pin Name
Input/Output
Compare Match
Register
Buffer Register
0
FTIOA0
Output
GRA_0
GRC_0
GRA_1
GRC_1
GRB_0
GRD_0
GRB_1
GRD_1
General I/O port
General I/O port
FTIOB0
FTIOC0
I/O
FTIOD0
1
FTIOA1
FTIOB1
FTIOC1
FTIOD1
Compare match signal
TRDCNT_0
FTIOA0
Output
control
Comparator
GRA_0
GRC_0
Comparator
GRA_1
GRC_1
Comparator
GRB_0
GRD_0
Comparator
GRB_1
GRD_1
Compare match signal
Compare match signal
FTIOB0
Output
control
Compare match signal
Figure 16.35 Block Diagram in PWM3 Mode
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Section 16 Timer RD
PWM mode 3
Select counter clock
[1]
Select counter clearing source
[2]
Set PWM mode 3
[3]
[1] Select the counter clock with bits TPSC2
to TPSC0 in TRDCR. When an external
clock is selected, select the external
clock edge with bits CKEG1 and CKEG0
in TRDCR.
[2] Use bits CCLR2 to CCLR0 in TRDCR to
select counter clearing source GRA_0.
[3] Select PWM mode 3 with bit PWM3 in
TRDFCR.
Set output level
[4]
[4] Set output levels with bits TOB0 and
TOA0 in TRDOCR.
Select buffer operation
[5]
Set GR
[6]
[5] Set the GR buffer operation with bits
BFC0, BFC1, BFD0, and BFD1 in
TRDMDR.
Enable waveform output
[7]
[6] Set a cycle in GRA. Set the duty cycle in
other GR registers.
Start counter operation
[8]
[7] Enable or disable the timer output by
TRDOER.
[8] Set the STR bit in TRDSTR to 1 and start
the counter operation.
<PWM mode 3>
Figure 16.36 Flowchart of Setting in PWM3 Mode
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Section 16 Timer RD
Figure 16.37 is an example when non-overlapped pulses are output on pins FTIOA0 and FTIOB0.
In this example, TRDCNT_0 functions as a periodic counter which is cleared on compare match
A0 (bits CCLR2 to CCLR0 in TRDCR_0 are set to B'001), and PWM3 mode is selected (bit
PWM3 in TRDFCR is cleared to 0). The cycle of the pulse is arbitrary.
TRDCNT value
Counter cleared on GRA_0
compare match
H'FFFF
GRA_0
GRA_1
GRB_0
GRB_1
H'0000
Time
FTIOA0
FTIOB0
Figure 16.37 Example of Non-Overlap Pulses
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Section 16 Timer RD
Figures 16.38 and 16.39 show examples of stopping operation of the counter in PWM3 mode,
when the CCLR2 to CCLR0 bits in TRDCR are set to clear TRDCNT_0 on GRA_0 compare
match. For details on PWM3 mode, see section 16.3.8, PWM3 Mode Operation.
Counter cleared by GRA_0 compare match
The value of TRDCNT
H'FFFF
GRA_0
GRA_1
GRB_0
GRB_1
H'0000
Time
FTIOA0
FTIOB0
STR0
CSTPN0
Cleared to 0 by GRA_0 compare match
Set to 1 by writing from the CPU
Figure 16.38 Example (1) of Stopping Operation of the Counter (in PWM3 Mode)
Counter cleared by GRA_0 compare match
The value of TRDCNT
H'FFFF
GRA_0
GRA_1
GRB_0
GRB_1
H'0000
Time
FTIOA0
FTIOB0
STR0
High
CSTPN0
Set to 1 by writing from the CPU
Cleared to 0 by writing from the CPU
Figure 16.39 Example (2) of Stopping Operation of the Counter (in PWM3 Mode)
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Section 16 Timer RD
Figure 16.40 shows an example of starting and stopping operations of counters in PWM3 mode,
when TRDCNT_0 is set to be cleared and stopped on GRA_0 compare match (CCLR2 to CCLR0
= 001, CSTPNT0 = 0) and TRDCNT_1 is used as a free-running counter. When TRDCNT_1
starts counting by setting the STR1 bit to 1 after TRDCNT_0 has started counting by setting the
STR0 bit to 1, set 0 in the STR0 bit and 1 in the STR1 bit by using a MOV instruction. If the bit
manipulation instruction is used to set 1 in the STR1 bit, there is a possibility that the STR0 bit is
set to 1 after the counting has stopped on GRA_0 compare match, and that TRDCNT_0 starts
counting again.
Counter cleared by GRA_0
compare match
The value of TRDCNT
TRDCNT_0
TRDCNT_1
H'FFFF
GRA_0
GRA_1
GRB_0
GRB_1
H'0000
Time
FTIOA0
FTIOB0
STR0
CSTPN0
Low
0 written in STR0 by the CPU
is not reflected
STR1
High
CSTPN1
0 is written in STR0, 1 in STR1, 0 in CSTPN0,
and 1 in CSTPN1 by the CPU
Figure 16.40 Example of Starting and Stopping Operations of Counters (in PWM3 Mode)
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Section 16 Timer RD
16.3.9
Buffer Operation
Buffer operation differs depending on whether GR has been designated for an input capture
register or an output compare register, or in reset synchronous PWM mode or complementary
PWM mode.
Table 16.10 shows the register combinations used in buffer operation.
Table 16.10 Register Combinations in Buffer Operation
General Register (GR)
Buffer Register
GRA
GRC
GRB
GRD
(1)
When GR is an Output Compare Register
When a compare match occurs, the value in the buffer register of the corresponding channel is
transferred to the general register.
This operation is illustrated in figure 16.41.
Compare match signal
Buffer register
General
register
Comparator
TRDCNT
Figure 16.41 Compare Match Buffer Operation
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Section 16 Timer RD
(2)
When GR is an Input Capture Register
When an input capture occurs, the value in TRDCNT is transferred to GR and the value previously
stored in the general register is transferred to the buffer register.
This operation is illustrated in figure 16.42.
Input capture
signal
General
register
Buffer register
TRDCNT
Figure 16.42 Input Capture Buffer Operation
(3)
PWM3 Mode
When compare match A0 occurs, the value of the buffer register is transferred to GR.
(4)
Complementary PWM Mode
When the counter switches from counting up to counting down or vice versa, the value of the
buffer register is transferred to GR. Here, the value of the buffer register is transferred to GR in the
following timing:
• When TRDCNT_0 and GRA_0 are compared and their contents match
• When TRDCNT_1 underflows
(5)
Reset Synchronous PWM Mode
When compare match A0 occurs, the value in the buffer register is transferred to GR.
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Section 16 Timer RD
(6)
Example of Buffer Operation Setting Procedure
Figure 16.43 shows an example of the buffer operation setting procedure.
Buffer operation
[1]
Designate GR as an input capture register or
output compare register by means of TRDIOR.
Select GR function
[1]
[2]
Designate GR for buffer operation with bits
BFD1, BFC1, BFD0, or BFC0 in TRDMDR.
Set buffer operation
[2]
[3]
Set the STR bit in TRDSTR to 1 to start the
count operation of TRDCNT.
Start count operation
[3]
<Buffer operation>
Figure 16.43 Example of Buffer Operation Setting Procedure
(7)
Examples of Buffer Operation
Figure 16.44 shows an operation example in which GRA has been designated as an output
compare register, and buffer operation has been designated for GRA and GRC.
This is an example of TRDCNT operating as a periodic counter cleared by compare match B.
Pins FTIOA and FTIOB are set for toggle output by compare match A and B.
As buffer operation has been set, when compare match A occurs, the FTIOA pin performs toggle
outputs and the value in buffer register is simultaneously transferred to the general register. This
operation is repeated each time that compare match A occurs.
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Section 16 Timer RD
The timing to transfer data is shown in figure 16.45.
Counter is cleared by GRB compare match
TRDCNT value
GRB
H'0250
H'0200
H'0100
H'0000
Time
GRC
H'0200
H'0100
GRA
H'0250
H'0200
H'0200
H'0100
H'0200
FTIOB
FTIOA
Compare match A
Figure 16.44 Example of Buffer Operation (1)
(Buffer Operation for Output Compare Register)
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Section 16 Timer RD
φ
TRDCNT
n
n+1
Compare match
signal
Buffer transfer
signal
GRC
GRA
N
n
N
Figure 16.45 Example of Compare Match Timing for Buffer Operation
Figure 16.46 shows an operation example in which GRA has been designated as an input capture
register, and buffer operation has been designated for GRA and GRC.
Counter clearing by input capture B has been set for TRDCNT, and falling edges have been
selected as the FIOCB pin input capture input edge. And both rising and falling edges have been
selected as the FIOCA pin input capture input edge.
As buffer operation has been set, when the TRDCNT value is stored in GRA upon the occurrence
of input capture A, the value previously stored in GRA is simultaneously transferred to GRC. The
transfer timing is shown in figure 16.47.
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Section 16 Timer RD
TRDCNT value
Counter is cleared by
the input capture B
H'0180
H'0160
H'0005
H'0000
Time
FTIOB
FTIOA
GRA
H'0005
H'0160
GRC
H'0005
GRB
H'0160
H'0180
Input capture A
Figure 16.46 Example of Buffer Operation (2)
(Buffer Operation for Input Capture Register)
φ
FTIO pin
Input capture signal
TRDCNT
n
GRA
M
n
n
N
GRC
m
M
M
n
n+1
N
Figure 16.47 Input Capture Timing of Buffer Operation
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N+1
Section 16 Timer RD
Figures 16.48 and 16.49 show the operation examples when buffer operation has been designated
for GRB_0 and GRD_0 in complementary PWM mode. These are examples when a PWM
waveform of 0% duty is created by using the buffer operation and performing GRD_0 ≥ GRA_0.
Data is transferred from GRD_0 to GRB_0 according to the settings of CMD0 and CMD1 when
TRDCNT_0 and GRA_0 are compared and their contents match or when TRDCNT_1 underflows.
However, when GRD_0 ≥ GRA_0, data is transferred from GRD_0 to GRB_0 when TRDCNT_1
underflows regardless of the setting of CMD0 and CMD1. When GRD_0 = H'0000, data is
transferred from GRD_0 to GRB_0 when TRDCNT_0 and GRA_0 are compared and their
contents match regardless of the settings of CMD0 and CMD1.
TRDCNT values
GRA_0
GRB_0 (When restored, data will be transferred
to the saved location regardless of the
CMD1 and CMD0 values)
TRDCNT_0
TRDCNT_1
H'0999
H'0000
Time
GRD_0 H'0999
GRB_0 H'0999
H'1FFF
H'0999
H'1FFF
H'0999
H'0999
FTIOB0
FTIOD0
Figure 16.48 Buffer Operation (3)
(Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1)
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Section 16 Timer RD
TRDCNT values
GRB_0 (When restored, data will be transferred
to the saved location regardless of the
CMD1 and CMD0 values)
TRDCNT_0
GRA_0
TRDCNT_1
H'0999
H'0000
Time
GRB_0
GRD_0 H'0999
H'0000
GRB_0 H'0999
H'0999
H'0000
H'0999
FTIOC0
FTIOD0
Figure 16.49 Buffer Operation (4)
(Buffer Operation in Complementary PWM Mode CMD1 =1, CMD0 = 0)
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Section 16 Timer RD
16.3.10 Timer RD Output Timing
The outputs of channels 0 and 1 can be disabled or inverted by the settings of TRDOER1 and
TRDOCR and the external level.
(1)
Output Disable/Enable Timing of Timer RD by TRDOER1
Setting the master enable bit in TRDOER1 to 1 disables the output of timer RD. By setting the
PCR and PDR of the corresponding I/O port beforehand, any value can be output. Figure 16.50
shows the timing to enable or disable the output of timer RD by TRDOER1.
T1
T2
φ
TRDOER1 address
Address bus
TRDOER1
Timer RD
output pin
1
0
I/O port
Timer output
Timer RD output
I/O port
Figure 16.50 Example of Output Disable Timing of Timer RD by Writing to TRDOER1
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Section 16 Timer RD
(2)
Output Disable Timing of Timer RD by External Trigger
When PH5/TRDOI_0 (or PH6/TRDOI_1) is set as a TRDOI input pin, and low level is input to
TRDOI, the master enable bit in TRDOER1 is set to 1 and the output of timer RD will be disabled.
φ
TRDOI
TRDOER1
Timer RD
output pin
0
1
I/O port
Timer RD output
Timer RD output
I/O port
Figure 16.51 Example of Output Disable Timing of Timer RD by External Trigger
(3)
Output Inverse Timing by TRDFCR
The output level can be inverted by inverting the OLS1 and OLS0 bits in TRDFCR in reset
synchronous PWM mode or complementary PWM mode. Figure 16.52 shows the timing.
T1
T2
φ
Address bus
TRDFCR address
TRDFCR
Timer RD
output pin
Inverted
Figure 16.52 Example of Output Inverse Timing of Timer RD by Writing to TRDFCR
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Section 16 Timer RD
(4)
Output Inverse Timing by POCR
The output level can be inverted by inverting the POLD, POLC, and POLB bits in POCR in PWM
mode. Figure 16.53 shows the timing.
T1
T2
φ
Address bus
POCR address
POCR
Timer RD
output pin
Inverted
Figure 16.53 Example of Output Inverse Timing of Timer RD by Writing to POCR
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Section 16 Timer RD
16.3.11 Digital Filtering Function for Input Capture Inputs
Input signals on the FTIOA to FTIOD pins can be input via the digital filters. The digital filter
includes three latches connected in series and a match detector circuit. The latches operate on the
sampling clock specified by bits DFCK1 and DFCK0 in TRDDF and stores an input signal on the
FTIOA to FTIOD pins. When outputs of the three latches match, the match detector circuit outputs
the signal level of the input. Otherwise, the output remains unchanged. That is, when a pulse width
is equal to or greater than three sampling clock cycles, the pulse is input as a signal. When a pulse
width is less than three sampling clock cycles, the pulse is considered as a noise to be removed.
TPSC2 to
TPSC0
φ/32
φ/8
φ
FTIOA0 (TCLK)
φ40
φ/32
φ/8
φ/4
φ/2
φ
Sampling clock
C
FTIOA to FTIOD
DFCK1 and
DFCK2
C
Q
D
D
Latch
C
Q
D
Latch
C
Q
Latch
DFA to DFD
Q
D
Latch
Match
detector
circuit
Selecter
φ, φ40M
C
D
Q
Latch
Cycle of a clock specified by
TPSC2 to TPSC0 or DFCK1
and DFCK0
Sampling clock
FTIOA to FTIOD
input signals
Digital-filtered signal
Signal propagation delay:
5 sampling clocks
Signal change is not output unless
signal levels match three times.
Figure 16.54 Block Diagram of Digital Filter
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REJ09B0465-0100
IOA1, IOA0,
IOD1, and IOD0
Edge
detecting
circuit
Section 16 Timer RD
16.3.12 Function of Changing Output Pins for GR
With the settings of bits IOC3 and IOD3 in TRDIORC, pins for outputs of compare match signals
for GRC and GRD can be changed from the FTIOC and FTIOD pins to the FTIOA and FTIOB
pins. This means that the compare match A signal ORed with the compare match C signal can be
output on the FTIOA pin. The compare match B ORed with the compare match D signal can be
output on the FTIOB pin. Figure 16.55 is a block diagram of this function. The setting for channel
0 is independent of that for channel 1.
Channel 0
TRDCNT_0
Compare match signal
FTIOA0
Output
control
Comparator
GRA_0
Comparator
GRC_0
Comparator
GRB_0
Comparator
GRD_0
Compare match signal
FTIOC0
Output
control
Compare match signal
FTIOB0
Output
control
Compare match signal
FTIOD0
Output
control
Channel 1
TRDCNT_1
Compare match signal
FTIOA1
Output
control
Comparator
GRA_1
Comparator
GRC_1
Comparator
GRB_1
Comparator
GRD_1
Compare match signal
FTIOC1
Output
control
Compare match signal
FTIOB1
Output
control
Compare match signal
FTIOD1
Output
control
Figure 16.55 Block Diagram of Output Pins for GR
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Section 16 Timer RD
Figure 16.56 is an example when non-overlapped pulses are output on pins FTIOA0 and FTIOB0.
In this example, TRDCNT_0 functions as a periodic counter which is cleared on compare match
A0 (bits CCLR2 to CCLR0 in TRDCR_0 are set to B'001), an output signal is toggled on compare
match A (bits IOA2 to IOA0 in TRDIORA_1 are set to B'011), the output signal on the FTIOA
pin is toggled on compare match C (GRC_0) (bits IOC3 to IOC0 in TRDIORC_1 are set to
B'0X11), an output signal is toggled on compare match B (GRB_0) (bits IOB2 to IOB0 in
TRDIORA_1 are set to B’011), and the output signal on the FTIOB pin is toggled on compare
match D (GRD_0) (bits IOD3 to IOD0 in TRDIORC_1 are set to B'0X11). The cycle of the pulse
is arbitrary.
Similarly, figure 16.57 is an example when non-overlapped pulses are output using TRDCNT_1.
TRDCNT value
H'FFFF
Counter cleared on GRA_0
compare match
GRA_0
GRC_0
GRB_0
GRD_0
H'0000
Time
FTIOA0
FTIOB0
Figure 16.56 Example of Non-Overlapped Pulses Output on Pins FTIOA0 and FTIOB0
(TRDCNT_0 Used)
TRDCNT value
Counter cleared on GRA_1
compare match
H'FFFF
GRA_1
GRC_1
GRB_1
GRD_1
H'0000
Time
FTIOA1
FTIOB1
Figure 16.57 Example of Non-Overlapped Pulses Output on Pins FTIOA1 and FTIOB1
(TRDCNT_1 Used)
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Section 16 Timer RD
16.3.13 A/D Conversion Start Trigger Setting Function
Timer RD can generate the A/D conversion start trigger signal by setting the timer RD A/D
conversion start trigger control register (TRDADCR) or bits ADEG and ADTRG in the timer RD
function control register (TRDFCR).
Figures 16.58 and 16.59 show examples of the A/D conversion trigger signal generation in
complementary PWM mode.
GRA
GRB
GRC
GRD
H'0000
ADTRG
Figure 16.58 Example of A/D Conversion Trigger Signal Generation in Complementary
PWM Mode
(Trigger Asserted When TRDCNT_0 Matches GRA_0: ADEG = 0, ADTRG = 1)
GRA
GRB
GRC
GRD
H'0000
ADTRG
Figure 16.59 Example of A/D Conversion Trigger Signal Generation in Complementary
PWM Mode
(Trigger Asserted When TRDCNT_1 Underflows: ADEG = 1, ADTRG = 1)
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Section 16 Timer RD
Figure 16.60 shows an example where the A/D conversion start trigger signal is generated by
compare match. In this case, the TRDADCR register must be set.
GRA
GRB
GRC
H'0000
Setting of A/D conversion
start trigger
ADTRG
Figure 16.60 Example of A/D Conversion Trigger Signal Generation by Compare Match
Figure 16.61 shows the timing for generating the A/D conversion start trigger by compare match.
CK
TRDCNT input
TRDCNT
GRX
N
N+1
N
Compare match
signal
A/D conversion start
trigger signal
Figure 16.61 Timing of A/D Conversion Start Trigger Generation
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Section 16 Timer RD
16.3.14 Operation by Event Clear
Using the event link controller (ELC), timer RD unit 0 can be made to operate in the following
ways in relation to events occurring in other modules. Each channel 0 and 1 can be specified
independently.
(1)
Staring Counter Operation
The start of counting operations by timer RD can be selected by ELOPA and ELOPB of the ELC.
When the event specified by ELSR3 and ELSR4 occur, the STR[1:0] bits in TRDSTR are set to 1,
which stars counting by timer RD. However, if the specified event occurs when the STR bit has
already been set to 1, the event is not effective.
(2)
Counting Event
The counting of events by timer RD can be selected by ELOPA and ELOPB of the ELC. When
the event specified in ELSR3 and ELSR4 occurs, event counter operation proceeds with that event
as the source to drive counting, regardless of the setting of the TPSC[2:0] bits in TRDCR1. When
the value of the counter is read, the value read out is the actual number of input events.
(3)
Input Capture
Input capture operation of timer RD can be selected by ELOPA and ELOPB of the ELC. When
the event specified in ELSR3 and ELSR4 occurs, GRD captures the value of TRDCNT. When
input capture operation initiated by an event link is in use, set the IOD[3:0] bits = b'1101 in
TRDIORC of timer RD, set the STR bit in TRDSTR to 1, and then start the counter. Since input
on the FTIOD pin becomes valid at the same time, fix the input to the FTIOD pin or take other
measures such as not allocating the FTIOD pin to the port in the PMC, etc.
Rev. 1.00 Oct. 03, 2008 Page 589 of 962
REJ09B0465-0100
Section 16 Timer RD
16.4
Interrupt Sources
There are three kinds of timer RD interrupt sources; input capture/compare match, overflow, and
underflow. An interrupt is requested when the corresponding interrupt request flag is set to 1 while
the corresponding interrupt enable bit is set to 1.
16.4.1
(1)
Status Flag Set Timing
IMF Flag Set Timing
The IMF flag is set to 1 by the compare match signal that is generated when the GR matches with
the TRDCNT. The compare match signal is generated at the last state of matching (timing to
update the counter value when the GR and TRDCNT match). Therefore, when the TRDCNT and
GR matches, the compare match signal will not be generated until the TRDCNT input clock is
generated. Figure 16.62 shows the timing to set the IMF flag.
φ
TRDCNT
input clock
TRDCNT
N
GR
N+1
N
Compare match
signal
IMF
Figure 16.62 IMF Flag Set Timing when Compare Match Occurs
Rev. 1.00 Oct. 03, 2008 Page 590 of 962
REJ09B0465-0100
Section 16 Timer RD
(2)
IMF Flag Set Timing at Input Capture
When an input capture signal is generated, the IMF flag is set to 1 and the value of TRDCNT is
simultaneously transferred to corresponding GR. Figure 16.63 shows the timing.
φ
Input capture
signal
IMF
TRDCNT
N
GR
N
Figure 16.63 IMF Flag Set Timing at Input Capture
(3)
Overflow Flag (OVF) Set Timing
The overflow flag is set to 1 when the TRDCNT overflows. Figure 16.64 shows the timing.
φ
TRDCNT
H'FFFF
H'0000
Overflow signal
OVF
Figure 16.64 OVF Flag Set Timing
Rev. 1.00 Oct. 03, 2008 Page 591 of 962
REJ09B0465-0100
Section 16 Timer RD
16.4.2
Status Flag Clearing Timing
The status flag can be cleared by writing 0 after reading 1 from the CPU. Figure 16.65 shows the
timing in this case.
φ
TRDSR address
Address
WTRDSR
(internal write signal)
IMF, OVF
Figure 16.65 Status Flag Clearing Timing
16.5
(1)
Usage Notes
Input Pulse Width of Input Clock Signal and Input Capture Signal
When the digital filtering function for input is not in use, the pulse width of the input clock signal
and the input capture signal must be at least three system clock (φ) cycles when the TPSC2 to
TPSC0 bits in TRDCR = B'0XX or B'10X, and at least 3 × φ40 cycles for B'110; shorter pulses
will not be detected correctly.
Rev. 1.00 Oct. 03, 2008 Page 592 of 962
REJ09B0465-0100
Section 16 Timer RD
(2)
Conflict between TRDCNT Write and Clear Operations
If a counter clear signal is generated in the T2 state of a TRDCNT write cycle, TRDCNT clearing
has priority and the TRDCNT write is not performed. Figure 16.66 shows the timing in this case.
TRDCNT write cycle
T1
T2
φ
TRDCNT address
WTRDCNT
(internal write signal)
Counter clear signal
N
TRDCNT
H'0000
Clearing has priority.
Figure 16.66 Conflict between TRDCNT Write and Clear Operations
(3)
Conflict between TRDCNT Write and Increment Operations
If TRDCNT is incremented in the T2 state of a TRDCNT write cycle, writing has priority. Figure
16.67 shows the timing in this case.
TRDCNT write cycle
T1
T2
φ
TRDCNT address
WTRDCNT
(internal write signal)
TRDCNT input clock
TRDCNT
M
N
TRDCNT write data
Figure 16.67 Conflict between TRDCNT Write and Increment Operations
Rev. 1.00 Oct. 03, 2008 Page 593 of 962
REJ09B0465-0100
Section 16 Timer RD
(4)
Conflict between GR Write and Compare Match
If a compare match occurs in the T2 state of a GR write cycle, GR write has priority and the
compare match signal is disabled. Figure 16.68 shows the timing in this case.
GR write cycle
T1
T2
φ
GR address
WGR
(internal write signal)
TRDCNT
N
GR
N
N+1
M
GR write data
Disabled
Compare match
signal
Figure 16.68 Conflict between GR Write and Compare Match
Rev. 1.00 Oct. 03, 2008 Page 594 of 962
REJ09B0465-0100
Section 16 Timer RD
(5)
Conflict between TRDCNT Write and Overflow/Underflow
If overflow/underflow occurs in the T2 state of a TRDCNT write cycle, TRDCNT write has
priority without an increment operation. At this time, the OVF flag is set to 1. Figure 16.69 shows
the timing in this case.
TRDCNT write cycle
T1
T2
φ
TRDCNT address
WTRDCNT
(internal write signal)
TRDCNT input clock
Overflow signal
TRDCNT
M
H'FFFF
TRDCNT write data
OVF
Figure 16.69 Conflict between TRDCNT Write and Overflow
Rev. 1.00 Oct. 03, 2008 Page 595 of 962
REJ09B0465-0100
Section 16 Timer RD
(6)
Conflict between GR Read and Input Capture
If an input capture signal is generated in the T2 state of a GR read cycle, the data that is read will
be transferred before input capture transfer. Figure 16.70 shows the timing in this case.
GR read cycle
T2
T1
φ
GR address
Internal read
signal
Input capture
signal
GR
X
Internal
data bus
M
X
Figure 16.70 Conflict between GR Read and Input Capture
Rev. 1.00 Oct. 03, 2008 Page 596 of 962
REJ09B0465-0100
Section 16 Timer RD
(7)
Conflict between Count Clearing and Increment Operations by Input Capture
If an input capture and increment signals are simultaneously generated, count clearing by the input
capture operation has priority without an increment operation. The TRDCNT contents before
clearing counter are transferred to GR. Figure 16.71 shows the timing in this case.
φ
Input capture
signal
Counter clear
signal
TRDCNT input
clock
TRDCNT
GR
N
H'0000
N
Clearing has priority.
Figure 16.71 Conflict between Count Clearing and Increment Operations
by Input Capture
Rev. 1.00 Oct. 03, 2008 Page 597 of 962
REJ09B0465-0100
Section 16 Timer RD
(8)
Conflict between GR Write and Input Capture
If an input capture signal is generated in the T2 state of a GR write cycle, the input capture
operation has priority and the write to GR is not performed. Figure 16.72 shows the timing in this
case.
GR write cycle
T1
T2
φ
Address bus
GR address
WGR
(internal write signal)
Input capture signal
TRDCNT
N
GR
M
GR write data
Figure 16.72 Conflict between GR Write and Input Capture
Rev. 1.00 Oct. 03, 2008 Page 598 of 962
REJ09B0465-0100
Section 16 Timer RD
(9)
Notes on Setting Reset Synchronous PWM Mode/Complementary PWM Mode
When bits CMD1 and CMD0 in TRDFCR are set, note the following:
• Write bits CMD1 and CMD0 while TRDCNT_1 and TRDCNT_0 are halted.
• Changing the settings of reset synchronous PWM mode to complementary PWM mode or vice
versa is disabled. Set reset synchronous PWM mode or complementary PWM mode after the
normal operation (bits CMD1 and CMD0 are cleared to 0) has been set.
(10) Note on Writing to the TOA0 to TOD0 Bits and the TOA1 to TOD1 Bits in TRDOCR
The TOA0 to TOD0 bits and the TOA1 to TOD1 bits in TRDOCR decide the value of the FTIO
pin, which is output until the first compare match occurs. Once a compare match occurs and this
compare match changes the values of FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 output, the
values of the FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 pin output and the values read from the
TOA0 to TOD0 and TOA1 to TOD1 bits may differ. Moreover, when the writing to TRDOCR
and the generation of the compare match A0 to D0 and A1 to D1 occur at the same timing, the
writing to TRDOCR has the priority. Thus, output change due to the compare match is not
reflected to the FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 pins. Therefore, when bit
manipulation instruction is used to write to TRDOCR, the values of the FTIOA0 to FTIOD0 and
FTIOA1 to FTIOD1 pin output may result in an unexpected result. When TRDOCR is to be
written to while compare match is operating, stop the counter once before accessing to TRDOCR,
read the port 6 state to reflect the values of FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 output,
to TOA0 to TOD0 and TOA1 to TOD1, and then restart the counter. Figure 16.73 shows an
example when the compare match and the bit manipulation instruction to TRDOCR occur at the
same timing.
Rev. 1.00 Oct. 03, 2008 Page 599 of 962
REJ09B0465-0100
Section 16 Timer RD
TRDOCR has been set to H'06. Compare match B0 and compare match C0 are used. The FTIOB0 pin is in the 1
output state, and is set to the toggle output or the 0 output by compare match B0.
When BCLR#2, @TRDOCR is executed to clear the TOC0 bit (the FTIOC0 signal is low) and compare match B0
occurs at the same timing as shown below, the H'02 writing to TRDOCR has priority and compare match B0 does
not drive the FTIOB0 signal low; the FTIOB0 signal remains high.
7
6
5
4
3
2
1
0
TOD1
0
TOC1
0
TOB1
0
TOA1
0
TOD0
0
TOC0
1
TOB0
1
TOA0
0
Bit
TRDOCR
Set value
BCLR#2, @TRDOCR
(1) TRDOCR read operation: Read H'06
(2) Modify operation: Modify H'06 to H'02
(3) Write operation to TRDOCR: Write H'02
φ
TRDOCR
write signal
Compare match
signal B0
FTIOB0 pin
Expected
output
Remains high because the 1 writing to TOB has priority
Figure 16.73 When Compare Match and Bit Manipulation Instruction to TRDOCR
Occur at the Same Timing
Rev. 1.00 Oct. 03, 2008 Page 600 of 962
REJ09B0465-0100
Section 16 Timer RD
(11) Restrictions on Access to Registers when Internal φ40 Clock is Selected as Counter
Clock
When the internal φ40 clock is selected as the counter clock (the TPSC[2:0] bits in TRDCR =
110), if any register of timer RD is to be read immediately after writing to another register in a
given module, proceed with reading after having executed one NOP instruction.
Timer RD unit 0 and 1 are considered to be separate modules, but channels 0 and 1 (or channels 2
and 3) of the same unit are considered to be in the same module.
Write to TRDSTR.
Execute NOP.
Read TRDCNT.
Figure 16.74 Example of Flow for Reading Immediately after Writing to a Register
Rev. 1.00 Oct. 03, 2008 Page 601 of 962
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Section 16 Timer RD
Rev. 1.00 Oct. 03, 2008 Page 602 of 962
REJ09B0465-0100
Section 17 Timer RE
Section 17 Timer RE
Timer RE is a timer that provides a realtime clock function to count time ranging from a second to
a week and a compare-match function. Figure 17.1 shows a block diagram of the timer RE.
17.1
Features
• Realtime clock mode
 Counts seconds, minutes, hours, and day-of-week
 Start/stop function
 Reset function
 Readable/writable counter of seconds, minutes, hours, and day-of-week with BCD codes
 Periodic (seconds, minutes, hours, days, and weeks) interrupts
• Output-compare mode
 8-bit counter with a compare-match function
 Selection of clock source
 Compare-match interrupt
Rev. 1.00 Oct. 03, 2008 Page 603 of 962
REJ09B0465-0100
Section 17 Timer RE
TREO pin
TRECSR
PSC
divider
TREMIN
Clock count
control circuit
TREHR
TREWK
Bus interface
TRESEC
φsub
TRECR1
TREIFR
TRECR2
Interrupt
control circuit
Interrupt request
Figure 17.1 Block Diagram of Timer RE
Table 17.1 shows the timer RE input/output pin.
Table 17.1 Pin Configuration
Pin Name
I/O
Function
TREO
Output
Clock or compare-match output
Rev. 1.00 Oct. 03, 2008 Page 604 of 962
REJ09B0465-0100
Section 17 Timer RE
17.2
Register Descriptions
The timer RE has the following registers.
•
•
•
•
•
•
•
•
Timer RE second data register/counter data register (TRESEC)
Timer RE minute data register (TREMIN)
Timer RE hour data register (TREHR)
Timer RE day-of-week data register (TREWK)
Timer RE control register 1 (TRECR1)
Timer RE control register 2 (TRECR2)
Timer RE clock source select register (TRECSR)
Timer RE interrupt flag register (TREIRF)
Rev. 1.00 Oct. 03, 2008 Page 605 of 962
REJ09B0465-0100
Section 17 Timer RE
17.2.1
Timer RE Second Data Register/Counter Data Register (TRESEC)
Address: H'FFFFA8
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
BSY
SC12
SC11
SC10
SC03
SC02
SC01
SC00








• Realtime clock mode
Bit Symbol Bit Name
Description
R/W
7
BSY
Timer RE busy This bit is set to 1 when the timer RE is updating (calculating) R
the values of second, minute, hour, and day-of-week data
registers. When this bit is 0, the values of second, minute,
hour, and day-of-week data registers must be adopted.
6
SC12
5
SC11
Counting ten's Counts on 0 to 5 for 60-second counting.
position of
seconds
4
SC10
3
SC03
2
SC02
1
SC01
R/W
0
SC00
R/W
R/W
R/W
R/W
Counting one's Counts on 0 to 9 once per second. When a carry is
position of
generated, 1 is added to the ten's position.
seconds
R/W
R/W
• Output-compare mode
Bit Symbol
Bit Name
Description
R/W
7
BSY

Used as an 8-bit register for reading the counter data.
R
6
SC12
The counter value is retained when counting is stopped. R/W
5
SC11
This register is initialized to H’00 with a compare-match. R/W
4
SC10
R/W
3
SC03
R/W
2
SC02
R/W
1
SC01
R/W
0
SC00
R/W
TRESEC counts the BCD-coded second value in realtime clock mode. TRESEC is incremented
from decimal 00 to 59. TRESEC is used as an 8-bit register for reading the counter data in outputcompare mode.
Rev. 1.00 Oct. 03, 2008 Page 606 of 962
REJ09B0465-0100
Section 17 Timer RE
17.2.2
Timer RE Minute Data Register/Compare Data Register (TREMIN)
Address: H'FFFFA9
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
BSY
MN12
MN11
MN10
MN03
MN02
MN01
MN00








• Realtime clock mode
Bit Symbol Bit Name
Description
R/W
7
BSY
Timer RE busy This bit is set to 1 when the timer RE is updating (calculating) R
the values of second, minute, hour, and day-of-week data
registers. When this bit is 0, the values of second, minute,
hour, and day-of-week data registers must be adopted.
6
MN12
5
MN11
Counting ten's Counts on 0 to 5 for 60-minute counting.
position of
minutes
4
MN10
3
MN03
2
MN02
1
MN01
R/W
0
MN00
R/W
R/W
R/W
R/W
Counting one's Counts on 0 to 9 once per minute. When a carry is
position of
generated, 1 is added to the ten's position.
minutes
R/W
R/W
• Output-compare mode
Bit Symbol
Bit Name
Description
R/W
7
BSY

R
6
MN12
Used as an 8-bit register for storing the compare data.
The setting range is H'01 to H'FF.
5
MN11
4
MN10
R/W
This register can be written to only when counting is
R/W
stopped (when TSTART and TCSTF in TRECR1 are 0).
R/W
3
MN03
R/W
2
MN02
R/W
1
MN01
R/W
0
MN00
R/W
TREMIN counts the BCD-coded minute value on the carry generated once per minute by the
TRESEC counting in realtime clock mode. TREMIN is incremented from decimal 00 to 59.
TREMIN is used as an 8-bit register for storing the compare data in output-compare mode.
Rev. 1.00 Oct. 03, 2008 Page 607 of 962
REJ09B0465-0100
Section 17 Timer RE
17.2.3
Timer RE Hour Data Register (TREHR)
Address: H'FFFFAA
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
BSY

HR11
HR10
HR03
HR02
HR01
HR00

0






Bit Symbol Bit Name
Description
R/W
7
BSY
Timer RE busy This bit is set to 1 when the timer RE is updating (calculating) R
the values of second, minute, hour, and day-of-week data
registers. When this bit is 0, the values of second, minute,
hour, and day-of-week data registers must be adopted.
6

Reserved
This bit is read as 0. The write value should be 0.

5
HR11
Counts on 0 to 2 for ten's position of hours
R/W
4
HR10
Counting ten's
position of
hours
3
HR03
2
HR02
1
HR01
Counting one's Counts on 0 to 9 once per hour. When a carry is generated, 1 R/W
position of
is added to the ten's position.
R/W
hours
R/W
0
HR00
R/W
R/W
TREHR is used in realtime clock mode and counts the BCD-coded hour value on the carry
generated once per hour by TREMIN. TREHR is incremented either from decimal 00 to 11 or 00
to 23 by the selection of the 12/24 bit in TRECR1. This register is not used in output-compare
mode.
Rev. 1.00 Oct. 03, 2008 Page 608 of 962
REJ09B0465-0100
Section 17 Timer RE
17.2.4
Timer RE Day-of-Week Data Register (TREWK)
Address: H'FFFFAB
Bit:
Value after reset:
b7
b6
b5
b4
b3
BSY





0
0
0
0
b2
b1
b0
WK[2:0]


Description

Bit
Symbol Bit Name
R/W
7
BSY
Timer RE busy This bit is set to 1 when the timer RE is updating
R
(calculating) the values of second, minute, hour, and dayof-week data registers. When this bit is 0, the values of
second, minute, hour, and day-of-week data registers
must be adopted.
6 to 3

Reserved
2 to 0
WK[2:0] Day-of-week
counting
These bits are read as 0. The write value should be 0.

000: Sunday
R/W
001: Monday
010: Tuesday
011: Wednesday
100: Thursday
101: Friday
110: Saturday
111: Setting prohibited
TREWK is used in realtime clock mode and counts the BCD-coded day-of-week value on the
carry generated once per day by TREHR. Bits WK[2:0] indicate the day of the week with a binary
code, ranging from decimal 0 to 6. This register is not used in output-compare mode.
Rev. 1.00 Oct. 03, 2008 Page 609 of 962
REJ09B0465-0100
Section 17 Timer RE
17.2.5
Timer RE Control Register 1 (TRECR1)
Address: H'FFFFAC
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
TSTART
H12_H24
PM
TRERST
INT
TOENA
TCSTF




0
0
0

0
Value after reset:
• Realtime clock mode
Bit Symbol
Bit Name
Description
7
TSTART
0: Stops timer counter operation
Counter
operation start 1: Starts timer counter operation
6
H12_H24*1
Operating
mode
0: The timer RE operates in 12-hour mode. TREHR
counts on 0 to 11.
R/W
R/W
R/W
1: The timer RE operates in 24-hour mode. TREHR
counts on 0 to 23.
5
PM*1
a.m./p.m.
0: Indicates a.m. when the timer RE is in the 12-hour
mode.
1: Indicates p.m. when the timer RE is in the 12-hour
mode.
R/W
4
TRESET
Reset
0: Normal operation
1: Resets all the registers and control circuits, except
TRECSR and the TOENA and TRESET bits in this
register. Clear this bit to 0 after having been set to 1.
R/W
3
INT*1
Interrupt
generation
timing
0: Generates a second, minute, hour, or day-of-week
periodic interrupt during timer RE busy period.
R/W
1: Generates a second, minute, hour, or day-of-week
periodic interrupt immediately after completing timer
RE busy period.*2
2
TOENA
TREO pin
0: Disables timer RE divided clock output.
output enable 1: Enables timer RE divided clock output.
R/W
1
TCSTF
Operation
status flag
0: Indicates that timer RE operation has been stopped.
R
Reserved
This bit is read as 0. The write value should be 0.
0

Note:
1: Indicates that timer RE operation is in progress.

1. Bits H12_H24, PM, and INT should be set when the timer RE operation is stopped.
2. This bit should be set to 1 in realtime clock mode and cleared to 0 in output compare
mode.
Rev. 1.00 Oct. 03, 2008 Page 610 of 962
REJ09B0465-0100
Section 17 Timer RE
TRECR1 controls start/stop and reset of the counter. For the definition of time expression, see
figure 17.2.
Noon
24-hour
count
12-hour
count
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
0
1
2
3
4
5
6
7
8
9
10
11
0
1
2
3
4
5
PM
0 (Morning)
1 (Afternoon)
000 (Sunday)
TREWK
Date changes.
24-hour
count
12-hour
count
PM
TREWK
18
19
20
21
22
23
0
1
2
3
...
6
7
8
9
10
11
0
1
2
3
...
1 (Afternoon)
000 (Sunday)
0 (Morning)
...
001 (Monday)
...
Figure 17.2 Definition of Time Expression
Rev. 1.00 Oct. 03, 2008 Page 611 of 962
REJ09B0465-0100
Section 17 Timer RE
• Output-compare mode
Bit Symbol
Bit Name
Description
R/W
7
Counter
operation start
0: Stops timer counter operation.
R/W
TSTART
1: Starts timer counter operation.
6
H12_H24
Operating mode 0 should be written to this bit in output-compare mode.
R/W
5
PM
a.m./p.m.
0 should be written to this bit in output-compare mode.
R/W
4
TRESET
Reset
0: Normal operation
1: Resets all the registers and control circuits, except
TRECSR and the TOENA and TRESET bits in this
register. Clear this bit to 0 after having been set to 1.
R/W
3
INT
Interrupt
generation
timing
0 should be written to this bit in output-compare mode.
R/W
2
TOENA
TREO pin
output enable
0: Disables timer RE divided clock output.
R/W
1: Enables timer RE divided clock output.
1
TCSTF
Operation status 0: Indicates that timer RE operation has been stopped.
flag
1: Indicates that timer RE operation is in progress.
R
0

Reserved

This bit is read as 0. The write value should be 0.
Note: After writing 1 to TSTART, the timer RE should not be accessed before reading 1 from
TCSTF, with the exception of reading TCSTF. Similarly, after writing 0 to TSTART, the timer
RE should not be accessed before reading 0 from TCSTF, with the exception of reading
TCSTF.
Rev. 1.00 Oct. 03, 2008 Page 612 of 962
REJ09B0465-0100
Section 17 Timer RE
17.2.6
Timer RE Control Register 2 (TRECR2)
Address: H'FFFFAD
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0


COMIE
WKIE
DYIE
HRIE
MNIE
SEIE
0
0
0
0
0
0
0
0
Bit
Symbol Bit Name
Description
R/W
7, 6

Reserved
These bits are read as 0. The write value should be 0. 
5
COMIE
Compare-match
interrupt enable
0: Disables a compare-match interrupt
R/W
1: Enables a compare-match interrupt
This bit should be 0 in realtime clock mode.
4
3
2
1
0
WKIE
DYIE
HRIE
MNIE
SEIE
Week periodic
interrupt enable
0: Disables a week periodic interrupt
Day periodic
interrupt enable
0: Disables a day periodic interrupt
Hour periodic
interrupt enable
0: Disables an hour periodic interrupt
Minute periodic
interrupt enable
0: Disables a minute periodic interrupt
Second periodic
interrupt enable
0: Disables a second periodic interrupt
R/W
1: Enables a week periodic interrupt
This bit should be 0 in output-compare mode.
R/W
1: Enables a day periodic interrupt
This bit should be 0 in output-compare mode.
R/W
1: Enables an hour periodic interrupt
This bit should be 0 in output-compare mode.
R/W
1: Enables a minute periodic interrupt
This bit should be 0 in output-compare mode.
R/W
1: Enables a second periodic interrupt
This bit should be 0 in output-compare mode.
Notes: 1. When using interrupts, this register should be set last after other registers are set.
2. The COMIE bit should be set when counting operation is stopped.
3. Bits WKIE, DYIE, HRIE, MNIE, and SEIE should be set when timer RE operation is
stopped.
TRECR2 controls timer RE periodic interrupts of weeks, days, hours, minutes, and seconds in
realtime clock mode. Enabling interrupts of weeks, days, hours, minutes, and seconds sets the
interrupt request flag to 1 in the timer RE interrupt flag register (TREIFR) when an interrupt
occurs. It also controls a compare-match interrupt when output-compare mode is used.
Rev. 1.00 Oct. 03, 2008 Page 613 of 962
REJ09B0465-0100
Section 17 Timer RE
17.2.7
Timer RE Interrupt Flag Register (TREIFR)
Address: H'FFFFAE
Bit:
b7
b6
b5
b4
b3
b2
b1
b0


COMF
WKF
DYF
HRF
MNF
SECE
Value after reset:
0
0
0
0
0
0
0
0
Bit
Bit Name
Description
R/W
7, 6 
Reserved
These bits are read as 0. The write value should be 0.

5
Comparematch
interrupt
request flag
[Setting condition]
R/W
Symbol
COMF
•
When the counter value matches the value set in
TREMIN in output-compare mode.
[Clearing condition]
•
4
WKF
When 1 is read from the bit and then 0 is written to
the bit.
Week periodic [Setting condition]
R/W
interrupt
• When bits WK[2:0] in TREWK reach B’000 in realtime
request flag
clock mode.
[Clearing condition]
•
When 1 is read from the bit and then 0 is written to
the bit.
When the DTC is activated with a week periodic interrupt
and the DISEL bit in the MRB register of the DTC is 1.
3
DYF
Day periodic
interrupt
request flag
[Setting condition]
•
Each time TREWK is updated in realtime clock mode.
(Occurs every day)
[Clearing conditions]
•
When 1 is read from the bit and then 0 is written to
the bit.
•
When the DTC is activated with a day periodic
interrupt and the DISEL bit in the MRB register of the
DTC is 1.
Rev. 1.00 Oct. 03, 2008 Page 614 of 962
REJ09B0465-0100
R/W
Section 17 Timer RE
Bit
Symbol
Bit Name
Description
R/W
2
HRF
Hour periodic
interrupt
request flag
[Setting condition]
R/W
•
Each time TREHR is updated in realtime clock mode.
(Occurs every hour)
[Clearing conditions]
1
MNF
Minute
periodic
interrupt
request flag
•
When 1 is read from the bit and then 0 is written to
the bit.
•
When the DTC is activated with an hour periodic
interrupt and the DISEL bit in the MRB register of the
DTC is 1.
[Setting condition]
•
R/W
Each time TREMIN is updated in realtime clock mode.
(Occurs every minute)
[Clearing conditions]
0
SECF
Second
periodic
interrupt
request flag
•
When 1 is read from the bit and then 0 is written to
the bit.
•
When the DTC is activated with a minute periodic
interrupt and the DISEL bit in the MRB register of the
DTC is 1.
[Setting condition]
•
R/W
Each time TRESEC is updated in realtime clock
mode. (Occurs every second)
[Clearing conditions]
•
When 1 is read from the bit and then 0 is written to
the bit.
•
When the DTC is activated with a second periodic
interrupt and the DISEL bit in the MRB register of the
DTC is 1.
Rev. 1.00 Oct. 03, 2008 Page 615 of 962
REJ09B0465-0100
Section 17 Timer RE
17.2.8
Timer RE Clock Source Select Register (TRECSR)
Address: H'FFFFAF
Bit:
b7
b6

Value after reset:
Bit
Symbol
7

6 to 4
RCS[6:4]*
0
2
b5
b4
RCS[6:4]
0
0
0
b3
b2
RCS3
RCS2
1
0
b0
b1
RCS[1:0]
0
0
Bit Name
Description
R/W
Reserved
This bit is read as 0. The write value should be 0.

Clock output
select
000: φ/2
R/W
001: φ/4
010: φ/8
011: Compare-match output (Only valid in outputcompare mode)
100: φ/sub (32.768 kHz)
101: 1 Hz (Only valid in realtime clock mode)
11x: Setting prohibited
3
RCS3
Mode select
0: Output-compare mode
R/W
1: Realtime clock mode
2
RCS2
4-bit counter
select
(Only valid in output-compare mode)
R/W
0: Does not use the 4-bit counter.
1: Uses the 4-bit counter.
1, 0
RCS[1:0]
*1*3
Clock source
select
00: φ/2
R/W
01: φ/4
10: φ/8
11: φ/sub
[Legend]
X: Don't care
Notes: 1. RCS[1:0] should be set when realtime clock mode is used or when counter operation is
stopped.
2. RCS[6:4] should be set when the TOENA bit in TRECR1 is 0.
3. In output compare mode, when the CPU is in a φsub clock mode, do not select the φsub
clock as the clock source for the timer.
Rev. 1.00 Oct. 03, 2008 Page 616 of 962
REJ09B0465-0100
Section 17 Timer RE
TRECSR selects clock output, operating mode, and clock source.
• RCS6 to RCS4 (clock output select)
Selects a clock output from the TREO pin when the TOENA bit in TRECR1 is set to 1.
• RCS1 and RCS0 (clock source select)
Selects a clock source for output-compare mode. For realtime clock mode, the subclock φsub
(32.768 kHz) is selected regardless of the setting of these bits.
Rev. 1.00 Oct. 03, 2008 Page 617 of 962
REJ09B0465-0100
Section 17 Timer RE
17.3
Operation of Realtime Clock Mode
17.3.1
Initial Settings of Registers after Power-On
The timer RE registers that contain second, minute, hour, and day-of-week data are not initialized
by a reset by the RES pin, LVD, or watchdog timer. Therefore, all registers must be set to their
initial values after power-on. Once the register settings are made, the timer RE provides an
accurate time as long as power is supplied regardless of the RES pin, VLD, or watchdog timer
reset.
17.3.2
Initial Setting Procedure
Figure 17.3 shows the procedure for the initial setting of the timer RE to be used in realtime clock
mode. To set the timer RE again, also follow this procedure.
Rev. 1.00 Oct. 03, 2008 Page 618 of 962
REJ09B0465-0100
Section 17 Timer RE
TSTART in TRECR1=0
Timer RE operation is stopped.
TCSTF in TRECR1=0?
TRERST in TRECR1=1
Timer RE registers and control
circuit are reset.
TRERST in TRECR1=0
Set TRECSR, TRESEC,
TREMIN, TREHR,
TREWK, TRECR1,
H12_H24, PM, and INT.
Set TRECR2.
Clock output and clock source are
selected and second, minute, hour,
day-of-week, operating mode,
a.m/p.m, and interrupt source are set.
An interrupt source is selected.
TSTART in TRECR1=1
Timer RE operation is started.
TCSTF in TRECR1=1?
Figure 17.3 Initial Setting Procedure
Rev. 1.00 Oct. 03, 2008 Page 619 of 962
REJ09B0465-0100
Section 17 Timer RE
17.3.3
Data Reading Procedure in Realtime Clock Mode
When the seconds, minutes, hours, or day-of-week datum is updated while time data is being read,
the data obtained may not be correct, and so the time data must be read again. Figure 17.4 shows
an example in which correct data is not obtained. In this example, since only TRESEC is read after
data update, about 1-minute inconsistency occurs.
The following three methods can be used to avoid reading in this timing:
1. Check the setting of the BSY bit, and when the BSY bit changes from 1 to 0, read from the
second, minute, hour, and day-of-week registers. When about 62.5 ms is passed after the BSY
bit is set to 1, the registers are updated, and the BSY bit is cleared to 0.
2. Making use of interrupts, read from the second, minute, hour, and day-of week registers after
the SECF flag in TREIFR is set to 1 and the BSY bit is confirmed to be 0.
3. Read from the second, minute, hour, and day-of week registers twice in a row, and if there is
no change in the read data, the read data is used.
Before update
TREWK = H'03, TREHR = H'13, TREMIN = H'46, TRESEC = H'59
Processing flow
BSY bit = 0
(1) Day-of-week data register read
H'03
(2) Hour data register read
H'13
(3) Minute data register read
H'46
BSY bit -> 1 (under data update)
After update
TREWK = H'03, TREHR = H'13, TREMIN = H'47, TRESEC = H'00
BSY bit -> 0
(4) Second data register read
H'00
Figure 17.4 Example: Reading of Inaccurate Time Data
Rev. 1.00 Oct. 03, 2008 Page 620 of 962
REJ09B0465-0100
Section 17 Timer RE
17.3.4
Operation in Realtime Clock Mode
Figure 17.5 shows an example of realtime clock mode operation.
1s
Approx.
62.5ms
Approx.
62.5ms
BSY bit
SC12 to SC00
in TRESEC
MIN12 to MIN00
in TREMIN
HR11 to HR00
in TREHR
"1"
PM in TRECR
58
59
00
03
04
(Not change)
(Not change)
"0"
WK2 to WK0
in TREWK
SECF in
TREIFR
MNF in
TREIFR
(Not change)
"1"
Set to 0 by accepting an interrupt
request or by a program.
"0"
"1"
"0"
BSY: Bit in TRESEC, TREMIN, TREHR, and TREWK
Figure 17.5 Example of Realtime Clock Mode Operation
Rev. 1.00 Oct. 03, 2008 Page 621 of 962
REJ09B0465-0100
Section 17 Timer RE
17.4
Operation of Output Compare Mode
Writing 0 to the RCS3 bit in TRECSR sets the timer RE in output compare mode and causes it to
operate as a counter provided with an 8-bit compare match function. Four count sources can be
selected. When used in output compare mode, the timer RE should be initialized in reference to
figure 17.3.
The count source selected by the RCS1 and RCS0 bits is divided into two and counted with an 8bit counter. Setting 1 to the RCS2 bit in TRECSR causes the count source divided into two to be
counted with a 4-bit counter, and the 8-bit counter counts overflows of the 4-bit counter.
TREMIN sets a compare value. By reading TRESEC, it is possible to read values from the 8-bit
counter. In this mode, TREHR or TREWK is not used. Setting bits RCS6 to RCS4 in TRECSR to
B'011 and setting the TOENA bit in TRECR1 to 1 produces toggle output from the TREO pin
each time the value of the 8-bit counter matches the value of TREMIN (initial value: low output).
Also, by setting the COMIE bit in TRECR2 to 1, it is possible to generate a compare match
interrupt request. The counter, using the TSTART bit in TRECR1, controls the start/stop of
counter operation.
Figure 17.6 shows a block diagram of output compare mode; figure. 17.7 shows an operation
example.
Rev. 1.00 Oct. 03, 2008 Page 622 of 962
REJ09B0465-0100
Section 17 Timer RE
φ/2
φ/4
φ/8
φsub
Output
control
circuit
1/4
TREO pin
RCS[1:0]
1/2
4-bit
counter
φ/32
8-bit
counter
Match signal
RCS2
Comparison
circuit
TRESEC
Interrupt
control
circuit
Interrupt
request
TREMIN
Internal data bus
[Legend]
TRESEC: Timer RE second data register/counter data register
TREMIN: Timer RE minute data register/compare data register
RCS2 to RCS0: Bits 2 to 0 in TRECSR
Figure 17.6 Block Diagram of Output Compare Mode
Rev. 1.00 Oct. 03, 2008 Page 623 of 962
REJ09B0465-0100
8-bit counter content
Section 17 Timer RE
Value set
in TREMIN
Start counting.
Match
Match
Match
H'00
Time
Set to 1 by a program.
TSTART
in TRECR1
"1"
"0"
TCSTF
in TRECR1
"1"
"0"
Two cycles of the maximum count source
Set to 0 by a program.
COMF in TREIFR "1"
"0"
TREO output
"H"
"L"
Output polarity is inverted on a compare match .
Conditions for the above operation:
TOENA in TRECR1 = 1 (clock output enabled)
RCS[6:4] in TRECSR = B'011 (compare output)
Figure 17.7 Example of Output Compare Mode Operation
Rev. 1.00 Oct. 03, 2008 Page 624 of 962
REJ09B0465-0100
Section 17 Timer RE
17.5
Interrupt Sources
There are six kinds of timer RE interrupts: week interrupts, day interrupts, hour interrupts, minute
interrupts, and second interrupts in realtime clock mode, and compare-match interrupts in output
compare mode. Table 17.2 shows the interrupt sources.
When using an interrupt, initiate the timer RE last after other registers are set. Independent vector
addresses are allocated to each timer RE interrupt source.
Table 17.2 Interrupt Sources
Interrupt Name
Interrupt Source
Interrupt Enable Bit
Compare-match interrupt
Occurs when the count value matches the
compare data.
COMIE
Week periodic interrupt
Occurs every week when the day-of-week
data register value becomes 0.
WKIE
Day periodic interrupt
Occurs every day when the day-of-week data DYIE
register value is incremented.
Hour periodic interrupt
Occurs every hour when the hour date
register value is incremented.
HRIE
Minute periodic interrupt
Occurs every minute when the minute data
register value is incremented.
MNIE
Second periodic interrupt
Occurs every second when the second data
register value is incremented.
SCIE
Rev. 1.00 Oct. 03, 2008 Page 625 of 962
REJ09B0465-0100
Section 17 Timer RE
17.6
(1)
Usage Notes
Starting and Stopping Counting Process
The timer RE includes a TSTART bit that directs the start or stop of the counting process, and a
TCSTF bit that indicates that the counting process has started or stopped.
Setting the TSTART bit to 1 causes the timer RE to start counting and assigns 1 to the TCSTF bit.
From the time the TSTART bit is set to 1 and to the time the TCSTF bit turns 1, a maximum of 2
cycles of count sources are required. During this time period, the timer RE related registers*, with
the exception of the TCSTF bit, should not be accessed.
Similarly, clearing the TSTART bit to 0 causes the timer RE to stop counting, and assigns 0 to the
TCSTF bit. From the time the TSTART bit is set to 0 and to the time the TCSTF bit turns 0, the
timer RE related registers*, with the exception of the TCSTF bit, should not be accessed.
Note: Timer RE related registers: TRESEC, TREMIN, TREHR, TREWK, TRECR1, TRECR2,
and TRECSR
(2)
Register Settings of Timer RE
The following registers and bits should be written when the timer RE is stopped.
The condition "timer RE stopped" refers to the condition in which both the TSTART and TCSTF
bits in TRECR1 are 0. Set TRECR2 at the end of setting the above registers and bits (before the
timer RE counting process is started).
• Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2
• Bits H12_H24 bit, PM, and INT in TRECR1
• Bits RCS0 to RCS3 in TRECSR
(3)
Sampling Circuit for Noise Canceler in φ Subclock Signal
In realtime clock mode, always enable the sampling circuit with the SUBNC[1:0] bits in
SYSCCR. For details of the SUBNC[1:0] bits, see section 5.2.2, System Clock Control Register
(SYSCCR).
(4)
Restrictions on Clock Selection in Output Compare Mode
In output compare mode, do not select the φ subclock as the clock source for the timer if the CPU
is in φsub mode.
Rev. 1.00 Oct. 03, 2008 Page 626 of 962
REJ09B0465-0100
Section 18 Timer RG
Section 18 Timer RG
Timer RG is a 16-bit timer with output compare and input capture functions. Timer RG can count
using a number of internal or external clocks and output pulses with a desired duty cycle using the
compare match function between the timer counter and two general registers. Timer RG is also
able to decode the phase difference between two external clocks and increment. Timer RG
therefore provides an ideal solution for many systems with a requirement to decide position based
on a rotary encoder or tachometer as well as a wide range of other applications.
18.1
Features
• Selection of seven counter clock sources
Internal clocks: φ, φ/2, φ/4, φ/8, φ/32 and φ40
External clocks: TCLKA, TCLKB
• Timer mode
Waveform output by compare match (Selection of 0 output, 1 output, or toggle output)
Input capture function (Rising edge, falling edge, or both edges)
• PWM mode
Generates pulses with a desired period and duty cycle.
• Phase counting mode
Detects phase difference between two external clock inputs and increments/decrements the
TCNT.
• Fast access via internal 16-bit bus
Performs high-speed accesses to the timer counter and general registers using the 16-bit bus
interface.
• Four interrupt sources
TRGCNT overflow, TRGCNT underflow, compare match, and input capture
Rev. 1.00 Oct. 03, 2008 Page 627 of 962
REJ09B0465-0100
Section 18 Timer RG
Table 18.1 Functions of Timer RG
Input/Output Pins
Item
Counter
Counter clock
Internal clocks: φ, φ/2, φ/4, φ/8, φ/32, and φ40
External clock: TCLKA, TCLKB
General registers
(multiplexed registers with output
compare/input capture)

GRA
Buffer register

BRA
BRB
Counter clearing function

Compare match/
input capture
Compare match/
input capture



Yes
Yes
0 output

Yes
Yes
1 output

Yes
Yes
Toggle output

Yes
Yes
Input capture function

Yes
Yes
PWM mode

Yes
Yes
Phase counting mode

Yes
Yes
Interrupt sources
Overflow
Compare match/
input capture
Compare match/
input capture
Initial output value setting function 
Buffer operation
Compare
match output
Underflow
TGIOA
Write to TRGMDR.
Execute NOP.
Read TRGCNT.
Figure 18.1 Timer RG Block Diagram
Rev. 1.00 Oct. 03, 2008 Page 628 of 962
REJ09B0465-0100
TGIOB
GRB
Section 18 Timer RG
Table 18.2 summarizes the timer RG pins.
Table 18.2 Pin Configuration
Pin Name
I/O
Function
TCLKA
Input
External clock A input pin (Phase A input pin in phase
counting mode)
TCLKB
Input
External clock B input pin (Phase B input pin in phase
counting mode)
TGIOA
I/O
GRA output compare output pin/
GRA input capture input pin/
PWM output pin in PWM mode
TGIOAB
I/O
GRB output compare output pin/
GRB input capture input pin
Rev. 1.00 Oct. 03, 2008 Page 629 of 962
REJ09B0465-0100
Section 18 Timer RG
18.2
Register Descriptions
Timer RG has the following registers.
•
•
•
•
•
•
•
•
•
•
•
Timer RG mode register (TRGMDR)
Timer RG counter control register (TRGCNTCR)
Timer RG control register (TRGCR)
Timer RG I/O control register (TRGIOR)
Timer RG status register (TRGSR)
Timer RG interrupt enable register (TRGIER)
Timer RG counter (TRGCNT)
General register A (GRA)
General register B (GRB)
GRA buffer register (BRA)
GRB buffer register (BRB)
Rev. 1.00 Oct. 03, 2008 Page 630 of 962
REJ09B0465-0100
Section 18 Timer RG
18.2.1
Timer RG Mode Register (TRGMDR)
Address: H'FF0646
Bit:
Value after reset:
b7
b6
STR

0
1
b5
b4
DFCK[1:0]
0
0
b3
b2
b1
b0
DFB
DFA
MDF
PWM
0
0
0
0
Bit Symbol
Bit Name
Description
R/W
7
Counter start
0: TRGCNT stops counting.
R/W
STR
1: TRGCNT performs counting.
6

Reserved
This bit is read as 1. The write value should be 1.

5,
4
DFCK[1:0]
Digital filter
clock select
00: φ/32 (initial value)
R/W
01: φ/8
10: φ
11: φ/32Clock specified by bits CKS2 to CKS0 in TRGCR
3
DFB
TGIOB pin
0: Disables the digital filter for the TGIOB pin.
digital filter
1: Enables the digital filter for the TGIOB pin.
function select
R/W
2
DFA
TGIOB pin
0: Disables the digital filter for the TGIOA pin.
digital filter
1: Enables the digital filter for the TGIOA pin.
function select
R/W
1
MDF
Phase
0: Increments the counter.*1
counting mode 1: Phase counting mode
select
R/W
0
PWM
PWM mode
select
Note:
0: Usual mode*2
R/W
1: PWM mode
1. Select counting up in PWM mode.
2. Select normal mode here when the MDF bit is set for phase counting mode.
• STR bit (Counter start)
Clearing this bit to 0 stops counting by TRGCNT. Counting by TRGCNT proceeds while this
bit is set to 1.
This bit is set to 1 if the specified event occurs when operation of timer RG has been selected
in ELOPC of the event link controller.
Rev. 1.00 Oct. 03, 2008 Page 631 of 962
REJ09B0465-0100
Section 18 Timer RG
• MDF bit (Phase counting mode select)
When this bit is 0, the counter counts the clock pulses specified with the TPSC2 to TPSC0 bits
in TRGCR. When this bit is 1, the counter counts the phases produced by TCLKA and
TCLKB as specified in TRGCNTCR.
18.2.2
Timer RG Counter Control Register (TRGCNTCR)
Address: H'FF0647
b7
b6
b5
b4
b3
b2
b1
b0
CNTEN7
CNTEN6
CNTEN5
CNTEN4
CNTEN3
CNTEN2
CNTEN1
CNTEN0
0
0
0
0
0
0
0
0
Bit:
Value after reset:
Bit Symbol Bit Name
Description
R/W
7
CNTEN7 Count enable 0: Not affected by the TCLKB rising edge when TCLKA is low.
bit 7
1: Incremented at the TCLKB rising edge when TCLKA is low.
6
CNTEN6 Count enable 0: Not affected by the TCLKA rising edge when TCLKB is high. R/W
bit 6
1: Incremented at the TCLKA rising edge when TCLKB is high.
5
CNTEN5 Count enable 0: Not affected by the TCLKB falling edge when TCLKA is high. R/W
bit 5
1: Incremented at the TCLKB falling edge when TCLKA is high.
4
CNTEN4 Count enable 0: Not affected by the TCLKA falling edge when TCLKB is low. R/W
bit 4
1: Incremented at the TCLKA falling edge when TCLKB is low.
3
CNTEN3 Count enable 0: Not affected by the TCLKA falling edge when TCLKB is high. R/W
bit 3
1: Incremented at the TCLKA falling edge when TCLKB is high.
2
CNTEN2 Count enable 0: Not affected by the TCLKB falling edge when TCLKA is low. R/W
bit 2
1: Incremented at the TCLKB falling edge when TCLKA is low.
1
CNTEN1 Count enable 0: Not affected by the TCLKA rising edge when TCLKB is low.
bit 1
1: Incremented at the TCLKA rising edge when TCLKB is low.
0
CNTEN0 Count enable 0: Not affected by the TCLKB rising edge when TCLKA is high. R/W
bit 0
1: Incremented at the TCLKB rising edge when TCLKA is high.
Rev. 1.00 Oct. 03, 2008 Page 632 of 962
REJ09B0465-0100
R/W
R/W
Section 18 Timer RG
18.2.3
Timer RG Control Register (TRGCR)
Address: H'FF0648
Bit:
b7
b6

Value after reset:
1
b5
b4
CCLR[1:0]
0
b3
b2
CKEG[1:0]
0
0
b1
b0
TPSC[2:0]
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is read as 1. The write value should be 1.

6, 5
CCLR[1:0]
Counter clear
source select
00: Disables clearing TRGCNT.
R/W
01: Clears TRGCNT with a GRA compare match/input
capture.
1X: Clears TRGCNT with a GRB compare match/input
capture.
4, 3
CKEG[1:0]
External clock
detection edge
select
00: Incremented at the rising edges.
R/W
01: Incremented at the falling edges.
1x: Incremented at the rising and falling edges.
2 to 0 TPSC[2:0]* TRGCNT count 000: TRGCNT counts the internal clock φ
clock select
001: TRGCNT counts the internal clock φ/2
R/W
010: TRGCNT counts the internal clock φ/4
011: TRGCNT counts the internal clock φ/8
100: TRGCNT counts the internal clock φ/32
101: TRGCNT counts the TCLKA pin input
110: TRGCNT counts the internal clock φ/40
111: TRGCNT counts the TCLKB pin input
[Legend]
X:
Don't care.
Note: * If the internal φ/40 clock is selected, the high-speed on-chip oscillator must be
operating. As long as the internal φ40 clock is selected, do not stop the high-speed onchip oscillator. When the counter clock is switched over, the counter should be halted.
When the internal φ40 clock is selected, restrictions on access to registers are applied.
For details, see section 18.4, Usage Note. (1) Restrictions on Access to Registers when
Internal φ40 Clock is Selected as Counter Clock.
• CKEG1 bit and CLEG0 bit (external clock detection edge select)
Selects an edge of the external clock to be detected. When phase counting mode is used, the
phase counting operation is performed regardless of the CKEG[1:0] setting.
• TPSC2 bit to TPSC0 bit (TRGCNT count clock select)
The settings are invalid in phase counting mode.
Rev. 1.00 Oct. 03, 2008 Page 633 of 962
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Section 18 Timer RG
18.2.4
Timer RG I/O Control Register (TRGIOR)
Address:
H'FF0649
Bit:
b7
b6
BUFB
IOB2
0
0
Value after reset:
b5
b4
IOB[1:0]
0
0
b3
b2
BUFA
IOA2
0
0
b0
b1
IOA[1:0]
0
0
Bit
Symbol
Bit Name
Description
R/W
7
BUFB
BRB function
select
0: BRB does not function as the GRB buffer register.
R/W
GRB function
select
0: GRB is used as a compare match register.
GRB I/O
function select
When IOB2 = 0,
6
5, 4
IOB2
IOB[1:0]
1: BRB functions as the GRB buffer register.
1: GRB is used as an input capture register.
00: Disables pin output at a compare match.
01: Outputs 0 to the TGIOB pin at a GRB compare
match.
10: Outputs 1 to the TGIOB pin at a GRB compare
match.
11: Toggles the output to the TGIOB pin at a GRB
compare match.
When IOB2 = 1,
00: Input capture to GRB at the rising edge of the
TGIOB pin.
01: Input capture to GRB at the falling edge of the
TGIOB pin.
1X: Input capture to GRB at the rising and falling
edges of the TGIOB pin.
Rev. 1.00 Oct. 03, 2008 Page 634 of 962
REJ09B0465-0100
R/W
R/W
Section 18 Timer RG
Bit
Symbol
Bit Name
Description
R/W
3
BUFA
BRA function
select
0: BRA does not function as the GRA buffer register.
R/W
GRA function
select
0: GRA is used as a compare match register.
GRA I/O
function select
When IOA2 = 0,
2
1, 0
IOA2
IOA[1:0]
1: BRA functions as the GRA buffer.
R/W
1: GRA is used as an input capture register.
R/W
00: Disables pin output at a compare match.
01: Outputs 0 to the TGIOA pin at a GRA compare
match.
10: Outputs 1 to the TGIOA pin at a GRA compare
match.
11: Toggles the output to the TGIOA pin at a GRA
compare match.
When IOA2 = 1,
00: Input capture to GRA at the rising edge of the
TGIOA pin.
01: Input capture to GRA at the falling edge of the
TGIOA pin.
1X: Input capture to GRA at the rising and falling
edges of the TGIOA pin.
[Legend]
X:
Don't care.
Rev. 1.00 Oct. 03, 2008 Page 635 of 962
REJ09B0465-0100
Section 18 Timer RG
18.2.5
Timer RG Status Register (TRGSR)
Address: H'FF064A
Bit:
Value after reset:
Bit
Symbol
b7
b6
b5
b4
b3
b2
b1
b0



DIRF
OVF
UDF
IMFB
IMFA
1
1
1
0
0
0
0
0
Bit Name
Description
R/W
7 to 5 
Reserved
These bits are read as 1. The write value should be 1.

4
DIRF
Count
direction flag
0: TRGCNT is decremented.
R
3
OVF
Overflow flag
[Setting condition]
1: TRGCNT is incremented.
•
R/W
When TRGCNT overflows from H'FFFF to H'0000
[Clearing condition]
•
2
UDF
When OVF is read when OVF = 1, then 0 is written to.
Underflow flag [Setting condition]
•
R/W
When TRGCNT underflows from H'0000 to H'FFFF
[Clearing condition]
•
When UDF is read when UDF = 1, then 0 is written to.
UDF is valid when phase counting mode is used (MDF in
TRGMDR is 1).
1
IMFB
Input capture/ [Setting conditions]
compare
• TRGCNT = GRB when GRB functions as an output
match flag B
compare register
•
The TRGCNT value is transferred to GRB by an input
capture signal when GRB functions as an input
capture register
[Clearing condition]
•
When the DTC is activated by a IMFB interrupt, and
the DISEL bit in MRB of the DTC is 0.
•
When IMFB is read when IMBF = 1, then 0 is written
to.
Rev. 1.00 Oct. 03, 2008 Page 636 of 962
REJ09B0465-0100
R/W
Section 18 Timer RG
Bit
Symbol
Bit Name
Description
0
IMFA
Input capture/ [Setting conditions]
compare
• TRGCNT = GRA when GRA functions as an output
match flag A
compare register
•
R/W
R/W
The TRGCNT value is transferred to GRA by an input
capture signal when GRA functions as an input
capture register
[Clearing condition]
18.2.6
•
When the DTC is activated by an IMFA interrupt, and
the DISEL bit in MRB of the DTC is 0.
•
When IMFA is read when IMAF = 1, then 0 is written
to.
Timer RG Interrupt Enable Register (TRGIER)
TRGIER is a register that controls interrupt requests of timer RG.
Address: H'FF064B
Bit:
Value after reset:
Bit
b6
b5
b4
b3
b2
b1
b0




OVIE
UDIE
IMIEB
IMIEA
1
1
1
1
0
0
0
0
Bit Name
Description
R/W
7 to 4 
Reserved
These bits are read as 1. The write value should
always be 1.

3
Overflow interrupt
enable
0: Interrupt by the OVF flag is disabled.
R/W
Underflow interrupt
enable
0: Interrupt by the UDF flag is disabled.
Input capture/
compare match B
enable
0: Interrupt by the IMFB flag is disabled.
Input capture/
compare match A
enable
0: Interrupt by the IMFA flag is disabled.
2
1
0
Symbol
b7
OVIE
UDIE
IMIEB
IMIEA
1: Interrupt by the OVF flag is enabled.
R/W
1: Interrupt by the UDF flag is enabled.
R/W
1: Interrupt by the IMFB flag is enabled.
R/W
1: Interrupt by the IMFA flag is enabled.
Rev. 1.00 Oct. 03, 2008 Page 637 of 962
REJ09B0465-0100
Section 18 Timer RG
18.2.7
Timer RG Counter (TRGCNT)
Address: H'FF0640
Bit: b15
Value after reset:
0
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TRGCNT is a 16-bit readable/writable register that performs count operation with an input clock.
The input clock is selected by bits TPSC2 to TPSC0 in TRGCR.
TRGCNT is incremented or decremented in phase counting mode and is only incremented in other
modes.
TRGCNT can be cleared to H'0000 by a compare match with the relevant GRA or GRB or by an
input capture to GRA or GRB (counter clearing function).
When TRGCNT overflows (changes from H'FFFF to H'0000), the OVF flag in TRGSR is set to 1.
When TRGCNT underflows (changes from H'0000 to H'FFFF), the UDF flag in TRGSR is set to
1.
TRGCNT must always be read from or written to in units of 16 bits; 8-bit accesses are not
allowed. TRGCNT is initialized to H'0000 by a reset.
Rev. 1.00 Oct. 03, 2008 Page 638 of 962
REJ09B0465-0100
Section 18 Timer RG
18.2.8
General Registers A and B (GRA, GRB), GRA and GRB Buffer Registers (BRA,
BRB)
GRA
Address: H'FF0642
Bit:
Value after reset:
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GRB
Address: H'FF0644
Bit:
Value after reset:
BRA
Address: H'FF064C
Bit:
Value after reset:
BRB
Address: H'FF064E
Bit:
Value after reset:
Each of GRA and GRB is a 16-bit readable/writable register that can function as either an outputcompare register or an input-capture register. The function is selected with TRGIOR.
When a general register is used as an output-compare register, its value is constantly compared
with the TRGCNT value. When the two values match (a compare match), the corresponding flag
(the IMFA or IMFB bit) in TRGSR is set to 1. A compare match output can be selected in
TRGIOR.
When a general register is used as an input-capture register, an external input-capture signal is
detected and the current TRGCNT value is stored in the general register. The corresponding flag
(the IMFA or IMFB bit) in TRGSR is set to 1. The edge of the input-capture signal is selected in
TRGIOR. The setting of TRGIOR is ignored in PWM mode.
Rev. 1.00 Oct. 03, 2008 Page 639 of 962
REJ09B0465-0100
Section 18 Timer RG
BRA and BRB can be used as buffer registers of GRA and GRB, respectively, by setting BUFA
and BUFB in TRGIOR.
For example, when GRA is set as an output-compare register and BRA is set as the buffer register
for GRA, the value in TRGCNT is sent to GRA whenever compare match A is generated.
When GRA is set as an input-capture register and BRA is set as the buffer register for GRA, the
value in TRGCNT is transferred to GRA and the value in GRA is transferred to the buffer register
BRA whenever an input capture is generated.
General registers and buffer registers must be written or read in 16-bit units. General registers are
set as output compare registers and initialized to H'FFFF by a reset.
Rev. 1.00 Oct. 03, 2008 Page 640 of 962
REJ09B0465-0100
Section 18 Timer RG
18.3
Operation
Timer RG has the following operating modes.
• Timer mode (the waveform output function by a compare match, and the input-capture
function)
• PWM mode
• Phase counting mode
The TGIOA and TGIOB pins indicate the functions by each register setting.
• TGIOA pin
Register
Name
PMR
PCR TRGMDR TRGIOR
Bit Name PMR
PCR PWM
IOA2 to
IOA0
Function
Setting
values
X
1
XXX
PWM mode waveform output
X
0
001,
01X
Timer mode waveform output (output compare
function)
X
0
1XX
Timer mode (input capture function)
1
X
XXX
General output port
0
X
XXX
General input port
1
0
[Legend]
X:
Don't care.
Note: In timer mode (input capture function), do not select the relevant I/O pin to be an output in
the port control register.
Rev. 1.00 Oct. 03, 2008 Page 641 of 962
REJ09B0465-0100
Section 18 Timer RG
• TGIOB pin
Register
Name
PMR PCR TRGMDR TRGIOR
Bit Name
PMR PCR PWM
IOB2 to
IOB0
Setting
values
1
0
Function
X
X
001, 01X
Timer mode waveform output (output compare
function)
X
X
1XX
Timer mode (input capture function)
1
X
XXX
General output port
0
X
XXX
General input port
[Legend]
X:
Don't care.
Note: In timer mode (input capture function), do not select the relevant I/O pin to be an output in
the port control register.
18.3.1
Timer Mode
TRGCNT performs up-counting, and is also capable of free-running operation, periodic counting,
and external event counting.
Each of GRA and GRB can be used as an input capture register or output compare register.
(1)
Waveform Output by Compare Match:
The TPU can perform 0, 1, or toggle output from the corresponding output pin using a compare
match.
(a)
Example of setting procedure for waveform output by compare match
Figure 18.2 shows an example of the setting procedure for waveform output by a compare match.
Rev. 1.00 Oct. 03, 2008 Page 642 of 962
REJ09B0465-0100
Section 18 Timer RG
[1]
[1] Select 0 output, 1 output, or toggle output for
compare match output by means of TRGIOR.
When waveform output mode is selected,
the port functions for compare-match output
(TGIOA, TGIOB).
Set output timing
[2]
[2] Set the timing for compare match generation in
GRA/GRB.
[3] Set the STR bit in TRGMDR to 1 to start the
TRGCNT count operation.
Start counting
[3]
Output selection
Select waveform output mode
<Waveform output>
Figure 18.2 Example of Setting Procedure for Waveform Output by Compare Match
Table 18.3 Initial Output Values until the First Compare Match Occurs
Pin
0 is Output by Compare
Match
1 is Output by Compare
Match
Output is Toggled by
Compare Match
TGIOA
1
0
0*
TGIOB
1
0
0*
Note:
*
When the initial toggled output immediately after release from the reset state is
selected. In case where switching was from another output, the output value is that
which preceded the switch.
Rev. 1.00 Oct. 03, 2008 Page 643 of 962
REJ09B0465-0100
Section 18 Timer RG
(b)
Examples of waveform output operation
Figure 18.3 shows an example of 0 output/1 output.
In this example, TRGCNT has been designated as a free-running counter, and settings have been
made so that 1 is output by compare match A, and 0 is output by compare match B. When the set
level and the pin level match, the pin level does not change.
TRGCNT value
H'FFFF
GRB
GRA
Time
H'0000
No change
No change
1 output
TGIOB
No change
TGIOA
No change
0 output
Figure 18.3 Example of 0 Output/1 Output Operation
Figure 18.4 shows an example of toggle output. In this example TRGCNT has been designated as
a periodic counter (with counter clearing performed by compare match B), and settings have been
made so that output is toggled by both compare match A and compare match B.
TRGCNT value
Counter cleared by GRB compare match
H'FFFF
GRB
GRA
Time
H'0000
Toggle output
TGICBO
Toggle output
TGIOA
Figure 18.4 Example of Toggle Output Operation
Rev. 1.00 Oct. 03, 2008 Page 644 of 962
REJ09B0465-0100
Section 18 Timer RG
(c)
Output compare output timing
A compare match signal is generated in the final state in which TRGCNT and GR match (the point
at which the count value matched by TRGCNT is updated). When a compare match signal is
generated, the output value set in TRGIOR is output at the output compare output pin (TGIOA,
TGIOB). After a match between TRGCNT and GR, the compare match signal is not generated
until the TRGCNT input clock is generated.
Figure 18.5 shows output compare output timing.
φ
TRGCNT
input clock
N
TRGCNT
N+1
N
GRA , GRB
Compare
match signal
TGIOA, TGIOB
Figure 18.5 Output Compare Output Timing
(2)
Input Capture Function
The TRGCNT value can be transferred to GR on detection of the input-capture/output-compare
pin (TGIOA, TGIOB) input edge. Rising edge, falling edge, or both edges can be selected as the
detection edge. The pulse width and cycle period can be measured using the input capture
function.
Rev. 1.00 Oct. 03, 2008 Page 645 of 962
REJ09B0465-0100
Section 18 Timer RG
(a)
Example of setting procedure for input capture operation
Figure 18.6 shows an example of the setting procedure for input capture operation.
Input selection
Select input-capture input
[1]
Start counting
[2]
[1] Designate GR as an input capture register by
means of TRGIOR, and select the input capture
signal input edge (rising edge, falling edge, or
both edges).
[2] Set the STR bit in TRGMDR to 1 to start the
TRGCNT count operation.
<Input capture operation>
Figure 18.6 Example of Setting Procedure for Input Capture Operation
Rev. 1.00 Oct. 03, 2008 Page 646 of 962
REJ09B0465-0100
Section 18 Timer RG
(b)
Example of input capture operation
Figure 18.7 shows an example of input capture operation.
In this example both rising and falling edges have been selected as the TGIOA pin input capture
input edge, falling edge has been selected as the TGIOB pin input capture input edge, and counter
clearing by GRB input capture has been designated for TRGCNT.
TRGCNT value
H'0180
H'0160
H'0005
H'0000
Time
TGIOB
TGIOA
GRA
H'0005
GRB
H'0160
H'0180
Figure 18.7 Example of Input Capture Operation
(c)
Input capture signal timing
Rising edge, falling edge, or both edges can be selected as the detection edge for input capture
with TRGIOR.
Figure 18.8 shows input capture signal timing when the falling edge has been selected.
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection.
Rev. 1.00 Oct. 03, 2008 Page 647 of 962
REJ09B0465-0100
Section 18 Timer RG
φ
Input-capture
input
Input capture
signal
TRGCNT
N-1
N
GRA, GRB
N+1
N+2
N
Figure 18.8 Input Capture Input Signal Timing
18.3.2
PWM Mode
In PWM mode, the PWM waveform is output from the TGIOA output pin by using GRA and
GRB as a pair. When an output pin is set for PWM mode, the TRGIOR output setting is ignored.
The high level output timing for PWM waveform is set in GRA and the low level output timing in
GRB.
Designating GRA or GRB compare match as the TRGCNT counter clearing source enables
outputting a PWM waveform in the range of 0% to 100% duty cycle from the TGIOA pin.
The correspondence between PWM output pins and registers is shown in table 18.4. When the
same value is set in GRA and GRB, the output value does not change even if a compare match
occurs.
Table 18.4 PWM Output Pins and Registers
Output Pin
Output 1
Output 0
TGIOA
GRA
GRB
TGIOB
Rev. 1.00 Oct. 03, 2008 Page 648 of 962
REJ09B0465-0100
Functions as general I/O port
Section 18 Timer RG
(1)
Example of PWM Mode Setting Procedure
Figure 18.9 shows an example of the PWM mode setting procedure.
PWM mode
Select counter clock
[1]
Select counter clearing source
[2]
Set GRA
[3]
Set GRB
[4]
Set PWM mode
[5]
Start counting
[6]
[1] Select the counter clock with bits TPSC2 to
TPSC0 in TRGCR. When an external clock is
selected, select the external clock edge with bits
CKEG1 and CKEG0 in TRGCR.
[2] Use bits CCLR1 and CCLR0 in TRGCR to
select the counter clearing source.
[3] Set the 1-output timing for the output PWM
waveform with GRA.
[4] Set the 0-output timing for the output PWM
waveform with GRB.
[5] Select the PWM mode with the PWM bit in
TRGMDR. When PWM mode is set, GRA and
GRB are used as output compare registers for
setting 1-output/0-output for PWM output
waveform, regardless of the TRGIOR setting.
At this time, the TGIOA pin is automatically
designated as a PWM output pin and the TGIOB
pin is used as a general I/O for the relevant port.
[6] Set the STR bit in TRGMDR to 1 to start the
count operation.
<PWM mode>
Figure 18.9 Example of PWM Mode Setting Procedure
(2)
Examples of PWM Mode Operation
Figure 18.10 shows examples of PWM mode operation.
When PWM mode is set, the TGIOA pin is automatically set as an output pin. The TGIOA pin
outputs 1 on a GRA compare match and outputs 0 on a GRB compare match. The TGIOB pin
always functions as an I/O pin for the relevant port.
In the examples shown in the figure, GRA and GRB compare matches are set as the TRGCNT
clearing source. The initial value of TGIOA differs according to the counter clearing source. The
correspondence between counter clearing sources and initial values is shown in table 18.5.
Rev. 1.00 Oct. 03, 2008 Page 649 of 962
REJ09B0465-0100
Section 18 Timer RG
Table 18.5 Correspondence between Counter Clearing Sources and TGIOA Initial Values
Counter Clearing Source
TGIOA Initial Value
GRA compare match
1
GRB compare match
0
TRGCNT value
Counter cleared on
compare match A
GRA
GRB
H'0000
Time
TGIOA
(a) Counter cleared by GRA
TRGCNT value
Counter cleared
on compare match B
GRB
GRA
H'0000
Time
TGIOA
(b) Counter cleared by GRB
Figure 18.10 Example of PWM Mode Operation (1)
Rev. 1.00 Oct. 03, 2008 Page 650 of 962
REJ09B0465-0100
Section 18 Timer RG
Figure 18.11 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle
in PWM mode. When GRB compare match is set as the counter clearing source and the set value
in GRA is greater than the value in GRB, the duty cycle of the PWM waveform is 0%. When
GRA compare match is set as the counter clearing source and the set value in GRB is greater than
the value in GRA, the duty cycle is 100%.
Rev. 1.00 Oct. 03, 2008 Page 651 of 962
REJ09B0465-0100
Section 18 Timer RG
TRGCNT value
Counter cleared on compare match B
GRB
GRA
H'0000
Time
TGIOA
GRA write
GRA write
(a) 0% duty cycle
TRGCNT value
Counter cleared on compare match A
GRA
GRB
H'0000
Time
TGIOA
GRB write
GRB write
(b) 100% duty cycle
Figure 18.11 Example of PWM Mode Operation (2)
Rev. 1.00 Oct. 03, 2008 Page 652 of 962
REJ09B0465-0100
Section 18 Timer RG
18.3.3
Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs (TCLKA and
TCLKB pins) is detected and TRGCNT is incremented/decremented accordingly.
When phase counting mode is set, the TCLKA and TCLK pins function as external clock input
pins and TRGCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to
TPSC0 and bits CKEG1 and CKEG0 in TRGCR.
(1)
Example of Phase Counting Mode Setting Procedure
Figure 18.12 shows an example of the phase counting mode setting procedure.
[1] Select phase counting mode with the MDF bit in TRGMDR.
Phase counting mode
[2] Select phase counting condition by setting TRGCNTCR.
Select phase counting mode
[1]
Set phase counting condition
[2]
Start counting
[2]
[3] Set the STR bit in TRGMDR to 1 to start the count
operation.
<Phase counting mode>
Figure 18.12 Example of Phase Counting Mode Setting Procedure
Rev. 1.00 Oct. 03, 2008 Page 653 of 962
REJ09B0465-0100
Section 18 Timer RG
(2)
Examples of Phase Counting Mode Operation
Figures 18.13 to 18.16 show examples of phase counting mode operation, and tables 18.6 to 18.9
summarize the TRGCNT increment/decrement conditions.
Table 18.6 Increment/Decrement Conditions in Phase Counting Mode Operation Example
1 (TRGCNTCR = H'FF)
TRGCNTCR
Set Value
TCLKA
TCLKB
Operation
CNTEN7
1
Low level
CNTEN6
1
CNTEN5
1
CNTEN4
1
Low level
CNTEN3
1
High level
CNTEN2
1
CNTEN1
1
CNTEN0
1
Increment
High level
High level
Decrement
Low level
Low level
High level
[Legend]
: Rising edge
: Falling edge
TCLKB
TCLKA
Increment
Decrement
Figure 18.13 Phase Counting Mode Operation Example 1 (TRGCNTCR = H'FF)
Rev. 1.00 Oct. 03, 2008 Page 654 of 962
REJ09B0465-0100
Section 18 Timer RG
Table 18.7 Increment/Decrement Conditions in Phase Counting Mode Operation Example
2 (TRGCNTCR = H'24)
TRGCNTCR
Set Value
TCLKA
TCLKB
Operation
CNTEN7
0
Low level
CNTEN6
0
CNTEN5
1
CNTEN4
0
Low level
CNTEN3
0
High level
CNTEN2
1
CNTEN1
0
CNTEN0
0
Don't care
High level
High level
Increment
Don't care
Low level
Decrement
Low level
Don't care
High level
[Legend]
: Rising edge
: Falling edge
TCLKB
TCLKA
Increment
Decrement
Figure 18.14 Phase Counting Mode Operation Example 2 (TRGCNTCR = H'24)
Rev. 1.00 Oct. 03, 2008 Page 655 of 962
REJ09B0465-0100
Section 18 Timer RG
Table 18.8 Increment/Decrement Conditions in Phase Counting Mode Operation Example
3 (TRGCNTCR = H'28)
TRGCNTCR
Set Value
TCLKA
TCLKB
Operation
CNTEN7
0
Low level
CNTEN6
0
CNTEN5
1
CNTEN4
0
Low level
Don't care
CNTEN3
1
High level
Decrement
CNTEN2
0
CNTEN1
0
CNTEN0
0
Don't care
High level
High level
Increment
Don't care
Low level
Low level
High level
[Legend]
: Rising edge
: Falling edge
TCLKB
TCLKA
Increment
Decrement
Figure 18.15 Phase Counting Mode Operation Example 3 (TRGCNTCR = H'28)
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Section 18 Timer RG
Table 18.9 Increment/Decrement Conditions in Phase Counting Mode Operation Example
4 (TRGCNTCR = H'5A)
TRGCNTCR
Set Value
TCLKA
TCLKB
Operation
CNTEN7
0
Low level
CNTEN6
1
CNTEN5
0
CNTEN4
1
Low level
Increment
CNTEN3
1
High level
Decrement
CNTEN2
0
CNTEN1
1
CNTEN0
0
Don't care
High level
Increment
High level
Don't care
Low level
Don't care
Low level
Decrement
High level
Don't care
[Legend]
: Rising edge
: Falling edge
TCLKB
TCLKA
Increment
Decrement
Figure 18.16 Phase Counting Mode Operation Example 4 (TRGCNTCR = H'5A)
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Section 18 Timer RG
(3)
Note on Phase Counting Mode
In phase counting mode, the phase difference and overlap between TCLKA and TCLKB must be
at least 1.5 × φ cycle of the system clock when bits TPSC2 to TPSC0 in TRGCR = B'0XX or
B'100, and the pulse width must be at least 3 × φ cycle. If B'110 is selected as the value, the phase
difference and overlap must be at least 1.5 × φ40 cycles and the pulse width at least 3 × φ40
cycles. Figure 18.17 shows the input clock conditions in phase counting mode.
Pulse
width
Pulse
width
Phase
difference
Phase
difference
TCLKA
TCLKB
Overlap
Overlap
Phase difference and overlap: 1.5 states or more
Pulse width: 2.5 states or more
Figure 18.17 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Note: When CNTEN7 to CNTEN0 in TRGCNTCR are cleared, the counting is not performed
even if an increment/decrement condition matches.
18.3.4
Buffer Operation
Buffer operation differs depending on whether GR has been designated as an input capture register
or a compare match register.
Table 18.10 shows the register combinations used in buffer operation.
Table 18.10 Register Combinations in Buffer Operation
General Register
Buffer Register
GRA
BRA
GRB
BRB
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Section 18 Timer RG
(1)
When GR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the general register. This operation is illustrated in figure 18.18.
Compare match signal
Buffer register
General
register
Comparator
TRGCNT
Figure 18.18 Compare Match Buffer Operation
(2)
When TGR is an input capture register
When input capture occurs, the value in TRGCNT is transferred to GR and the value previously
held in the general register is transferred to the buffer register. This operation is illustrated in
figure 18.19.
Input capture
signal
Buffer register
General
register
TRGCNT
Figure 18.19 Input Capture Buffer Operation
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REJ09B0465-0100
Section 18 Timer RG
Figures 18.20 and 18.21 show the timings in buffer operation.
φ
Input capture
signal
TRGCNT
N
GRA
GRB
M
BRA
BRB
N+1
N
N+1
M
N
Figure 18.20 Buffer Operation Timing (Compare Match)
φ
Compare match
signal
TRGCNT
N
BRA
BRB
M
GRA
GRB
N
N+1
M
Figure 18.21 Buffer Operation Timing (Input Capture)
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Section 18 Timer RG
18.3.5
Operation through an Event Link
Using the event link controller (ELC), timer RG can be made to operate in the following ways in
relation to events occurring in other modules.
(1)
Staring Counter Operation
The start of counting operations by timer RG can be selected by ELOPC of the ELC. When the
event specified by ELSR8 occur, the STR bit in TRGMDR is set to 1, which starts counting by
timer RG. However, if the specified event occurs when the STR bit has already been set to 1, the
event is not effective.
(2)
Counting Event
The counting of events by timer RG can be selected by ELOPC of the ELC. When the event
specified in ELSR8 occurs, event counter operation proceeds with that event as the source to drive
counting, regardless of the setting of TPSC[2:0] bits in TRGCR. When the value of the counter is
read, the value read out is the actual number of input events.
(3)
Input Capture
Input capture operation of timer RG can be selected by ELOPC of the ELC. When the event
specified in ELSR8 occurs, GRB captures the value of TRGCNT. When input capture operation
initiated by an event link is in use, set IOB[2:0] = b'101 in the TRGIOR register of timer RG, set
the STR bit in TRGMDR, and then start the counter. Since input on the TGIOB pin becomes valid
at the same time, fix the input to the TGIOB pin or take other measures such as not allocating the
TGIOB pin to the port in the PMC, etc.
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Section 18 Timer RG
18.3.6
Digital Filtering Function for Input Capture Inputs
Input signals on the TGIOA and TGIOB pins can be input via the digital filters. The digital filter
includes three latches connected in series and a matching detecting circuit. The input signals on
the TGIOA and TGIOB pins are operated on the sampling clock specified by the DFCK1 and
DFCK0 bits in TRGMDR. When outputs of the three latches match, the matching detecting circuit
outputs the signal level of the input. Otherwise, the output remains unchanged. That is, when a
pulse width is equal to or greater than three sampling clock cycles, the pulse is input as a signal.
When a pulse width is less than three sampling clock cycles, the pulse is considered as a noise to
be removed.
TPSC2 to
TPSC0
φ/32
φ/8
φ
TCLKB
TCLKA
φ40
φ/32
φ/8
φ/4
φ/2
φ
TGIOA and TGIOB
input signals
DFCK1 and
DFCK0
DFA and DFB
Sampling clock
C
C
C
D
Q
Latch
D
D
Q
Latch
Latch
C
Q
Q
D
Latch
Matching
detecting
circuit
Selecter
φ, φ40
C
Q
D
Latch
Cycle of a clock specified
by TPSC2 to TPSC0
or DFCK1 and DFCK0
Sampling clock
TGIOA and TGIOB
input signal
Digital-filtered signal
Signal propagation delay:
5 sampling clocks
Signal change is not output unless
signal levels match three times.
Figure 18.22 Block Diagram of Digital Filter
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IOA[1:0] and
IOB[1:0]
Edge
detecting
circuit
Section 18 Timer RG
18.4
Usage Note
18.4.1
Restrictions on Access to Registers when Internal φ40 Clock is Selected as Counter
Clock
When the internal φ40 clock is selected as the counter clock (the TPSC[2:0] bits in TRGCR =
110), if any register of timer RG is to be read immediately after writing to another register in a
given module, proceed with reading after having executed one NOP instruction.
Write to TRGMDR.
Execute NOP.
Read TRGCNT.
Figure 18.23 Example of Flow for Reading Immediately after Writing to a Register
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Section 18 Timer RG
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Section 19 Watchdog Timer (WDT)
Section 19 Watchdog Timer (WDT)
The watchdog timer (WDT) is an 8-bit timer that can generate an internal reset signal for this LSI
if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow.
The block diagram of the watchdog timer is shown in figure 19.1.
Low-speed OCO
φ
Prescaler
Prescaler
TCWD
Subclock
Prescaler
TMWD
Internal data bus
TCSRWD
TICRWD
TIFRWD
Internal reset signal
WDT interrupt
Figure 19.1 Block Diagram of Watchdog Timer
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REJ09B0465-0100
Section 19 Watchdog Timer (WDT)
19.1
Features
• Selectable from fifteen clock sources
 Eight clocks generated by dividing φ: φ/64, φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096,
and φ/8192
 Five clocks generated by dividing low-speed OCO clock: φloco/8, φloco/32, φloco/128,
φloco/512, and φloco/1024
 Two clocks generated by dividing subclock: φsub/4 and φsub/256
When the low-speed OCO clock or subclock is selected, the WDT operates as the watchdog
timer in any operating mode.
• Reset signal generated on counter overflow
An overflow period of 1 to 256 times the selected clock can be set.
• The watchdog timer is enabled in the initial state.
The watchdog timer starts operating after a reset is released.
• Periodic timer function
The timer counter can also be used as a periodic timer. Interrupts can be generated with a
specific count value.
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Section 19 Watchdog Timer (WDT)
19.2
Register Descriptions
The watchdog timer has the following registers.
•
•
•
•
•
Timer control/status register WD (TCSRWD)
Timer counter WD (TCWD)
Timer mode register WD (TMWD)
Timer interrupt control/status register WD (TICRWD)
Timer interrupt flag register WD (TIFRWD)
19.2.1
Timer Control/Status Register WD (TCSRWD)
Address: H'FFFF9A
b7
b6
b5
b4
b3
b2
b1
b0
B6WI
TCWE
B4WI
TCSRWE
TMWLOCK
TMWI


Value after reset:
1
0
1
0
0
1
1
1
Bit
Symbol
Bit Name
Description
R/W
7
B6WI
Bit 6 write
inhibit
0: Writing to the TCWE bit (bit 6 in this register) is
enabled.
R/W
Bit:
1: Writing to the TCWE bit (bit 6 in this register) is
disabled.
This bit is always read as 1.
6
TCWE
Timer counter 0: Writing to the TCWD register is disabled.
WD write
1: Writing to the TCWD register is enabled.
enable
Before writing data to this bit, the B6WI bit must be
cleared to 0.
R/W
5
B4WI
Bit 4 write
inhibit
R/W
0: Writing to the TCSRWE bit (bit 4) is enabled.
1: Writing to the TCSRWE bit (bit 4) is disabled.
This bit is always read as 1.
4
TCSRWE
Timer
0: Writing to TMWLOCK and TMWI (bits 3 and 2 in this
R/W
control/status
register) is disabled.
register WD 1: 0: Writing to TMWLOCK and TMWI (bits 3 and 2 in this
write enable
register) is enabled.
Before writing data to this bit, the B4WI bit must be
cleared to 0.
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Section 19 Watchdog Timer (WDT)
Bit
Symbol
Bit Name
3
TMWLOCK Timer mode
register WD
lockdown
Description
R/W
This register is write-protected when this bit is 1. Once
this bit is set to 1, this bit can be cleared only by a reset.
R/W
0: Writing to the TMWD register is enabled.
1: Writing to the TMWD register is disabled.
[Setting condition]
•
When 1 is written to this bit
[Clearing condition]
•
2
TMWI
Resetting
Timer mode 0: Writing to the TMWD register is enabled.
register write 1: Writing to the TMWD register is disabled.
inhibit
[Setting conditions]
R/W
•
This bit is automatically set to 1 after TMWD is written
to.
•
When 1 is written to this bit.
[Clearing condition]
•
1, 0 
Reserved
When 0 is written to TMWI while TMWI is 1
These bits are read as 1. The write value should always
be 1.

Note: TCSRWD must be rewritten by using the MOV instruction. The bit manipulation instruction
cannot be used to change the setting value.
19.2.2
Timer Counter WD (TCWD)
Address: H'FFFF98
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
Value after reset:
0
0
0
0
0
0
0
0
TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the
internal reset signal is generated. TCWD is initialized to H'00. TCWD can also be used as a
periodic timer. It issues an interrupt request to the CPU when the upper two bits in TCWD are
B'01, B'10, or B'11 according to the TICRWD setting.
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Section 19 Watchdog Timer (WDT)
19.2.3
Timer Mode Register WD (TMWD)
Address: H'FFFF99
Bit:
b7
b6
b5
b4




1
1
1
1
Value after reset:
b3
b2
0
0
b1
b0
0
0
CKS[3:0]
Bit
Symbol
Bit Name
Description
R/W
7 to 4

Reserved
These bits are read as 1. The write value should
always be 1.

3 to 0
CKS[3:0]
Clock select
0000: Internal clock: counts on φloco/8 (initial value) R/W
0001: Internal clock: counts on φloco/32
0010: Internal clock: counts on φloco/128
0011: Internal clock: counts on φloco/512
0100: Internal clock: counts on φloco/1024
0101: Internal clock: counts on sub/4
0110: Internal clock: counts on φsub/256
0111: Clock input prohibited.
1000: Internal clock: counts on φ/64
1001: Internal clock: counts on φ/128
1010: Internal clock: counts on φ/256
1011: Internal clock: counts on φ/512
1100: Internal clock: counts on φ/1024
1101: Internal clock: counts on φ/2048
1110: Internal clock: counts on φ/4096
1111: Internal clock: counts on φ8192
• CK3[3:0] bits (clock select)
The method by which this register is written differs from other registers. The register must be
written by using the MOV instruction twice in succession. First, write the data to be loaded to
TMWD in a first operation, then write a bit reversal value of the data to be loaded in a second
operation. When correct operation is executed, CKS[3:0] bits are rewritten after the second
write. If the first data and the second reversal data do not match, all bits are not modified. Set
CK3[3:0] bits to B'0111 (clock input prohibited) to stop WDT operation.
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Section 19 Watchdog Timer (WDT)
19.2.4
Timer Interrupt Control Register WD (TICRWD)
Address: H'FFFF9B
Bit:
b7
Value after reset:
1
b6
INTSEL[1:0]
1
Bit Name
b5
b4
b3
b2
b1
b0
IWIE





0
1
1
1
1
1
Bit
Symbol
Description
7, 6
INTSEL[1:0] WDT periodic 00: Setting prohibited
interrupt
01: An interrupt is generated when the upper two bits
condition
in TCWD is B'01.
select
10: An interrupt is generated when the upper two bits
in TCWD is B'10.
R/W
R/W
11: An interrupt is generated when the upper two bits
in TCWD is B'11. (Initial value)
5
IWIE
4 to 0 
WDT periodic 0: Periodic interrupt request is disabled.
interrupt
1: Periodic interrupt request is enabled.
enable
R/W
Reserved

These bits are read as 1. The write value should
always be 1.
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Section 19 Watchdog Timer (WDT)
19.2.5
Timer Interrupt Flag Register WD (TIFRWD)
Address: H'FFFF9C
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
IWF







0
1
1
1
1
1
1
1
Bit
Symbol
Bit Name
Description
R/W
7
IWF
WDT periodic
interrupt
request flag
0: No periodic interrupt request
R/W
1: Periodic interrupt request is generated.
[Setting condition]
•
When the upper two bits in the timer counter WD
agree with the value set by the INTSEL[1:0] bits in
TICRWD.
[Clearing condition]
•
6 to 0

Reserved
When 0 is written to IWF after reading IWF = 1.
These bits are read as 1. The write value should
always be 1.

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Section 19 Watchdog Timer (WDT)
19.3
Operation
19.3.1
Watchdog Timer Overflow Reset
The watchdog timer is provided with an 8-bit counter. After a reset is released, TCWD starts
counting up. When the TCWD count value overflows H'FF, an internal reset signal is generated.
Since TCWD is a writable counter, it starts counting from the value set in TCWD. An overflow
period in the range of 1 to 256 input clock cycles can therefore be set, according to the TCWD set
value.
When the watchdog timer is not used, write 0 simultaneously to TMWLOCK and TMWI in
TCSRWD while the TCSRWE bit is 1 and set CKS[3:0] in TMWD to B'0111 (clock input
prohibited).
Figure 19.2 shows an example of watchdog timer operation.
Example: With 30-ms overflow period when φ = 4 MHz (selects φ/8192 for clock source)
4 x 106
x 30 x 10–3 = 14.6
8192
Therefore, 256 – 15 = 241 (H'F1) is set in TCW.
TCWD overflow
H'FF
H'F1
TCWD
count value
H'00
H'F1 written to
TCWD
H'F1 written to TCWD
Reset generated
Internal reset signal
Figure 19.2 Watchdog Timer Operation Example
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Section 19 Watchdog Timer (WDT)
19.3.2
Watchdog Timer Setting Flow
The watchdog timer should be set using the procedure shown in figure 19.3.
Reset released
Clear B4WI to 0 and set
TCSRWE to 1 in TCSRWD.
After reset is released, the WDT starts counting
with φloco/8.
[1][2]Set TMWD to write-enable.
[1]
[3][4]The clock source is changed. In this
flowchart, the clock is changed to
φloco/32. In [3], the set value is
continuously written to with the MOV
instruction. In [4], the bit-set value is
bit-inverted and written.
[2]
Clear TMWI in TCSRWD to 0.
N
Is WDT used?
[5][6]When the watchdog timer is not used,
clock input is set to be disabled. In [5],
the set value is continuously written to
with the MOV instruction. In [6], the bitset value is bit-inverted and written.
Y
N
Is clock source
changed?
Y
Set TMWD to H'F1
[3]
Set TMWDto H'F7
[5]
Set TMWD to H'FE
[4]
Set TMWD to H'F8
[6]
Set TMWI in TCSRWD to 1.
[7]
[7]
After TMWD is written to, the TMWI bit
in TCSRWD is automatically set to 1.
[8]
To lock down TMWD, set the
TMWLOCK bit in TCSRWD to 1.
N
Is TMD locked down?
Y
TMWLOCK in TCSRWD
1.
[8]
End
Figure 19.3 Watchdog Timer Setting Flow
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Section 19 Watchdog Timer (WDT)
19.3.3
Watchdog Timer Periodic Interrupt
When the INTSEL[1:0] bits in TICRWD are set and the timer WD counter reaches the set value,
the IWF bit in TIRWD is set to 1. At this time, if the IWIE bit in TICRWD is 1, an interrupt
request is generated. Figure 19.4 shows the interrupt generation timing when INTSEL is B'01.
φ
TCWD
H'3F
H'40
Interrupt request
flag setting signal
IWF
Figure 19.4 Periodic Interrupt Generation Timing (INTSEL = B'01)
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REJ09B0465-0100
Section 19 Watchdog Timer (WDT)
19.4
Usage Notes
19.4.1
Notes on System Design
While the watchdog timer is a useful function that restores the LSI to normal condition if the
system runs erratically for some reason, the watchdog timer may fail to be reset properly in
situations such as the perpetuation of an endless loop in a specific programming routine in which a
counter setting operation is executed. Also, there is a possibility of the watchdog timer not being
reset properly despite an erratic system condition if an interrupt is enabled and a counter value is
set within the interrupt processing.
These notes should be taken into consideration in the system design phases.
19.4.2
Notes on Stopping the Watchdog Timer or Switching the Count Clock
The MSTWDT bit in MSTCR1 is set to 1 after release from a reset, but the watchdog timer will
operate since φloco/8 is selected as the counter clock. (and, since the WDT is in module standby
mode, access to the registers is disabled). To stop the watchdog timer or switch the count clock,
proceed after releasing the WDT from module standby by clearing the MSTWDT bit in MSTCR1
to 0.
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Section 19 Watchdog Timer (WDT)
Rev. 1.00 Oct. 03, 2008 Page 676 of 962
REJ09B0465-0100
Section 20 Serial Communication Interface 3 (SCI3, IrDA)
Section 20 Serial Communication Interface 3 (SCI3, IrDA)
This LSI includes a serial communication interface 3 (SCI3), which has three independent
channels. The SCI3 can handle both asynchronous and clocked synchronous serial
communication. In asynchronous mode, serial data communication can be carried out using
standard asynchronous communication chips such as a Universal Asynchronous
Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA). A
function is also provided for serial communication between processors (multiprocessor
communication function).
Table 20.1 shows the SCI3 channel configuration and figure 20.1 shows a block diagram of the
SCI3. Since pin functions are identical for each of the three channels (SCI3, SCI3_2, and SCI3_3),
separate explanations are not given in this section.
20.1
Features
• Choice of asynchronous or clocked synchronous serial communication mode
• Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously.
Double-buffering is used in both the transmitter and the receiver, enabling continuous
transmission and continuous reception.
• On-chip baud rate generator allows any bit rate to be selected
• External clock or on-chip baud rate generator can be selected as a transfer clock source.
• Six interrupt sources
Transmit-end, transmit-data-empty, receive-data-full, overrun error, framing error, and parity
error. The DTC can be activated by the transmit-data-empty interrupt and receive-data-full
interrupt sources.
Asynchronous mode
•
•
•
•
•
Data length: 7 or 8 bits
Stop bit length: 1 or 2 bits
Parity: Even, odd, or none
Receive error detection: Parity, overrun, and framing errors
Break detection: Break can be detected by reading the RXD pin level directly in the case of a
framing error
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
Clocked synchronous mode
• Data length: 8 bits
• Receive error detection: Overrun errors
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
Table 20.1 Channel Configuration
Channel
Channel 1
Channel 2
Channel 3
Abbreviation Pin
SCI3*
1
SCI3_2*2
SCI3_3
SCK3
RXD
TXD
SCK3_2
RXD_2/IrRxD
TXD_2/IrTxD
SCK3_3
RXD_3
TXD_3
Register
Register Address
Noise Canceler
SMR
H'FF0550
Available
BRR
H'FF0551
SCR3
H'FF0552
TDR
H'FF0553
SSR
H'FF0554
RDR
H'FF0555
RSR

TSR

SPMR
H'FF0556
SMR_2
H'FF0558
BRR_2
H'FF0559
SCR3_2
H'FF055A
TDR_2
H'FF055B
SSR_2
H'FF055C
RDR_2
H'FF055D
RSR_2

TSR_2

SPMR
H'FF055E
IrCR
H'FF05DE
SMR_3
H'FF0560
BRR_3
H'FF0561
SCR3_3
H'FF0562
TDR_3
H'FF0563
SSR_3
H'FF0564
RDR_3
H'FF0565
RSR_3

TSR_3

SPMR_3
H'FF0566
Available
Available
Notes: 1. Channel 1 of the SCI3 is used in on-board programming mode by boot mode.
2. SCI3_2 provides IrDA (Infrared Data Association) communication waveform
transmission/reception according IrDA standard version 1.0.
Rev. 1.00 Oct. 03, 2008 Page 679 of 962
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
SCK3
External
clock
Internal clock (φ/64, φ/16, φ/4, φ)
Baud rate generator
BRC
BRR
Clock
Internal data bus
SMR
Transmit/receive
control circuit
SCR3
SSR
RXD
TXD
TSR
TDR
SPMR
RSR
RDR
Interrupt request
(TEI, TXI, RXI, ERI)
(1) SCI3 and SCI3_3
External
clock
SCK3
Baud rate generator
Internal clock (φ/64, φ/16, φ/4, φ)
BRC
BRR
Clock
SCR3
SSR
TSR
TDR
RSR
RDR
Internal data bus
SMR
Transmit/receive
control circuit
TxD_2/IrTxD
RXD_2/IrRxD
SPMR
IrCR
Interrupt request
(TEI, TXI, RXI, ERI)
(2) SCI3_2
Figure 20.1 Block Diagram of SCI3
Rev. 1.00 Oct. 03, 2008 Page 680 of 962
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
Table 20.2 shows the SCI3 pin configuration.
Table 20.2 Pin Configuration
Channel
Pin Name
I/O
Function
1
SCK3
I/O
Clock input/output for channel 1
RXD
Input
Receive data input for channel 1
TXD
Output
Transmit data output for channel 1
SCK3_2
I/O
Clock input/output for channel 2
RXD_2/IrRxD
Input
Receive data input for channel 2/IrDA receive data
input
TXD_2/IrTxD
Output
Transmit data output for channel 2/IrDA transmit data
output
SCK3_3
I/O
Clock input/output for channel 3
RXD_3
Input
Receive data input for channel 3
TXD_3
Output
Transmit data output for channel 3
2
3
Rev. 1.00 Oct. 03, 2008 Page 681 of 962
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
20.2
Register Descriptions
The SCI3 has the following registers.
Channel 1
• Receive shift register (RSR)
• Receive data register (RDR)
• Transmit shift register (TSR)
• Transmit data register (TDR)
• Serial mode register (SMR)
• Serial control register (SCR3)
• Serial status register (SSR)
• Bit rate register (BRR)
• Sampling mode register (SPMR)
Channel 2
• Receive shift register (RSR)
• Receive data register (RDR)
• Transmit shift register (TSR)
• Transmit data register (TDR)
• Serial mode register (SMR)
• Serial control register (SCR3)
• Serial status register (SSR)
• Bit rate register (BRR)
• Sampling mode register (SPMR)
• IrDA control register (IrCR)
Channel 3
• Receive shift register (RSR)
• Receive data register (RDR)
• Transmit shift register (TSR)
• Transmit data register (TDR)
• Serial mode register (SMR)
• Serial control register (SCR3)
• Serial status register (SSR)
• Bit rate register (BRR)
• Sampling mode register (SPMR)
Rev. 1.00 Oct. 03, 2008 Page 682 of 962
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
20.2.1
Receive Shift Register (RSR)
Address: 
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
Value after reset:








RSR is a shift register that is used to receive serial data input from the RXD pin and convert it into
parallel data. When one frame of data has been received, it is transferred to RDR automatically.
RSR cannot be directly accessed by the CPU.
20.2.2
Receive Data Register (RDR)
Address: H'FF0555, H'FF055D, H'FF0565
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
Value after reset:
0
0
0
0
0
0
0
0
RDR is an 8-bit register that stores received data. When the SCI3 has received one frame of data,
it transfers the received data from RSR to RDR, where it is stored. After this, RSR is receiveenabled. As RSR and RDR function as a double buffer in this way, continuous receive operations
are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only once. RDR
cannot be written to by the CPU. RDR is initialized to H'00.
20.2.3
Transmit Shift Register (TSR)
Address: 
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
Value after reset:








TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI3 first
transfers transmit data from TDR to TSR automatically, then sends the data that starts from the
LSB to the TXD pin. TSR cannot be directly accessed by the CPU.
Rev. 1.00 Oct. 03, 2008 Page 683 of 962
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
20.2.4
Transmit Data Register (TDR)
Address: H'FF0553, H'FF055B, H'FF0563
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
Value after reset:
1
1
1
1
1
1
1
1
TDR is an 8-bit register that stores data for transmission. When the SCI3 detects that TSR is
empty, it transfers the transmit data written in TDR to TSR and starts transmission. The doublebuffered structure of TDR and TSR enables continuous transmission. If the next transmit data has
already been written to TDR during transmission of one-frame data, the SCI3 transfers the written
data to TSR to continue transmission. To achieve reliable serial transmission, write transmit data
to TDR only once after confirming that the TDRE bit in SSR is set to 1. TDR is initialized to
H'FF.
20.2.5
Serial Mode Register (SMR)
Address: H'FF0550, H'FF0558, H'FF0560
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
COM
CHR
PE
PM
STOP
MP
0
0
0
0
0
0
Bit
Symbol
Bit Name
7
COM
Communication mode 0: Asynchronous mode
b0
b1
CKS[1:0]
0
Description
0
R/W
R/W
1: Clocked synchronous mode
6
CHR
Character length
(Enabled only in asynchronous mode)
R/W
0: Selects 8 bits as the data length.
1: Selects 7 bits as the data length.
5
PE
Parity enable
(Enabled only in asynchronous mode)
0: Parity bit addition and parity check are
disabled.
1: The parity bit is added in transmission and the
parity bit is checked in reception.
Rev. 1.00 Oct. 03, 2008 Page 684 of 962
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
Bit
Symbol
Bit Name
Description
R/W
4
PM
Parity mode
(Enabled only when the PE bit is 1 in
asynchronous mode)
R/W
0: Selects even parity.
1: Selects odd parity.
3
STOP
Stop bit length
(Enabled only in asynchronous mode)
R/W
0: 1 stop bit
1: 2 stop bits
2
MP
Multiprocessor mode
0: The multiprocessor communication function is R/W
disabled.
1: The multiprocessor communication function is
enabled*2
1
CKS1
0
CKS0
Clock select 0 and 1
00: φ clock (n = 0)
R/W
01: φ/4 clock (n = 1)
10: φ/14 clock (n = 2)
11: φ/64 clock (n = 3)
Notes: 1. The SMR value is retained when (module) standby mode is entered.
2. In clocked synchronous mode, clear this bit to 0.
• STOP bit (stop bit length)
Selects the stop bit length in transmission. For reception, only the first stop bit is checked,
regardless of the value in the bit. If the second stop bit is 0, it is treated as the start bit of the
next transmit character.
• MP bit (multiprocessor mode)
When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit
and PM bit settings are invalid in multiprocessor mode.
• CKS1 bit and CKS0 bit (clock select 1, 0)
These bits select the clock source for the baud rate generator.
For the relationship between the bit rate register setting and the baud rate, see section 20.2.8,
Bit Rate Register (BRR). n is the decimal representation of the value of n in BRR (see section
20.2.8, Bit Rate Register (BRR)).
Rev. 1.00 Oct. 03, 2008 Page 685 of 962
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
20.2.6
Serial Control Register 3 (SCR3)
Address: H'FF0552, H'FF055A, H'FF0562
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
TIE
RIE
TE
RE
MPIE
TEIE
0
0
0
0
0
0
b0
b1
CKE[1:0]
0
0
Bit
Symbol
Bit Name
Description
R/W
7
TIE
Transmit
interrupt enable
0: The TXI interrupt request is disabled.
R/W
1: The TXI interrupt request is enabled.
6
RIE
Receive interrupt 0: RXI and ERI interrupt requests are disabled.
enable
1: RXI and ERI interrupt requests are enabled.
R/W
5
TE
Transmit enable 0: Transmission is disabled.
R/W
1: Transmission is enabled.
4
RE
Receive enable
0: Reception is disabled.
R/W
1: Reception is enabled.
3
MPIE
Multiprocessor
interrupt enable
(Enabled only when the MP bit in SMR is 1 in
asynchronous mode)
R/W
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and OER status flags in SSR is disabled.
On receiving data in which the multiprocessor bit is 1,
this bit is automatically cleared and normal reception is
resumed. For details, see section 20.5, Multiprocessor
Communication Function.
2
TEIE
Transmit end
interrupt enable
0: The TEI interrupt request is disabled.
1: The TEI interrupt request is enabled.
Rev. 1.00 Oct. 03, 2008 Page 686 of 962
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
Bit
Symbol
Bit Name
Description
1,
CKE1
0
CKE0
Clock enable 0 Selects the clock source.
and 1
Asynchronous mode:
R/W
R/W
00: On-chip baud rate generator
01: On-chip baud rate generator
Outputs a clock of the same frequency as the bit rate
from the SCK3 pin.
10: External clock
A clock with a frequency 16 times the bit rate should
be input from the SCK3 pin.
11:Reserved
Clocked synchronous mode:
00: On-chip clock (The SCK3 pin functions as clock
output.)
01: Reserved
10: External clock (The SCK3 pin functions as clock
input.)
11: Reserved
Notes: 1. The TE and RE bits are reset and the other bits are retained when (module) standby
mode is entered.
2. For details on interrupt requests, see section 20.8, Interrupt Requests.
Rev. 1.00 Oct. 03, 2008 Page 687 of 962
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
20.2.7
Serial Status Register (SSR)
Address: H'FF0554, H'FF055C, H'FF0564
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
TDRE
RDRF
OER
FER
PER
TEND
MPBR
MPBT
1
0
0
0
0
1
0
0
Value after reset:
Bit
Symbol Bit Name
7
TDRE
Description
Transmit
[Setting conditions]
data register
• When the TE bit in SCR3 is 0
empty flag
• When data is transferred from TDR to TSR
R/W
R/W
[Clearing conditions]
6
RDRF
•
When the CPU writes 0 after reading TDRE = 1.
•
When the CPU writes transmit data to TDR.
•
When the DTC transfers data to TDR with a TXI interrupt
request and the DTC settings satisfy the flag clearing
conditions.
Receive
[Setting condition]
data register
• When reception ends normally and receive data is
full flag
transferred from RSR to RDR
R/W
[Clearing conditions]
5
OER
Overrun
error flag
•
When the CPU writes 0 after reading RDRF = 1.
•
When the CPU reads data from RDR.
•
When the DTC transfers data from RDR with an RXI
interrupt request and the DTC settings satisfy the flag
clearing conditions. *
[Setting condition]
•
When an overrun error occurs in reception
[Clearing condition]
•
When the CPU writes 0 after reading OER = 1.
Rev. 1.00 Oct. 03, 2008 Page 688 of 962
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
Bit
Symbol Bit Name
4
FER
Description
R/W
R/W
Framing error [Setting condition]
flag
• When a framing error occurs in reception
[Clearing condition]
•
3
PER
Parity error
flag
When the CPU writes 0 after reading FER = 1.
R/W
[Setting condition]
•
When a parity error is detected during reception
[Clearing condition]
•
2
TEND
Transmit end
flag
When the CPU writes 0 after reading PER = 1.
R/W
[Setting conditions]
•
When the TE bit in SCR3 is 0
•
When TDRE = 1 at transmission of the last bit of a
transmit character
[Clearing conditions]
•
When 0 is written to TDRE after reading TDRE = 1
•
When the transmit data is written to TDR
1
MPBR
Multiprocessor Stores the multiprocessor bit in the receive character data.
bit receive
When the RE bit in SCR3 is cleared to 0, its state is
retained.
R/W
0
MPBT
Multiprocessor Specifies the multiprocessor bit value to be added to the
bit transfer
transmit character data.
R/W
Note:
The DTC clears the peripheral module flags when all of the following three conditions
are satisfied:
1. The DISEL bit is 0.
2. The value in the transfer counter (count register CRA in normal and repeat modes or
count register CRB in block mode) is not 0.
3. A chain transfer is not used.
*
Rev. 1.00 Oct. 03, 2008 Page 689 of 962
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
20.2.8
Bit Rate Register (BRR)
Address: H'FF0551, H'FF0559, H'FF0561
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
Value after reset:
1
1
1
1
1
1
1
1
BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 20.3
shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0
SMR in asynchronous mode. Table 20.4 shows the maximum bit rate for each frequency in
asynchronous mode. The values shown in both tables 20.3 and 20.4 are values in active (highspeed) mode. Table 20.5 shows of the relationship between the N setting in BRR and the n setting
in bits CKS1 and CKS0 of SMR in clocked synchronous mode. The values shown in table 20.5 are
values in active (high-speed) mode. The N setting in BRR and error for other operating
frequencies and bit rates can be obtained by the following formulas:
Note: The BRR value is retained in (module) standby mode.
[Asynchronous Mode]
φ
N=
x 106 -1
64 x 22n-1 x B
φ x 106
Error (%) =
-1
(N + 1) x B x 64 x 22n-1
[Clocked Synchronous Mode]
φ
N=
8x
22n-1
x 106 -1
xB
[Legend]
B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n: CSK1 and CSK0 settings in SMR (0 ≤ n ≤ 3)
Rev. 1.00 Oct. 03, 2008 Page 690 of 962
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x 100
Section 20 Serial Communication Interface 3 (SCI3, IrDA)
Table 20.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode)
Operating Frequency φ (MHz)
4
4.9152
5
6
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
70
0.03
2
86
0.31
2
88
–0.25
2
106
–0.44
150
1
207
0.16
1
255
0.00
2
64
0.16
2
77
0.16
300
1
103
0.16
1
127
0.00
1
129
0.16
1
155
0.16
600
0
207
0.16
0
255
0.00
1
64
0.16
1
77
0.16
1200
0
103
0.16
0
127
0.00
0
129
0.16
0
155
0.16
2400
0
51
0.16
0
63
0.00
0
64
0.16
0
77
0.16
4800
0
25
0.16
0
31
0.00
0
32
–1.36
0
38
0.16
9600
0
12
0.16
0
15
0.00
0
15
1.73
0
19
–2.34
19200
0
6
–6.99
0
7
0.00
0
7
1.73
0
9
–2.34
31250
0
3
0.00
0
4
–1.70
0
4
0.00
0
5
0.00
38400
0
2
8.51
0
3
0.00
0
3
1.73
0
4
–2.34
Operating Frequency φ (MHz)
6.144
Error
(%)
7.3728
9.8304
Bit Rate
(bit/s)
n
N
110
2
108
0.08
2
130
–0.07
2
141
0.03
2
174
–0.26
150
2
79
0.00
2
95
0.00
2
103
0.16
2
127
0.00
300
1
159
0.00
1
191
0.00
1
207
0.16
1
255
0.00
600
1
79
0.00
1
95
0.00
1
103
0.16
1
127
0.00
1200
0
159
0.00
0
191
0.00
0
207
0.16
0
255
0.00
2400
0
79
0.00
0
95
0.00
0
103
0.16
0
127
0.00
4800
0
39
0.00
0
47
0.00
0
51
0.16
0
63
0.00
9600
0
19
0.00
0
23
0.00
0
25
0.16
0
31
0.00
19200
0
9
0.00
0
11
0.00
0
12
0.16
0
15
0.00
31250
0
5
2.40
0
6
5.33
0
7
0.00
0
9
–1.70
38400
0
4
0.00
0
5
0.00
0
6
-6.99
0
7
0.00
n
N
Error
(%)
8
n
N
Error
(%)
n
N
Error
(%)
Rev. 1.00 Oct. 03, 2008 Page 691 of 962
REJ09B0465-0100
Section 20 Serial Communication Interface 3 (SCI3, IrDA)
Operating Frequency φ (MHz)
10
12
12.888
14
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
177
–0.25
2
212
0.03
2
217
0.08
2
248
–0.17
150
2
129
0.16
2
155
0.16
2
159
0.00
2
181
0.16
300
2
64
0.16
2
77
0.16
2
79
0.00
2
90
0.16
600
1
129
0.16
1
155
0.16
1
159
0.00
1
181
0.16
1200
1
64
0.16
1
77
0.16
1
79
0.00
1
90
0.16
2400
0
129
0.16
0
155
0.16
0
159
0.00
0
181
0.16
4800
0
64
0.16
0
77
0.16
0
79
0.00
0
90
0.16
9600
0
32
–1.36
0
38
0.16
0
39
0.00
0
45
–0.93
19200
0
15
1.73
0
19
–2.34
0
19
0.00
0
22
–0.93
31250
0
9
0.00
0
11
0.00
0
11
2.40
0
13
0.00
38400
0
7
1.73
0
9
–2.34
0
9
0.00



Operating Frequency φ (MHz)
14.7456
16
18
20
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
3
64
0.70
3
70
0.03
3
79
–0.12
3
88
–0.25
150
2
191
0.00
2
207
0.16
2
233
0.16
3
64
0.16
300
2
95
0.00
2
103
0.16
2
114
0.16
2
129
0.16
600
1
191
0.00
1
207
0.16
1
233
0.16
2
64
0.16
1200
1
95
0.00
1
103
0.16
1
114
0.16
1
129
0.16
2400
0
191
0.00
0
207
0.16
0
233
0.16
1
64
0.16
4800
0
95
0.00
0
103
0.16
0
114
0.16
0
129
0.16
9600
0
47
0.00
0
51
0.16
0
58
–0.96
0
64
0.16
19200
0
23
0.00
0
25
0.16
0
28
1.02
0
32
–1.36
31250
0
14
–1.70
0
15
0.00
0
17
0.00
0
19
0.00
38400
0
11
0.00
0
12
0.16
0
14
–2.34
0
15
1.73
[Legend]
: A setting is available but error occurs.
Rev. 1.00 Oct. 03, 2008 Page 692 of 962
REJ09B0465-0100
Section 20 Serial Communication Interface 3 (SCI3, IrDA)
Table 20.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
φ (MHz)
Maximum Bit
Rate (bit/s)
n
N
φ (MHz)
Maximum Bit
Rate (bit/s)
n
N
4
125000
0
0
12
375000
0
0
4.9152
153600
0
0
12.288
384000
0
0
5
156250
0
0
14
437500
0
0
6
187500
0
0
14.7456
460800
0
0
6.144
192000
0
0
16
500000
0
0
7.3728
230400
0
0
17.2032
537600
0
0
8
250000
0
0
18
562500
0
0
9.8304
307200
0
0
20
625000
0
0
10
312500
0
0
Rev. 1.00 Oct. 03, 2008 Page 693 of 962
REJ09B0465-0100
Section 20 Serial Communication Interface 3 (SCI3, IrDA)
Table 20.5 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode)
Operating Frequency φ (MHz)
Bit Rate
(bit/s)
4
8
10
16
n
N
n
N
n
N
n
N
250
2
249
3
124


3
249
500
2
124
2
249


3
1k
1
249
2
124


2.5k
1
99
1
199
1
5k
0
199
1
99
10k
0
99
0
25k
0
39
0
50k
0
19
100k
0
9
250k
0
3
500k
0
1M
0
18
20
n
N
n
N
124




2
249




249
2
99


2
124
1
124
1
199
1
224
1
249
199
0
249
1
99


1
124
79
0
99
0
159
0
179
0
199
0
39
0
49
0
79
0
89
0
99
0
19
0
24
0
39
0
44
0
49
0
7
0
9
0
15
0
17
0
19
1
0
3
0
4
0
7
0
8
0
9
0*
0
1


0
3
0
4
0
4
0
0*


0
1




0
0*




0
1
0
0*
110
2M
2.5M
5M
[Legend]
Blank: No setting is available.
:
A setting is available but error occurs.
*:
Continuous transfer is not possible.
Rev. 1.00 Oct. 03, 2008 Page 694 of 962
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
20.2.9
Sampling Mode Register (SPMR)
Address: H'FF0556, H'FF055E, H'FF0566
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0





NFEN


1
1
1
1
1
0
1
1
Bit
Symbol
Bit Name
Description
R/W
7 to 3

Reserved
These bits are read as 1. The write value should 
be 1.
2
NFEN
Noise cancellation 0: The noise cancellation function is invalid for
function select
the RXD pin input.
R/W
1: The noise cancellation function is valid for the
RXD pin input (when the COM bit in SMR is
0).
1, 0

Reserved
These bits are read as 1. The write value should 
be 1.
Note: The SPMR value is retained in (module) standby mode.
• NFEN bit (noise cancellation function select)
Performs noise cancellation for the RXD pin input when the COM bit in SMR is 0 and NFEN
bit is 1.
20.2.10 IrDA Control Register (IrCR)
Address: H'FF05DE
Bit:
b7
b6
IrE
Value after reset:
0
b5
b4
IrCK[2:0]
0
0
0
b3
b2
b1
b0
IrTXINV
IrRXINV


0
0
1
1
Rev. 1.00 Oct. 03, 2008 Page 695 of 962
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
Bit
Symbol
Bit Name
Description
R/W
7
IrE
IrDA enable
0: The TXD_2/IrTXD and RXD_2/IrRXD pins
function as the TXD_2 and RXD_2 pins.
R/W
1: The TXD_2/IrTXD and RXD_2/IrRXD pins
function as the IrTXD and IrRXD pins.
6 to 4
IrCK[2:0]
IrDA clock select 000: Bit rate × 3/16
2 to 0
001: φ/2
R/W
010: φ/4
011: φ/8
100: φ/16
101: φ/32
110: φ/64
111: φ/128
3
IrTXINV
IrTX data polarity 0: Transmit data is output from IrTXD as is.
inversion
1: Transmit data is inverted to be output from
IrTXD.
R/W
2
IrRXINV
IrRX data polarity 0: IrRXD input is used for receive data as is.
inversion
1: IrRXD input is inverted to be used for receive
data.
R/W
1, 0

Reserved
These bits are read as 1. The write value should 
be 1.
Note: The IrCR value is retained in (module) standby mode.
• IrE bit (IrDA enable)
Selects the SCI3_2 I/O pin function between the usual serial function and IrDA function.
• IrCK[2:0] bit (IrDA clock select 2 to 0)
Sets the high pulse width for IrTXD output pulse encoding when the IrDA function is
• IrTXINV bit (IrTX data polarity inversion)
Sets to invert the logic level of the IrTXD output. When inversion is specified, the high pulse
width set with IrCR[2:0] is handled as low pulse width.
• IrRXINV bit (IrRX data polarity inversion)
Sets to invert the logic level of the IrRXD input. When inversion is specified, the high pulse
width set with IrCR[2:0] is handled as low pulse width.
Rev. 1.00 Oct. 03, 2008 Page 696 of 962
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
20.3
Operation in Asynchronous Mode
Figure 20.2 shows the general format for asynchronous communication. One character (or frame)
consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low
level), and finally stop bits (high level). Inside the SCI3, the transmitter and receiver are
independent units, enabling full-duplex. Both the transmitter and the receiver also have a doublebuffered structure, so data can be read or written during transmission or reception, enabling
continuous data transfer.
LSB
1
MSB
Serial Start
data
bit
Parity
bit
Transmit/receive data
7 or 8 bits
1 bit
Stop bit
Mark state
1 or
2 bits
1 bit
or none
One unit of transfer data (character or frame)
Figure 20.2 Data Format in Asynchronous Communication
20.3.1
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK3 pin can be selected as the SCI3's transfer clock, according to the setting of the COM bit
in SMR and the CKE0 and CKE1 bits in SCR3. When an external clock is input at the SCK3 pin,
the clock frequency should be 16 times the bit rate used.
When the SCI3 is operated on an internal clock, the clock can be output from the SCK3 pin. The
frequency of the clock output in this case is equal to the bit rate, and the phase is such that the
rising edge of the clock is in the middle of the transmit data, as shown in figure 20.3.
Clock
Serial data
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 character (frame)
Figure 20.3 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
20.3.2
SCI3 Initialization
Figure 20.4 shows a sample flowchart to initialize the SCI3. When the TE bit is cleared to 0, the
TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the
RDRF, PER, FER, and OER flags, or the contents of RDR. When the external clock is used in
asynchronous mode, the clock must be supplied even during initialization.
Rev. 1.00 Oct. 03, 2008 Page 698 of 962
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
[1]
With the PMC, select which of the TXD,
RXD, and SCK3 pins are to be used.
Set the clock selection in SCR3. Be sure
to clear the other bits in SCR3 to 0.
When clock output is selected in
asynchronous mode, after the CKE1 and
CKE0 settings have been made, output
of the clock signal begins immediately
upon setting of the PMR bits that
correspond to pins selected by SCK3.
When clock output is selected with
reception in clock-synchronous mode,
and CKE1, CKE0, and RE are set to 1,
output of the clock signal begins
immediately upon setting of the PMR bits
that correspond to pins selected by
SCK3.
[2]
Set the data transfer format in SMR.
[3]
Write the value corresponding to the bit
rate to BRR. Not necessary if an
external clock is used.
[4]
Wait at least one bit interval, then set the
TE bit or RE bit in SCR3 to 1.
For transmission, enable use of the TXD
output pin by setting the PMR bit for the
pin selected as TXD by the PMC to 1.
For reception, enable use of the RXD
input pin by setting the PMR bit for the
pin selected as RXD by the PMC to 1.
Start initialization
Clear TE and RE bits in SCR3 to 0.
Set TXD, RXD, and SCK3 pins by PMC.
Set CKE1 and CKE0 bits in SCR3.
[1]
Set data transfer format in SMR.
[2]
Set value in BRR.
[3]
Wait
No
1-bit interval elapsed?
Yes
Set TE and RE bits in SCR3 to 1,
and set RIE, TIE, TEIE, and MPIE bits.
Set PMR bit corresponding to TXD and
RXD pins to 1.
<Initialization completion>
[4]
Also set the RIE, TIE, TEIE, and MPIE
bits, according to the required interrupts.
In asynchronous mode, SCI3 is in the
mark state (active) for transmission and
in the space state (idle) while waiting for
the start bit during reception. After the
TE bit has been set to 1 in the case of
transmission, transmission is enabled
after the output of a frame with all bits 1.
Figure 20.4 Sample Flowchart for Initializing SCI3
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REJ09B0465-0100
Section 20 Serial Communication Interface 3 (SCI3, IrDA)
20.3.3
Data Transmission
Figure 20.5 shows an example of operation for transmission in asynchronous mode. In
transmission, the SCI3 operates as described below.
1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that
data has been written to TDR, and transfers the data from TDR to TSR.
2. The SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time,
a TXI interrupt request is generated. Continuous transmission is possible because the TXI
interrupt routine writes next transmit data to TDR before transmission of the current transmit
data has been completed.
3. The SCI3 checks the TDRE flag at the timing for sending the stop bit.
4. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
transmission of the next frame is started.
5. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark
state" is entered, in which 1 is output. If the TEIE bit in SCR3 is set to 1 at this time, a TEI
interrupt request is generated.
6. Figure 20.6 shows a sample flowchart for transmission in asynchronous mode.
Start
bit
Serial
data
1
0
Transmit
data
D0
D1
D7
1 frame
Parity Stop Start
bit
bit bit
0/1
1
0
Transmit
data
D0
D1
D7
Parity Stop
bit
bit
0/1
1
Mark
state
1
1 frame
TDRE
TEND
TXI interrupt
LSI
operation request
generated
User
processing
TDRE flag
cleared to 0
TXI interrupt request generated
TEI interrupt request
generated
Data written
to TDR
Figure 20.5 Example of Transmission in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
Start transmission
[1]
Read TDRE flag in SSR
No
TDRE = 1
Yes
Write transmit data to TDR
[2]
Yes
Is data transmission continued?
No
Read TEND flag in SSR
[1] Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. When data is
written to TDR, the TDRE flag is
automaticaly cleared to 0.
[2] To continue data transmission,
read 1 from the TDRE flag to
confirm that writing is possible,
then write data to TDR. When data
is written to TDR, the TDRE flag is
automaticaly cleared to 0.
If data is transferred to TDR by the
DTC with a transmit data empty
interrupt (TXI) request, the TDRE
flag is automatically checked and
cleared.
[3] To output a break at the end of
data transmission, clear PMR
corresponding to TxD to 0, after
setting PCR to 1 and PDR to 0,
then clear the TE bit in SCR3 to 0.
No
TEND = 1
Yes
[3]
No
Break output?
Yes
Clear PDR to 0, set PCR to 1,
and clear PMR to 0
Clear TE bit in SCR3 to 0
<End>
Figure 20.6 Sample Flowchart for Transmitting Data (Asynchronous Mode)
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
20.3.4
Data Reception
Figure 20.7 shows an example of operation for reception in asynchronous mode. In reception, the
SCI3 operates as described below.
1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs
internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this time, an
ERI interrupt request is generated. Receive data is not transferred to RDR.
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated.
4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive
data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt
request is generated.
5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is
generated. Continuous reception is possible because the RXI interrupt routine reads the receive
data transferred to RDR before reception of the next receive data has been completed.
Start
bit
Serial
data
1
0
Receive
data
D0
D1
D7
Parity Stop Start
bit
bit bit
0/1
1
0
1 frame
Receive
data
D0
D1
Parity Stop
bit
bit
D7
0/1
Mark state
(idle state)
0
1
1 frame
RDRF
FER
LSI
operation
RXI request
User
processing
RDRF
cleared to 0
0 stop bit
detected
RDR data read
Figure 20.7 Example of Reception in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)
Rev. 1.00 Oct. 03, 2008 Page 702 of 962
REJ09B0465-0100
ERI request in
response to
framing error
Framing error
processing
Section 20 Serial Communication Interface 3 (SCI3, IrDA)
Table 20.6 shows the states of the SSR status flags and receive data handling when a receive error
is detected. If a receive error is detected, the RDRF flag retains its state before receiving data.
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 20.8 shows a sample flowchart
for data reception.
Table 20.6 SSR Status Flags and Receive Data Handling
SSR Status Flag
RDRF*
OER
FER
PER
Receive Data
Receive Error Type
1
1
0
0
Lost
Overrun error
0
0
1
0
Transferred to RDR
Framing error
0
0
0
1
Transferred to RDR
Parity error
1
1
1
0
Lost
Overrun error + framing error
1
1
0
1
Lost
Overrun error + parity error
0
0
1
1
Transferred to RDR
Framing error + parity error
1
1
1
1
Lost
Overrun error + framing error +
parity error
Note:
*
The RDRF flag retains the state it had before data reception.
Rev. 1.00 Oct. 03, 2008 Page 703 of 962
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
Start reception
Read OER, PER, and
FER flags in SSR
[1]
Yes
OER+PER+FER = 1
[4]
No
Receive error processing
(Continued on next page)
Read RDRF flag in SSR
[2]
No
RDRF = 1
Yes
Read receive data in RDR
Yes
Is data reception continued?
[3]
[1] Read the OER, PER, and FER flags in
SSR to identify the error. If a receive
error occurs, performs the appropriate
error processing.
[2] Read SSR and check that RDRF = 1,
then read the receive data in RDR.
The RDRF flag is cleared automatically.
[3] To continue data reception, before the
stop bit for the current frame is
received, read the RDRF flag and read
RDR. The RDRF flag is cleared
automatically by te RDR read.
If RDR data is transferred by the DTC
which was activated by an RXI
interrupt, the RDRF flag is cleared
automatically.
[4] If a receive error occurs, read the OER,
PER, and FER flags in SSR to identify
the error. After performing the
appropriate error processing, ensure
that the OER, PER, and FER flags are
all cleared to 0. Reception cannot be
resumed if any of these flags are set to
1. In the case of a framing error, a
break can be detected by reading the
value of the RxD pin.
No
(A)
Clear RE bit in SCR3 to 0
<End>
Figure 20.8 Sample Flowchart for Data Reception (Asynchronous Mode) (1)
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REJ09B0465-0100
Section 20 Serial Communication Interface 3 (SCI3, IrDA)
[4]
Receive error processing
No
OER = 1
Yes
Overrun error processing
No
FER = 1
Yes
Yes
Break?
No
Framing error processing
No
PER = 1
Yes
Parity error processing
(A)
Clear OER, PER, and
FER flags in SSR to 0
<End>
Figure 20.8 Sample Flowchart for Data Reception (Asynchronous Mode) (2)
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
20.4
Operation in Clocked Synchronous Mode
Figure 20.9 shows the format for clocked synchronous communication. In clocked synchronous
mode, data is transmitted or received synchronous with clock pulses. A single character in the
transmit data consists of the 8-bit data starting from the LSB. In transmission, data is output from
one falling edge of the synchronization clock to the next. In reception, data is received in
synchronization with the rising edge of the synchronization clock. After 8-bit data is output, the
transmission line holds the MSB state. In clocked synchronous mode, no parity or multiprocessor
bit is added. Inside the SCI3, the transmitter and receiver are independent units, enabling fullduplex communication through the use of a common clock. Both the transmitter and the receiver
also have a double-buffered structure, so data can be read or written during transmission or
reception, enabling continuous data transfer.
8 bits
One unit of transfer data (character or frame)
*
*
Synchronization
clock
LSB
Bit 0
Serial data
MSB
Bit 1
Don’t care
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Don’t care
Note: * High except in continuous transfer
Figure 20.9 Data Format in Clocked Synchronous Communication
20.4.1
Clock
Either an internal clock generated by the on-chip baud rate generator or an external
synchronization clock input at the SCK3 pin can be selected, according to the setting of the COM
bit in SMR and CKE0 and CKE1 bits in SCR3. When the SCI3 is operated on an internal clock,
the synchronization clock is output from the SCK3 pin. Eight synchronization clock pulses are
output in the transfer of one character, and when no transfer is performed the clock is fixed high.
20.4.2
SCI3 Initialization
Before transmitting and receiving data, the SCI3 should be initialized as described in a sample
flowchart in figure 20.4.
Rev. 1.00 Oct. 03, 2008 Page 706 of 962
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
20.4.3
Data Transmission
Figure 20.10 shows an example of SCI3 operation for transmission in clocked synchronous mode.
In transmission, the SCI3 operates as described below.
1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI3 recognizes that data
has been written to TDR, and transfers the data from TDR to TSR.
2. The SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR3 is set to 1 at
this time, a transmit data empty interrupt (TXI) is generated.
3. The SCI3 outputs eight synchronization clock pulses when clock output mode has been
specified. Data is output in synchronization with the input clock when use of an external clock
has been specified. Serial data is transmitted sequentially from the LSB (bit 0), from the TXD
pin.
4. The SCI3 checks the TDRE flag at the timing for sending the MSB (bit 7).
5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and transmission of the
next frame is started.
6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains the
output state of the MSB. If the TEIE bit in SCR3 is set to 1 at this time, a TEI interrupt request
is generated.
7. The SCK3 pin is fixed high at the end of transmission.
Figure 20.11 shows a sample flowchart for data transmission. Transmission will not start while a
receive error flag (OER, FER, or PER) is set to 1. Make sure that the receive error flags are
cleared to 0 before starting transmission.
Serial
clock
Serial
data
Bit 0
Bit 1
1 frame
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
1 frame
TDRE
TEND
LSI
TXI interrupt
operation request
generated
TDRE flag
cleared
to 0
User
processing
Data written
to TDR
TXI interrupt request generated
TEI interrupt request
generated
Figure 20.10 Example of Transmission in Clocked Synchronous Mode
Rev. 1.00 Oct. 03, 2008 Page 707 of 962
REJ09B0465-0100
Section 20 Serial Communication Interface 3 (SCI3, IrDA)
Start transmission
[1]
[1]
Read TDRE flag in SSR
No
TDRE = 1
Yes
[2]
Write transmit data to TDR
[2]
Is data transmission continued?
Read SSR and check that the TDRE flag is
set to 1, then write transmit data to TDR.
When data is written to TDR, the TDRE flag
is automatically cleared to 0 and clocks are
output to start the data transmission.
If data is transferred to TDR by the DTC
with a transmit data empty interrupt (TXI)
request, the TDRE flag is automatically
checked and cleared.
To continue data transmission, be sure to
read 1 from the TDRE flag to confirm that
writing is possible, then write data to TDR.
When data is written to TDR, the TDRE flag
is automatically cleared to 0.
Yes
No
Read TEND flag in SSR
No
TEND = 1
Yes
Clear TE bit in SCR3 to 0
<End>
Figure 20.11 Sample Flowchart for Data Transmission (Clocked Synchronous Mode)
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REJ09B0465-0100
Section 20 Serial Communication Interface 3 (SCI3, IrDA)
20.4.4
Data Reception (Clocked Synchronous Mode)
Figure 20.12 shows an example of SCI3 operation for reception in clocked synchronous mode. In
reception, the SCI3 operates as described below.
1. The SCI3 performs internal initialization synchronous with a synchronization clock input or
output and starts receiving data.
2. The SCI3 stores the receive data in RSR.
3. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
in SSR is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this
time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the
RDRF flag remains to be set to 1.
4. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is
generated.
Serial
clock
Serial
data
Bit 7
Bit 0
Bit 7
1 frame
Bit 0
Bit 1
Bit 6
Bit 7
1 frame
RDRF
OER
LSI
operation
User
processing
RXI interrupt
request
generated
RDRF flag
cleared
to 0
RDR data read
RXI interrupt request generated
RDR data has
not been read
(RDRF = 1)
ERI interrupt request
generated by
overrun error
Overrun error
processing
Figure 20.12 Example of Reception in Clocked Synchronous Mode
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 20.13 shows a sample flowchart
for data reception.
Rev. 1.00 Oct. 03, 2008 Page 709 of 962
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
Start reception
[1]
[1]
Read OER flag in SSR
[2]
Yes
OER = 1
[4]
No
Overrun error processing
(Continued below)
[3]
Read RDRF flag in SSR
[2]
No
RDRF = 1
[4]
Yes
Read receive data in RDR
Read the OER flag in SSR to determine if
there is an error. If an overrun error has
occurred, execute overrun error processing.
Read SSR and check that the RDRF flag is
set to 1, then read the receive data in RDR.
When data is read from RDR, the RDRF
flag is automatically cleared to 0.
If RDR data is transferred by the DTC with a
receive data full interrupt (RXI) request, the
RDRF flag is cleared automatically.
To continue data reception, before the MSB
(bit 7) of the current frame is received,
reading the RDRF flag and reading RDR
should be finished. When data is read from
RDR, the RDRF flag is automatically
cleared to 0.
If an overrun error occurs, read the OER
flag in SSR, and after performing the
appropriate error processing, clear the OER
flag to 0. Reception cannot be resumed if
the OER flag is set to 1.
Yes
Is data reception continued?
[3]
No
Clear RE bit in SCR3 to 0
<End>
[4]
Overrun error processing
Overrun error processing
Clear OER flag in SSR to 0
<End>
Figure 20.13 Sample Flowchart for Data Reception (Clocked Synchronous Mode)
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
20.4.5
Simultaneous Data Transmission and Reception
Figure 20.14 shows a sample flowchart for simultaneous transmit and receive operations. The
following procedure should be used for simultaneous data transmit and receive operations. To
switch from transmit mode to simultaneous transmit and receive mode, after checking that the
SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0. Then
simultaneously set TE and RE to 1 with a single instruction. To switch from receive mode to
simultaneous transmit and receive mode, after checking that the SCI3 has finished reception, clear
RE to 0. Then after checking that the RDRF and receive error flags (OER, FER, and PER) are
cleared to 0, simultaneously set TE and RE to 1 with a single instruction.
Rev. 1.00 Oct. 03, 2008 Page 711 of 962
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
Start transmission/reception
[1]
[1]
Read TDRE flag in SSR
No
[2]
TDRE = 1
Yes
Write transmit data to TDR
[3]
Read OER flag in SSR
Yes
OER = 1?
No
[4]
Overrun error processing
Read RDRF flag in SSR
[2]
If data is transferred to TDR by the
DTC with a transmit data empty
interrupt (TXI) request, the TDRE
flag is automatically checked and
cleared. If RDR data is transferred
by the DTC with a receive data full
iterrupt (RXI) request, the RDRF
flag is automatically cleared.
No
RDRF = 1?
Yes
Read receive data in RDR
[4]
Yes
Is data transfer continued?
No
Clear TE and RE bits in SCR to 0
Read SSR and check that the TDRE
flag is set to 1, then write transmit
data to TDR.
When data is written to TDR, the
TDRE flag is automatically cleared to
0.
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR.
When data is read from RDR, the
RDRF flag is automatically cleared to
0.
To continue data transmission/
reception, before the MSB (bit 7) of
the current frame is received, finish
reading the RDRF flag, reading RDR.
Also, before the MSB (bit 7) of the
current frame is transmitted, read 1
from the TDRE flag to confirm that
writing is possible. Then write data to
TDR.
When data is written to TDR, the
TDRE flag is automatically cleared to
0. When data is read from RDR, the
RDRF flag is automatically cleared to
0.
[3]
If an overrun error occurs, read the
OER flag in SSR, and after
performing the appropriate error
processing, clear the OER flag to 0.
Transmission/reception cannot be
resumed if the OER flag is set to 1.
For overrun error processing, see
figure 20.13.
<End>
Figure 20.14 Sample Flowchart of Simultaneous Transmit and Receive Operations
(Clocked Synchronous Mode)
Rev. 1.00 Oct. 03, 2008 Page 712 of 962
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
20.5
Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer between a number of
processors sharing communication lines by asynchronous serial communication using the
multiprocessor format, in which a multiprocessor bit is added to the transfer data. When
multiprocessor communication is performed, each receiving station is addressed by a unique ID
code. The serial communication cycle consists of two component cycles; an ID transmission cycle
that specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to
differentiate between the ID transmission cycle and the data transmission cycle. If the
multiprocessor bit is 1, the cycle is an ID transmission cycle; if the multiprocessor bit is 0, the
cycle is a data transmission cycle. Figure 20.15 shows an example of inter-processor
communication using the multiprocessor format. The transmitting station first sends the ID code
of the receiving station with which it wants to perform serial communication as data with a 1
multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added.
When data with a 1 multiprocessor bit is received, the receiving station compares that data with its
own ID. The station whose ID matches then receives the data sent next. Stations whose IDs do not
match continue to skip data until data with a 1 multiprocessor bit is again received.
The SCI3 uses the MPIE bit in SCR3 to implement this function. When the MPIE bit is set to 1,
transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags,
RDRF, FER, and OER, to 1, are inhibited until data with a 1 multiprocessor bit is received. On
reception of a receive character with a 1 multiprocessor bit, the MPBR bit in SSR is set to 1 and
the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR3 is
set to 1 at this time, an RXI interrupt is generated.
When the multiprocessor format is selected, the parity bit setting is rendered invalid. All other bit
settings are the same as those in normal asynchronous mode. The clock used for multiprocessor
communication is the same as that in normal asynchronous mode.
Rev. 1.00 Oct. 03, 2008 Page 713 of 962
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
Transmitting
station
Serial transmission line
Receiving
station A
Receiving
station B
Receiving
station C
Receiving
station D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
Serial
data
H'01
H'AA
(MPB = 1)
ID transmission cycle =
Receiving station
specification
(MPB = 0)
Data transmission cycle =
Data transmission to
receiving station specified by ID
Legend
MPB: Multiprocessor bit
Figure 20.15 Example of Inter-Processor Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)
20.5.1
Multiprocessor Data Transmission
Figure 20.16 shows a sample flowchart for multiprocessor data transmission. For an ID
transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI3 operations are the same
as those in asynchronous mode.
Rev. 1.00 Oct. 03, 2008 Page 714 of 962
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
Start transmission
[1]
[1]
Read TDRE flag in SSR
No
TDRE = 1
[2]
Yes
Set MPBT bit in SSR
Write transmit data to TDR
Yes
[2]
Is data transmission continued?
No
[3]
Read SSR and check that the TDRE
flag is set to 1, set the MPBT bit in
SSR to 0 or 1, then write transmit
data to TDR. When data is written to
TDR, the TDRE flag is automatically
cleared to 0.
To continue data transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR. When data is
written to TDR, the TDRE flag is
automatically cleared to 0.
If data is transferred to TDR by the
DTC with a transmit data empty
interrupt (TXI) request, the TDRE flag
is automatically checked and cleared.
To output a break in serial
transmission, set the port PCR to 1,
clear PDR and PMR to 0, then clear
the TE bit in SCR3 to 0.
Read TEND flag in SSR
No
TEND = 1
Yes
No
[3]
Break output?
Yes
Clear PDR to 0, set PCR to 1
and clear PMR to 0
Clear TE bit in SCR3 to 0
<End>
Figure 20.16 Sample Flowchart for Multiprocessor Data Transmission
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
20.5.2
Multiprocessor Data Reception
Figure 20.17 shows a sample flowchart for multiprocessor data reception. If the MPIE bit in SCR3
is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1
multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at
this time. All other SCI3 operations are the same as those in asynchronous mode. Figure 20.18
shows an example of SCI3 operation for multiprocessor data reception.
Rev. 1.00 Oct. 03, 2008 Page 716 of 962
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
[1]
[2]
Start reception
Set MPIE bit in SCR3 to 1
[1]
Read OER and FER flags in SSR
[2]
[3]
Yes
FER+OER = 1
No
Read RDRF flag in SSR
[3]
No
[4]
[5]
RDRF = 1
Yes
Read receive data in RDR
No
This station’s ID?
Set the MPIE bit in SCR3 to 1.
Read OER and FER in SSR to check for
errors. Receive error processing is performed
in cases where a receive error occurs.
Read SSR and check that the RDRF flag is
set to 1, then read the receive data in RDR
and compare it with this station’s ID.
If the data is not this station’s ID, set the MPIE
bit to 1 again.
When data is read from RDR, the RDRF flag
is automatically cleared to 0.
Read SSR and check that the RDRF flag is
set to 1, then read the data in RDR.
If a receive error occurs, read the OER and
FER flags in SSR to identify the error. After
performing the appropriate error processing,
ensure that the OER and FER flags are all
cleared to 0.
Reception cannot be resumed if either of
these flags is set to 1.
In the case of a framing error, a break can be
detected by reading the RxD pin value.
Yes
Read OER and FER flags in SSR
Yes
FER+OER = 1
No
Read RDRF flag in SSR
[4]
No
RDRF = 1
[5]
Receive error processing
Yes
Read receive data in RDR
(Continued on
next page)
Yes
Is data reception continued?
No
[A]
Clear RE bit in SCR3 to 0
<End>
Figure 20.17 Sample Flowchart for Multiprocessor Data Reception (1)
Rev. 1.00 Oct. 03, 2008 Page 717 of 962
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
[5]
Receive error processing
No
OER = 1
Yes
Overrun error processing
No
FER = 1
Yes
Yes
Break?
No
[A]
Framing error processing
Clear OER, and
FER flags in SSR to 0
<End>
Figure 20.17 Sample Flowchart for Multiprocessor Data Reception (2)
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
Start
bit
Serial
data
1
0
Receive
data (ID1)
D0
D1
D7
MPB
1
Stop Start
bit bit
1
0
Receive data
(Data1)
D0
1 frame
D1
D7
MPB
Stop
bit
Mark state
(idle state)
0
1
1
1 frame
MPIE
RDRF
RDR
value
ID1
LSI
operation
RDRF flag
cleared
to 0
RXI interrupt
request
MPIE cleared
to 0
User
processing
RXI interrupt request
is not generated, and
RDR retains its state
RDR data read
When data is not
this station's ID,
MPIE is set to 1
again
(a) When data does not match this receiver's ID
Start
bit
Serial
data
1
0
Receive
data (ID2)
D0
D1
D7
MPB
1
Stop Start
bit bit
1
0
Receive data
(Data2)
D0
1 frame
D1
D7
MPB
Stop
bit
Mark state
(idle state)
0
1
1
1 frame
MPIE
RDRF
RDR
value
LSI
operation
User
processing
ID1
ID2
RXI interrupt
request
MPIE cleared
to 0
RDRF flag
cleared
to 0
RDR data read
Data2
RXI interrupt
request
When data is
this station's
ID, reception
is continued
RDRF flag
cleared
to 0
RDR data read
MPIE set to 1
again
(b) When data matches this receiver's ID
Figure 20.18 Example of Reception Using Multiprocessor Format
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
20.6
IrDA Operation
The SCI3_2 provides the IrDA function. If the IrDA function is enabled using the IrE bit in IrCR,
the TxD_2 and RxD_2 pins in SCI2_3 are allowed to encode and decode the waveform based on
the IrDA Specifications version 1.0 (function as the IrTxD and IrRxD pins)*. Connecting these
pins to the infrared data transceiver achieves infrared data communications based on the system
defined by the IrDA Specifications version 1.0.
In the system defined by the IrDA Specifications version 1.0, communication is started at a
transfer rate of 9600 bps, which can be modified later as required. Since the IrDA interface
provided by this LSI does not incorporate the capability of automatic modification of the transfer
rate, the transfer rate must be modified through programming.
Figure 20.19 is the IrDA block diagram.
IrDA
TXD_2/IrTxD
Phase
inversion
Pulse encoder
RXD_2/IrRxD
Phase
inversion
Pulse decoder
SCI3_2
TxD
RxD
IrCR
Figure 20.19 IrDA Block Diagram
IrDA operation should be set according to the following procedures.
(1) Set the corresponding pin in the MCR register or PMR register.
(2) Set the IrCR register.
(3) Set the register related to SCI3_2.
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
20.6.1
Transmission
During transmission, the output signals from the SCI3_2 (UART frames) are converted to IR
frames using the IrDA interface (see figure 20.20). For serial data of level 0, a high-level pulse
having a width of 3/16 of the bit rate (1-bit interval) is output (initial setting). The high-level pulse
can be selected using the IrCKS2 to IrCKS0 bits in IrCR. The high-level pulse width is defined to
be 1.41 µs at minimum and (3/16 + 2.5%) × bit rate or (3/16 × bit rate) +1.08 µs at maximum. For
example, when the frequency of system clock φ is 20 MHz, a high-level pulse width of 1.6 µs can
be specified because it is the smallest value in the range greater than 1.41 µs. For serial data of
level 1, no pulses are output.
UART frame
Stop
bit
Data
Start
bit
0
1
0
1
0
0
1
Transmission
1
0
1
Reception
IR frame
Data
Start
bit
0
Bit
cycle
1
0
1
0
Stop
bit
0
1
1
0
1
Pulse width is 1.6 ms to
3/16 bit cycle.
Figure 20.20 IrDA Transmission and Reception
20.6.2
Reception
During reception, IR frames are converted to UART frames using the IrDA interface before
inputting to SCI3_2. 0 is output when the high level pulse is detected while 1 is output when no
pulse is detected during one bit period. Note that a pulse shorter than the minimum pulse width of
1.41 µs is regarded as a 0 signal.
Rev. 1.00 Oct. 03, 2008 Page 721 of 962
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
20.6.3
High-Level Pulse Width Selection
Table 20.7 shows possible settings for bits IrCKS2 to IrCKS0 (minimum pulse width), and this
LSI's operating frequencies and bit rates, for making the pulse width shorter than 3/16 times the bit
rate in transmission.
Table 20.7 Settings of Bits IrCKS2 to IrCKS0
Bit Rate (bps) (Above)/Bit Period × 3/16 (Below)
Operating
Frequency φ
2400
(MHz)
78.13
9600
19200
38400
57600
115200
19.53
9.77
4.88
3.26
1.63
4.9152
011
011
011
011
011
011
5
011
011
011
011
011
011
6
100
100
100
100
100
100
6.144
100
100
100
100
100
100
7.3728
100
100
100
100
100
100
8
100
100
100
100
100
100
9.3804
100
100
100
100
100
100
10
100
100
100
100
100
100
12
101
101
101
101
101
101
12.288
101
101
101
101
101
101
14
101
101
101
101
101
101
14.7456
101
101
101
101
101
101
16
101
101
101
101
101
101
16.9344
101
101
101
101
101
101
17.2032
101
101
101
101
101
101
18
101
101
101
101
101
101
19.6608
101
101
101
101
101
101
20
101
101
101
101
101
101
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
20.7
Noise Canceler
Figure 20.21 shows a block diagram of the noise canceler circuit. When the noise canceler
function is enabled, the RXD input signal is routed through the noise canceler before being
provided internally. The noise canceler consists of three cascaded latches and a match detector.
The RXD input signal is sampled at the basic clock frequency, 16 times the transfer rate, and when
the outputs of three latches agree, the level is passed to the next circuit. If they do not agree, the
previous value is held.
In other words, if the input level changes and the level remains the same for three or more clock
cycles after the change, it is recognized as a signal. However, if the level remains the same for less
than three clock cycles, it is recognized as a noise, not as a signal.
Sampling clock
C
RXD
input signal
C
Q
D
Latch
D
C
Q
Latch
D
Q
Latch
Match
detector
circuit
SPMR
(NFEN)
Internal
RXD signal
in figure 20.1
Internal basic clock
cycle
Sampling clock
Figure 20.21 Block Diagram of Noise Canceler
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
20.8
Interrupt Requests
The SCI3 creates the following six interrupt requests: transmission end, transmit data empty,
receive data full, and receive errors (overrun error, framing error, and parity error). Table 20.8
shows the interrupt sources.
Table 20.8 SCI3 Interrupt Requests
Interrupt
Requests
Abbreviation
Interrupt Sources
DTC
Activation
Receive Data Full RXI
Setting RDRF in SSR
Possible
Transmit Data
Empty
TXI
Setting TDRE in SSR
Possible
Transmission End TEI
Setting TEND in SSR
Impossible
Receive Error
Setting OER, FER, and PER in SSR
Impossible
ERI
When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag
in SSR is set to 1, a TEI interrupt request is generated. The DTC can be activated to perform data
transfers with the TXI interrupt request. The TDRE flag is automatically cleared to 0 by the DTC
data transfer.
When the RDRF flag in SSR is set to 1, a RXI interrupt request is generated. When any of the
ORER, PER and FER flags is set to 1, an ERI interrupt request is generated. The DTC can be
activated to perform data transfers with the RXI interrupt request. The RDRE flag is automatically
cleared to 0 by the DTC data transfer.
The TEI interrupt is generated if the TEND flag is set to 1 when the TEIE bit is 1. If the TEI and
TXI interrupts are generated at the same time, the TXI interrupt is accepted first. Therefore, if the
TDRE and TEND flags are to be simultaneously cleared in a TXI interrupt routine, branching to a
TEI interrupt routine cannot be performed.
The initial value of the TDRE flag in SSR is 1. Thus, when the TIE bit in SCR3 is set to 1 before
transferring the transmit data to TDR, a TXI interrupt request is generated even if the transmit data
is not ready. The initial value of the TEND flag in SSR is 1. Thus, when the TEIE bit in SCR3 is
set to 1 before transferring the transmit data to TDR, a TEI interrupt request is generated even if
the transmit data has not been sent. It is possible to make use of the most of these interrupt
requests efficiently by transferring the transmit data to TDR in the interrupt routine. To prevent
the generation of these interrupt requests (TXI and TEI), set the enable bits (TIE and TEIE) that
correspond to these interrupt requests to 1, after transferring the transmit data to TDR.
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
20.9
Usage Notes
20.9.1
Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RXD pin value
directly. In a break, the input from the RXD pin becomes all 0s, setting the FER flag, and possibly
the PER flag. Note that as the SCI3 continues the receive operation after receiving a break, even if
the FER flag is cleared to 0, it will be set to 1 again.
20.9.2
Mark State and Break Sending
When the PMR bit corresponding to the pin selected by the PMC is 0, the TXD pin is used as an
I/O port whose direction (input or output) and level are determined by PCR and PDR. This can be
used to set the TXD pin to mark state (high level) or send a break during data transmission. To
maintain the communication line at mark state until the PMR bit is set to 1, set both PCR and PDR
to 1. As the PMR bit is cleared to 0 at this point, the TXD pin becomes an I/O port, and 1 is output
from the TXD pin. To send a break during transmission, first set PCR to 1 and clear PDR to 0, and
then clear the PMR bit to 0. When the PMR bit is cleared to 0, the transmitter is initialized
regardless of the current transmission state, the TXD pin becomes an I/O port, and 0 is output
from the TXD pin.
20.9.3
Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Transmission cannot be started when a receive error flag (OER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared
to 0.
Rev. 1.00 Oct. 03, 2008 Page 725 of 962
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
20.9.4
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the
transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock,
and performs internal synchronization. Receive data is latched internally at the rising edge of the
8th pulse of the basic clock as shown in figure 20.22. Thus, the reception margin in asynchronous
mode is given by formula (1) below.
M=
{( 0.5 -
1
) -
2N
D - 0.5
N
- (L - 0.5) F } x 100 (%)... Formula 1
... Formula (1)
[Legend]
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in
formula (1), the reception margin can be given by the formula.
M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed for in
system design.
16 clocks
8 clocks
0
7
15 0
7
15 0
Internal basic
clock
Receive data
(RxD)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 20.22 Receive Data Sampling Timing in Asynchronous Mode
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
20.9.5
Relation between Writes to TDR and TDRE Flag
Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is
written to TDR when the DRE flag is cleared to 0, the data stored in TDR will be lost since it has
not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1
before writing transmit data TDR.
20.9.6
Restrictions on Using DTC
When the external clock source is used as a synchronization clock, update TDR by the DTC or
CPU and wait for at least five φ clock cycles before allowing the transmit clock to be input. If the
transmit clock is input within four clock cycles after TDR modification, the SCI3 may malfunction
(see figure 20.23).
When using the DTC to read RDR, be sure to set the receive end interrupt (RXI) for the relevant
SCI3 as the DTC activation source.
SCK
t
TDRE
LSB
Serial data
D0
D1
D2
D3
D4
D5
D6
D7
Note: When an external clock is supplied, t must be more than four clock cycles.
Figure 20.23 Example of DTC Transmission in Clock Synchronous Mode
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Section 20 Serial Communication Interface 3 (SCI3, IrDA)
Rev. 1.00 Oct. 03, 2008 Page 728 of 962
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2
Section 21 I C Bus Interface 2 (IIC2)
Section 21 I2C Bus Interface 2 (IIC2)
The I2C bus interface 2 conforms to and provides a subset of the Philips I2C bus (inter-IC bus)
interface functions. The register configuration that controls the I2C bus differs partly from the
Philips configuration, however. Figure 21.1 shows a block diagram of the I2C bus interface 2.
Figure 21.2 shows an example of I/O pin connections to external circuits.
Either the IIC2 or SSU incorporated in this LSI can be used at a time. Accordingly, when the IIC2
function is used, the SSU function is not available.
21.1
Features
• Selectable for I2C bus format or clock synchronous serial format
• Continuous transmission/reception
Since the shift register, transmit data register, and receive data register are independent from
each other, the continuous transmission/reception can be performed.
I2C Bus Format:
•
•
•
•
Start and stop conditions generated automatically in master mode
Selectable for acknowledge output levels when receiving
Automatic loading of acknowledge bit when transmitting
Bit synchronization/wait function stored
In master mode, the state of SCL is monitored per bit, and the timing is synchronized
automatically. If transmission/reception is not yet possible, set the SCL to low until
preparations are completed.
• Six interrupt sources
Transmit data empty (including slave-address match), transmit end, receive data full (including
slave-address match), arbitration lost, NACK detection, and stop condition detection. The DTC
can be activated by the transmit-data-empty and receive-data-full interrupts.
• Direct bus drive possible
Two pins, SCL and SDA pins, function as NMOS open-drain outputs when the bus drive
function is selected.
Clock Synchronous Format:
• Four interrupt sources
Transmit-data-empty, transmit-end, receive-data-full, and overrun error. The DTC can be
activated by the transmit-data-empty and receive-data-full interrupt sources.
Rev. 1.00 Oct. 03, 2008 Page 729 of 962
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2
Section 21 I C Bus Interface 2 (IIC2)
Transfer clock
generation
circuit
SCL
Transmission/
reception
control circuit
Output
control
ICCR1
ICCR2
ICMR
Internal data bus
Noise canceler
ICDRT
SDA
Output
control
ICDRS
SAR
Address
comparator
Noise canceler
ICDRR
Bus state
decision circuit
Arbitration
decision circuit
ICSR
ICIER
Interrupt
generator
Figure 21.1 Block Diagram of I2C Bus Interface 2
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Interrupt request
2
Section 21 I C Bus Interface 2 (IIC2)
Vcc
SCL in
Vcc
SCL
SCL
SDA
SDA
SCL out
SDA in
SCL in
SCL out
SCL
SDA
(Master)
SCL
SDA
SDA out
SCL in
SCL out
SDA in
SDA in
SDA out
SDA out
(Slave 1)
(Slave 2)
Figure 21.2 External Circuit Connections of I/O Pins
Table 21.1 summarizes the pin configuration used by the I2C bus interface 2.
Table 21.1 Pin Configuration
Pin Name
I/O
Function
SCL
I/O
IIC serial clock input/output
SDA
I/O
IIC serial data input/output
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Section 21 I C Bus Interface 2 (IIC2)
21.2
Register Descriptions
The IIC2 has the following registers.
•
•
•
•
•
•
•
•
•
•
IIC2/SSU select register (ICSUSR)
I2C bus control register 1 (ICCR1)
I2C bus control register 2 (ICCR2)
I2C bus mode register (ICMR)
I2C bus interrupt enable register (ICIER)
I2C bus status register (ICSR)
I2C bus slave address register (SAR)
I2C bus transmit data register (ICDRT)
I2C bus receive data register (ICDRR)
I2C bus shift register (ICDRS)
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Section 21 I C Bus Interface 2 (IIC2)
21.2.1
IIC2/SSU Select Register (ICSUSR)
Address: H'FF000B
Bit:
Value after reset:
Bit
b7
b6
b5
b4
b3
b2
b1
b0







SELICSU
0
0
0
0
0
0
0
0
Symbol
Bit Name
Description
R/W
7 to 1 
Reserved
These bits are read as 0. The write value should
be 0.

0
IIC2/SSU
0: IIC2 function is selected.*
module function 1: SSU function is selected.
select
SELICSU
R/W
Note: To select the IIC2 function, this bit should be set to 0 without fail.
21.2.2
I2C Bus Control Register 1 (ICCR1)
Address: H'FF05C8
Bit:
Value after reset:
Bit
7
6
Symbol
ICE
RCVD
b7
b6
b5
b4
ICE
RCVD
MST
TRS
0
0
0
0
Bit Name
b3
b2
0
0
b1
b0
0
0
CKS[3:0]
Description
R/W
I C bus
interface 2
enable
0: This module is stopped. (SCL and SDA pins are
set to port function.)
R/W
Reception
disable
0: Enables next reception
2
1: This bit is enabled for transfer operations. (SCL
and SDA pins are bus drive state.)
R/W
1: Disables next reception
5
MST
Master/slave
select
00: Slave receive mode
4
TRS
Transmit/
receive select
10: Master receive mode
Transfer clock
select 3 to 0
These bits should be set according to the necessary R/W
transfer rate (see table 21.2) in master mode.
3 to 0 CKS[3:0]
R/W
01: Slave transmit mode
R/W
11: Master transmit mode
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Section 21 I C Bus Interface 2 (IIC2)
• RCVD bit (reception disable)
Selects to enable or disable the next operation when TRS is 0 and ICDRR is read.
• MST bit (master/slave select) and TRS bit (transmit/receive select)
In master mode with the I2C bus format, when arbitration is lost, MST and TRS are both reset
by hardware, causing a transition to slave receive mode. Modification of the TRS bit should be
performed between transfer frames.
After data receive has been started in slave receive mode, when the first seven bits of the
receive data agree with the slave address that is set to SAR and the eighth bit is 1, TRS is
automatically set to 1. If an overrun error occurs in master mode with the clock synchronous
serial format, MST is cleared to 0 and slave receive mode is entered.
Operating modes are described above according to MST and TRS combination. When clock
synchronous serial format is selected and MST is 1, clock is output.
• CKS[3:0] bits (transfer clock select 3 to 0)
These bits should be set according to the necessary transfer rate (see table 21.2) in master
mode. In slave mode, these bits are used for reservation of the data setup time in transmit
mode. The time is 10 tcyc when CKS3 = 0 and 20 tcyc when CKS3 = 1.
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Section 21 I C Bus Interface 2 (IIC2)
Table 21.2 Transfer Rate
Bit 3
Bit 2
Bit 1
Transfer Rate
Bit 0
CKS3
CKS2
CKS1
CKS0
Clock
φ = 5 MHz
φ = 8 MHz
φ = 10 MHz
φ = 16 MHz
φ = 20 MHz
0
0
0
0
φ/28
179 kHz
286 kHz
357 kHz
571 kHz
714 kHz
1
φ/40
125 kHz
200 kHz
250 kHz
400 kHz
500 kHz
0
φ/48
104 kHz
167 kHz
208 kHz
333 kHz
417 kHz
1
φ/64
78.1 kHz
125 kHz
156 kHz
250 kHz
313 kHz
0
0
φ/80
62.5 kHz
100 kHz
125 kHz
200 kHz
250 kHz
1
φ/100
50.0 kHz
80.0 kHz
100 kHz
160 kHz
200 kHz
1
0
φ/112
44.6 kHz
71.4 kHz
89.3 kHz
143 kHz
179 kHz
1
φ/128
39.1 kHz
62.5 kHz
78.1 kHz
125 kHz
156 kHz
1
1
1
0
0
1
1
0
1
0
φ/56
89.3 kHz
143 kHz
179 kHz
286 kHz
357 kHz
1
φ/80
62.5 kHz
100 kHz
125 kHz
200 kHz
250 kHz
0
φ/96
52.1 kHz
83.3 kHz
104 kHz
167 kHz
208 kHz
1
φ/128
39.1 kHz
62.5 kHz
78.1 kHz
125 kHz
156 kHz
0
φ/160
31.3 kHz
50.0 kHz
62.5 kHz
100 kHz
125 kHz
1
φ/200
25.0 kHz
40.0 kHz
50.0 kHz
80.0 kHz
100 kHz
0
φ/224
22.3 kHz
35.7 kHz
44.6 kHz
71.4 kHz
89.3 kHz
1
φ/256
19.5 kHz
31.3 kHz
39.1 kHz
62.5 kHz
78.1 kHz
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Section 21 I C Bus Interface 2 (IIC2)
21.2.3
I2C Bus Control Register 2 (ICCR2)
Address: H'FF05C9
Bit:
Value after reset:
Bit
Symbol
1
b7
b6
b5
b4
b3
b2
b1
b0
BBSY
SCP
SDAO
SDAOP
SCLO

IICRST

0
1
1
1
1
1
0
1
Bit Name
Description
R/W
2
7
BBSY*
6
SCP
Start/stop
The SCP bit controls the issue of start/stop
R/W
condition issue conditions in master mode. To issue a start
disable
condition, write 1 in BBSY and 0 in SCP. A
retransmit start condition is issued in the same way.
To issue a stop condition, write 0 in BBSY and 0 in
SCP. This bit is always read as 1. If 1 is written, the
data is not stored.
5
SDAO
SDA output
value control
Bus busy
This bit enables to confirm whether the I C bus is
R/W
occupied or released and to issue start/stop
conditions in master mode. With the clock
synchronous serial format, this bit has no meaning.
2
With the I C bus format, this bit is set to 1 when the
SDA level changes from high to low under the
condition of SCL = high, assuming that the start
condition has been issued. This bit is cleared to 0
when the SDA level changes from low to high under
the condition of SCL = high, assuming that the stop
condition has been issued. Write 1 to BBSY and 0
to SCP to issue a start condition. Follow this
procedure when also re-transmitting a start
condition. Write 0 in BBSY and 0 in SCP to issue a
stop condition. To issue start/stop conditions, use
the MOV instruction.
This bit is used with SDAOP (bit 4) when modifying R/W
output level of SDA. This bit should not be
manipulated during transfer.
0: When reading, SDA pin outputs low.
When writing, SDA pin is changed to output low.
1: When reading, SDA pin outputs high.
When writing, SDA pin is changed to output Hi-Z
(outputs high by external pull-up resistance).
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Section 21 I C Bus Interface 2 (IIC2)
Bit
Symbol
Bit Name
Description
R/W
4
SDAOP
SDAO write
protect
This bit controls change of output level of the SDA
pin by modifying the SDAO bit. To change the
output level, clear SDAO and SDAOP to 0 or set
SDAO to 1 and clear SDAOP to 0 by the MOV
instruction. This bit is always read as 1.
R/W
3
SCLO
SCL output
level monitor
This bit monitors SCL output level. When reading
and SCLO is 1, SCL pin outputs high. When
reading and SCLO is 0, SCL pin outputs low.
R
2

Reserved
This bit is read as 1. The write value should be 1.

1
IICRST*2
R/W
IIC control part This bit resets the control part except for I2C
reset
registers. If this bit is set to 1 when hang-up occurs
2
because of communication failure during I C
2
operation, I C control part can be reset without
setting ports and initializing registers.
0

Reserved
Note:
This bit is read as 1. The write value should be 1.

1. In standby mode, the BBSY bit in ICCR2 is reset.
2. Clear IICRST to 0 by software since this bit is not cleared automatically.
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Section 21 I C Bus Interface 2 (IIC2)
I2C Bus Mode Register (ICMR)
21.2.4
Address: H'FF05CA
Bit:
Value after reset:
b7
b6
b5
b4
b3
MLS
WAIT


BCWP
0
0
0
1
1
b2
b1
b0
BC[2:0]
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
MLS
MSB-first/LSB- 0: Transfer in MSB-first*
first select
1: Transfer in LSB-first
R/W
6
WAIT
Wait insertion
R/W
0: Data and acknowledge bits are transferred
consecutively with no wait inserted.
1: After the fall of the clock for the final data bit, low
period is extended for two transfer clocks.
5

Reserved
This bit is read as 0. The write value should be 0.

4

Reserved
This bit is read as 1. The write value should be 1.

3
BCWP
BC write
protect
0: When writing, modifying BC2 to BC0 values is
valid.
R/W
1: When writing, modifying BC2 to BC0 values is
invalid.
2 to 0 BC[2:0]
Note:
*
2
Bit counter 2 to I C Bus Format
0
000: 9 bits
Clock Synchronous Serial Format R/W
001: 1 bits
010: 3 bits
010: 2 bits
011: 4 bits
011: 3 bits
100: 5 bits
100: 4 bits
101: 6 bits
101: 5 bits
110: 7 bits
110: 6 bits
111: 8 bits
111: 7 bits
2
Set this bit to 0 when the I C bus format is used.
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000: 8 bits
001: 2 bits
2
Section 21 I C Bus Interface 2 (IIC2)
• WAIT bit (wait insertion)
In master mode with the I2C bus format, this bit selects whether to insert a wait after data
transfer except the acknowledge bit. When WAIT is set to 1, after the fall of the clock for the
final data bit, low period is extended for two transfer clocks. If WAIT is cleared to 0, data and
acknowledge bits are transferred consecutively with no wait inserted.
The setting of this bit is invalid in slave mode with the I2C bus format or with the clock
synchronous serial format.
• BCWP bit (BC write protect)
Controls the BC2 to BC0 modifications. When modifying BC2 to BC0, this bit should be
cleared to 0 and use the MOV instruction. In clock synchronous serial mode, BC should not be
modified.
• BC[2:0] bits (bit counter 2 to 0)
Specifies the number of bits to be transferred next. When read, the remaining number of
transfer bits is indicated. With the I2C bus format, the data is transferred with one additional
acknowledge bit. Bit BC2 to BC0 should be set during an interval between transfer frames. If
bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL
pin is low. The value automatically returns to 000 at the end of a data transfer, including the
acknowledge bit. With the clock synchronous serial format, these bits should not be modified.
21.2.5
I2C Bus Interrupt Enable Register (ICIER)
Address: H'FF05CB
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
TIE
TEIE
RIE
NAKIE
STIE
ACKE
ACKBR
ACKBT
0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
TIE
Transmit
0: Transmit data empty interrupt request (TXI) is
interrupt enable
disabled.
R/W
1: Transmit data empty interrupt request (TXI) is
enabled.
6
TEIE
Transmit end
0: Transmit end interrupt request (TEI) is disabled.
interrupt enable 1: Transmit end interrupt request (TEI) is enabled.
R/W
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Section 21 I C Bus Interface 2 (IIC2)
Bit
Symbol
Bit Name
Description
5
RIE
Receive
0: Receive data full interrupt request (RXI) is
interrupt enable
disabled.
R/W
R/W
1: Receive data full interrupt request (RXI) is
enabled.
4
NAKIE
NACK receive 0: NACK receive interrupt request (NAKI) and
interrupt enable
overrun error interrupt request (ERI) with the
clock synchronous format are disabled.
R/W
1: NACK receive interrupt request (NAKI) and
overrun error interrupt request (ERI) with the
clock synchronous format are enabled.
3
STIE
Stop condition 0: Stop condition detection interrupt request (STPI) R/W
detection
is disabled.
interrupt enable 1: Stop condition detection interrupt request (STPI)
is enabled.
2
ACKE
Acknowledge
bit judgment
select
0: The value of the receive acknowledge bit is
ignored, and continuous transfer is performed.
Receive
acknowledge
0: Receive acknowledge = 0
Transmit
acknowledge
0: 0 is sent at the acknowledge timing.
1
0
ACKBR
ACKBT
R/W
1: If the receive acknowledge bit is 1, continuous
transfer is stopped.
R
1: Receive acknowledge = 1
R/W
1: 1 is sent at the acknowledge timing.
• TIE bit (transmit interrupt enable)
When the TDRE bit in ICSR is set to 1, this bit enables or disables the transmit data empty
interrupt (TXI).
• TEIE bit (transmit end interrupt enable)
This bit enables or disables the transmit end interrupt (TEI) at the rising of the ninth clock
while the TDRE bit in ICSR is 1. TEI can be canceled by clearing the TEND bit or the TEIE
bit to 0.
• RIE bit (receive interrupt enable)
This bit enables or disables the receive data full interrupt request (RXI) when a receive data is
transferred from ICDRS to ICDRR and the RDRF bit in ICSR is set to 1. RXI can be canceled
by clearing the RDRF or RIE bit to 0.
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Section 21 I C Bus Interface 2 (IIC2)
• NAKIE bit (NACK receive interrupt enable)
This bit enables or disables the NACK receive interrupt request (NAKI) and the overrun error
(setting of the OVE bit in ICSR) interrupt request (ERI) with the clock synchronous format,
when the NACKF and AL bits in ICSR are set to 1. NAKI can be canceled by clearing the
NACKF, OVE, or NAKIE bit to 0.
• STIE bit (stop condition detection interrupt enable)
This bet should be set to 1 while the STOP bit in ICSR is 0.
• ACKBR bit (receive acknowledge)
In transmit mode, this bit stores the acknowledge data that are returned by the receive device.
This bit cannot be modified.
• ACKBT bit (transmit acknowledge)
In receive mode, this bit specifies the bit to be sent at the acknowledge timing.
21.2.6
I2C Bus Status Register (ICSR)
Address: H'FF05CC
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
TDRE
TEND
RDRF
NACKF
STOP
AL_OVE
AAS
ADZ
Value after reset:
0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
TDRE
Transmit data
empty flag
[Setting conditions]
R/W
•
When data is transferred from ICDRT to ICDRS
and ICDRT becomes empty
• When TRS is set
• When a start condition (including re-transfer) has
been issued
• When transmit mode is entered from receive
mode in slave mode
[Clearing conditions]
• When 0 is written in TDRE after reading
TDRE = 1
• When data is written to ICDRT with an instruction
• When the DTC transfers data to ICDRT by a TXI
interrupt request, and the DTC settings satisfy
the flag clearing conditions.
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Section 21 I C Bus Interface 2 (IIC2)
Bit
Symbol
Bit Name
Description
6
TEND
Transmit end flag [Setting conditions]
R/W
R/W
•
When the ninth clock of SCL rises with the I C bus
format while the TDRE flag is 1
•
When the final bit of transmit frame is sent with the
clock synchronous serial format
2
[Clearing conditions]
5
RDRF
Receive data
register full flag
•
When 0 is written in TEND after reading
TEND = 1
•
When data is written to ICDRT with an instruction
[Setting condition]
•
R/W
When a receive data is transferred from ICDRS to
ICDRR
[Clearing conditions]
4
NACKF
•
When 0 is written in RDRF after reading
RDRF = 1
•
When ICDRR is read with an instruction
•
When the DTC transfers data to ICDRR by an RXI
interrupt request, and the DTC settings satisfy the
flag clearing conditions.
No acknowledge [Setting condition]
R/W
detection flag
• When no acknowledge is detected from the
receive device in transmission while the ACKE bit
in ICIER is 1
[Clearing condition]
•
3
STOP
Stop condition
detection flag
When 0 is written in NACKF after reading NACKF
=1
[Setting conditions]
•
When a stop condition is detected after frame
transfer end
[Clearing condition]
•
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When 0 is written in STOP after reading STOP = 1
R/W
2
Section 21 I C Bus Interface 2 (IIC2)
Bit
Symbol
Bit Name
Description
R/W
2
AL_OVE
Arbitration lost
[Setting conditions]
flag/overrun error
• If the internal SDA and SDA pin disagree at the
flag
rise of SCL in master transmit mode
•
When the SDA pin outputs high in master mode
while a start condition is detected
•
When the final bit is received with the clock
synchronous format while RDRF = 1
R/W
[Clearing condition]
•
1
AAS
Slave address
recognition flag
When 0 is written in AL/OVE after reading AL/OVE
=1
R/W
[Setting conditions]
•
When the slave address is detected in slave
receive mode
•
When the general call address is detected in slave
receive mode.
[Clearing condition]
•
0
ADZ
General call
address
recognition flag
When 0 is written in AAS after reading AAS = 1
This bit is enabled in slave receive mode with I2C bus R/W
format.
[Setting condition]
•
When the general call address is detected in slave
receive mode
[Clearing condition]
•
When 0 is written in ADZ after reading ADZ = 1
Notes: In standby mode, ICSR is reset.
* The DTC clears the peripheral module flags when all of the following three conditions
are satisfied.
1. When the DISEL bit is 0.
2. When the transfer counter is not 0. (DTC transfer count register A (CRA) in normal
mode and repeat mode, or DTC transfer count register B (CRB) in block mode)
3. When chain transfer is not used.
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Section 21 I C Bus Interface 2 (IIC2)
• AL_OVE bit (arbitration lost flag/overrun error flag)
This flag indicates that arbitration was lost in master mode with the I2C bus format and that the
final bit has been received while RDRF = 1 with the clock synchronous format.
When two or more master devices attempt to seize the bus at nearly the same time, if the I2C
bus interface detects data differing from the data it sent, it sets AL to 1 to indicate that the bus
has been taken by another master.
• AAS bit (slave address recognition flag)
In slave receive mode, this flag is set to 1 if the first frame following a start condition matches
bits SVA6 to SVA0 in SAR.
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Section 21 I C Bus Interface 2 (IIC2)
21.2.7
Slave Address Register (SAR)
Address: H'FF05CD
Bit:
Value after reset:
Bit
b7
b6
b5
b4
b3
b2
b1
b0
SVA6
SVA5
SVA4
SVA3
SVA2
SVA1
SVA0
FS
0
0
0
0
0
0
0
0
Symbol
Bit Name
Description
R/W
7 to 1 SVA6 to
SVA0
Slave address
6 to 0
These bits set a unique address in bits SVA6 to
SVA0, differing form the addresses of other slave
devices connected to the I2C bus.
R/W
0
Format select
0: I2C bus format is selected.
R/W
FS
1: Clock synchronous serial format is selected.
SAR selects the format and sets the slave address. When SAR is in slave mode with the I2C bus
format, if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start
condition, SAR operates as the slave device.
21.2.8
I2C Bus Transmit Data Register (ICDRT)
Address: H'FF05CE
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
Value after reset:
1
1
1
1
1
1
1
1
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the
space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to
ICDRS and starts transferring data. If the next transfer data is written to ICDRT during
transferring data of ICDRS, continuous transfer is possible. If the MLS bit of ICMR is set to 1 and
when the data is written to ICDRT, the MSB/LSB inverted data is read. The initial value of
ICDRT is H'FF. ICDRT is reset in standby mode.
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Section 21 I C Bus Interface 2 (IIC2)
21.2.9
I2C Bus Receive Data Register (ICDRR)
Address: H'FF05CF
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
Value after reset:
1
1
1
1
1
1
1
1
ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR
transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a
receive-only register, therefore the CPU cannot write to this register. The initial value of ICDRR is
H'FF. ICDRR is reset in standby mode.
21.2.10 I2C Bus Shift Register (ICDRS)
Address: 
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
Value after reset:








ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from
ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from
ICDRS to ICDRR after data of one byte is received. This register cannot be read directly from the
CPU. ICDRS is reset in standby mode.
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Section 21 I C Bus Interface 2 (IIC2)
21.3
Operation
The I2C bus interface 2 can communicate either in I2C bus mode or clock synchronous serial mode
by setting FS in SAR.
I2C Bus Format
21.3.1
Figure 21.3 shows the I2C bus formats. Figure 21.4 shows the I2C bus timing. The first frame
following a start condition always consists of 8 bits.
(a) I2C bus format (FS = 0)
S
SLA
R/W
A
DATA
A
A/A
P
1
7
1
1
n
1
1
1
1
n: Transfer bit count
(n = 1 to 8)
m: Transfer frame count
(m ≥ 1)
m
(b) I2C bus format (Start condition retransmission, FS = 0)
S
SLA
R/W
A
DATA
A/A
S
SLA
R/W
A
DATA
A/A
P
1
7
1
1
n1
1
1
7
1
1
n2
1
1
1
m1
1
m2
n1 and n2: Transfer bit count (n1 and n2 = 1 to 8)
m1 and m2: Transfer frame count (m1 and m2 ≥ 1)
Figure 21.3 I2C Bus Formats
SDA
SCL
S
1-7
8
9
SLA
R/W
A
1-7
DATA
8
9
1-7
A
DATA
8
9
A
P
Figure 21.4 I2C Bus Timing
[Legend]
S:
Start condition. The master device drives SDA from high to low while SCL is high.
SLA:
Slave address
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Section 21 I C Bus Interface 2 (IIC2)
R/W:
Indicates the direction of data transfer: from the slave device to the master device when
R/W is 1, or from the master device to the slave device when R/W is 0.
A:
Acknowledge. The receive device drives SDA to low.
DATA: Transfer data
P:
21.3.2
Stop condition. The master device drives SDA from low to high while SCL is high.
Master Transmit Operation
In master transmit mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. For master transmit mode operation timing, see
figures 21.5 and 21.6. The transmission procedure and operations in master transmit mode are
described below.
1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
bits in ICCR1 to 1. (Initial setting)
2. Read the BBSY flag in ICCR2 to confirm that the bus is released. Set the MST and TRS bits in
ICCR1 to select master transmit mode. Then, write 1 to BBSY and 0 to SCP using MOV
instruction. (Start condition issued) This generates the start condition.
3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte data
show the slave address and R/W) to ICDRT. At this time, TDRE is automatically cleared to 0,
and data is transferred from ICDRT to ICDRS. TDRE is set again.
4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1
at the rise of the 9th transmit clock pulse. Read the ACKBR bit in ICIER, and confirm that the
slave device has been selected. Then, write second byte data to ICDRT. When ACKBR is 1,
the slave device has not been acknowledged, so issue the stop condition. To issue the stop
condition, write 0 to BBSY and SCP using MOV instruction. SCL is fixed low until the
transmit data is prepared or the stop condition is issued.
5. The transmit data after the second byte is written to ICDRT every time TDRE is set.
6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last
byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR = 1) from the
receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or
NACKF.
7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.
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Section 21 I C Bus Interface 2 (IIC2)
SCL
(Master output)
1
2
3
4
5
6
SDA
(Master output)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
7
8
Bit 1
Slave address
9
1
Bit 0
Bit 7
2
Bit 6
R/W
SDA
(Slave output)
A
TDRE
TEND
Address + R/W
ICDRT
ICDRS
User
processing
Data 1
Address + R/W
[2] Instruction of start
condition issuance
Data 2
Data 1
[4] Write data to ICDRT (second byte)
[5] Write data to ICDRT (third byte)
[3] Write data to ICDRT (first byte)
Figure 21.5 Master Transmit Mode Operation Timing (1)
SCL
(Master output)
9
SDA
(Master output)
SDA
(Slave output)
1
2
3
4
5
6
7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
8
9
Bit 0
A/A
A
TDRE
TEND
Data n
ICDRT
ICDRS
Data n
User
[5] Write data to ICDRT
processing
[6] Issue stop condition. Clear TEND.
[7] Set slave receive mode
Figure 21.6 Master Transmit Mode Operation Timing (2)
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Section 21 I C Bus Interface 2 (IIC2)
21.3.3
Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data from the slave
device, and returns an acknowledge signal. For master receive mode operation timing, see figures
21.7 and 21.8. The reception procedure and operations in master receive mode are shown below.
1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master
transmit mode to master receive mode. Then, clear the TDRE bit to 0.
2. When ICDRR is read (dummy read), reception is started. And the receive clock is output to
receive data in synchronization with the internal clock. The master device outputs the level
specified by ACKBT in ICIER to SDA at the 9th receive clock pulse.
3. After the reception of first frame data is completed, the RDRF bit in ICSR is set to 1 at the rise
of 9th receive clock pulse. At this time, the receive data is read by reading ICDRR, and RDRF
is cleared to 0.
4. The continuous reception is performed by reading ICDRR every time RDRF is set. If 8th
receive clock pulse falls after reading ICDRR by the other processing while RDRF is 1, SCL is
fixed low until ICDRR is read.
5. If next frame is the last receive data, set the RCVD bit in ICCR1 to 1 before reading ICDRR.
This enables the issuance of the stop condition after the next reception.
6. When the RDRF bit is set to 1 at rise of the 9th receive clock pulse, issue the stop condition.
7. When the STOP bit in ICSR is set to 1, read ICDRR. Then clear the RCVD bit to 0.
8. The operation returns to the slave receive mode.
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Section 21 I C Bus Interface 2 (IIC2)
Master transmit mode
SCL
(Master output)
Master receive mode
9
1
2
3
4
5
6
7
8
9
SDA
(Master output)
SDA
(Slave output)
1
A
A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
TDRE
TEND
TRS
RDRF
ICDRS
Data 1
ICDRR
User
processing
Data 1
[3] Read ICDRR
[1] Clear TDRE after clearing
TEND and TRS
[2] Read ICDRR (dummy read)
Figure 21.7 Master Receive Mode Operation Timing (1)
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Section 21 I C Bus Interface 2 (IIC2)
SCL
(Master output)
9
SDA
(Master output)
A
SDA
(Slave output)
1
2
3
4
5
6
7
8
9
A/A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RDRF
RCVD
ICDRS
Data n
Data n-1
ICDRR
User
processing
Data n
Data n-1
[5] Read ICDRR after setting RCVD
[6] Issue stop
condition
[7] Read ICDRR,
and clear RCVD
[8] Set slave
receive mode
Figure 21.8 Master Receive Mode Operation Timing (2)
21.3.4
Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data while the master device outputs
the receive clock and returns an acknowledge signal. For slave transmit mode operation timing,
see figures 21.9 and 21.10.
The transmission procedure and operations in slave transmit mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
bits in ICCR1 to 1 (Initial setting). Set the MST and TRS bits in ICCR1 to select slave receive
mode, and wait until the slave address matches.
2. When the slave address matches in the first frame following detection of the start condition,
the slave device outputs the level specified by ACKBT in ICIER to SDA at the rise of the 9th
clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS and ICSR bits in ICCR1 are
set to 1, and the mode changes to slave transmit mode automatically. The continuous
transmission is performed by writing transmit data to ICDRT every time TDRE is set.
3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1,
with TDRE = 1. When TEND is set, clear TEND.
4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is released.
5. Clear TDRE.
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Section 21 I C Bus Interface 2 (IIC2)
Slave receive mode
SCL
(Master output)
Slave transmit mode
9
1
2
3
4
5
6
7
8
9
SDA
(Master output)
1
A
SCL
(Slave output)
SDA
(Slave output)
A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
TDRE
TEND
TRS
ICDRT
ICDRS
Data 1
Data 2
Data 1
Data 3
Data 2
ICDRR
User
processing
[2] Write data to ICDRT (data 1)
[2] Write data to ICDRT (data 2)
[2] Write data to ICDRT (data 3)
Figure 21.9 Slave Transmit Mode Operation Timing (1)
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Section 21 I C Bus Interface 2 (IIC2)
Slave receive
mode
Slave transmit mode
SCL
(Master output)
9
SDA
(Master output)
A
1
2
3
4
5
6
7
8
9
A
SCL
(Slave output)
SDA
(Slave output)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TDRE
TEND
TRS
ICDRT
ICDRS
Data n
ICDRR
User
processing
[3] Clear TEND
[4] Read ICDRR (dummy read)
after clearing TRS
Figure 21.10 Slave Transmit Mode Operation Timing (2)
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[5] Clear TDRE
2
Section 21 I C Bus Interface 2 (IIC2)
21.3.5
Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. For slave receive mode operation timing, see figures
21.11 and 21.12. The reception procedure and operations in slave receive mode are described
below.
1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive
mode, and wait until the slave address matches.
2. When the slave address matches in the first frame following detection of the start condition,
the slave device outputs the level specified by ACKBT in ICIER to SDA at the rise of the 9th
clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the
read data show the slave address + R/W, it is not used.)
3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is set to 1,
SCL is fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR,
which is returned to the master device, is reflected to the next transmit frame.
4. The last byte data is read by reading ICDRR.
SCL
(Master output)
9
SDA
(Master output)
1
2
3
4
5
6
7
8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
9
1
Bit 7
SCL
(Slave output)
SDA
(Slave output)
A
A
RDRF
ICDRS
Data 1
Data 2
ICDRR
User
processing
Data 1
[2] Read ICDRR
[2] Read ICDRR (dummy read)
Figure 21.11 Slave Receive Mode Operation Timing (1)
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Section 21 I C Bus Interface 2 (IIC2)
SCL
(Master output)
9
SDA
(Master output)
1
2
3
4
5
6
7
8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
9
SCL
(Slave output)
SDA
(Slave output)
A
A
RDRF
ICDRS
Data 2
Data 1
ICDRR
Data 1
User
processing
[3] Set ACKBT
[3] Read ICDRR [4] Read ICDRR
Figure 21.12 Slave Receive Mode Operation Timing (2)
21.3.6
Clock Synchronous Serial Format
This module can be operated with the clock synchronous serial format by setting the FS bit in
SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When
MST is 0, the external clock input is selected.
(1)
Data Transfer Format
Figure 21.13 shows the clock synchronous serial transfer format.
The transfer data is output from the rise to the fall of the SCL clock, and the data at the rising edge
of the SCL clock is guaranteed. The MLS bit in ICMR sets the order of data transfer: in either the
MSB first or LSB first. The output level of SDA can be changed during the transfer wait by the
SDAO bit in ICCR2.
SCL
SDA
Bit 0
Bit 1
Bit 2 Bit 3 Bit 4
Bit 5 Bit 6
Bit 7
Figure 21.13 Clock Synchronous Serial Transfer Format
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Section 21 I C Bus Interface 2 (IIC2)
(2)
Transmit Operation
In transmit mode, transmit data is output from SDA in synchronization with the fall of the transfer
clock. The transfer clock is output when MST in ICCR1 is 1 and is input when MST is 0. For
transmit mode operation timing, see figure 21.14. The transmission procedure and operations in
transmit mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1 (Initial
setting).
2. Set the TRS bit in ICCR1 to select the transmit mode. Then, TDRE in ICSR is set.
3. Confirm that TDRE has been set. Then, write the transmit data to ICDRT. The data is
transferred from ICDRT to ICDRS, and TDRE is set automatically. The continuous
transmission is performed by writing data to ICDRT every time TDRE is set. When changing
from transmit mode to receive mode, clear TRS while TDRE is set to 1.
SCL
1
2
7
8
1
7
SDA
(Output)
Bit 0
Bit 1
Bit 6
Bit 7
Bit 0
Bit 6
8
1
Bit 7
Bit 0
TRS
TDRE
ICDRT
ICDRS
User
processing
Data 1
Data 2
Data 1
[3] Write data [3] Write data
to ICDRT
to ICDRT
[2] Set TRS
Data 3
Data 2
Data 3
[3] Write data
to ICDRT
[3] Write data
to ICDRT
Figure 21.14 Transmit Mode Operation Timing
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Section 21 I C Bus Interface 2 (IIC2)
(3)
Receive Operation
In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when
MST in ICCR1 is 1 and is input when MST is 0. For receive mode operation timing, see figure
21.15. The reception procedure and operations in receive mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1 (Initial
setting).
2. When the transfer clock is output, set MST to 1 to start outputting the receive clock.
3. When the receive operation is completed, data is transferred from ICDRS to ICDRR and
RDRF in ICSR is set. When MST = 1, the next byte can be received, so the clock is
continually output. The continuous reception is performed by reading ICDRR every time
RDRF is set. When the 8th clock is risen while RDRF is set to 1, the overrun is detected and
AL/OVE in ICSR is set. At this time, the previous reception data is retained in ICDRR.
4. To stop receiving when MST = 1, read ICDRR after setting RCVD in ICCR1 to 1. Then, SCL
is fixed high after receiving the next byte data.
SCL
1
2
7
8
1
7
8
1
2
SDA
(Input)
Bit 0
Bit 1
Bit 6
Bit 7
Bit 0
Bit 6
Bit 7
Bit 0
Bit 1
MST
TRS
RDRF
Data 1
ICDRS
Data 1
ICDRR
User
processing
Data 2
[2] Set MST
(when outputting the clock)
[3] Read ICDRR
Figure 21.15 Receive Mode Operation Timing
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Data 3
Data 2
[3] Read ICDRR
2
Section 21 I C Bus Interface 2 (IIC2)
21.3.7
Noise Filter Circuit
The signal state on the SCL and SDA pins are internally latched via the noise filter circuit. Figure
21.16 shows a block diagram of the noise filter circuit.
The noise filter consists of two cascaded latches and a match detector. The SCL (or SDA) input
signal is sampled on the system clock. When both outputs of the latches match, its level is output
to other blocks by the match detector circuit. If they do not match, the previous value is held.
Sampling clock
C
SCL or SDA
input signal
D
C
Q
Latch
Q
D
Latch
Match detector
circuit
Internal
SCL or SDA
signal
System clock
cycle
Sampling
clock
Figure 21.16 Block Diagram of Noise Filter Circuit
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Section 21 I C Bus Interface 2 (IIC2)
21.3.8
Example of Use
Flowcharts in respective modes that use the I2C bus interface 2 are shown in figures 21.17 to
21.20.
Start
Initialize
Read BBSY in ICCR2
[1]
Test the state of the SCL and SDA lines.
[2]
Set master transmit mode.
[3]
Issue the start condition.
[1]
No
BBSY=0 ?
Yes
Set MST and TRS
in ICCR1 to 1.
[2]
[4]
Set the first byte (slave address + R/W) of transmit data.
Write 1 to BBSY
and 0 to SCP.
[3]
[5]
Wait for 1 byte to be transmitted.
Write transmit data
in ICDRT
[4]
[6]
Test the acknowledge transferred from the specified slave device.
[7]
Set the second and subsequent bytes (except for the last byte) of transmit data.
[8]
Wait for ICDRT empty.
[9]
Set the last byte of transmit data.
Read TEND in ICSR
[5]
No
TEND=1 ?
Yes
Read ACKBR in ICIER
[6]
ACKBR=0 ?
[10] Wait for last byte to be transmitted.
No
[11] Clear the TEND flag.
Yes
Transmit
mode?
Yes
No
Write transmit data in ICDRT
Mater receive mode
[7]
[13] Issue the stop condition.
Read TDRE in ICSR
No
[8]
TDRE=1 ?
Yes
No
[12] Clear the STOP flag.
[14] Wait for the generation of stop condition.
[15] Set slave receive mode. Clear TDRE.
Last byte?
[9]
Yes
Write transmit data in ICDRT
Read TEND in ICSR
No
[10]
TEND=1 ?
Yes
Clear TEND in ICSR
[11]
Clear STOP in ICSR
[12]
Write 0 to BBSY
and SCP
[13]
Read STOP in ICSR
No
[14]
STOP=1 ?
Yes
Set MST to 1 and TRS
to 0 in ICCR1
[15]
Clear TDRE in ICSR
End
Figure 21.17 Sample Flowchart for Master Transmit Mode
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Section 21 I C Bus Interface 2 (IIC2)
Mater receive mode
[1]
Clear TEND, select master receive mode, and then clear TDRE.*
[2]
Set acknowledge to the transmit device.*
[3]
Dummy-read ICDDR.*
[4]
Wait for 1 byte to be received
[5]
Check whether it is the (last receive - 1).
[6]
Read the receive data.
[7]
Set acknowledge of the last byte. Disable continuous reception (RCVD = 1).
[8]
Read the (last byte - 1) of receive data.
[9]
Wait for the last byte to be receive.
Clear TEND in ICSR
Clear TRS in ICCR1 to 0
[1]
Clear TDRE in ICSR
Clear ACKBT in ICIER to 0
[2]
Dummy-read ICDRR
[3]
Read RDRF in ICSR
No
[4]
RDRF=1 ?
Yes
Last receive
- 1?
No
Read ICDRR
Yes
[5]
[10] Clear the STOP flag.
[6]
[11] Issue the stop condition.
[12] Wait for the generation of stop condition.
Set ACKBT in ICIER to 1
[7]
Set RCVD in ICCR1 to 1
Read ICDRR
[13] Read the last byte of receive data.
[14] Clear RCVD.
[8]
[15] Set slave receive mode.
Read RDRF in ICSR
No
RDRF=1 ?
[9]
Yes
Clear STOP in ICSR.
Write 0 to BBSY
and SCP
[10]
[11]
Read STOP in ICSR
No
[12]
STOP=1 ?
Yes
Read ICDRR
[13]
Clear RCVD in ICCR1 to 0
[14]
Clear MST in ICCR1 to 0
[15]
End
Note: Do not activate an interrupt during the execution of steps [1] to [3].
Supplementary explanation: When one byte is received, steps [2] to [6] are
skipped after step [1] before jumping to step [7].
The step [8] is dummy-read in ICDRR.
Figure 21.18 Sample Flowchart for Master Receive Mode
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Section 21 I C Bus Interface 2 (IIC2)
[1] Clear the AAS flag.
Slave transmit mode
Clear AAS in ICSR
[1]
Write transmit data
in ICDRT
[2]
[3] Wait for ICDRT empty.
[4] Set the last byte of transmit data.
Read TDRE in ICSR
[5] Wait for the last byte to be transmitted.
[3]
No
TDRE=1 ?
Yes
Yes
[6] Clear the TEND flag .
[7] Set slave receive mode.
Last
byte?
No
[2] Set transmit data for ICDRT (except for the last data).
[8] Dummy-read ICDRR to release the SCL.
[4]
[9] Clear the TDRE flag.
Write transmit data
in ICDRT
Read TEND in ICSR
[5]
No
TEND=1 ?
Yes
Clear TEND in ICSR
[6]
Clear TRS in ICCR1 to 0
[7]
Dummy read ICDRR
[8]
Clear TDRE in ICSR
[9]
End
Figure 21.19 Sample Flowchart for Slave Transmit Mode
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Section 21 I C Bus Interface 2 (IIC2)
Slave receive mode
[1] Clear the AAS flag.
Clear AAS in ICSR
[1]
Clear ACKBT in ICIER to 0
[2]
Dummy-read ICDRR
[3]
[2] Set acknowledge to the transmit device.
[3] Dummy-read ICDRR.
[5] Check whether it is the (last receive - 1).
Read RDRF in ICSR
No
[4]
RDRF=1 ?
[6] Read the receive data.
[7] Set acknowledge of the last byte.
Yes
Last receive
- 1?
[4] Wait for 1 byte to be received.
Yes
No
Read ICDRR
[5]
[8] Read the (last byte - 1) of receive data.
[9] Wait the last byte to be received.
[6]
[10] Read for the last byte of receive data.
Set ACKBT in ICIER to 1
[7]
Read ICDRR
[8]
Read RDRF in ICSR
No
[9]
RDRF=1 ?
Yes
Read ICDRR
[10]
End
Supplementary explanation: When one byte is received, steps [2] to [6] are skipped after step [1]
before jumping to step [7]. The step [8] is dummy-read in ICDRR.
Figure 21.20 Sample Flowchart for Slave Receive Mode
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Section 21 I C Bus Interface 2 (IIC2)
21.4
Interrupt Request
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK detection, STOP condition detection, and arbitration lost/overrun error. Table 21.3 shows
the contents of each interrupt request.
Table 21.3 Interrupt Requests
Interrupt Request
Abbreviation
Interrupt Condition
Clock
Synchronous
I2C Mode Mode
Transmit Data Empty
TXI
(TDRE=1) • (TIE=1)
O
O
Transmit End
TEI
(TEND=1) • (TEIE=1)
O
O
Receive Data Full
RXI
(RDRF=1) • (RIE=1)
O
O
STOP Condition Detection
STPI
(STOP=1) (STIE=1)
O
×
NACK Detection
NAKI
{(NACKF=1)+(AL=1)}
(NAKIE=1)
Arbitration Lost/
Overrun Error
•
•
O
×
O
O
When an exception processing is executed under interrupt conditions described in table 21.3,
interrupt sources should be cleared in the exception processing. TDRE and TEND are
automatically cleared to 0 by writing the transmit data to ICDRT. RDRF are automatically cleared
to 0 by reading ICDRR. TDRE is set to 1 again at the same time when transmit data is written to
ICDRT. When TDRE is cleared to 0, then an excessive data of one byte may be transmitted.
The DTC can be activated by a TXI interrupt request to transfer data. The TDRE flag is
automatically cleared upon data transfer by the DTC. The DTC can also be activated by an RXI
interrupt request to transfer data. The RDRF flag is automatically cleared to 0 upon data transfer
by the DTC.
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2
Section 21 I C Bus Interface 2 (IIC2)
21.5
Bit Synchronous Circuit
In master mode, this module has a possibility that high level period may be shortened in the two
states described below.
• When SCL is driven to low by the slave device
• When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pullup resistance)
Therefore, it monitors SCL and communicates by bit with synchronization.
Figure 21.21 shows the timing of the bit synchronous circuit and table 21.4 shows the time when
SCL output changes from low to Hi-Z and then SCL is monitored.
SCL monitor
timing reference
clock
VIH
SCL
Internal SCL
Figure 21.21 The Timing of the Bit Synchronous Circuit
Table 21.4 Time for Monitoring SCL
CKS3
CKS2
Time for Monitoring SCL
0
0
7.5 tcyc
1
19.5 tcyc
0
17.5 tcyc
1
41.5 tcyc
1
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2
Section 21 I C Bus Interface 2 (IIC2)
21.6
Usage Notes
21.6.1
SCL and SDA pins selected by PMC
This LSI incorporates the IIC2 and SSU modules, one of which module functions should be
selected by the SELICSU bit in ICSUSR. Therefore, when assigning the pin functions using the
peripheral function mapping controller (PMC), the SCL and SDA pin functions should be
assigned to the P56 and P57 pins when the IIC2 function is selected. If these pin functions are
assigned to other pins, correct operation cannot be guaranteed.
21.6.2
Restriction on Use of Bit Manipulation Instructions to Set MST and TRS in MultiMaster Usage
When master transmission is selected by consecutively manipulating the MST and TRS bits in
multi-master usage, an arbitration loss during execution of the bit-manipulation instruction for
TRS leads to the contradictory situation where AL in ICSR is 1 in master transmit mode
(MST = 1, TRS = 1).
Ways to avoid this effect are listed below.
• Use the MOV instruction to set MST and TRS when used in multi-master mode.
• When arbitration is lost, confirm that MST = 0 and TRS = 0. If the setting of MST = 0 and
TRS = 0 is not confirmed, then set MST = 0 and TRS = 0 again.
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Section 22 Synchronous Serial Communication Unit (SSU)
Section 22 Synchronous Serial Communication Unit (SSU)
Note: In this section, the synchronous serial communication unit is abbreviated as SSU for
convenience.
The synchronous serial communication unit (SSU) can handle clocked synchronous serial data
communication.
Figure 22.1 shows a block diagram of the SSU.
Either the SSU or IIC2 incorporated in this LSI can be used at a time. Accordingly, when the SSU
function is used, the IIC2 function is not available.
22.1
Features
• Can be operated in clocked synchronous communication mode or four-line bus communication
mode (including bidirectional communication mode)
• Can be operated as a master or a slave device
• Choice of seven internal clocks (φ/256, φ/128, φ/64, φ/32, φ/16, φ/8, φ/4) and an external clock
as a clock source
• Clock polarity and phase of SSCK can be selected
• Choice of data transfer direction (MSB-first or LSB-first)
• Receive error detection: overrun error
• Multimaster error detection: conflict error
• Five interrupt sources: transmit-end, transmit-data-empty, receive-data-full, overrun error, and
conflict error. The DTC can be activated by the transmit-data-empty and receive-data-full
interrupts.
• The transmitter and receiver with buffer structure allow continuous transmission and reception
of serial data.
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Section 22 Synchronous Serial Communication Unit (SSU)
Internal clock
Multiplexer
SSCK
SSMR
SSMR2
SSCRL
SCS
SSCRH
SSER
SSSR
Internal data bus
Transmission/
reception
control circuit
SSTDR
SSO
SSI
Selector
SSTRSR
SSRDR
Interrupt request
(TXI, TEI, RXI, OEI, CEI)
Figure 22.1 Block Diagram of SSU
Table 22.1 shows the pin configuration of the SSU.
Table 22.1 Pin Configuration
Pin Name
I/O
Function
SSCK
I/O
SSU clock input/output
SSI
I/O
SSU data input/output
SSO
I/O
SSU data input/output
SCS
I/O
SSU chip select input/output
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Section 22 Synchronous Serial Communication Unit (SSU)
22.2
Register Descriptions
The SSU has the following registers.
•
•
•
•
•
•
•
•
•
•
IIC2/SSU select register (ICSUSR)
SS control register H (SSCRH)
SS control register L (SSCRL)
SS mode register (SSMR)
SS mode register 2 (SSMR2)
SS enable register (SSER)
SS status register (SSSR)
SS receive data register (SSRDR)
SS transmit data register (SSTDR)
SS shift register (SSTRSR)
22.2.1
IIC2/SSU Select Register (ICSUSR)
Address: H'FF000B
Bit:
Value after reset:
Bit
b6
b5
b4
b3
b2
b1
b0







SELICSU
0
0
0
0
0
0
0
0
Bit Name
Description
R/W
7 to 1 
Reserved
These bits are read as 0. The write value should
be 0.

0
IIC2/SSU module 0: IIC2 function is selected.
function select
1: SSU function is selected.*
Note:
Symbol
b7
SELICSU
*
R/W
To select the SSU function, this bit should be set to 1 without fail.
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Section 22 Synchronous Serial Communication Unit (SSU)
22.2.2
SS Control Register H (SSCRH)
Address: H'FF05C8
Bit:
b7
b6
b5
b4
b3

RSSTP
MSB


Value after reset:
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is read as 0. The write value should be 0.

6
RSSTP
Receive single
stop
0: After receiving 1 byte of data, reception continues.
R/W
Master/slave
device select
0: Operates as a slave device
Reserved
These bits are read as 0. The write value should be 0. 
Transfer clock
rate select
000: φ/256
5
4, 3
MSS

2 to 0 CKS[2:0]
b2
b1
b0
CKS[2:0]
0
0
0
1: After receiving 1 byte of data, reception ends.*
R/W
1: Operates as a master device
R/W
001: φ/128
010: φ/64
011: φ/32
100: φ/16
101: φ/8
110: φ/4
111: Reserved
Note:
*
The setting of the RSSTP bit is invalid when the MSS bit is cleared to 0.
• MSS bit (master/slave device select)
Selects whether this module is used as a master device or a slave device. When this module is
used as a master device, transfer clock is output from the SSCK pin. When the CE bit in SSSR
is set, this bit is automatically cleared.
• CKS[2:0] bits (transfer clock rate select)
Sets transfer clock rate (prescaler division ratio) when the internal clock is selected.
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Section 22 Synchronous Serial Communication Unit (SSU)
22.2.3
SS Control Register L (SSCRL)
Address: H'FF05C9
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0


SOL
SOLP


SRES

0
1
1
1
1
1
0
1
Bit
Symbol
Bit Name
Description
R/W
7

Reserved
This bit is read as 0. The write value should be 0.

6

Reserved
This bit is read as 1. The write value should be 1.

Serial data
output level
setting
0: When reading, serial data output level is low.
When writing, serial data output level is
changed to low.
R/W
5
SOL*
1
1: When reading, serial data output level is high.
When writing, serial data output level is
changed to high.
4
SOLP
SOL write
protect

0: When writing, output level can be changed
according to the value of the SOL bit.
1: When reading, this bit is always read as 1.
When writing, modifying to the SOL bit is invalid.
3, 2

Reserved
These bits are read as 1. The write value should
be 1.
1
SRES
Software reset
0: Does not reset.
1: The SSU internal sequencer is forcibly reset.*
0
Note:

Reserved

2
This bit is read as 1. The write value should be 1.

1. When the output level is changed, the SOLP bit (bit4) should be cleared to 0 and the
MOV instruction should be used. If this bit is written during data transfer, erroneous
operation may occur. Therefore this bit must not be manipulated during transmission.
2. This bit should always be cleared by software as this bit is not cleared automatically.
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Section 22 Synchronous Serial Communication Unit (SSU)
• SOL bit (serial data output level setting)
Although the value in the last bit of transmit data is retained in the serial data output after the
end of transmission, the output level of serial data can be changed by manipulating this bit
before or after transmission.
• SOLP bit (SOL write protect)
When output level of serial data is changed, the MOV instruction is used to set the SOL bit to
1 and clear this bit to 0 or to clear the SOL bit and this bit to 0.
• SRES bit (software reset)
When this bit is set to 1, the SSU internal sequencer is forcibly reset. The register value in the
SSU is retained.
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Section 22 Synchronous Serial Communication Unit (SSU)
22.2.4
SS Mode Register (SSMR)
Address: H'FF05CA
Bit:
Value after reset:
b7
b6
b5
b4
b3
MLS
CPOS
CPHS


0
0
0
1
1
b2
b1
b0
BC[2:0]
0
0
0
Bit
Symbol
Bit Name
7
MLS
MSB-first/LSB- 0: Transfer by MSB-first
first select
1: Transfer by LSB-first
R/W
6
CPOS
Clock polarity
select
0: SSCK clock idling state = high
R/W
5
CPHS
Clock phase
select
0: Data change at first edge
Reserved
This bit is read as 1. The write value should be 1.
4, 3

2 to 0 BC[2:0]
Description
R/W
1: SSCK clock idling state = low
R/W
1: Data latch at first edge
Bit counter 2 to 000: 8 bits
0
001: 1 bit

R/W
010: 2 bits
011: 3 bits
100: 4 bits
101: 5 bits
110: 6 bits
111: 7 bits
• BC[2:0] bits (bit counter 2 to 0)
When read, the remaining number of transfer bits is indicated.
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Section 22 Synchronous Serial Communication Unit (SSU)
22.2.5
SS Mode Register 2 (SSMR2)
Address: H'FF05CD
Bit:
Value after reset:
b7
b6
BIDE
SCKS
0
0
b5
b4
CSS[1:0]
0
b3
b2
b1
b0
SCKOS
SOOS
CSOS
SSUMS
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
BIDE
Bidirectional
mode enable
0: Normal mode.
Communication is performed by using two pins.
R/W
1: Bidirectional mode.
Communication is performed by using only one
pin.
6
5, 4
SCKS
CSS[1:0]
SSCK pin
select
0: Functions as a port*1
R/W
1: Functions as a serial clock pin
SCS pin select 00: Functions as a port*1
R/W
01: Functions as an SCS input
1X: Functions as an SCS output (however,
functions as an SCS input before starting
transfer)
3
SCKOS
SSCK pin
open-drain
output select
R/W
0: CMOS output
2
1: NMOS open-drain output*
2
SOOS
SSO pin open- 0: CMOS output
2
drain output
1: NMOS open-drain output*
select
R/W
1
CSOS
SCS pin opendrain output
select
R/W
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0: CMOS output
2
1: NMOS open-drain output*
Section 22 Synchronous Serial Communication Unit (SSU)
Bit
Symbol
Bit Name
Description
R/W
0
SSUMS
SSU mode
select
0: Clocked synchronous communication mode
R/W
Data input: SSI pin, Data output: SSO pin
1: Four-line bus communication mode
When MSS = 1 in SSCRH and BIDE = 0 in
SSMR2:
Data input: SSI pin, Data output: SSO pin
When MSS = 0 in SSCRH and BIDE = 0 in
SSMR2:
Data input: SSO pin, Data output: SSI pin
When BIDE = 1 in SSMR2:
Data input and output: SSO pin
[Legend]
X:
Don't care.
Note: 1. To function these pins as ports, clear the PMR bit corresponding to the pin to 0.
2. If the NMOS open-drain output is selected, use the PMC to allocate the pin from port 5.
If the pin is allocated from a port other than port 5, only the CMOS output can be
selected.
• BIDE bit (bidirectional mode enable)
Selects whether the serial data input pin and the output pin are both used or only one pin is
used. For details, see section 22.3.3, Relationship between Data Input/Output Pin and Shift
Register. When the SSUMS bit in SSMR2 is 0, this setting is invalid.
• SCKS bit (SSCK pin select)
Selects whether the SSCK pin functions as a port or a serial clock pin.
• CSS[1:0] bits (SCS pin select)
Selects whether the SCS pin functions as a port, an SCS input, or SCS output. When the
SSUMS bit in SSMR2 is 0, the SCS pin functions as a port regardless of the setting of this bit.
• SOOS bit (SSO pin open-drain output select)
Selects whether the serial data output pin is CMOS output or NMOS open-drain output. The
serial data output pin is changed according to the register setting value. For details, see section
22.3.3, Relationship between Data Input/Output Pin and Shift Register.
• SSUMS bit (SSU mode select)
Selects which combination of the serial data input pin and serial data output pin is used.
For details, see section 22.3.3, Relationship between Data Input/Output Pin and Shift Register.
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Section 22 Synchronous Serial Communication Unit (SSU)
22.2.6
SS Enable Register (SSER)
Address: H'FF05CB
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
TIE
TEIE
RIE
TE
RE


CEIE
0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
7
TIE
Transmit interrupt 0: A TXI interrupt request is disabled.
enable
1: A TXI interrupt request is enabled.
R/W
6
TEIE
Transmit end
interrupt enable
R/W
5
RIE
Receive interrupt 0: An RXI and an OEI interrupt requests are disabled. R/W
enable
1: An RXI and an OEI interrupt requests are enabled.
4
TE*
Transmit enable
0: A TEI interrupt request is disabled.
R/W
1: A TEI interrupt request is enabled.
0: Transmit operation is disabled.
R/W
1: Transmit operation is enabled.
3
RE*
Receive enable
0: Receive operation is disabled.
R/W
1: Receive operation is enabled.
2, 1

Reserved
These bits are read as 0. The write value should be 0. 
0
CEIE
Conflict error
interrupt enable
0: A CEI interrupt request is disabled.
Note:
*
1: A CEI interrupt request is enabled.
The TE and RE bits are reset in standby mode.
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REJ09B0465-0100
R/W
Section 22 Synchronous Serial Communication Unit (SSU)
22.2.7
SS Status Register (SSSR)
Address: H'FF05CC
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
TDRE
TEND
RDRF


ORER

CE
0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
TDRE
Transmit data
empty flag
[Setting conditions]
R/W
•
When the TE bit in SSER is 0
•
When data transfer is performed from SSTDR to
SSTRSR and data can be written in SSTDR
[Clearing conditions]
6
TEND
Transmit end
flag
•
When 0 is written to this bit after reading 1
•
When data is written in SSTDR
•
When the DTC transfers data to SSTDR by a
TXI interrupt request, and the DTC settings
satisfy the flag clearing conditions.*
[Setting condition]
•
R/W
When the last bit of data is transmitted, the
TDRE bit is 1
[Clearing conditions]
5
RDRF
•
When 0 is written to this bit after reading 1
•
When data is written in SSTDR
Receive data
[Setting condition]
R/W
register full flag
• When serial reception is completed normally
and receive data is transferred from SSTRSR to
SSRDR
[Clearing conditions]
•
When 0 is written to this bit after reading 1
•
When data is read from SSRDR
•
When the DTC transfers data to SSRDR by an
RXI interrupt request, and the DTC settings
satisfy the flag clearing conditions.*
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Section 22 Synchronous Serial Communication Unit (SSU)
Bit
Symbol
Bit Name
Description
R/W
4, 3

Reserved
These bits are read as 0. The write value should
be 0.

2
ORER
Overrun error flag [Setting condition]
•
R/W
When the next serial reception is completed
while RDRF = 1
[Clearing condition]
•
When 0 is written to this bit after reading 1
1

Reserved
0
CE
Conflict error flag [Setting conditions]
These bits are read as 0. The write value should
be 0.
•
When serial communication is started while
SSUMS = 1 in SSMR2 and MSS = 1 in
SSCRH, the SCS pin input is low
•
When the SCS pin level changes from low to
high during transfer while SSUMS = 1 in
SSMR2 and MSS = 0 in SSCRH

R/W
[Clearing condition]
•
When 0 is written to this bit after reading 1
Notes: In standby mode, SSSR is reset.
* The DTC clears the peripheral module flags when all of the following three conditions
are satisfied.
1. When the DISEL bit is 0.
2. When the transfer counter (DTC transfer count register A (CRA) in normal mode
and repeat mode, or DTC transfer count register B (CRB) in block mode) is not 0.
3. When chain transfer is not used.
• ORER bit (overrun error flag)
Indicates that the RDRF bit is abnormally terminated in reception because an overrun error has
occurred. SSRDR retains received data before the overrun error occurs and the received data
after the overrun error occurs is lost. When this bit is set to 1, subsequent serial reception
cannot be continued. When the MSS bit in SSCRH is 1, this is also applied to serial
transmission.
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Section 22 Synchronous Serial Communication Unit (SSU)
22.2.8
SS Receive Data Register (SSRDR)
Address: H'FF05CF
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
Value after reset:
1
1
1
1
1
1
1
1
SSRDR is an 8-bit register that stores received serial data. When the SSU has received one byte of
serial data, it transfers the received serial data from SSTRSR to SSRDR to end receive operation.
After this, SSTRSR is receive-enabled. As SSTRSR and SSRDR function as a double buffer in
this way, continuous receive operations are possible. SSRDR is a read-only register and cannot be
written to by the CPU. SSRDR is initialized to H'FF. In standby mode, SSRDR is initialized.
22.2.9
SS Transmit Data Register (SSTDR)
Address: H'FF05CE
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
Value after reset:
1
1
1
1
1
1
1
1
SSTDR is an 8-bit register that stores serial data for transmission. SSTDR can be read or written
to by the CPU at all times. When the SSU detects that SSTRSR is empty, it transfers the transmit
data written in SSTDR to SSTRSR and starts serial transmission. If the next transmit data has
already been written to SSTDR during serial transmission, continuous serial transmission is
possible. SSTDR is initialized to H′FF. In standby mode, SSTDR is initialized.
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Section 22 Synchronous Serial Communication Unit (SSU)
22.2.10 SS Shift Register (SSTRSR)
Address: 
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
Value after reset:








SSTRSR is a shift register that transmits and receives serial data. When transmit data is transferred
from SSTDR to SSTRSR, bit 0 in SSTDR is transferred to bit 0 in SSTRSR while the MLS bit in
SSMR is 0 (LSB-first transfer) and bit 7 in SSTDR is transferred to bit 0 in SSTRSR while the
MLS bit in SSMR is 1 (MSB-first transfer). SSTRSR cannot be directly accessed by the CPU. In
standby mode, SSTRSR is initialized.
22.3
Operation
22.3.1
Transfer Clock
Transfer clock can be selected from seven internal clocks and an external clock. When this module
is used, the SSCK pin must be selected as a serial clock by setting the SCKS bit in SSMR2 to 1.
When the MSS bit in SSCRH is 1, an internal clock is selected and the SSCK pin is in the output
state. If transfer is started, the SSCK pin outputs clocks of the transfer rate set in the CKS2 to
CKS0 bits in SSCRH. When the MSS bit is 0, an external clock is selected and the SSCK pin is in
the input state.
22.3.2
Relationship between Clock Polarity and Phase, and Data
Relationship between clock polarity and phase, and transfer data changes according to a
combination of the SSUMS bit in SSMR2 and the CPOS and CPHS bits in SSMR. Figure 22.2
shows the relationship.
MSB-first transfer or LSB first transfer can be selected by the setting of the MLS bit in SSMR.
When the MLS bit is 0, transfer is started from LSB to MSB. When the MLS bit is 1, transfer is
started from MSB to LSB.
Rev. 1.00 Oct. 03, 2008 Page 780 of 962
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Section 22 Synchronous Serial Communication Unit (SSU)
(1) When CPHS = 0, CPOS =0, and SSUMS = 0:
SSCK
Bit 0
SSO, SSI
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
(2) When CPHS = 0 and SSUMS = 1:
SSCK
(CPOS = 0)
SSCK
(CPOS = 1)
SSO, SSI
Bit 0
SCS
(3) When CPHS = 1 and SSUMS = 1:
SSCK
(CPOS = 0)
SSCK
(CPOS = 1)
SSO, SSI
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
SCS
Figure 22.2 Relationship between Clock Polarity and Phase, and Data
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Section 22 Synchronous Serial Communication Unit (SSU)
22.3.3
Relationship between Data Input/Output Pin and Shift Register
Relationship of connection between the data input/output pin and SSTRSR changes according to a
combination of the MSS bit in SSCRH and the SSUMS bit in SSMR2. It also changes by the
BIDE bit in SSMR2. Figure 22.3 shows the relationship.
(1) When SSUMS = 0:
Shift register
(SSTRSR)
(2) When SSUMS = 1, BIDE = 0, and MSS = 1:
SSO
Shift register
(SSTRSR)
SSI
(3) When SSUMS = 1, BIDE = 0, and MSS = 0:
Shift register
(SSTRSR)
SSI
(4) When SSUMS = 1 and BIDE = 1:
SSO
Shift register
(SSTRSR)
SSI
Figure 22.3 Relationship between Data Input/Output Pin and Shift Register
Rev. 1.00 Oct. 03, 2008 Page 782 of 962
REJ09B0465-0100
SSO
SSO
SSI
Section 22 Synchronous Serial Communication Unit (SSU)
22.3.4
Communication Modes and Pin Functions
The SSU switches functions of the input/output pin in each communication mode according to the
settings of the MSS bit in SSCRH and the RE and TE bits in SSER. Table 22.2 shows the
relationship between communication modes and the input/output pins. In bidirectional
communication mode, the TE and RE bits should not be set to 1 at the same time.
Table 22.2 Relationship between Communication Modes and Input/Output Pins
Communication
Mode
Clocked
Synchronous
Communication
Mode
Register State
SSUMS
BIDE
MSS
TE
RE
SSI
SSO
SSCK
0
*
0
0
1
In

In
1
0

Out
In
1
In
Out
In
0
1
In

Out
1
0

Out
Out
1
In
Out
Out
0
1

In
In
1
0
Out

In
1
Out
In
In
0
1
In

Out
1
0

Out
Out
1
In
Out
Out
0
1

In
In
1
0

Out
In
0
1

In
Out
1
0

Out
Out
1
Four-Line Bus
Communication
Mode
1
0
0
1
Four-Line Bus
(Bidirectional)
Communication
Mode
Pin State
1
1
0
1
[Legend]
: Can be used as a general I/O port.
Rev. 1.00 Oct. 03, 2008 Page 783 of 962
REJ09B0465-0100
Section 22 Synchronous Serial Communication Unit (SSU)
22.3.5
(1)
Operation in Clocked Synchronous Communication Mode
Initialization in Clocked Synchronous Communication Mode
Figure 22.4 shows the initialization in clocked synchronous communication mode. Before
transmitting and receiving data, the TE and RE bits in SSER should be cleared to 0, then the SSU
should be initialized.
Note: When the operating mode, or transfer format, is changed for example, the TE and RE bits
must be cleared to 0 before making the change using the following procedure. When the
TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not
change the contents of the RDRF and ORER flags, or the contents of SSRDR.
Start
Clear TE and RE bits in SSER to 0
Clear SSUMS bit in SSMR2 to 0
Clear CPOS and CPHS bits in SSMR
to 0 and set MLS and CKS2 to CKS0
bits in SSCRH
Set SCKS bit in SSMR2 to 1 and
set MSSS bit in SOOS and SSCRH
Clear ORER bit in SSSR to 0
Set the TE and RE bits in SSER to 1
and set RIE, TIE and TEIE bits, and
RSSTP bit in SSCRH according to
transmission/reception/transmission
and reception
End
Figure 22.4 Initialization in Clocked Synchronous Communication Mode
Rev. 1.00 Oct. 03, 2008 Page 784 of 962
REJ09B0465-0100
Section 22 Synchronous Serial Communication Unit (SSU)
(2)
Serial Data Transmission
Figure 22.5 shows an example of the SSU operation for transmission. In serial transmission, the
SSU operates as described below.
When the SSU is set as a master device, it outputs a synchronous clock and data. When the SSU is
set as a slave device, it outputs data in synchronized with the input clock.
When the SSU writes transmit data in SSTDR after setting the TE bit to 1, the TDRE flag is
automatically cleared to 0 and data is transferred from SSTDR to SSTRSR. Then the SSU sets the
TDRE flag to 1 and starts transmission. If the TIE bit in SSER is set to 1 at this time, a TXI is
generated.
When the TDRE flag is 0 and one frame of data has transferred, data is transferred from SSTDR to
SSTRSR and serial transmission of the next frame is started. If the eighth bit is transmitted while
the TDRE flag is 1, the TEND bit in SSSR is set to 1 and the state is retained. If the TEIE bit in
SSER is set to 1 at this time, a TEI is generated. After transmission is ended, the SSCK pin is
fixed high.
While the ORER bit in SSSR is set to 1, transmission cannot be performed. Therefore confirm that
the ORER bit is cleared to 0 before transmission.
Figure 22.6 shows a sample flowchart for serial data transmission.
SSCK
SSO
Bit 0
Bit 1
Bit 7
One frame
Bit 0
Bit 1
Bit 7
One frame
TDRE
TEND
LSI Operation
User
processing
TXI generated
Write data
in SSTDR
TXI generated
TEI generated
Write data
in SSTDR
Figure 22.5 Example of Operation in Data Transmission
Rev. 1.00 Oct. 03, 2008 Page 785 of 962
REJ09B0465-0100
Section 22 Synchronous Serial Communication Unit (SSU)
Start
Initialization
[1]
Read TDRE bit in SSSR
No
TDRE = 1?
[1] After reading SSSR and confirming
that the TDRE bit is 1, write transmit
data in SSTDR. Then the TDRE bit is
automatically cleared to 0.
Yes
Write transmit data
in SSTDR
[2]
Data transmission
continued?
Yes
[2] Determine whether data transmission
is continued.
No
[3]
Read TEND bit in SSSR
No
TEND = 1?
[3] Read 1 from the TEND bit in SSSR
to confirm that data transmission is
completed. After the TEND bit is set to 1,
clear the TEND bit and TE bit in SSER
to 0 and transmit mode is ended.
Yes
Clear TEND bit and
TE bit in SSER to 0
End
Figure 22.6 Sample Serial Transmission Flowchart
Rev. 1.00 Oct. 03, 2008 Page 786 of 962
REJ09B0465-0100
Section 22 Synchronous Serial Communication Unit (SSU)
(3)
Serial Data Reception
Figure 22.7 shows an example of the SSU operation for reception. In serial reception, the SSU
operates as described below.
When the SSU is set as a master device, it outputs a synchronous clock and inputs data. When the
SSU is set as a slave device, it inputs data in synchronized with the input clock. When the SSU is
set as a master device, it outputs a receive clock and starts reception by performing dummy read
on SSRDR.
After eight bits of data is received, the RDRF bit in SSSR is set to 1 and received data is stored in
SSRDR. If the RIE bit in SSER is set to 1 at this time, a RXI is generated. If SSRDR is read, the
RDRF bit is automatically cleared to 0.
When the SSU is set as a master device and reception is ended, received data is read after setting
the RSSTP bit in SSCRH to 1. Then the SSU outputs eight bits of clocks and operation is stopped.
After that, the RE and RSSTP bits are cleared to 0 and the last received data is read. Note that if
SSRDR is read while the RE bit is set to 1, received clock is output again.
When the eighth clock rises while the RDRF bit is 1, the ORER bit in SSSR is set. Then an
overrun error (OEI) is generated and operation is stopped. When the ORER bit in SSSR is set to 1,
reception cannot be performed. Therefore confirm that the ORER bit is cleared to 0 before
reception.
Figure 22.8 shows a sample flowchart for serial data reception.
SSCK
SSO
Bit 0
Bit 7
One frame
Bit 0
Bit 7
Bit 0
Bit 7
One frame
RDRF
RSSTP
LSI operation
User
processing
RXI generated
Dummy read
on SSRDR
RXI generated
Read data in SSRDR
Set RSSTP to 1
RXI generated
Read data
in SSRDR
Figure 22.7 Example of Operation in Data Reception (MSS = 1)
Rev. 1.00 Oct. 03, 2008 Page 787 of 962
REJ09B0465-0100
Section 22 Synchronous Serial Communication Unit (SSU)
Start
Initialization
[1]
Dummy read on SSRDR
[2]
Last reception?
[1] After setting each register in the SSU,
dummy read on SSRDR is performed
and reception is started.
Yes
[2] Determine whether the last one byte of
data is received. When the last one byte
of data is received, set to stop reception
after the data is received.
No
Read ORER
[3]
ORER = 1?
Yes
[3][6] When a receive error occurs, clear the
ORER flag to 0 after the ORER flag in
SSSR is read and an appropriate error
processing is performed. When the ORER
flag is set to 1, transmission/reception
cannot be started again.
No
Read RDRF
[4]
No
[4] Confirm that the RDRF bit is 1. If the RDRF
bit is 1, receive data in SSRDR is read. If the
SSRDR bit is read, the RDRF bit is automatically
cleared.
RDRF = 1?
Yes
Read receive data
in SSRDR
[5]
[5] Before the last one byte of data is received,
set the RSSTP bit to 1 and reception is stopped
after the data is received.
Set RSSTP to 1
Read ORER
Yes
[6]
ORER = 1?
No
Read RDRF
No
[7] Confirm that the RDRF bit is 1. To end
reception, clear the RE and RSSTP bits to
0 and then read the last receive data. If the
SSRDR bit is read before clearing the RE bit,
reception is started again.
RDRF = 1?
[7]
Yes
RE = 0, RSSTP = 0
Overrun error
processing
Read receive data
in SSRDR
End
Figure 22.8 Sample Serial Reception Flowchart (MSS = 1)
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REJ09B0465-0100
Section 22 Synchronous Serial Communication Unit (SSU)
(4)
Serial Data Transmission and Reception
Data transmission and reception is a combined operation of data transmission and reception which
are described before. Transmission and reception is started by writing data in SSTDR. When the
eighth clock rises while the TDRE bit is set to 1 or the ORER bit is set to 1, transmission and
reception is stopped.
To switch from transmit mode (TE = 1) or receive mode (RE = 1) to transmit and receive mode
(TE = RE = 1), the TE and RE bits should be cleared to 0. After confirming that the TEND,
RDRF, and ORER bits are cleared to 0, set the TE and RE bits to 1.
When the module is released from transmit and receive mode (TE = 1 and RE = 1), setting TE = 0
(and RE = 1) after the SSRDR has been read can cause output of the clock signal. For this reason,
start by setting RE = 0 and only set TE = 0 after that (or set both RE = 0 and TE = 0 at the same
time). When TE = 0 and RE = 1 is subsequently set, only set RE = 1 after changing SRES from 1
to 0.
Figure 22.9 shows a sample flowchart for serial transmit and receive operations.
Rev. 1.00 Oct. 03, 2008 Page 789 of 962
REJ09B0465-0100
Section 22 Synchronous Serial Communication Unit (SSU)
Start
Initialization
[1]
Read TDRE in SSSR
No
TDRE = 1?
[1] After reading SSSR and confirming that
the TDRE bit is 1, write transmit data in
SSTDR. Then the TDRE bit is automatically
cleared to 0.
Yes
Write transmit data
in SSTDR
[2]
No
[2] Confirm that the RDRF bit is 1. If the RDRF
bit is 1, receive data in SSRDR is read. If the
SSRDR bit is read, the RDRF bit is automatically
cleared.
Read RDRF in SSSR
RDRF = 1?
Yes
Read receive data
in SSRDR
[3]
Data transmission
continued?
Yes
[3] Determine whether data transmission is continued.
No
[4]
Clear TEND to 0 and
clear TE and RE in
SSER to 0
[4] To end transmit and receive mode, clear the
TEND bit to 0 and clear the TE and RE bits in
SSER to 0.
End
Figure 22.9 Sample Flowchart for Serial Transmit and Receive Operations
Rev. 1.00 Oct. 03, 2008 Page 790 of 962
REJ09B0465-0100
Section 22 Synchronous Serial Communication Unit (SSU)
22.3.6
Operation in Four-Line Bus Communication Mode
Four-line bus communication mode is a mode which communicates with the four-line bus; a clock
line, a data input line, a data output line, and a chip select line. This mode includes bidirectional
mode in which the data input line and the data output line function as a single pin. The data input
line and the data output line are changed according to the settings of the MSS bit in SSCRH and
BIDE bit in SSMR2. For details, see section 22.3.3, Relationship between Data Input/Output Pin
and Shift Register. In this mode, relationship between clock polarity and phase, and data can be set
by the CPOS and CPHS bits in SSMR. For details, see section 22.3.2, Relationship between Clock
Polarity and Phase, and Data.
When the SSU is set as a master device, the chip select line controls output. When the SSU is set
as a slave device, the chip select line controls input. When the SSU is set as a master device, the
chip select line controls output of the SCS pin or controls output of a general port by setting the
CSS1 bit in SSMR2 to 1. When the SSU is set as a slave device, the chip select line sets the SCS
pin as an input pin by setting the CSS1 and CSS0 bits in SSMR2 to 01.
In four-line bus communication mode, the MLS bit in SSMR is set to 1 and transfer is performed
in MSB-first order.
(1)
Initialization in Four-Line Bus Communication Mode
Figure 22.10 shows the initialization in four-line bus communication mode. Before transmitting
and receiving data, the TE and RE bits in SSER should be cleared to 0, then the SSU should be
initialized.
Note: When the operating mode, or transfer format, is changed for example, the TE and RE bits
must be cleared to 0 before making the change using the following procedure. Note that
clearing the RE bit to 0 does not change the contents of the RDRF and ORER flags, or the
contents of SSRDR.
Rev. 1.00 Oct. 03, 2008 Page 791 of 962
REJ09B0465-0100
Section 22 Synchronous Serial Communication Unit (SSU)
Start
Clear TE and RE in SSER to 0
Set SSUMS in SSMR2 to 1
[1]
Set MLS in SSMR to 1 and
set CPOS and CPHS, and
CKS2 to CKS0 inSSCRH
[2]
Set SCKS in SSMR2 to 1 and
set BIDE, SOOS, CSS1and CSS0,
and MSS in SSCRH
[1] The MLS bit is set to 1 for MSB-first transfer.
The clock polarity and phase are set in the
CPOS and CPHS bits.
[2] In bidirectional mode, the BIDE bit is set
to 1 and input/output of the SCS pin is set
by the CSS1 and CSS0 bits.
Clear ORER in SSSR to 0
Set TE and RE in SSER to 1 and
set RIE, TIE and TEIE, and RSSTP in
SSCRH according to transmission/
reception/transmission and reception
End
Figure 22.10 Initialization in Four-Line Bus Communication Mode
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REJ09B0465-0100
Section 22 Synchronous Serial Communication Unit (SSU)
(2)
Serial Data Transmission
Figure 22.11 shows an example of the SSU operation for transmission. In serial transmission, the
SSU operates as described below.
When the SSU is set as a master device, it outputs a synchronous clock and data. When the SSU is
set as a slave device, the SCS pin is in the low-input state and the SSU outputs data in
synchronized with the input clock.
When the SSU writes transmit data in SSTDR after setting the TE bit to 1, the TDRE flag is
automatically cleared to 0 and data is transferred from SSTDR to SSTRSR. Then the SSU sets the
TDRE flag to 1 and starts transmission. If the TIE bit in SSER is set to 1 at this time, a TXI is
generated.
When the TDRE flag is 0 and one frame of data has transferred, data is transferred from SSTDR to
SSTRSR and serial transmission of the next frame is started. If the eighth bit is transmitted while
the TDRE flag is 1, the TEND bit in SSSR is set to 1 and the state is retained. If the TEIE bit in
SSER is set to 1 at this time, a TEI is generated. After transmission is ended, the SSCK pin is
fixed high and the SCS pin goes high. When continuous transmission is performed with the SCS
pin low, the next data should be written to SSTDR before transmitting the eighth bit of the frame.
While the ORER bit in SSSR is set to 1, transmission cannot be performed. Therefore confirm that
the ORER bit is cleared to 0 before transmission.
The difference between this mode and clocked synchronous communication mode is as follows:
when the SSU is set as a master device, the SSO pin is in the high impedance state if the SCS pin
is in the high impedance state and when the SSU is set as a slave device, the SSI pin is in the high
impedance state if the SCS pin is in the high-input state. The sample flowchart for serial data
transmission is the same as that in clocked synchronous communication mode.
Rev. 1.00 Oct. 03, 2008 Page 793 of 962
REJ09B0465-0100
Section 22 Synchronous Serial Communication Unit (SSU)
(1) When CPOS = 0 and CPHS = 0:
SCS
(output)
(High
impedance)
SSCK
SSO
Bit 7
Bit 6
Bit 0
Bit 7
One frame
Bit 6
Bit 0
One frame
TDRE
TEND
LSI operation
User
processing
TXI generated
Write data
in SSTDR
TXI generated
TEI generated
Write data
in SSTDR
(2) When CPOS = 0 and CPHS = 1:
SCS
(output)
(High
impedance)
SSCK
Bit 7
SSO
Bit 6
Bit 0
Bit 7
One frame
Bit 6
Bit 0
One frame
TDRE
TEND
LSI operation
User
processing
TXI generated
Write data
in SSTDR
TXI generated
TEI generated
Write data
in SSTDR
Figure 22.11 Example of Operation in Data Transmission (MSS = 1)
Rev. 1.00 Oct. 03, 2008 Page 794 of 962
REJ09B0465-0100
Section 22 Synchronous Serial Communication Unit (SSU)
(3)
Serial Data Reception
Figure 22.12 shows an example of the SSU operation for reception. In serial reception, the SSU
operates as described below.
When the SSU is set as a master device, it outputs a synchronous clock and inputs data. When the
SSU is set as a slave device, the SCS pin is in the low-input state and inputs data in synchronized
with the input clock. When the SSU is set as a master device, it outputs a receive clock and starts
reception by performing dummy read on SSRDR.
After eight bits of data is received, the RDRF bit in SSSR is set to 1 and received data is stored in
SSRDR. If the RIE bit in SSER is set to 1 at this time, an RXI is generated. If SSRDR is read, the
RDRF bit is automatically cleared to 0.
When the SSU is set as a master device and reception is ended, received data is read after setting
the RSSTP bit in SSER to 1. Then the SSU outputs eight bits of clocks and operation is stopped.
After that, the RE and RSSTP bits are cleared to 0 and the last received data is read. Note that if
SSRDR is read while the RE bit is set to 1, received clock is output again.
When the eighth clock rises while the RDRF bit is 1, the ORER bit in SSSR is set. Then an
overrun error (OEI) is generated and operation is stopped. When the ORER bit in SSSR is set to 1,
reception cannot be performed. Therefore confirm that the ORER bit is cleared to 0 before
reception.
The set timings of the RDRF and ORER flags differ according to the CPHS setting. These timings
are shown in figure 22.2. When the CPHS bit is set to 1, the flag is set during the frame. Therefore
care should be taken at the end of reception.
The sample flowchart for serial data reception is the same as that in clocked synchronous
communication mode.
Rev. 1.00 Oct. 03, 2008 Page 795 of 962
REJ09B0465-0100
Section 22 Synchronous Serial Communication Unit (SSU)
(1) When CPOS = 0 and CPHS = 0:
SCS
(output)
(High
impedance)
SSCK
SSI
Bit 7
Bit 0
Bit 7
One frame
Bit 0
Bit 7
Bit 0
One frame
RDRF
RSSTP
RXI generated
LSI operation
User
processing
Dummy read on SSRDR
RXI generated
Read data in SSRDR
Set RSSTP to 1
RXI generated
Read data in SSRDR
(2) When CPOS = 0 and CPHS = 1:
SCS
(output)
(High
impedance)
SSCK
SSI
Bit 7
Bit 0
One frame
Bit 7
Bit 0
Bit 7
Bit 0
One frame
RDRF
RSSTP
LSI operation
User
processing
RXI generated
Dummy read on SSRDR
RXI generated
Read data in SSRDR
Set RSSTP to 1
RXI generated
Read data in SSRDR
Figure 22.12 Example of Operation in Data Reception (MSS = 1)
Rev. 1.00 Oct. 03, 2008 Page 796 of 962
REJ09B0465-0100
Section 22 Synchronous Serial Communication Unit (SSU)
22.3.7
SCS Pin Control and Arbitration
When the SSUMS bit in SSMR2 is set to 1 and the CSS1 bit is set to 1, the MSS bit in SSCRH is
set to 1 and then the arbitration of the SCS pin is checked before starting serial transfer. If the SSU
detects that the synchronized internal SCS pin goes low in this period, the CE bit in SSSR is set
and the MSS bit in SSCRH is cleared.
Note: When a conflict error is set, subsequent transmit operation is not possible. Therefore the
CE bit must be cleared to 0 before starting transmission.
When the multimaster error is used, the CSOS bit in SSMR2 should be set to 1.
SCS input
Internal SCS
(synchronized)
MSS
Transfer start
Write data
in SSTDR
CE
SCS output
(Hi-Z)
Maximum time of SCS internal synchronization
Arbitration detection
period
Figure 22.13 Arbitration Check Timing
Rev. 1.00 Oct. 03, 2008 Page 797 of 962
REJ09B0465-0100
Section 22 Synchronous Serial Communication Unit (SSU)
22.4
Interrupt Requests
The SSU has five interrupt requests: transmit data empty, transmit end, receive data full, overrun
error, and conflict error. Since these interrupt requests are assigned to the common vector address,
interrupt sources must be determined by flags. Table 22.3 lists the interrupt requests.
Table 22.3 Interrupt Requests
Interrupt Request
Abbreviation
Interrupt Condition
DTC Activation
Possible
Transmit data empty
TXI
(TIE = 1), (TDRE = 1)
Transmit end
TEI
(TEIE = 1), (TEND = 1) Impossible
Receive data full
RXI
(RIE = 1), (RDRF = 1)
Possible
Overrun error
OEI
(RIE = 1), (ORER = 1)
Impossible
Conflict error
CEI
(CEIE = 1), (CE = 1)
Impossible
When an interrupt exception handling by an interrupt source shown in table 22.4 is executed, each
interrupt source must be cleared during the exception handling. Note that the TDRE and TEND
bits are automatically cleared by writing transmit data in SSTDR and the RDRF bit is
automatically cleared by reading SSRDR. When transmit data is written in SSTDR, the TDRE bit
is set again at the same time. Then if the TDRE bit is cleared, additional one byte of data may be
transmitted. The DTC can be activated by a TXI interrupt to transfer data. The TDRE flag is
automatically cleared upon data transfer by the DTC. The DTC can also be activated by an RXI
interrupt to transfer data. The RDRF flag is automatically cleared upon data transfer by the DTC.
Rev. 1.00 Oct. 03, 2008 Page 798 of 962
REJ09B0465-0100
Section 22 Synchronous Serial Communication Unit (SSU)
22.5
(1)
Usage Notes
If the NMOS open-drain output is selected for the SSCK output pin, the SSO output pin, and
the SCS output pin, use the PMC to allocate that pin from port 5. If the pins are allocated
from a port other than port 5, only the CMOS output is available.
Rev. 1.00 Oct. 03, 2008 Page 799 of 962
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Section 22 Synchronous Serial Communication Unit (SSU)
Rev. 1.00 Oct. 03, 2008 Page 800 of 962
REJ09B0465-0100
Section 23 Hardware LIN
Section 23 Hardware LIN
The hardware LIN works in cooperation with timer RA and SCI3_1 to provide LIN
communications.
23.1
Overview
• Master mode
Generates Sync Break.
Detects bus conflicts.
• Slave mode
Detects Sync Break.
Measures Sync Field.
Controls Sync Break and Sync Field signal inputs to SCI3_1.
Detects bus conflicts.
Figure 23.1 shows a block diagram of the hardware LIN interface.
Hardware LIN
Sync Field
controller
RXD pin
Timer RA
Timer RA
TIOSEL = 0
RXD data
LSTART bit
SBE bit
LINE bit
RXD input
controller
Timer RA
underflow signal
TIOSEL = 1
Timer RA
Timer RA
interrupt
Interrupt
controller
Bus conflict
detector
SCI3_1
BCIE, SBIE,
and SFIE bits
SCI3_1 transfer clock
SCI3_1 TE bit
Timer RA output pulse
MST bit
TXD pin
SCI3_1 TXD data
Figure 23.1 Block Diagram of Hardware LIN
Rev. 1.00 Oct. 03, 2008 Page 801 of 962
REJ09B0465-0100
Section 23 Hardware LIN
Table 23.1 shows the hardware LIN pins.
Table 23.1 Pin Configuration
Pin Symbol
I/O
Description
RXD
Input
Receive-data input to the hardware LIN
TXD
Output
Transmit-data output from the hardware LIN
23.2
Register Configuration
The hardware LIN interface has the following registers.
• LIN control register (LINCR)
• LIN status register (LINST)
23.2.1
LIN Control Register (LINCR)
Address: H'FF0518
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
LINE
MST
SBE
LSTART
RXDSF
BCIE
SBIE
SFIE
0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
7
LINE
LIN start
0: Enables LIN operation.
R/W
R/W
1
1: Disables LIN operation.*
6
5
MST
SBE
LIN operating
2
mode setting*
0: Slave mode (Enables the Sync Break detector.)
RXD input
mask
cancellation
timing select
(Valid only in slave mode)
Rev. 1.00 Oct. 03, 2008 Page 802 of 962
REJ09B0465-0100
R/W
1: Master mode (Takes the OR between timer RA
output and TXD data.)
0: Cancels the mask upon Sync Break detection.
1: Cancels the mask upon completion of Sync Field
measurement.
R/W
Section 23 Hardware LIN
Bit
Symbol
Bit Name
Description
R/W
4
LSTART
Sync Break
detection start
0: Don't care.
R/W
RXD input
status flag
0: Indicates that RXD input has been enabled.
3
RXDSF
1: Enables timer RA input and disables RXD input.
R
1: Indicates that RXD input has been disabled.
2
BCIE
Bus conflict
0: Disables a bus conflict detection interrupt.
detection
1: Enables a bus conflict detection interrupt.
interrupt enable
R/W
1
SBIE
Sync Break
0: Disables a Sync Break detection interrupt.
detection
1: Enables a Sync Break detection interrupt.
interrupt enable
R/W
0
SFIE
Sync Field
measurement
end interrupt
enable
R/W
Note:
0: Disables a Sync Field measurement end
interrupt.
1: Enables a Sync Field measurement end interrupt.
1. Immediately after setting this bit to 1, inputs to timer RA and SCI3_1 are prohibited.
2. Before switching the LIN operating modes, temporarily disable the LIN (LINE = 0).
3. After setting LSTART and then checking that the RXDSF flag is 1, start inputting Sync
Break.
Rev. 1.00 Oct. 03, 2008 Page 803 of 962
REJ09B0465-0100
Section 23 Hardware LIN
23.2.2
LIN Status Register (LINST)
Address: H'FF0519
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0


B2CLR
B1CLR
B0CLR
BCDCT
SBDCT
SFDCT
0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7, 6

Reserved
These bits are read as 0. The write value should
be 0.

5
B2CLR
BCDCT flag clear
The BCDCT flag is cleared when 1 is written to
this bit.
R/W
This bit is always read as 0.
4
B1CLR
SBDCT flag clear
The SBDCT flag is cleared when 1 is written to
this bit.
R/W
This bit is always read as 0.
3
B0CLR
SFDCT flag clear
The SFDCT flag is cleared when 1 is written to
this bit.
R/W
This bit is always read as 0.
2
1
0
BCDCT
SBDCT
SFDCT
Bus conflict
detection flag
0: No bus conflict is detected.
Sync Break
detection flag
0: Sync Bread is not detected.
Sync Field
measurement end
flag
0: Sync Field measurement is not ended.
Rev. 1.00 Oct. 03, 2008 Page 804 of 962
REJ09B0465-0100
R
1: Indicates that bus conflict has been detected.
R
1: Indicates that Sync Break has been detected.
1: Indicates that Sync Field measurement has
been ended.
R
Section 23 Hardware LIN
23.3
Operation
23.3.1
Master Mode
Figure 23.2 shows the example of hardware LIN interface operation for transmitting the header
field in master mode. Figures 23.3 and 23.4 show the flowcharts for header field transmission.
The hardware LIN interface operates as follows for header field transmission.
1. When 1 is written to the TSTART bit in TRACR register of timer RA, the hardware LIN keeps
outputting a low level from the TXD pin for the period specified by the TRAPRE and TRATR
registers of timer RA.
2. When timer RA underflows, the hardware LIN inverts the TXD pin output, thus setting the
SBDCT flag in the LINST register to 1. In this case, if the SBIE bit in the LINCR register is
set to 1, the timer RA/HW-LIN interrupt occurs.
3. The hardware LIN interface transmits H'55 using SCI3_1.
4. After completing H'55 transmission, the hardware LIN interface transmits the ID field using
SCI3_1.
5. After completing ID field transmission, the hardware LIN interface performs response field
communications.
Sync Break
Sync Field
IDENTIFIER
1
0
TXD pin
Write 1 to the B1CLR bit
in LINST.
SBDCT flag
in LINST
1
0
Timer RA/
HW-LIN interrupt
1
0
1.
2.
3.
4.
5.
Note: The following conditions are assumed:
LINE = 1, MST = 1, SBIE =1.
Figure 23.2 Example of LIN Operation for Transmitting Header Field
Rev. 1.00 Oct. 03, 2008 Page 805 of 962
REJ09B0465-0100
Section 23 Hardware LIN
Timer RA
Set to timer mode by setting the TMOD[2:0] bits in the TRAMR register to b'000.
Timer RA
Set the TEDGSEL bit in the TRAIOC register to 1 to set the initial timer pulse
output level to low.
Timer RA
Set the TRAIO pin to RXD by setting the TIOSEL bit in the TRAIOC register to 1.
Timer RA
Select the count source by setting the TCK[2:0] bits in the TRAMR register.
Timer RA
Set the Sync Break width by setting the TRAPRE and TRATR registers.
For the hardware LIN function,
set the TIOSEL bit in the TRAIOC
register to 1.
Set the count source,
TRAPRE register, and
TRATR register appropriately
for the Sync Break width.
Hardware LIN
Stop operation by setting the LINE bit in the LINCR register to 0.
Hardware LIN
Set to master mode by setting the MST bit in the LINCR register to 1.
Hardware LIN
Start operation by setting the LINE bit in the LINCR register to 1.
Hardware LIN
Clear the status flags (bus conflict detection, Sync Break detection, and
Sync Field measurement end) by setting the B2CLR, B1CLR, and B0CLR bits
in the LINST register to 0.
The Sync Field measurement
end interrupt cannot be used
in master mode.
Hardware LIN
Enable/disable the interrupts (bus conflict detection and Sync Break detection)
by setting the BCIE and SBIE bits in the LINCR register.
A
Figures 23.3 Header Field Transmission Flowchart (1)
Rev. 1.00 Oct. 03, 2008 Page 806 of 962
REJ09B0465-0100
Section 23 Hardware LIN
A
Timer RA
Start the timer counter by setting the TSTART bit in the
TRACR register to 1.
Timer RA
Read the count status flag (TCSTF) from the TRACR register.
TCSTF = 1?
Generate Sync Break by timer RA.
After writing 1 to the TSTART bit,
reading 1 from the TCSTF flag can
be omitted if neither TRAPRE register
nor TRATR register of timer RA is
read or modified.
No
Yes
Hardware LIN
Read the Sync Break detection flag (SBDCT) from the LINST
register.
SBDCT = 1?
The timer RA interrupt can be used
upon completion of Sync Break
generation.
No
Yes
Timer RA
Read the Sync Break detection flag (SBDCT) from the LINST
register.
Timer RA
Stop the timer counter by setting the TSTART bit in the
TRACR register to 0.
TC STF = 0?
No
After generating timer RA Sync Break,
stop the timer counter.
After writing 0 to the TSTART bit,
reading 0 from the TCSTF flag can
be omitted if neither TRAPRE register
nor TRATR register of timer RA is
read or modified.
Yes
SCI3_1
Initialize SCI3_1 and set asynchronous mode, transmission,
and clock source by setting the SCR3, SMR, and BRR
registers.
Initialize SCI3 following the initialization
procedure and set the appropriate clock
source for Sync Field transmission.
SCI3_1
Perform communications using SCI3_1.
Read 1 from the TDRE bit in the SSR register.
Transfer H'55 to TDR register.
Transmit the Sync Field.
SCI3_1
Perform communications using SCI3_1.
Transfer the ID field to TDR register.
Transmit the ID field.
Figures 23.4 Header Field Transmission Flowchart (2)
Rev. 1.00 Oct. 03, 2008 Page 807 of 962
REJ09B0465-0100
Section 23 Hardware LIN
23.3.2
Slave Mode
Figure 23.5 shows the example of hardware LIN interface operation for receiving the header field
in slave mode. Figures 23.6 to 23.8 show the flowcharts for header field reception.
The hardware LIN interface operates as follows for header field reception.
1. When 1 is written to the LSTART bit in LINCR register of the hardware LIN interface, Sync
Break detection is enabled.
2. When a low level input is longer than the time set in timer RA, it is detected as Sync Break,
thus setting the SBDCT flag in the LINST register to 1. In this case, if the SBIE bit in the
LINCR register is set to 1, the timer RA/HW-LIN interrupt occurs. The hardware LIN
interface then measures the Sync Field.
3. The hardware LIN interface receives the Sync Field (H'55). During reception, the hardware
LIN interface measures the time from the start bit through bit 6. Here, the Sync Field input to
the SCI3 RXD can be either enabled or disabled depending on the SBE bit setting in the
LINCR register.
4. Completion of Sync Field measurement sets the SFDCT flag in the LINST register to 1. In this
case, if the SFIE bit in the LINCR register is 1, the timer RA/HW-LIN interrupt occurs.
5. After completing Sync Field measurement, the hardware LIN interface calculates the transfer
rate from the timer RA count value and sets the rate in SCI3_1, and also updates the TRAPRE
and TRATR registers in timer RA. Then the hardware LIN interface receives the ID field using
SCI3_1.
6. After completing ID field reception, the hardware LIN interface performs response field
communications.
Rev. 1.00 Oct. 03, 2008 Page 808 of 962
REJ09B0465-0100
Section 23 Hardware LIN
Sync Break
RXD pin
"1"
"0"
RXD input
to SCI3_1
"1"
"0"
RXDSF flag
in LINCR
Sync Field
IDENTIFIER
Write 1 to the
LSTART bit in LINCR.
Automatically cleared to 0
after Sync Field
measurement.
"1"
"0"
Write 1 to the
B1CLR bit in LINST.
SBDCT flag
in LINST
"1"
"0"
Measure this period.
SFDCT flag
in LINST
Write 1 to the B0CLR bit
in LINST.
"1"
"0"
Timer RA/
"1"
HW-LIN interrupt "0"
1.
2.
3.
4.
5.
6.
Note: The following conditions are assumed:
LINE = 1, MST = 0, SBE = 1, SBIE =1, SFIE = 1.
Figure 23.5 Example of LIN Operation for Receiving Header Field
Rev. 1.00 Oct. 03, 2008 Page 809 of 962
REJ09B0465-0100
Section 23 Hardware LIN
Timer RA
Set to pulse width measurement mode by setting the TMOD[2:0] bits in the
TRAMR register to b'011.
Timer RA
Set the TEDGSEL bit in the TRAIOC register to 0 to measure the low level width
of pulses.
Timer RA
Set the TRAIO pin to RXD by setting the TIOSEL bit in the TRAIOC register to 1.
For the hardware LIN function,
set the TIOSEL bit in the TRAIOC
register to 1.
Timer RA
Select the count source by setting the TCK[2:0] bits in the TRAMR register.
Timer RA
Set the Sync Break width by setting the TRAPRE and TRATR registers.
Set the count source, TRAPRE
register, and TRATR register
appropriately for the Sync Break
width.
Hardware LIN
Stop operation by setting the LINE bit in LINCR register to 0.
Hardware LIN
Set to slave mode by setting the MST bit in LINCR register to 0.
Hardware LIN
Start operation by setting the LINE bit in the LINCR register to 1.
Hardware LIN
Select the RXD input mask cancellation timing (upon Sync Break detection or
completion of Sync Field measurement) by setting the SBE bit in the LINCR
register.
Select the mask cancellation
timing of the RXD input to SCI3_1.
When a timing is selected such
that the mask is cancelled upon
Sync Break detection, the Sync Field
signal is also input to SCI3_1.
Hardware LIN
Clear the status flags (bus conflict detection, Sync Break detection, and Sync
Field measurement end) by setting the B2CLR, B1CLR, and B0CLR bits in the
LINST register to 1.
A
Figures 23.6 Header Field Reception Flowchart (1)
Rev. 1.00 Oct. 03, 2008 Page 810 of 962
REJ09B0465-0100
Section 23 Hardware LIN
A
Hardware LIN
Enable/disable the interrupts (bus conflict detection,
Sync Break detection, and Sync Field measurement
end) by setting the BCIE, SBIE, and SFIE bits in the
LINCR register.
Timer RA
Start pulse width measurement by setting the TSTART
bit in the TRACR register to 1.
Wait until timer RA starts counting.
Timer RA
Read the count status flag (TCSTF) from the TRACR
register.
TCSTF = 1?
No
Yes
Hardware LIN
Start Sync Break detection by setting the LSTART bit in the
LINCR register to 1.
Hardware LIN
Read the RXD input status flag (RXDSF) from the LINCR
register.
RXDSF = 1?
No
Wait until the RXD input to SCI3_1 is
masked by the hardware LIN.
After writing 1 to the LSTART bit,
do not input a low level to the RXD
pin until 1 is read from the RXDSF flag;
during this period, the low level input is
directly input to the SCI3_1. After 1 is
read from the RXDSF flag, input to
timer RA and SCI3_1 is possible.
Yes
Hardware LIN
Read the Sync Break detection flag (SBDCT) from the
LINST register.
SBDCT = 1?
Yes
B
No
Detect the hardware LIN Sync Break.
The timer RA interrupt can be used.
When Sync Break is detected, the timer
RA counter is reloaded with the initially
set value.
If the low level input is shorter than the
specified time, the timer RA counter is
also reloaded with the initially set value
and waits for another low level input.
When the SBE bit in the LINCR register
is 0 (the input mask is cancelled upon
Sync Break detection), timer RA can be
used in timer mode after the SBDCT flag
in the LINST register becomes 1.
Figure 23.7 Header Field Reception Flowchart (2)
Rev. 1.00 Oct. 03, 2008 Page 811 of 962
REJ09B0465-0100
Section 23 Hardware LIN
B
Yes
Hardware LIN
Read the Sync Field measurement end flag (SFDCT) from
the LINST register.
SFDCT = 1?
No
Calculate the hardware LIN Sync Field.
The timer RA/HW-LIN interrupt can be used.
(When the timer RA counter underflows,
the SBDCT flag is set).
When the SBE bit in the LINCR register is 1
(the input mask is cancelled upon completion
of Sync Break measurement), timer RA can be
used in timer mode after the SFDCT flag in the
LINST register becomes 1.
Yes
SCI3_1
Set the SCI3_1 transfer rate by setting the BRR register.
Timer RA
Update the Sync Break width by setting the TRAPRE and
TRATR registers.
SCI3_1
Perform communications using SCI3_1.
Receive the ID field in clock asynchronous serial interface
(UART) mode.
Set the appropriate transfer rate according
to the Sync Field measurement results.
Perform communications using SCI3_1
(when the timer RA counter underflows,
the SBDCT flag is set).
Figure 23.8 Header Field Reception Flowchart (3)
Rev. 1.00 Oct. 03, 2008 Page 812 of 962
REJ09B0465-0100
Section 23 Hardware LIN
23.3.3
Bus Conflict Detection Function
The hardware LIN interface can detect bus conflicts if SCI3_1 is enabled for transmission (TE bit
in SCR3_1 register is 1).
Figure 23.9 shows the example of hardware LIN interface operation for detecting bus conflicts.
TXD pin
"1"
"0"
RXD pin
"1"
"0"
Transfer clock
"1"
"0"
LINE bit
in LINCR
"1"
"0"
Set to 1 through programming.
Set to 1 through programming.
TE bit in
"1"
SCR3_1 register "0"
Write 1 to the
B2CLR bit in LINST.
BCDCT flag
in LINST
"1"
"0"
Timer RA/
"1"
HW-LIN
"0"
interrupt TRAIF
Figure 23.9 Example of LIN Operation for Detecting Bus Conflicts
Rev. 1.00 Oct. 03, 2008 Page 813 of 962
REJ09B0465-0100
Section 23 Hardware LIN
23.3.4
Terminating Hardware LIN
Figure 23.10 shows the flowchart for terminating hardware LIN communications. The hardware
LIN interface should be terminated at the following timing.
• Case 1: When the bus conflict detection function is used
After checksum field transmission
• Case 2: When the bus conflict detection function is not used
After header field transmission/reception
Timer RA
Stop the timer counter by setting the TSTART bit in the TRACR
register to 0.
Timer RA
Read the count status flag (TCSTF) from the TRACR register.
TCSTF = 0?
Stop the timer counter.
No
Yes
SCI3_1
Terminate SCI3_1 communications.
Hardware LIN
Clear the status flags (bus conflict detection, Sync Break
detection, and Sync Field measurement end) by setting the
B2CLR, B1CLR, and B0CLR bits in the LINST register to 1.
When the bus conflict detection
function is not used, SCI3_1
transmission does not need to
be terminated.
Before stopping the hardware LIN,
clear the status flags of the
hardware LIN.
Hardware LIN
Stop operation by setting the LINE bit in LINCR register to 0.
Figure 23.10 Flowchart for Terminating Hardware LIN Communications
Rev. 1.00 Oct. 03, 2008 Page 814 of 962
REJ09B0465-0100
Section 23 Hardware LIN
23.4
Interrupt Requests
The hardware LIN interface can request four types of interrupts: Sync Break detection, Sync
Break generation end, Sync Field measurement end, and bus conflict detection. All these
interrupts are requested as the timer RA interrupt. Table 23.2 describes these interrupt requests.
Table 23.2 Interrupt Requests by Hardware LIN
Interrupt Request
Status Flag
Interrupt Source
Sync Break detection
SBDCT
•
The low-level period of the RXD input is
measured using timer RA and the counter
underflows
•
The low-level period of the RXD input is
longer than the Sync Break period during
communications.
Sync Break generation end
The low level has been output via TXD for the
period specified by timer RA.
Sync Field measurement end
SFDCT
Measuring the 8-bit Sync Field period has been
completed using timer RA.
Bus conflict detection
BCDCT
The RXD input and TXD output values differ
from each other when data is latched while
SCI3_1 is enabled for transmission.
23.5
Usage Note
For processing the header and response field timeout, measure the time from the Sync Break
detection interrupt using another timer.
Rev. 1.00 Oct. 03, 2008 Page 815 of 962
REJ09B0465-0100
Section 23 Hardware LIN
Rev. 1.00 Oct. 03, 2008 Page 816 of 962
REJ09B0465-0100
Section 24 A/D Converter
Section 24 A/D Converter
This LSI includes a successive approximation type 10-bit A/D converter (one unit or two units)
that allows up to sixteen analog input channels to be selected. Figures 24.1 and 24.2 show the
block diagrams of A/D converters unit 1 and unit 2, respectively.
The differences between unit 1 and unit 2 are the number of analog input channels and the number
of data registers. The other functions of units 1 and 2 are the same.
24.1
Features
• 10-bit resolution
• Input channels
 Unit 1: 12 channels for the H8S/20223 and H8S/20203 groups and 8 channels for the
H8S/20103 group
 Unit 2: 4 channels for the H8S/20223 group
• Conversion time: 2 µs per channel (at 20 MHz operation)
• Operating modes: Two
 A/D conversion mode: A selected analog input is A/D converted
 Compare mode: A selected analog input is compared with the voltage specified by the user
• Channel select modes
 Single mode: Single-channel A/D conversion or comparison
 Scan mode: Continuous A/D conversion on 1 to 4 channels, or 1 to 8 channels
• Data registers: 8 data registers for unit 1 and 4 data registers for unit 2
 Conversion results are held in a 16-bit data register for each channel
• Sample and hold function
• Three kinds of conversion start
 Conversion can be started by software, conversion start trigger by 16-bit timer (timer RC or
RD), or external trigger signal.
• Interrupt request
 A/D conversion end interrupt (ADI) request can be generated
 Compare result change interrupt (CMPI) request can be generated
• Module standby function can be set
Rev. 1.00 Oct. 03, 2008 Page 817 of 962
REJ09B0465-0100
Section 24 A/D Converter
Internal data bus
Bus interface
ADCR
ADMR
ADCSR
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3/CMPVALL
ADDR2/CMPVALH
AVss
ADDR0/CMPR
10-bit D/A
ADDR1/CMPCSR
AVcc
Successive approximations
register
Module data bus
+
Comparator
Multiplexer
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
Control circuit
Sample-and-hold circuit
CMPI interrupt signal
AAZB
ADI interrupt signal
Conversion start trigger from timer RC or RD
ADTRG1
Figure 24.1 Block Diagram of A/D Converter (Unit 1)
Rev. 1.00 Oct. 03, 2008 Page 818 of 962
REJ09B0465-0100
Section 24 A/D Converter
Internal data bus
Bus interface
ADCR_2
ADCSR_2
ADMR_2
ADDR3_2/CMPVALL_2
ADDR2_2/CMPVALH_2
AVss
ADDR1_2/CMPCSR_2
10-bit D/A
ADDR0_2/CMPR_2
AVcc
Successive aproximations
register
Module data bus
AN0_2
AN1_2
AN2_2
AN3_2
Multiplexer
+
Comparator
Control circuit
Sample-and-hold circuit
CMPI interrupt signal
AD interrupt signal
Conversion start trigger from timer RC or RD
ADTRG2
Figure 24.2 Block Diagram of A/D Converter (Unit 2)
Rev. 1.00 Oct. 03, 2008 Page 819 of 962
REJ09B0465-0100
Section 24 A/D Converter
Table 24.1 shows the pin configuration of the A/D converter.
The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter.
Unit 1 has 12 analog input pins; unit 2 has four analog input pins. Note that the actual number of
analog inputs in units 1 and 2 depends on the product group.
Table 24.1 Pin Configuration
Unit
Pin Name
I/O
Function
Common
AVCC
Input
Analog block power supply
AVSS
Input
Analog block ground
AN0
Input
Unit 1 group 0 analog inputs
AN1
Input
AN2
Input
AN3
Input
AN4
Input
AN5
Input
AN6
Input
AN7
Input
AN8
Input
AN9
Input
AN10
Input
AN11
Input
ADTRG1
Input
External trigger input 1 for starting A/D conversion
AN0_2
Input
Unit 2 group 0 analog inputs*2
AN1_2
Input
AN2_2
Input
AN3_2
Input
ADTRG2
Input
Unit 1
Unit 2
Unit 1 group 1 analog inputs
Unit 1 group 2 analog inputs*1
External trigger input 2 for starting A/D conversion
Notes: 1. Not supported in the H8S/20103 and H8S/20203 groups.
2. Supported only in the H8S/20223 group.
Rev. 1.00 Oct. 03, 2008 Page 820 of 962
REJ09B0465-0100
Section 24 A/D Converter
24.2
Register Description
The A/D converter has the following registers.
Unit 1:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
A/D data register 0 (ADDR0)
A/D data register 1 (ADDR1)
A/D data register 2 (ADDR2)
A/D data register 3 (ADDR3)
A/D data register 4 (ADDR4)
A/D data register 5 (ADDR5)
A/D data register 6 (ADDR6)
A/D data register 7 (ADDR7)
A/D control/status register (ADCSR)
A/D control register (ADCR)
A/D mode register (ADMR)
Compare data register (CMPR)
Compare control status register (CMPCSR)
Compare voltage register H (CMPVALH)
Compare voltage register L (CMPVALL)
Unit 2:
•
•
•
•
•
•
•
•
•
•
•
A/D data register 0_2 (ADDR0_2)
A/D data register 1_2 (ADDR1_2)
A/D data register 2_2 (ADDR2_2)
A/D data register 3_2 (ADDR3_2)
A/D control/status register_2 (ADCSR_2)
A/D control register_2 (ADCR_2)
A/D mode register_2 (ADMR_2)
Compare data register_2 (CMPR_2)
Compare control status register_2 (CMPCSR_2)
Compare voltage register H_2 (CMPVALH_2)
Compare voltage register L_2 (CMPVALL_2)
Rev. 1.00 Oct. 03, 2008 Page 821 of 962
REJ09B0465-0100
Section 24 A/D Converter
24.2.1
A/D Data Registers 0 to 7 (ADDR0 to ADDR7)
Address: H'FF05E0 to H'FF05EE, H'FF0600 to H'FF0606
Bit:
Value after reset:
b15
0
b14
0
b13
0
b12
0
b11
0
b10
0
b9
0
b8
0
b7
0
b6
0
b5
b4
b3
b2
b1
b0
−
−
−
−
−
−
0
0
0
0
0
0
ADDR registers are 16-bit read-only registers which are used to store the results of A/D
conversion. Unit 1 incorporates eight registers ADDR0 to ADDR7. Unit 2 incorporates four
registers ADDR0_2 to ADDR3_2. The ADDR registers, which store a conversion result for each
channel, are shown in table 24.2.
The converted 10-bit data is stored to bits 15 to 6. The lower 6-bit data is always read as 0.
The data bus between the CPU and the A/D converter is 16-bit width. Data can be accessed in 16
bits at one time or 8 bits at two times.
Table 24.2 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel
Channel Set 0 (CH3 = 0)
Channel Set 1 (CH3 = 1)
A/D Data Register which
Stores Conversion Result
AN0
AN8
ADDR0
AN1
AN9
ADDR1
AN2
AN10
ADDR2
AN3
AN11
ADDR3
AN4

ADDR4
AN5

ADDR5
AN6

ADDR6
AN7

ADDR7
Rev. 1.00 Oct. 03, 2008 Page 822 of 962
REJ09B0465-0100
Section 24 A/D Converter
24.2.2
A/D Control/Status Register (ADCSR)
Address: H'FF05F0, H'FF0610
Bit:
Value after reset:
b7
b6
b5
b4
ADF
ADIE
ADST

0
0
0
0
b3
b2
b1
b0
0
0
CH[3:0]
0
0
Bit
Symbol
Bit Name
Description
R/W
7
ADF
A/D end flag
0: A/D conversion or comparison is in progress.
R/W*
1: A/D conversion or comparison has been
completed.
[Setting conditions]
•
When A/D conversion ends in single mode
•
When A/D conversion ends on all specified
channels in scan mode
[Clearing conditions]
6
5
ADIE
ADST
•
When 0 is written after reading ADF = 1
•
When the DTC is activated by an ADI interrupt
and ADDR is read
A/D interrupt
enable
0: Disables an ADF interrupt.
A/D start
0: Stops A/D conversion and places the A/D
converter in the wait state.
R/W
1: Enables an ADF interrupt.
R/W
1: Starts A/D conversion.
4

3 to 0 CH[3:0]
Reserved bit
This bit is read as 0. The write value should be 0.
Channel select When SCANE = 0 and SCANS = ×
3 to 0
0000: AN0
0111: AN7

R/W
0001: AN1
1000: AN8
0010: AN2
1001: AN9
0011: AN3
1010: AN10
0100: AN4
1011: AN11
0101: AN5
11xx: Setting prohibited
0110: AN6
Rev. 1.00 Oct. 03, 2008 Page 823 of 962
REJ09B0465-0100
Section 24 A/D Converter
Bit
Symbol
3 to 0 CH[3:0]
Bit Name
Description
R/W
Channel select When SCANE = 1 and SCANS = 0
3 to 0
0000: AN0
0111: AN4 to AN7
0001: AN0 and AN1
R/W
1000: AN8
0010: AN0 to AN2
1001: AN8 and AN9
0011: AN0 to AN3
1010: AN8 to AN10
0100: AN4
1011: AN8 to AN11
0101: AN4 and AN5
11xx: Setting prohibited
0110: AN4 to AN6
When SCANE = 1 and SCANS = 1
0000: AN0
0111: AN0 to AN7
0001: AN0 and AN1
1000: AN8
0010: AN0 to AN2
1001: AN8 and AN9
0011: AN0 to AN3
1010: AN8 to AN10
0100: AN0 to AN4
1011: AN8 to AN11
0101: AN0 to AN5
11xx: Setting prohibited
0110: AN0 to AN6
[Legend]
×:
Don't care.
Notes: * Only 0 can be written in bit 7, to clear the flag.
1. The A/D converter should be stopped (ADST = 0) while the Input channels are being
selected.
2. In unit 2, channels can be selected from four channels AN0_2 to AN3_2. Accordingly,
the CH3 and CH2 bits should be cleared to 0 in unit 2.
• ADST bit (A/D start)
Clearing this bit to 0 stops A/D conversion, and the A/D converter enters wait state. When this
bit is set to 1 by software, timer RC, timer RD (conversion start trigger), or the ADTRG pin,
A/D conversion starts. This bit remains set to 1 during A/D conversion. In single mode, this bit
is cleared to 0 automatically when conversion on the specified channel ends. In scan mode,
conversion continues sequentially on the specified channels until this bit is cleared to 0 by a
reset, a transition to standby mode or software. ADST is cleared to 0 if A/D conversion of all
the selected channels has been completed while the ADSTCLR bit is 1.
The event link function can be used to set the ADST bit. When the event specified in ELSR10
or ELS11 of the ELC occurs, the corresponding ADST bits (in A/D converter unit 1 or A/D
converter unit 2, respectively) are set and the A/D conversion starts.
Rev. 1.00 Oct. 03, 2008 Page 824 of 962
REJ09B0465-0100
Section 24 A/D Converter
24.2.3
A/D Control Register (ADCR)
Address: H'FF05F0, H'FF0611
Bit:
b7
b6
TRGS[1:0]
Value after reset:
0
0
b5
b4
SCANE
SCANS
0
0
b3
1
b1
b0
ADSTCLR
EXTRGS
0
0
b2
CKS[1:0]
0
Bit
Symbol
Bit Name
Description
R/W
7, 6
TRGS[1:0]
Trigger select 1 b0 b7 b6
and 0
0 0 0: A/D conversion start by external trigger is
disabled.
R/W
0 0 1: A/D conversion start by external trigger pin
1 (ADTRG1) is enabled.
0 1 0: A/D conversion start by external trigger pin
1
2 (ADTRG2) is enabled.*
0 1 1: A/D conversion start by external trigger
2
(timer RC) is enabled.*
1 0 0: A/D conversion start by external trigger
(timer RD_0) is enabled.
1 0 1: A/D conversion start by external trigger
(timer RD_1) is enabled.*3
1 1 x: Reserved (setting prohibited)
5
SCANE
4
SCANS
Channel
0×: Single mode
selection mode 10: Scan mode (A/D conversion is performed
continuously for channels 1 to 4)
R/W
11: Scan mode (A/D conversion is performed
continuously for channels 1 to 8.)
3, 2
CKS[1:0]*4
Clock select 1
to 0
00: Setting prohibited
R/W
01: Setting prohibited
10: A/D conversion time = 84 states (max) (initial
value)
11: A/D conversion time = 43 states (max)
1
ADSTCLR
ADST clear
If ADSTCLR is set to 1 in scan mode, the ADST bit R/W
is automatically cleared to 0 when A/D conversion of
all the selected channels has been completed.
0
EXTRGS
External trigger EXTRGS combined with the TRGS1 and TRGS0
select
bits selects a trigger signal. For details, see the
above description for the TRGS1 and TRGS0 bits.
R/W
Rev. 1.00 Oct. 03, 2008 Page 825 of 962
REJ09B0465-0100
Section 24 A/D Converter
[Legend]
×:
Don't care.
Note: 1. Selected only for the H8S/20223 group.
2. Selected only for the H8S/20103 group.
3. Not selected only for the H8S/20103 group.
4. Select these bits to fall the conversion time within the specified time.
• TRGS[1:0] bits (trigger select 1 and 0)
These bits combined with the EXTRGS bit select enable or disable the A/D conversion start by
a trigger signal.
• CKS[1:0] bits (clock select 1 to 0)
These bits the A/D conversion time.
The conversion time should be set while the A/D conversion is stopped (ADST = 0).
Rev. 1.00 Oct. 03, 2008 Page 826 of 962
REJ09B0465-0100
Section 24 A/D Converter
24.2.4
A/D Mode Register (ADMR)
Address: H'FF05F4, H'FF0614
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0


ADM1





0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7, 6

Reserved
These bits are read as 0. The write value should
be 0.

5
ADM1
A/D converter
operating mode
selection
0: A/D conversion mode
R/W
All 0
These bits are read as 0. The write value should
be 0.
4 to 0 
1: Compare mode

Note: The A/D converter operating mode should be changed while the ADST bit in ADCSR is 0.
• ADM1 bit (A/D conversion mode selection)
If the A/D converter operating mode changes from conversion mode to compare mode, CMPR,
CMPCSR, and CMPVAL are initialized to H'00.
Rev. 1.00 Oct. 03, 2008 Page 827 of 962
REJ09B0465-0100
Section 24 A/D Converter
24.2.5
Compare Data Register (CMPR)
Address: H'FF05E0, H'FF0600
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
CMP7
CMP6
CMP5
CMP4
CMP3
CMP2
CMP1
CMP0
0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
CMP7
Compare data
7
[Setting condition]
R
6
CMP6
Compare data
6
When the voltage of the selected analog input
channel is greater than the voltage set in the
CMPVAL register in compare mode.
R
5
CMP5
Compare data
5
[Clearing conditions]
R
4
CMP4
Compare data
4
3
CMP3
Compare data
3
2
CMP2
Compare data
2
1
CMP1
Compare data
1
0
CMP0
Compare data
0
•
When the A/D converter operating mode is
changed from A/D conversion mode to compare R
mode according to the ADM bit in ADMR
R
setting.
•
When the voltage of the selected analog input
channel is equal to or lower than the voltage set R
in the CMPVAL register in compare mode.
R
R
[Legend]
×:
Don't care.
Note: * Only 0 can be written to clear the flag.
CMPR holds the comparison result. CMPR is a read-only register that is assigned to the same
address as ADDR0 and ADDR0_2. CMPR is valid in compare mode.
Rev. 1.00 Oct. 03, 2008 Page 828 of 962
REJ09B0465-0100
Section 24 A/D Converter
CMP bits and the corresponding analog input channels are shown in table 24.3.
Table 24.3 Relationship between CMP Bits and Corresponding Analog Input Channels
Unit
Unit 1
Unit 2
Channel
Corresponding
Compare Data Bit
AN0
AN8
CMP0
AN1
AN9
CMP1
AN2
AN10
CMP2
AN3
AN11
CMP3
AN4

CMP4
AN5

CMP5
AN6

CMP6
AN7

CMP7
AN0_2

CMP0
AN1_2

CMP1
AN2_2

CMP2
AN3_2

CMP3
Rev. 1.00 Oct. 03, 2008 Page 829 of 962
REJ09B0465-0100
Section 24 A/D Converter
24.2.6
Compare Control Status Register (CMPCSR)
Address: H'FF05E2, H'FF0602
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
CMPF
CMPIE
CMPFC1
CMPFC0




0
0
0
0
0
0
0
0
Bit
Symbol
Bit Name
Description
R/W
7
CMPF
CMPI interrupt
status
[Setting condition]
R/W
If the condition specified by the CMPFC1 or CMPFC0
bit is satisfied when comparison has been completed.
[Clearing conditions]
6
CMPIE
CMPI interrupt
enable
•
When the A/D converter operating mode is
changed from A/D conversion mode to compare
mode according to the ADM bit in ADMR setting.
•
When 0 is written to this bit after this bit is read as
1.
•
When the DTC is activated by a CMPI interrupt
and the DISEL bit in MRB of the DTC is 0.
•
When this LSI enters standby mode or module
standby mode.
0: Disables a compare match interrupt (CMPI).
1: Enables a compare match interrupt (CMPI).
Rev. 1.00 Oct. 03, 2008 Page 830 of 962
REJ09B0465-0100
R/W
Section 24 A/D Converter
Bit
Symbol
Bit Name
Description
R/W
5
CMPFC1
CMPI interrupt
condition 1
0: Does not generate an interrupt by a comparison
result change.
R/W
1:
In single compare mode:
Sets the CMPF bit to 1 if the comparison result of
the selected channel changes from 0 to 1.
In scan compare mode:
Sets the CMPF bit to 1 if the comparison result of
any of the selected channels changes from 0 to 1.
4
CMPFC0
CMPI interrupt
condition 0
0: Does not generate an interrupt by a comparison
result change.
R/W
1:
In single compare mode:
Sets the CMPF bit to 1 if the comparison result of
the selected channel changes from 0 to 1.
In scan compare mode:
Sets the CMPF bit to 1 if the comparison result of
any of the selected channels changes from 0 to 1.
3 to 0 
Reserved
These bits are read as 0. The write value should be 0. 
Rev. 1.00 Oct. 03, 2008 Page 831 of 962
REJ09B0465-0100
Section 24 A/D Converter
24.2.7
Compare Analog Level Registers H and L (CMPVALH and CMPVALL)
CMPVALH
Address: H'FF05E4, H'FF0604
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0






VAL9
VAL8
0
0
0
0
0
0
0
0
CMPVALL
Address: H'FF05E6, H'FF0606
Bit:
Value after reset:
b7
b6
b5
b4
b3
b2
b1
b0
VAL7
VAL6
VAL5
VAL4
VAL3
VAL2
VAL1
VAL0
0
0
0
0
0
0
0
0
• CMPVALH
Bit
Symbol
Bit Name
Description
R/W
7 to 2 
Reserved
This bit is read as 0. The write value should be 0.

1
VAL9

These bits set the compare voltage VAL[9:8].
R/W
0
VAL8

R/W
• CMPVALL
Bit
Symbol
Bit Name
Description
R/W
7
VAL7

These bits set the compare voltage VAL[7:0].
R/W
6
VAL6

R/W
5
VAL5

R/W
4
VAL4

R/W
3
VAL3

R/W
2
VAL2

R/W
1
VAL1

R/W
0
VAL0

R/W
Rev. 1.00 Oct. 03, 2008 Page 832 of 962
REJ09B0465-0100
Section 24 A/D Converter
CMPVALL and the lower 2 bits of CMPVALH specify the voltage to be compared.
CMPVALH and CMPVALL are assigned to the same addresses as ADDR2 (ADDR2_2) and
ADDR3 (ADDR3_2), respectively. CMPVALH and CMPVALL become valid in compare mode.
Table 24.4 shows the correspondence between VAL[9:0] setting and the voltage to be compared.
Table 24.4 VAL[9:0] Setting and Corresponding Voltage to be Compared
VAL[9:0] Setting
Voltage to be Compared
B'0000000000
AVss
B'0000000001
AVcc × 1/1024
B'0000000010
AVcc × 2/1024
:
:
B'111111100
AVcc × 1020/1024
B'111111101
AVcc × 1021/1024
B'111111110
AVcc × 1022/1024
B'111111111
AVcc × 1023/1024
Rev. 1.00 Oct. 03, 2008 Page 833 of 962
REJ09B0465-0100
Section 24 A/D Converter
24.3
Operation
The A/D converter operates in two operating modes as shown in table 24.5. In A/D conversion
mode, the A/D converter converts the analog input of the selected channel by successive
approximation with 10-bit resolution. In compare mode, the analog input of the selected channel is
compared with the voltage to be specified.
Each operating mode has two operating modes: single mode and scan mode. When changing the
analog input channel, to prevent incorrect operation, first clear the ADST bit in ADCSR to 0. The
ADST bit can be set at the same time as the operating mode or analog input channel is changed.
Table 24.5 A/D Converter Operating Mode
Operating Mode
Channel Selection Mode
Register Setting
A/D conversion mode
Single mode
ADM1 = 0, SCANE = 0
Scan mode
ADM1 = 0, SCANE = 1
Single mode
ADM1 = 1, SCANE = 0
Scan mode
ADM1 = 1, SCANE = 1
Compare mode
Rev. 1.00 Oct. 03, 2008 Page 834 of 962
REJ09B0465-0100
Section 24 A/D Converter
24.4
A/D Conversion Mode Operation
24.4.1
Single Mode in A/D Conversion Mode
In single mode in A/D conversion mode, A/D conversion is to be performed only once on the
specified single channel. Operations are as follows.
1. A/D conversion is started when the ADST bit in ADCSR is set to 1, according to the software
or external trigger input.
2. When A/D conversion is completed, the result is transferred to the A/D data register
corresponding to the channel.
3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at
this time, an ADI interrupt request is generated.
4. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when
conversion ends. When the ADST bit is cleared to 0 during A/D conversion, A/D conversion
stops and the A/D converter enters wait state.
Rev. 1.00 Oct. 03, 2008 Page 835 of 962
REJ09B0465-0100
Section 24 A/D Converter
Set*
ADIE
ADST
A/D conversion
start
Set*
Set*
Clear*
Clear*
ADF
Channel 0 (AN0)
operating status
Wait for A/D conversion
Channel 1 (AN1)
operating status
Wait for A/D conversion A/D conversion 1
Channel 2 (AN2)
operating status
Wait for A/D conversion
Channel 3 (AN3)
operating status
Wait for A/D conversion
Wait for A/D conversion
A/D conversion 2
Wait for A/D conversion
ADDR0
ADDR1
Conversion result read
A/D conversion result 1
Conversion result read
A/D conversion result 2
ADDR2
ADDR3
Note: * At , an instruction is executed by software.
Figure 24.3 A/D Converter Operation in A/D Conversion Mode
(When Channel 1 Is Selected in Single Mode)
Rev. 1.00 Oct. 03, 2008 Page 836 of 962
REJ09B0465-0100
Section 24 A/D Converter
24.4.2
Scan Mode in A/D Conversion Mode
In scan mode in A/D conversion mode, A/D conversion is to be performed sequentially on the
specified channels: maximum four channels or maximum eight channels. Operations are as
follows.
1. When the ADST bit in ADCSR is set to 1 by a software, timer RC, timer RD or external
trigger input, A/D conversion starts on the first channel of the channel set.
The consecutive A/D conversion on maximum four channels (SCANE = 1 and SCANS = 0) or
on maximum eight channels (SCANE = 1 and SCANS = 1) can be selected. When the
consecutive A/D conversion is performed on the four channels, the A/D conversion starts on
AN0 when CH3 = 0 and CH2 =0, AN4 when CH3 = 0 and CH2 = 1, or AN8 when CH3 = 1
and CH2 = 0. When the consecutive A/D conversion is performed on the eight channels, the
A/D conversion starts on AN0 when CH3 = 0 and CH2 = 0.
2. When A/D conversion for each channel is completed, the result is sequentially transferred to
the A/D data register corresponding to each channel.
3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1.
If the ADIE bit is set to 1 at this time, an ADI interrupt is requested. The A/D conversion starts
again from the first channel of the channel set again.
4. The ADST bit is not cleared automatically, and steps [2] to [3] are repeated as long as the
ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the
A/D converter enters wait state. If the ADST bit is later set to 1, A/D conversion starts again
from the first channel of the channel set.
Rev. 1.00 Oct. 03, 2008 Page 837 of 962
REJ09B0465-0100
Section 24 A/D Converter
A/D conversion is performed sequentially.
Clear*1
Set*1
ADST
Clear*1
ADF
A/D conversion time
Channel 0 (AN0)
operating status
Wait for A/D conversion
Channel 1 (AN1)
operating status
Channel 2 (AN2)
operating status
A/D conversion 1
Wait for A/D conversion
Wait for A/D conversion
A/D conversion 2
Wait for A/D conversion
Channel 3 (AN3)
operating status
A/D conversion 4
Wait for A/D conversion
Wait for A/D conversion
A/D conversion 5 *2 Wait for A/D conversion
Wait for A/D conversion
A/D conversion 3
Wait for A/D conversion
Transfer
ADDR0
ADDR1
ADDR2
A/D conversion result 1
A/D conversion result 4
A/D conversion result 2
A/D conversion result 3
ADDR3
Notes: 1. At , an instruction is executed by software.
2. Data to be converted is ignored.
Figure 24.4 A/D Converter Operation in A/D Conversion Mode
(When AN0 to AN2 Channels are Selected in Scan Mode)
Rev. 1.00 Oct. 03, 2008 Page 838 of 962
REJ09B0465-0100
Section 24 A/D Converter
24.5
Compare Mode Operation
24.5.1
Single Mode in Compare Mode
In single mode in compare mode, the analog input of one selected channel is compared with the
specified voltage. Operations are as follows. The setting of the channel by the CH[3:0] bits in
ADCSR is the same as that in A/D conversion mode.
1. Comparison between the analog input of the selected channel and the voltage specified by the
VAL[9:0] bits is started when the ADST bit in ADCSR is set to 1 by software or external
trigger input.
2. When the comparison is completed, the result is transferred to a bit corresponding to the
channel.
3. On completion of comparison, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at
this time, an ADI interrupt request is generated. In addition, if a condition specified by the
CMPFC1 or CMPFC0 bit is satisfied, the CMPF bit in CMPCSR is set to 1. If the CMPIE bit
is set to 1 at this time, a CMPI interrupt is requested.
4. The ADST bit remains set to 1 during comparison, and is automatically cleared to 0 when
comparison ends. When the ADST bit is cleared to 0 during comparison, the A/D converter
stops operation and enters wait state.
ADST
ADF
Comparison voltage input
AN0
VAL[9:0]
CMP0 in CMPR
Wait for comparison
Specified voltage
Previous comparison result
Comparison result
Figure 24.5 A/D Converter Operation in Compare Mode
(When Channel 0 Is Selected in Single Mode)
Rev. 1.00 Oct. 03, 2008 Page 839 of 962
REJ09B0465-0100
Section 24 A/D Converter
24.5.2
Scan Mode in Comparison Mode
In scan mode in comparison mode, the analog input of the selected channels (four or eight
maximum) are compared sequentially with the specified voltage. Operations are as follows.
1. When the ADST bit in ADCSR is set to 1 by a software, timer RC, timer RD or external
trigger input, comparison between the analog input of the selected channels and the voltage
specified by the VAL[9:0] bits is started.
The comparison on maximum four channels (SCANE = 1 and SCANS= 0) or on maximum
eight channels (SCANE = 1 and SCANS= 1) can be selected. When the consecutive
comparison is performed on the four channels, the comparison starts on AN0 when CH3 = 0
and CH2 = 0, AN4 when CH3 = 0 and CH2 = 1, or AN8 when CH3 = 1 and CH2 = 0. When
the consecutive comparison is performed on the eight channels, the comparison starts on AN0
when CH3 = 0 and CH2 = 0.
2. When comparison for each channel is completed, the result is sequentially transferred to a bit
corresponding to each channel.
3. When comparison of all the selected channels is completed, the ADF bit in ADCSR is set to 1.
If the ADIE bit is set to 1 at this time, an ADI interrupt is requested. In addition, i