Infineon HYB18L128160BF Drams for mobile application Datasheet

D a t a S h e e t , V 1 . 4 , A p r i l 2 00 4
HYB18L128160BF-7.5
HYE18L128160BF-7.5
HYB18L128160BC-7.5
HYE18L128160BC-7.5
D R A M s fo r M o b i l e A p p l i c a ti o n s
128-Mbit Mobile-RAM
M e m or y P r o du c t s
N e v e r
s t o p
t h i n k i n g .
Edition 2004-04-30
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
D a t a S h e e t , V 1 . 4 , A p r i l 2 00 4
HYB18L128160BF-7.5
HYE18L128160BF-7.5
HYB18L128160BC-7.5
HYE18L128160BC-7.5
D R A M s fo r M o b i l e A p p l i c a ti o n s
128-Mbit Mobile-RAM
M e m or y P r o du c t s
N e v e r
s t o p
t h i n k i n g .
HYB18L128160BF-7.5, HYE18L128160BF-7.5, HYB18L128160BC-7.5, HYE18L128160BC-7.5
Revision History:
V1.4
2004-04-30
45
Table 20: tT removed
47
Table 23: driver characteristics for half drive and full drive merged
Previous Version:
V1.3 (Preliminary Datasheet)
2004-03-19
12
power-up sequence: 2 instead of 8 ARF commands required
47
Table 22: IDD6 specification modified: typ. and max. values given
Previous Version:
all
V1.2 (Preliminary Datasheet)
Package option with lead-containing (“black”) balls added
Previous Version:
V1.1 (Preliminary Datasheet)
all
-8 speed grade removed
39
deep power-down exit: clarification added
45
Table 20: tOH changed
46
Table 21: IDD parameter values changed
48
package drawing updated
Previous Version:
all
2004-01-28
2004-01-08
V1.0 (Preliminary Datasheet)
2003-07-02
derived from HY[B/E]18L256160B[C/F] Preliminary Datasheet V1.0
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
[email protected]
Template: mp_a4_v2.0_2003-06-06.fm
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Table of Contents
1
1.1
1.2
1.3
1.4
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Definition and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2
2.1
2.2
2.2.1
2.2.1.1
2.2.1.2
2.2.1.3
2.2.1.4
2.2.1.5
2.2.1.6
2.2.1.7
2.2.1.8
2.3
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.5.1
2.4.5.2
2.4.5.3
2.4.5.4
2.4.5.5
2.4.6
2.4.6.1
2.4.6.2
2.4.6.3
2.4.6.4
2.4.6.5
2.4.7
2.4.8
2.4.8.1
2.4.8.2
2.4.9
2.4.9.1
2.4.9.2
2.4.10
2.4.10.1
2.5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power On and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Partial Array Self Refresh (PASR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Compensated Self Refresh (TCSR) with On-Chip Temperature Sensor . . . . . . . .
Selectable Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NO OPERATION (NOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODE REGISTER SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ Burst Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Suspend Mode for READ Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ - DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WRITE Burst Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Suspend Mode for WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WRITE - DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WRITE to READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WRITE to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AUTO PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CONCURRENT AUTO PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AUTO REFRESH and SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
POWER DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DEEP POWER DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Function Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
11
12
12
13
13
14
14
14
14
15
15
16
17
18
18
19
20
21
25
25
26
26
27
28
31
31
32
32
33
33
34
34
35
37
37
38
39
39
40
3
3.1
3.2
3.3
3.4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pullup and Pulldown Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
43
45
46
47
4
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Data Sheet
5
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Figure 41
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Data Sheet
Standard Ballout 128-Mbit Mobile-RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-Up Sequence and Mode Register Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Address / Command Inputs Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
No Operation Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Mode Register Set Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ACTIVE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Bank Activate Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Basic READ Timing Parameters for DQs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Single READ Burst (CAS Latency = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Single READ Burst (CAS Latency = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Random READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Non-Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Clock Suspend Mode for READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
READ Burst - DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
READ to WRITE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
READ to PRECHARGE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
WRITE Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Basic WRITE Timing Parameters for DQs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
WRITE Burst (CAS Latency = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
WRITE Burst (CAS Latency = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Consecutive WRITE Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Random WRITE Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Non-Consecutive WRITE Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Clock Suspend Mode for WRITE Bursts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
WRITE Burst - DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
WRITE to READ Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
WRITE to PRECHARGE Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
BURST TERMINATE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
READ with Auto Precharge Interrupted by READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
READ with Auto Precharge Interrupted by WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
WRITE with Auto Precharge Interrupted by READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
WRITE with Auto Precharge Interrupted by WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
AUTO REFRESH Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Auto Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
SELF REFRESH Entry Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Self Refresh Entry and Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Power Down Entry Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Power Down Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
P-VFBGA-54-2 (Plastic Very Thin Fine Ball Grid Array Package) . . . . . . . . . . . . . . . . . . . . . . . . . 48
6
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Overview
1
Overview
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
4 banks × 2 Mbit × 16 organization
Fully synchronous to positive clock edge
Four internal banks for concurrent operation
Programmable CAS latency: 2, 3
Programmable burst length: 1, 2, 4, 8 or full page
Programmable wrap sequence: sequential or interleaved
Programmable drive strength
Auto refresh and self refresh modes
4096 refresh cycles / 64 ms
Auto precharge
Commerical (0°C to +70°C) and Extended (-25oC to +85oC) operating temperature range
54-ball P-VFBGA package (12.0 × 8.0 × 1.0 mm)
Power Saving Features
•
•
•
•
•
Low supply voltages: VDD = 1.8 V ± 0.15 V, VDDQ = 1.8 V ± 0.15 V
Optimized self refresh (IDD6) and standby currents (IDD2/IDD3)
Programmable Partial Array Self Refresh (PASR)
Temperature Compensated Self-Refresh (TCSR), controlled by on-chip temperature sensor
Power-Down and Deep Power Down modes
Table 1
Performance
Part Number Speed Code
- 7.5
Unit
Speed Grade
133
MHz
CL = 3
5.4
ns
CL = 2
6.0
ns
CL = 3
7.5
ns
CL = 2
9.5
ns
Access Time (tACmax)
Clock Cycle Time (tCKmin)
Table 2
Memory Addressing Scheme
Item
Addresses
Banks
BA0, BA1
Rows
A0 - A11
Columns
A0 - A8
Data Sheet
7
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Overview
Table 3
Ordering Information
1)
Type
Package
Description
Commercial Temperature Range
HYB18L128160BC-7.5
P-VFBGA-54-2
133 MHz 4 Banks × 2 Mbit × 16 LP-SDRAM
HYB18L128160BF-7.5
P-VFBGA-54-2
133 MHz 4 Banks × 2 Mbit × 16 LP-SDRAM
Extended Temperature Range
HYE18L128160BC-7.5
P-VFBGA-54-2
133 MHz 4 Banks × 2 Mbit × 16 LP-SDRAM
HYE18L128160BF-7.5
P-VFBGA-54-2
133 MHz 4 Banks × 2 Mbit × 16 LP-SDRAM
1) HYB / HYE: Designator for memory products (HYB: standard temp. range; HYE: extended temp. range)
18L: 1.8V Mobile-RAM
128: 128 MBit density
160: 16 bit interface width
B: die revision
C / F: lead-containing product (C) / green product (F)
-7.5: speed grade(s): min. clock cycle time
1.2
Pin Configuration
1
2
3
7
8
9
VSS
DQ15
VSSQ
A
VDDQ
DQ0
VDD
DQ14
DQ13
VDDQ
B
VSSQ
DQ2
DQ1
DQ12
DQ11
VSSQ
C
VDDQ
DQ4
DQ3
DQ10
DQ9
VDDQ
D
VSSQ
DQ6
DQ5
DQ8
NC
VSS
E
VDD
LDQM
DQ7
UDQM
CLK
CKE
F
CAS
RAS
WE
NC (*)
A11
A9
G
BA0
BA1
CS
A8
A7
A6
H
A0
A1
A10/AP
VSS
A5
A4
J
A3
A2
VDD
(*) = no function; -0.3V .. VDDQ + 0.3V
Figure 1
Data Sheet
Standard Ballout 128-Mbit Mobile-RAM
8
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Overview
1.3
Description
The HY[B/E]18L128160B[C/F] is a high-speed CMOS, dynamic random-access memory containing 134,217,728
bits. It is internally configured as a quad-bank DRAM.
The HY[B/E]18L128160B[C/F] achieves high speed data transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the output data to the system clock. Read and write accesses are
burst-oriented; accesses start at a selected location and continue for a programmed number of locations (1, 2, 4,
8 or full page) in a programmed sequence.
The device operation is fully synchronous: all inputs are registered at the positive edge of CLK.
The HY[B/E]18L128160B[C/F] is especially designed for mobile applications. It operates from a 1.8V power
supply. Power consumption in self refresh mode is drastically reduced by an On-Chip Temperature Sensor
(OCTS); it can further be reduced by using the programmable Partial Array Self Refresh (PASR).
A conventional data-retaining Power-Down (PD) mode is available as well as a non-data-retaining Deep PowerDown (DPD) mode.
The HY[B/E]18L128160B[C/F] is housed in a 54-ball P-VFBGA package. It is available in Commercial (0 °C to
70 °C) and Extended (-25 °C to +85 °C) temperature range.
Command
Decode
CS
RAS
CAS
WE
Control Logic
CKE
CLK
9
Data Sheet
4096
Bank 3
Bank 0
Memory Array
(4096 x 512 x 16)
2
Sense Amplifier
2
Column Address
Counter / Latch
2
Data
Output
Reg.
16
Bank Column Logic
2
Figure 2
12
Bank 2
12
14
Refresh Counter
A0-A11
BA0,BA1
Address Register
12
Bank 0
Row Address Latch
& Decoder
12
Mode
Registers
Row Address Mux
Bank 1
IO Gating
DQM Mask Logic
16
Data
Input
Reg.
LDQM
UDQM
DQ0DQ15
Column
Decoder
9
Functional Block Diagram
9
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Overview
1.4
Pin Definition and Description
Table 4
Pin Description
Ball
Type
Detailed Function
CLK
Input
Clock: all inputs are sampled on the positive edge of CLK.
CKE
Input
Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals,
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWERDOWN (row active in any bank) or SUSPEND (access in progress). Input buffers,
excluding CLK and CKE are disabled during power-down. Input buffers, excluding CKE
are disabled during SELF REFRESH.
CS
Input
Chip Select: All commands are masked when CS is registered HIGH. CS provides for
external bank selection on systems with multiple memory banks. CS is considered part of
the command code.
RAS, CAS,
WE
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being
entered.
DQ0 - DQ15
I/O
Data Inputs/Output: Bi-directional data bus (16 bit)
LDQM,
UDQM
Input
Input/Output Mask: input mask signal for WRITE cycles and output enable for READ
cycles. For WRITEs, DQM acts as a data mask when HIGH. For READs, DQM acts as
an output enable and places the output buffers in High-Z state when HIGH (two clocks
latency).
LDQM corresponds to the data on DQ0 - DQ7; UDQM to the data on DQ8 - DQ15.
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVATE, READ, WRITE
or PRECHARGE command is being applied. BA0, BA1 also determine which mode
register is to be loaded during a MODE REGISTER SET command (MRS or EMRS).
A0 - A11
Input
Address Inputs: A0 - A11 define the row address during an ACTIVE command cycle. A0
- A8 define the column address during a READ or WRITE command cycle. In addition,
A10 (= AP) controls Auto Precharge operation at the end of the burst read or write cycle.
During a PRECHARGE command, A10 (= AP) in conjunction with BA0, BA1 controls
which bank(s) are to be precharged: if A10 is HIGH, all four banks will be precharged
regardless of the state of BA0 and BA1; if A10 is LOW, BA0, BA1 define the bank to be
precharged. During MODE REGISTER SET commands, the address inputs hold the opcode to be loaded.
VDDQ
Supply I/O Power Supply: Isolated power for DQ output buffers for improved noise immunity:
VDDQ = 1.8 V ± 0.15 V
VSSQ
VDD
VSS
Supply I/O Ground
N.C.
–
Data Sheet
Supply Power Supply: Power for the core logic and input buffers, VDD = 1.8 V ± 0.15 V
Supply Ground
No Connect
10
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
2
Functional Description
The 128-Mbit Mobile-RAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits.
It is internally configured as a quad-bank DRAM.
READ and WRITE accesses to the Mobile-RAM are burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration
of an ACTIVE command, followed by a READ or WRITE command. The address bits registered coincident with
the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the banks, A0 - A11
select the row). The address bits registered coincident with the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the Mobile-RAM must be initialized. The following sections provide detailed information
covering device initialization, register definition, command description and device operation.
2.1
Power On and Initialization
The Mobile-RAM must be powered up and initialized in a predefined manner (see Figure 3). Operational
procedures other than those specified may result in undefined operation.
VDD
VDDQ
200µs
tCK
tRP
tRFC
tRFC
tMRD
tMRD
CLK
CKE
Command
NOP
PRE
ARF
Address
All
Banks
A10
ARF
MRS
MRS
NOP
ACT
CODE
CODE
NOP
RA
CODE
CODE
NOP
RA
BA0=L
BA1=L
BA0=L
BA1=H
Load
Mode
Register
Load
Ext.
Mode
Register
BA0,BA1
NOP
BA
DQM
(H Level)
DQ
(High-Z)
Power-up:
VDD and CK stable
= Don't Care
Figure 3
Data Sheet
Power-Up Sequence and Mode Register Sets
11
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
1. At first, device core power (VDD) and device IO power (VDDQ) must be brought up simultaneously. Typically VDD
and VDDQ are driven from a single power converter output.
Assert and hold CKE and DQM to a HIGH level.
2. After VDD and VDDQ are stable and CKE is HIGH, apply stable clocks.
3. Wait for 200µs while issuing NOP or DESELECT commands.
4. Issue a PRECHARGE ALL command, followed by NOP or DESELECT commands for at least tRP period.
5. Issue two AUTO REFRESH commands, each followed by NOP or DESELECT commands for at least tRFC
period.
6. Issue two MODE REGISTER SET commands for programming the Mode Register and Extended Mode
Register, each followed by NOP or DESELECT commands for at least tMRD period; the order in which both
registers are programmed is not important.
Following these steps, the Mobile-RAM is ready for normal operation.
2.2
Register Definition
2.2.1
Mode Register
The Mode Register is used to define the specific mode of operation of the Mobile-RAM. This definition includes
the selection of a burst length (bits A0-A2), a burst type (bit A3), a CAS latency (bits A4-A6), and a write burst
mode (bit A9). The Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and
BA1 = 0) and will retain the stored information until it is programmed again or the device loses power.
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before
initiating any subsequent operation. Violating either of these requirements results in unspecified operation.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
MR
Mode Register Definition
(BA[1:0] = 00B)
BA1
BA0
A11
A10
A9
A8
A7
0
0
0
0
WB
0
0
Field
Bits
Type
Description
WB
9
w
Write Burst Mode
0
Burst Write
1
Single Write
CL
[6:4]
w
CAS Latency
010 2
011 3
A6
A5
CL
A4
A3
BT
A2
A1
A0
BL
Note: All other bit combinations are RESERVED.
BT
3
w
Burst Type
0
Sequential
1
Interleaved
BL
[2:0]
w
Burst Length
000 1
001 2
010 4
011 8
111 full page (Sequential burst type only)
Note: All other bit combinations are RESERVED.
Data Sheet
12
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
2.2.1.1
Burst Length
READ and WRITE accesses to the Mobile-RAM are burst oriented, with the burst length being programmable. The
burst length determines the maximum number of column locations that can be accessed for a given READ or
WRITE command. Burst lengths of 1, 2, 4, 8 locations are available for both the sequential and interleaved burst
types, and a full-page burst mode is available for the sequential burst type.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary
is reached. The block is uniquely selected by A1-A8 when the burst length is set to two, by A2-A8 when the burst
length is set to four and by A3-A8 when the burst length is set to eight. The remaining (least significant) address
bit(s) is (are) used to select the starting location within the block.
Full page bursts wrap within the page if the boundary is reached. Please note that full page bursts do not selfterminate; this implies that full-page read or write bursts with Auto Precharge are not legal commands.
Table 5
Burst Definition
Burst Length
Starting Column Address
A2
A1
2
Full Page
A0
Sequential
Interleaved
0
0-1
0-1
1
1-0
1-0
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
n
n
n
Cn, Cn+1, Cn+2, …
not supported
4
8
Order of Accesses Within a Burst
Notes
1.
2.
3.
4.
5.
For a burst length of 2, A1-Ai select the two-data-element block; A0 selects the first access within the block.
For a burst length of 4, A2-Ai select the four-data-element block; A0-A1 select the first access within the block.
For a burst length of 8, A3-Ai select the eight-data-element block; A0-A2 select the first access within the block.
For a full page burst, A0-Ai select the starting data element.
Whenever a boundary of the block is reached within a given sequence, the following access wraps within the
block.
2.2.1.2
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the
burst type and the starting column address, as shown in Table 5.
Data Sheet
13
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
2.2.1.3
Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a READ command and
the availability of the first piece of output data. The latency can be programmed to 2 or 3 clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available with clock
edge n + m (for details please refer to the READ command description).
2.2.1.4
Write Burst Mode
When A9 = 0, the burst length programmed via A0-A2 applies to both read and write bursts; when A9 = 1, write
accesses consist of single data elements only.
2.2.1.5
Extended Mode Register
The Extended Mode Register controls additional low power features of the device. These include the Partial Array
Self Refresh (PASR, bits A0-A2)), the Temperature Compensated Self Refresh (TCSR, bits A3-A4)) and the drive
strength selection for the DQs (bits A5-A6). The Extended Mode Register is programmed via the MODE
REGISTER SET command (with BA0 = 0 and BA1 = 1) and will retain the stored information until it is programmed
again or the device loses power.
The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified
time before initiating any subsequent operation. Violating either of these requirements result in unspecified
operation.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
EMR
Extended Mode Register
(BA[1:0] = 10B)
BA1
BA0
A11
A10
A9
A8
A7
1
0
0
0
0
0
0
Field
Bits
Type
Description
DS
[6:5]
w
Selectable Drive Strength
00 Full Drive Strength
01 Half Drive Strength
A6
A5
DS
A4
A3
(TCSR)
A2
A1
A0
PASR
Note: All other bit combinations are RESERVED.
TCSR [4:3]
w
Temperature Compensated Self Refresh
XX Superseded by on-chip temperature sensor (see text)
PASR [2:0]
w
Partial Array Self Refresh
000 all banks
001 1/2 array (BA1 = 0)
010 1/4 array (BA1 = BA0 = 0)
101 1/8 array (BA1 = BA0 = RA11 = 0)
110 1/16 array (BA1 = BA0 = RA11 = RA10 = 0)
Note: All other bit combinations are RESERVED.
2.2.1.6
Partial Array Self Refresh (PASR)
Partial Array Self Refresh is a power-saving feature specific to Mobile RAMs. With PASR, self refresh may be
restricted to variable portions of the total array. The selection comprises all four banks (default), two banks, one
bank, half of one bank, and a quarter of one bank. Data written to the non activated memory sections will get lost
after a period defined by tREF (cf. Table 13).
Data Sheet
14
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
2.2.1.7
Temperature Compensated Self Refresh (TCSR) with On-Chip Temperature
Sensor
DRAM devices store data as electrical charge in tiny capacitors that require a periodic refresh in order to retain
the stored information. This refresh requirement heavily depends on the die temperature: high temperatures
correspond to short refresh periods, and low temperatures correspond to long refresh periods.
The Mobile-RAM is equipped with an on-chip temperature sensor which continuously senses the actual die
temperature and adjusts the refresh period in Self Refresh mode accordingly. This makes any programming of the
TCSR bits in the Extended Mode Register obsolete. It also is the superior solution in terms of compatibility and
power-saving, because
•
•
•
it is fully compatible to all processors that do not support the Extended Mode Register
it is fully compatible to all applications that only write a default (worst case) TCSR value, e.g. because of the
lack of an external temperature sensor
it does not require any processor interaction for regular TCSR updates
2.2.1.8
Selectable Drive Strength
The drive strength of the DQ output buffers is selectable via bits A5 and A6. The default value (“half drive strength”)
is suitable for typical applications of a Mobile-RAM. For heavier loaded systems, a stronger output buffer (“full drive
strength”) is available. I-V curves for the full drive strength and half drive strength are included in this document.
Data Sheet
15
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
2.3
State Diagram
Power
On
Power
applied
Deep
Power
Down
DPDSX
Precharge
All
PREALL
Self
Refresh
DPDS
REFSX
REFS
Mode
Register
Set
MRS
Auto
Refresh
REFA
Idle
CKEL
CKEH
Active
Power
Down
Precharge
Power
Down
ACT
CKEH
CKEL
T
BS
W
Row
Active
RE
AD
WRITEA
Clock
Suspend
WRITE
CKEL
CKEH
WRITE
WRITEA
Clock
Suspend
WRITEA
CKEL
CKEH
WRITE A
PRE
BS
T
TE
RI
READA
WRITE
READ
WRITEA
PRE
PRE
CKEH
Clock
Suspend
READ
READA
READ
A
PRE
CKEL
READ
READ A
CKEL
CKEH
Clock
Suspend
READA
Precharge
Automatic Sequence
Command Sequence
PREALL = Precharge All Banks
REFS = Enter Self Refresh
REFSX = Exit Self Refresh
REFA = Auto Refresh
DPDS = Enter Deep Power Down
DPDSX = Exit Deep Power Down
Figure 4
Data Sheet
CKEL = Enter Power Down
CKEH = Exit Power Down
READ = Read w/o Auto Precharge
READA = Read with Auto Precharge
WRITE = Write w/o Auto Precharge
WRITEA = Write with Auto Precharge
ACT = Active
PRE = Precharge
BST = Burst Terminate
MRS = Mode Register Set
State Diagram
16
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
2.4
Commands
Table 6
Command Overview
CS RAS CAS WE DQM
Command
Address
Notes
DESELECT
H
X
X
X
X
X
1)
NO OPERATION
L
H
H
H
X
X
1)
ACT
ACTIVE (Select bank and row)
L
L
H
H
X
Bank / Row
2)
RD
READ (Select bank and column and start read burst)
L
H
L
H
L/H
Bank / Col
3)
WR
WRITE (Select bank and column and start write burst)
L
H
L
L
L/H
Bank / Col
3)
BST
BURST TERMINATE or
DEEP POWER DOWN
L
H
H
L
X
X
4)
PRE
PRECHARGE (Deactivate row in bank or banks)
L
L
H
L
X
Code
5)
NOP
ARF
AUTO REFRESH or
SELF REFRESH (enter self refresh mode)
L
L
L
H
X
X
6)7)
MRS
MODE REGISTER SET
L
L
L
L
X
Op-Code
8)
–
Data Write / Output Enable
–
–
–
–
L
–
9)
–
Write Mask / Output Disable (High-Z)
–
–
–
–
H
–
9)
1) DESELECT and NOP are functionally interchangeable.
2) BA0, BA1 provide bank address, and A0 - A11 provide row address.
3) BA0, BA1 provide bank address, A0 - A8 provide column address; A10 HIGH enables the Auto Precharge feature
(nonpersistent), A10 LOW disables the Auto Precharge feature.
4) This command is BURST TERMINATE if CKE is HIGH, DEEP POWER DOWN if CKE is LOW. The BURST TERMINATE
command is defined for READ or WRITE bursts with Auto Precharge disabled only.
5) A10 LOW: BA0, BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.
6) This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7) Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8) BA0, BA1 select either the Mode Register (BA0 = 0, BA1 = 0) or the Extended Mode Register (BA0 = 0, BA1 = 1); other
combinations of BA0, BA1 are reserved; A0 - A11 provide the op-code to be written to the selected mode register.
9) DQM LOW: data present on DQs is written to memory during write cycles; DQ output buffers are enabled during read
cycles;
DQM HIGH: data present on DQs are masked and thus not written to memory during write cycles; DQ output buffers are
placed in High-Z state (two clocks latency) during read cycles.
Address (A0 - A11, BA0, BA1), write data (DQ0 - DQ15) and command inputs (CKE, CS, RAS, CAS, WE, DQM)
are all registered on the positive edge of CLK. Figure 5 shows the basic timing parameters, which apply to all
commands and operations.
tCK
tCH
tCL
CLK
tIS
Input *)
Valid
tIH
Valid
Valid
= Don't Care
*) = A0 - A11, BA0, BA1, CS, CKE, RAS, CAS, WE
Figure 5
Data Sheet
Address / Command Inputs Timing Parameters
17
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
Table 7
Inputs Timing Parameters
Parameter
Symbol
Clock cycle time
CL = 3
tCK
CL = 2
Clock frequency
CL = 3
fCK
CL = 2
Clock high-level width
Clock low-level width
Address and command input setup time
Address and command input hold time
2.4.1
tCH
tCL
tIS
tIH
- 7.5
Unit
Notes
–
min.
max.
7.5
–
ns
9.5
–
ns
–
133
MHz
–
105
MHz
2.5
–
ns
–
2.5
–
ns
–
1.5
–
ns
–
0.8
–
ns
–
–
NO OPERATION (NOP)
CLK
CKE
(High)
CS
RAS
CAS
WE
A0-A11
BA0,BA1
= Don't Care
Figure 6
No Operation Command
The NO OPERATION (NOP) command is used to perform a NOP to a Mobile-RAM which is selected (CS = LOW).
This prevents unwanted commands from being registered during idle states. Operations already in progress are
not affected.
2.4.2
DESELECT
The DESELECT function (CS = HIGH) prevents new commands from being executed by the Mobile-RAM. The
Mobile-RAM is effectively deselected. Operations already in progress are not affected.
Data Sheet
18
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
2.4.3
MODE REGISTER SET
CLK
CKE
(High)
CS
RAS
CAS
WE
A0-A11
Code
BA0,BA1
Code
= Don't Care
Figure 7
Mode Register Set Command
The Mode Register and Extended Mode Register are loaded via inputs A0 - A11 (see mode register descriptions
in Chapter 2.2). The MODE REGISTER SET command can only be issued when all banks are idle and no bursts
are in progress. A subsequent executable command cannot be issued until tMRD is met.
CLK
Command
MRS
NOP
Valid
tMRD
Address
Code
Valid
= Don't Care
Code = Mode Register / Extended Mode Register selection
(BA0, BA1) and op-code (A0 - A11)
Figure 8
Mode Register Definition
Table 8
Timing Parameters for Mode Register Set Command
Parameter
MODE REGISTER SET command period
Data Sheet
Symbol
tMRD
19
- 7.5
min.
max.
2
–
Units
Notes
tCK
–
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
2.4.4
ACTIVE
CLK
CKE
(High)
CS
RAS
CAS
WE
A0-A11
RA
BA0,BA1
BA
= Don't Care
BA = Bank Address
RA = Row Address
Figure 9
ACTIVE Command
Before any READ or WRITE commands can be issued to a bank within the Mobile-RAM, a row in that bank must
be “opened” (activated). This is accomplished via the ACTIVE command and addresses A0 - A11, BA0 and BA1
(see Figure 9), which decode and select both the bank and the row to be activated. After opening a row (issuing
an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the tRCD specification.
A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active
row has been “closed” (precharged).
The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A
subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results
in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands
to different banks is defined by tRRD.
CLK
Command
ACT
A0-A11
ROW
ROW
COL
BA0, BA1
BA x
BA y
BA y
NOP
ACT
NOP
tRRD
Figure 10
Data Sheet
NOP
tRCD
RD/WR
NOP
= Don't Care
Bank Activate Timings
20
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
Table 9
Timing Parameters for ACTIVE Command
Parameter
Symbol
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE bank A to ACTIVE bank B delay
tRC
tRCD
tRRD
- 7.5
Units
Notes
min.
max.
67
–
ns
1)
19
–
ns
1)
15
–
ns
1)
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
2.4.5
READ
CLK
CKE
(High)
CS
RAS
CAS
WE
A0-A8
CA
Enable AP
A10
AP
Disable AP
BA0,BA1
BA
= Don't Care
BA = Bank Address
CA = Column Address
AP = Auto Precharge
Figure 11
READ Command
Subsequent to programming the mode register with CAS latency and burst length, READ bursts are initiated with
a READ command, as shown in Figure 11. Basic timings for the DQs are shown in Figure 12; they apply to all
read operations and therefore are omitted from all subsequent timing diagrams.
The starting column and bank addresses are provided with the READ command and Auto Precharge is either
enabled or disabled for that burst access. If Auto Precharge is enabled, the row being accessed starts precharge
at the completion of the burst, provided tRAS has been satisfied. For the generic READ commands used in the
following illustrations, Auto Precharge is disabled.
Data Sheet
21
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
CLK
tDQZ
DQM
tAC
tAC
tLZ
tOH
DQ
DO n
tHZ
tOH
DO n+1
= Don't Care
Figure 12
Data Sheet
Basic READ Timing Parameters for DQs
22
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
Table 10
Timing Parameters for READ
Parameter
Symbol
Access time from CLK
CL = 3
CL = 2
DQ low-impedance time from CLK
DQ high-impedance time from CLK
Data out hold time
DQM to DQ High-Z delay (READ Commands)
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE to PRECHARGE command period
PRECHARGE command period
- 7.5
tAC
tAC
tLZ
tHZ
tOH
tDQZ
tRC
tRCD
tRAS
tRP
Units
Notes
–
min.
max.
–
5.4
ns
–
6.0
ns
1.0
–
ns
3.0
7.0
ns
2.5
–
ns
–
2
tCK
–
–
–
67
–
ns
1)
19
–
ns
1)
45
100k
ns
1)
19
–
ns
1)
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
During READ bursts, the valid data-out element from the starting column address is available following the CAS
latency after the READ command. Each subsequent data-out element is valid nominally at the next positive clock
edge. Upon completion of a READ burst, assuming no other READ command has been initiated, the DQs go to
High-Z state.
Figure 13 and Figure 14 show single READ bursts for each supported CAS latency setting.
CLK
tRCD
Command
Address
ACT
NOP
tRAS
READ
Ba A,
Row x
Ba A,
Col n
Row x
Dis AP
tRP
tRC
NOP
NOP
NOP
PRE
NOP
ACT
Ba A,
Row b
Pre All
A10 (AP)
AP
Pre Bank A
Row b
CL=2
DQ
DO n
DO n+1
DO n+2
AP = Auto Precharge
Ba A, Col n = bank A, column n
Dis AP = Disable Auto Precharge
DO n = Data Out from column n
Burst Length = 4 in the case shown.
3 subsequent elements of Data Out are provided in the programmed order following DO n.
Figure 13
Data Sheet
DO n+3
= Don't Care
Single READ Burst (CAS Latency = 2)
23
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
CLK
tRCD
Command
ACT
NOP
tRAS
NOP
READ
Address
Ba A,
Row x
Ba A,
Col n
A10 (AP)
Row x
Dis AP
tRP
tRC
NOP
NOP
NOP
PRE
NOP
NOP
ACT
Ba A,
Row b
Pre All
AP
Row b
Pre Bank A
CL=3
DQ
DO n
DO n+1
DO n+2
DO n+3
= Don't Care
Ba A, Col n = bank A, column n
AP = Auto Precharge
DO n = Data Out from column n
Dis AP = Disable Auto Precharge
Burst Length = 4 in the case shown.
3 subsequent elements of Data Out are provided in the programmed order following DO n.
Figure 14
Single READ Burst (CAS Latency = 3)
Data from any READ burst may be concatenated with data from a subsequent READ command. In either case, a
continuous flow of data can be maintained. A READ command can be initiated on any clock cycle following a
previous READ command, and may be performed to the same or a different (active) bank. The first data element
from the new burst follows either the last element of a completed burst (Figure 15) or the last desired data element
of a longer burst which is being truncated (Figure 16). The new READ command should be issued x cycles after
the first READ command, where x equals the number of desired data elements.
CLK
Command
READ
Address
Ba A,
Col n
NOP
NOP
NOP
READ
NOP
NOP
NOP
NOP
Ba A,
Col b
CL=2
DQ
DO n
DO n+1
DO n+2
DO n+3
DO b
DO b+1
DO b+2
DO n
DO n+1
DO n+2
DO n+3
DO b
DO b+1
CL=3
DQ
Ba A, Col n (b) = Bank A, Column n (b)
DO n (b) = Data Out from column n (b)
Burst Length = 4 in the case shown.
3 subsequent elements of Data Out are provided in the programmed order following DO n (b).
Figure 15
Data Sheet
= Don't Care
Consecutive READ Bursts
24
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
CLK
Command
READ
READ
READ
READ
Address
Ba A,
Col n
Ba A,
Col a
Ba A,
Col x
Ba A,
Col m
NOP
NOP
NOP
NOP
NOP
CL=2
DQ
DO n
DO a
DO x
DO m
DO m+1
DO m+2
DO m+3
DO n
DO a
DO x
DO m
DO m+1
DO m+2
CL=3
DQ
= Don't Care
Ba A, Col n etc. = Bank A, Column n etc.
DO n etc. = Data Out from column n etc.
Burst Length = 4 in the case shown; bursts are terminated by consecutive READ commands
3 subsequent elements of Data Out are provided in the programmed order following DO m.
Figure 16
Random READ Bursts
Non-consecutive READ bursts are shown in Figure 17.
CLK
Command
READ
Address
Ba A,
Col n
NOP
NOP
NOP
NOP
READ
NOP
NOP
NOP
Ba A,
Col b
CL=2
DQ
DO n
DO n+1
DO n+2
DO n+3
DO n
DO n+1
DO n+2
DO b
DO b+1
CL=3
DQ
DO n+3
Ba A, Col n (b) = Bank A, Column n (b)
DO n (b) = Data Out from column n (b)
Burst Length = 4 in the case shown.
3 subsequent elements of Data Out are provided in the programmed order following DO n (b).
Figure 17
Data Sheet
DO b
= Don't Care
Non-Consecutive READ Bursts
25
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
2.4.5.1
READ Burst Termination
Data from any READ burst may be truncated using the BURST TERMINATE command (see Page 33), provided
that Auto Precharge was not activated. The BURST TERMINATE latency is equal to the CAS latency, i.e. the
BURST TERMINATE command must be issued x clock cycles before the clock edge at which the last desired data
element is valid, where x equals the CAS latency for READ bursts minus 1. This is shown in Figure 18. The
BURST TERMINATE command may be used to terminate a full-page READ which does not self-terminate.
CLK
Command
READ
Address
Ba A,
Col n
NOP
NOP
BST
NOP
NOP
NOP
NOP
NOP
CL=2
DQ
DO n
DO n+1
DO n+2
DO n
DO n+1
CL=3
DQ
DO n+2
= Don't Care
Ba A, Col n = Bank A, Column n
DO n = Data Out from column n
Burst Length = 4 in the case shown.
2 subsequent elements of Data Out are provided in the programmed order following DO n.
The burst is terminated after the 3rd data element.
Figure 18
Terminating a READ Burst
2.4.5.2
Clock Suspend Mode for READ Cycles
Clock suspend mode allows to extend any read burst in progress by a variable number of clock cycles. As long as
CKE is registered LOW, the following internal clock pulse(s) will be ignored and data on DQ will remain driven, as
shown in Figure 19.
CLK
CKE
internal
clock
Command
READ
Address
Ba A,
Col n
NOP
NOP
NOP
tCSL
DQ
DO n
tCSL
DO n+1
Data Sheet
NOP
tCSL
DO n+1
DO n+2
= Don't Care
Ba A, Col n etc. = Bank A, Column n etc.
DO n etc. = Data Out from column n etc.
CL = 2 in the case shown
Clock suspend latency tCSL is 1 clock cycle
Figure 19
NOP
Clock Suspend Mode for READ Bursts
26
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
2.4.5.3
READ - DQM Operation
DQM may be used to suppress read data and place the output buffers into High-Z state. The generic timing
parameters as listed in Table 10 also apply to this DQM operation. The read burst in progress is not affected and
will continue as programmed.
CLK
Command
READ
Address
Ba A,
Col n
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQZ
DQM
DQ
DO n
DO n+2
DO n+3
= Don't Care
Ba A, Col n = bank A, column n
DO n = Data Out from column n
CL = 2 in the case shown.
DQM read latency tDQZ is 2 clock cycles
Figure 20
READ Burst - DQM Operation
2.4.5.4
READ to WRITE
A READ burst may be followed by or truncated with a WRITE command. The WRITE command can be performed
to the same or a different (active) bank. Care must be taken to avoid bus contention on the DQs; therefore it is
recommended that the DQs are held in High-Z state for a minimum of 1 clock cycle. This can be achieved by either
delaying the WRITE command, or suppressing the data-out from the READ by pulling DQM HIGH two clock cycles
prior to the WRITE command, as shown in Figure 21. With the registration of the WRITE command, DQM acts as
a write mask: when asserted HIGH, input data will be masked and no write will be performed.
CLK
Command
READ
Address
Ba A,
Col n
NOP
NOP
NOP
NOP
WRITE
NOP
NOP
Ba A,
Col b
DQM
CL=2
DQ
DO n
DO n+1
High-Z
DI b
DI b+1
DI b+2
DO n
High-Z
DI b
DI b+1
DI b+2
CL=3
DQ
= Don't Care
Ba A, Col n (b) = bank A, column n (b)
DO n = Data Out from column n; DI b = Data In to column b;
DQM is asserted HIGH to set DQs to High-Z state for 1 clock cycle prior to the WRITE command.
Figure 21
Data Sheet
READ to WRITE Timing
27
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
2.4.5.5
READ to PRECHARGE
A READ burst may be followed by, or truncated with a PRECHARGE command to the same bank, provided that
Auto Precharge was not activated. This is shown in Figure 22.
The PRECHARGE command should be issued x clock cycles before the clock edge at which the last desired data
element is valid, where x equals the CAS latency for READ bursts minus 1. Following the PRECHARGE
command, a subsequent ACTIVE command to the same bank cannot be issued until tRP is met. Please note that
part of the row precharge time is hidden during the access of the last data elements.
In the case of a READ being executed to completion, a PRECHARGE command issued at the optimum time (as
described above) provides the same operation that would result from the same READ burst with Auto Precharge
enabled. The disadvantage of the PRECHARGE command is that it requires that the command and address
busses be available at the appropriate time to issue the command. The advantage of the PRECHARGE command
is that it can be used to truncate bursts.
CLK
tRP
Command
READ
Address
Ba A,
Col n
A10
(AP)
NOP
NOP
NOP
PRE
NOP
NOP
ACT
Ba A,
Row a
Ba A
Pre All
Dis AP
AP
Pre Bank A
CL=3
DQ
DO n
DO n+1
DO n+2
DO n+3
= Don't Care
Ba A, Col n = bank A, column n; BA Am Row = bank A, row x
DO n = Data Out from column n
Burst Length = 4 in the case shown.
CAS latency = 3 in the case shown
3 subsequent elements of Data Out are provided in the programmed order following DO n.
Figure 22
Data Sheet
READ to PRECHARGE Timing
28
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
2.4.6
WRITE
CLK
CKE
(High)
CS
RAS
CAS
WE
A0-A8
CA
Enable AP
A10
AP
Disable AP
BA0,BA1
BA
= Don't Care
BA = Bank Address
CA = Column Address
AP = Auto Precharge
Figure 23
WRITE Command
WRITE bursts are initiated with a WRITE command, as shown in Figure 23. Basic timings for the DQs are shown
in Figure 24; they apply to all write operations.
The starting column and bank addresses are provided with the WRITE command, and Auto Precharge is either
enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the
completion of the write burst. For the generic WRITE commands used in the following illustrations, Auto Precharge
is disabled.
CLK
tIH
tIS
DQM
tIH
tIS
DQ
DI n
DI n+2
= Don't Care
Figure 24
Basic WRITE Timing Parameters for DQs
During WRITE bursts, the first valid data-in element is registered coincident with the WRITE command, and
subsequent data elements are registered on each successive positive edge of CLK. Upon completion of a burst,
assuming no other commands have been initiated, the DQs remain in High-Z state, and any additional input data
is ignored.
Figure 25 and Figure 26 show a single WRITE burst for each supported CAS latency setting.
Data Sheet
29
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
Data Sheet
30
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
Table 11
Timing Parameters for WRITE
Parameter
Symbol
DQ and DQM input setup time
DQ and DQM input hold time
DQM write mask latency
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE to PRECHARGE command period
WRITE recovery time
PRECHARGE command period
- 7.5
Units
Notes
min.
max.
tIS
tIH
1.5
–
ns
–
0.8
–
ns
–
tDQW
tRC
tRCD
tRAS
tWR
tRP
0
–
tCK
–
67
–
ns
1)
19
–
ns
1)
45
100k
ns
1)
14
–
ns
1)
19
–
ns
1)
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
CLK
tRCD
Command
ACT
Address
Ba A,
Row x
Ba A,
Col n
A10 (AP)
Row x
Dis
AP
NOP
tWR
tRAS
tRP
tRC
WRITE
NOP
NOP
NOP
NOP
PRE
NOP
ACT
Ba A,
Row b
Pre All
Row b
AP
Pre Bank A
DQ
DI n
DI n+1
DI n+2
DI n+3
Ba A, Col n = bank A, column n
DI n = Data In to column n
Burst Length = 4 in the case shown.
3 subsequent elements of Data In are provided in the programmed order following DI n.
Figure 25
= Don't Care
WRITE Burst (CAS Latency = 2)
CLK
tRCD
Command
ACT
Ba A,
Address Row
n
NOP
tRAS
NOP
WRITE
tWR
tRP
tRC
NOP
NOP
NOP
NOP
PRE
Ba A,
Col n
NOP
NOP
ACT
Ba A,
Row b
Pre All
A10 (AP)
DQ
Row
x
Dis
AP
DI n
AP
Pre Bank A
DI n+1
DI n+2
DI n+3
Ba A, Col n = bank A, column n
DI n = Data In to column n
Burst Length = 4 in the case shown.
3 subsequent elements of Data In are provided in the programmed order following DI n.
Figure 26
Data Sheet
Row
b
= Don't Care
WRITE Burst (CAS Latency = 3)
31
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either
case, a continuous flow of input data can be maintained. A WRITE command can be issued on any positive edge
of clock following the previous WRITE command. The first data element from the new burst is applied after either
the last element of a completed burst (Figure 27) or the last desired data element of a longer burst which is being
truncated (Figure 28). The new WRITE command should be issued x cycles after the first WRITE command,
where x equals the number of desired data elements.
CLK
Command
NOP
WRITE
NOP
NOP
NOP
Ba A,
Col n
Address
DQ
DI n
WRITE
NOP
NOP
NOP
DI b+1
DI b+2
DI b+3
Ba A,
Col b
DI n+1
DI n+2
DI n+3
DI b
= Don't Care
Ba A, Col n (b) = Bank A, Column n (b)
DI n (b) = Data In to column n (b)
Burst Length = 4 in the case shown.
3 subsequent elements of Data In are provided in the programmed order following DI n (b).
Figure 27
Consecutive WRITE Bursts
CLK
Command
NOP
Address
DQ
WRITE
WRITE
WRITE
WRITE
Ba A,
Col n
Ba A,
Col a
Ba A,
Col x
Ba A,
Col m
DI n
DI a
DI x
DI m
NOP
NOP
NOP
DI m+1
DI m+2
DI m+3
Ba A, Col n etc. = Bank A, Column n etc.
DI n etc. = Data In to column n etc.
Burst Length = 4 in the case shown; bursts are terminated by consecutive WRITE commands.
3 subsequent elements of Data In are provided in the programmed order following DI m .
Figure 28
NOP
= Don't Care
Random WRITE Bursts
Non-consecutive WRITE bursts are shown in Figure 29.
CLK
Command
Address
DQ
NOP
WRITE
NOP
NOP
NOP
Ba A,
Col n
DI n
NOP
WRITE
Data Sheet
NOP
DI b+1
DI b+2
Ba A,
Col b
DI n+1
DI n+2
DI n+3
DI b
Ba A, Col n (b) = Bank A, Column n (b)
DI n (b) = Data In to column n (b)
Burst Length = 4 in the case shown.
3 subsequent elements of Data In are provided in the programmed order following DI n (b).
Figure 29
NOP
= Don't Care
Non-Consecutive WRITE Bursts
32
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
2.4.6.1
WRITE Burst Termination
Data from any WRITE burst may be truncated using the BURST TERMINATE command (see Page 33), provided
that Auto Precharge was not activated. The input data provided coincident with the BURST TERMINATE
command will be ignored. This is shown in Figure 30. The BURST TERMINATE command may be used to
terminate a full-page WRITE which does not self-terminate.
CLK
Command
NOP
WRITE
NOP
NOP
DI n+1
DI n+2
BST
NOP
NOP
Ba A,
Col n
Address
DQ
DI n
= Don't Care
Ba A, Col n = Bank A, Column n
DI n = Data In to column n
Burst Length = 4 in the case shown.
2 subsequent elements of Data In are written in the programmed order following DI n.
The burst is terminated after the 3rd data element.
Figure 30
Terminating a WRITE Burst
2.4.6.2
Clock Suspend Mode for WRITE Cycles
Clock suspend mode allows to extend any WRITE burst in progress by a variable number of clock cycles. As long
as CKE is registered LOW, the following internal clock pulse(s) will be ignored and no data will be captured, as
shown in Figure 31.
CLK
CKE
internal
clock
Command
NOP
WRITE
Address
Ba A,
Col n
DQ
DI n
NOP
tCSL
tCSL
DI n+1
Data Sheet
NOP
tCSL
DI n+2
= Don't Care
Ba A, Col n etc. = Bank A, Column n etc.
DO n etc. = Data Out from column n etc.
CL = 2 in the case shown
Clock suspend latency tCSL is 1 clock cycle
Figure 31
NOP
Clock Suspend Mode for WRITE Bursts
33
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
2.4.6.3
WRITE - DQM Operation
DQM may be used to mask write data: when asserted HIGH, input data will be masked and no write will be
performed. The generic timing parameters as listed in Table 11 also apply to this DQM operation. The write burst
in progress is not affected and will continue as programmed.
CLK
Command
NOP
WRITE
NOP
NOP
NOP
DI n+2
DI n+3
NOP
Ba A,
Col n
Address
DQM
DQ
DI n
= Don't Care
Ba A, Col n = Bank A, Column n
DI n = Data In to column n
Burst Length = 4 in the case shown.
3 subsequent elements of Data In are provided in the programmed order following
DI n, with the first element (DI n+1) being masked.
DQM write latency is 0 clock cycles.
Figure 32
WRITE Burst - DQM Operation
2.4.6.4
WRITE to READ
A WRITE burst may be followed by, or truncated with a READ command. The READ command can be performed
to the same or a different (active) bank. With the registration of the READ command, data inputs will be ignored
and no WRITE will be performed, as shown in Figure 33.
CLK
Command
Address
WRITE
NOP
NOP
Ba A,
Col n
READ
NOP
NOP
NOP
NOP
Ba A,
Col b
CL=2
DQ
DI n
DI n+1
High-Z
DI n+2
Write data
are ignored
DQ
DI n
DI n+1
DO b
DO b+1
DO b+2
DO b
DI b+1
CL=3
High-Z
DI n+2
Ba A, Col n (b) = bank A, column n (b)
= Don't Care
DI n = Data In to column n; DO b = Data Out from column b;
Burst Length = 4 in the case shown.
3 subsequent elements of Data In (Out) are provided in the programmed order following DI n (DO b).
DI n+3 is ignored due to READ command. No DQM masking required at this point.
Figure 33
Data Sheet
WRITE to READ Timing
34
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
2.4.6.5
WRITE to PRECHARGE
A WRITE burst may be followed by, or truncated with a PRECHARGE command to the same bank, provided that
Auto Precharge was not activated. This is shown in Figure 34.
The PRECHARGE command should be issued tWR after the clock edge at which the last desired data element of
the WRITE burst was registered. Additionally, when truncating a WRITE burst, DQM must be pulled to mask input
data presented during tWR prior to the PRECHARGE command. Following the PRE-CHARGE command, a
subsequent ACTIVE command to the same bank cannot be issued until tRP is met.
In the case of a WRITE being executed to completion, a PRECHARGE command issued at the optimum time (as
described above) provides the same operation that would result from the same WRITE burst with Auto Precharge
enabled. The disadvantage of the PRECHARGE command is that it requires that the command and address
busses be available at the appropriate time to issue the command. The advantage of the PRECHARGE command
is that it can be used to truncate bursts.
CLK
tWR
Command
NOP
WRITE
NOP
NOP
Ba A,
Col n
Address
NOP
tRP
PRE
Ba A
NOP
ACT
Ba A,
Row a
Pre All
A10
(AP)
Dis AP
AP
Pre Bank A
DQM
DQ
DI n
DI n+1
DI n+2
Ba A, Col n = bank A, column n
AP = Auto Precharge
= Don't Care
DI n = Data In to column n
Dis AP = Disable Auto Precharge
Burst Length = 4 in the case shown.
3 subsequent elements of Data In are provided in the programmed order following DI n.
DI n+3 is masked due to DQM pulled HIGH during tWR period prior to PRECHARGE command.
Figure 34
WRITE to PRECHARGE Timing
2.4.7
BURST TERMINATE
CLK
CKE
(High)
CS
RAS
CAS
WE
A0-A11
BA0,BA1
= Don't Care
Figure 35
Data Sheet
BURST TERMINATE Command
35
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
The BURST TERMINATE command is used to truncate READ or WRITE bursts (with Auto Precharge disabled).
The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be
truncated, as shown in Figure 18 and Figure 30, respectively.
The BURST TERMINATE command is not allowed for truncation of READ or WRITE bursts with Auto Precharge
enabled.
2.4.8
PRECHARGE
CLK
CKE
(High)
CS
RAS
CAS
WE
A0-A9
A11
All Banks
A10
One Bank
BA0,BA1
BA
= Don't Care
BA = Bank Address
(if A10 = L, otherwise Don't Care)
Figure 36
PRECHARGE Command
The PRECHARGE command is used to deactivate (close) the open row in a particular bank or the open row in all
banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE
command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where
only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t
Care”.
Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE
commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row
in that bank, or if the previously open row is already in the process of precharging.
2.4.8.1
AUTO PRECHARGE
Auto Precharge is a feature which performs the same individual-bank precharge functions described above, but
without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction
with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or
WRITE command is automatically performed upon completion of the READ or WRITE burst. Auto Precharge is
nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. Auto Precharge
ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another
command to the same bank until the precharge (tRP) is completed. This is determined as if an explicit
PRECHARGE command was issued at the earliest possible time, as described for each burst type.
Data Sheet
36
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
Table 12
Timing Parameters for PRECHARGE
Parameter
ACTIVE to PRECHARGE command period
WRITE recovery time
PRECHARGE command period
Symbol
tRAS
tWR
tRP
- 7.5
Units
Notes
min.
max.
45
100k
ns
1)
14
–
ns
1)
19
–
ns
1)
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
Data Sheet
37
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
2.4.8.2
CONCURRENT AUTO PRECHARGE
A READ or WRITE burst with Auto Precharge enabled can be interrupted by a subsequent READ or WRITE
command issued to a different bank.
Figure 37 shows a READ with Auto Precharge to bank n, interrupted by a READ (with or without Auto Precharge)
to bank m. The READ to bank m will interrupt the READ to bank n, CAS latency later. The precharge to bank n
will begin when the READ to bank m is registered.
Figure 38 shows a READ with Auto Precharge to bank n, interrupted by a WRITE (with or without Auto Precharge)
to bank m. The precharge to bank n will begin when the WRITE to bank m is registered. DQM should be pulled
HIGH two clock cycles prior to the WRITE to prevent bus contention.
Figure 39 shows a WRITE with Auto Precharge to bank n, interrupted by a READ (with or without Auto Precharge)
to bank m. The precharge to bank n will begin tWR after the new command to bank m is registered. The last valid
data-in to bank n is one clock cycle prior to the READ to bank m.
Figure 40 shows a WRITE with Auto Precharge to bank n, interrupted by a WRITE (with or without Auto
Precharge) to bank m. The precharge to bank n will begin tWR after the WRITE to bank m is registered. The last
valid data-in to bank n is one clock cycle prior to the WRITE to bank m.
CLK
Command
NOP
RD-AP
NOP
Bank n
Col b
Address
READ
NOP
NOP
NOP
Bank m
Col x
CL=2
DQ
tRP (bank n)
DO b
DO b+1
DO x
DO x+1
DO x+2
= Don't Care
RD-AP = Read with Auto Precharge; READ = Read with or without Auto Precharge
CL = 2 and Burst Length = 4 in the case shown
Read with Auto Precharge to bank n is interrupted by subsequent Read to bank m
Figure 37
NOP
READ with Auto Precharge Interrupted by READ
CLK
Command
Address
NOP
RD-AP
NOP
NOP
Bank n
Col b
WRITE
NOP
NOP
NOP
Bank m
Col x
DQM
CL=2
DQ
tRP (bank n)
DO b
DI x
DI x+1
RD-AP = Read with Auto Precharge; WRITE = Write with or without Auto Precharge
CL = 2 and Burst Length = 4 in the case shown
Read with Auto Precharge to bank n is interrupted by subsequent Write to bank m
Figure 38
Data Sheet
DI x+2
DI x+3
= Don't Care
READ with Auto Precharge Interrupted by WRITE
38
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
CLK
Command
WR-AP
Address
Bank n
Col b
NOP
READ
NOP
NOP
DO b
NOP
tRP (bank n)
DO b+1
DO x
DO x+1
DO x+2
WR-AP = Write with Auto Precharge; READ = Read with or without Auto Precharge
CL = 2 and Burst Length = 4 in the case shown
Write with Auto Precharge to bank n is interrupted by subsequent Read to bank m
Figure 39
NOP
Bank m
Col x
tWR (bank n)
CL=2
DQ
NOP
DO x+3
= Don't Care
WRITE with Auto Precharge Interrupted by READ
CLK
Command
WR-AP
Address
Bank n
Col b
NOP
WRITE
NOP
NOP
DI b
NOP
DI b+1
DI x
DI x+1
tRP (bank n)
DI x+1
DI x+1
WR-AP = Write with Auto Precharge; WRITE = Write with or without Auto Precharge
Burst Length = 4 in the case shown
Write with Auto Precharge to bank n is interrupted by subsequent Write to bank m
Figure 40
Data Sheet
NOP
Bank m
Col x
tWR (bank n)
DQ
NOP
= Don't Care
WRITE with Auto Precharge Interrupted by WRITE
39
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
2.4.9
AUTO REFRESH and SELF REFRESH
The Mobile-RAM requires a refresh of all rows in a rolling interval. Each refresh is generated in one of two ways:
by an explicit AUTO REFRESH command, or by an internally timed event in SELF REFRESH mode.
2.4.9.1
AUTO REFRESH
CLK
CKE
(High)
CS
RAS
CAS
WE
A0-A11
BA0,BA1
= Don't Care
Figure 41
AUTO REFRESH Command
Auto Refresh is used during normal operation of the Mobile-RAM. The command is nonpersistent, so it must be
issued each time a refresh is required. A minimum row cycle time (tRC) is required between two AUTO REFRESH
commands. The same rule applies to any access command after the Auto Refresh operation. All banks must be
precharged prior to the AUTO REFRESH command.
The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care”
during an AUTO REFRESH command. The Mobile-RAM requires Auto Refresh cycles at an average periodic
interval of 15.6 µs (max.). Partial Array mode has no influence on Auto Refresh mode.
CLK
tRP
Command
PRE
NOP
tRC
ARF
tRC
NOP
NOP
DQ
Data Sheet
NOP
ACT
Row n
Pre All
High-Z
= Don't Care
Ba A, Row n = bank A, row n
Figure 42
NOP
Ba A,
Row n
Address
A10 (AP)
ARF
Auto Refresh
40
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
2.4.9.2
SELF REFRESH
CLK
CKE
CS
RAS
CAS
WE
A0-A11
BA0,BA1
= Don't Care
Figure 43
SELF REFRESH Entry Command
The SELF REFRESH command can be used to retain data in the Mobile-RAM, even if the rest of the system is
powered down. When in the self refresh mode, the Mobile-RAM retains data without external clocking. The SELF
REFRESH command is initiated like an AUTO REFRESH command except CKE is LOW. Input signals except
CKE are “Don’t Care” during SELF REFRESH.
The procedure for exiting SELF REFRESH requires a stable clock prior to CKE returning HIGH. Once CKE is
HIGH, NOP commands must be issued for tRC because time is required for a completion of any internal refresh in
progress.
The use of SELF REFRESH mode introduces the possibility that an internally timed event can be missed when
CKE is raised for exit from SELF REFRESH mode. Upon exit from SELF REFRESH an extra AUTO REFRESH
command is recommended.
CLK
tRP
> tRC
tRC
tSREX
tRC
CKE
Command
PRE
NOP
ARF
NOP
NOP
NOP
ARF
NOP
Ba A,
Row n
Address
A10 (AP)
DQ
Row n
Pre All
High-Z
Self Refresh
Entry Command
Figure 44
Data Sheet
ACT
Self Refresh
Exit Command
Exit from
Self Refresh
Any Command
(Auto Refresh
Recommended)
= Don't Care
Self Refresh Entry and Exit
41
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
Table 13
Timing Parameters for AUTO REFRESH and SELF REFRESH
Parameter
Symbol
ACTIVE to ACTIVE command period
PRECHARGE command period
Refresh period (4096 rows)
Self refresh exit time
tRC
tRP
tREF
tSREX
- 7.5
Units
Notes
min.
max.
67
–
ns
1)
19
–
ns
1)
–
64
ms
1)
1
–
tCK
1)
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
2.4.10
POWER DOWN
CLK
CKE
CS
RAS
CAS
WE
A0-A11
BA0,BA1
= Don't Care
Figure 45
Power Down Entry Command
Power-down is entered when CKE is registered LOW (no accesses can be in progress). If power-down occurs
when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a
row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input
and output buffers, excluding CLK and CKE. CKE LOW must be maintained during power-down.
Power-down duration is limited by the refresh requirements of the device (tREF).
The power-down state is synchronously exited when CKE is registered HIGH (along with a NOP or DESELECT
command). One clock delay is required for power down entry and exit.
Data Sheet
42
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
CLK
tRP
CKE
Command
PRE
NOP
NOP
NOP
Valid
Address
A10 (AP)
Valid
Pre All
Valid
High-Z
DQ
Power Down
Entry
Exit from
Power Down
Any
Command
Precharge Power Down mode shown: all banks are idle and tRP met
when Power Down Entry Command is issued
Figure 46
Power Down Entry and Exit
2.4.10.1
DEEP POWER DOWN
= Don't Care
The deep power down mode is an unique function on Low Power SDRAM devices with extremely low current
consumption. Deep power down mode is entered using the BURST TERMINATE command (cf. Figure 35) except
that CKE is LOW. All internal voltage generators inside the device are stopped and all memory data is lost in this
mode. To enter the deep power down mode all banks must be precharged.
The deep power down mode is asynchronously exited by asserting CKE HIGH. After the exit, the same command
sequence as for power-up initialization, including the 200µs initial pause, has to be applied before any other
command may be issued (cf. Figure 3 and Figure 4).
2.5
Function Truth Tables
Table 14
Current State Bank n - Command to Bank n
Current State
Any
Idle
Row Active
Read
(AutoPrecharge
Disabled)
Data Sheet
CS
RAS CAS WE Command / Action
Notes
H
X
X
X
DESELECT (NOP / continue previous operation)
1)2)3)4)5)6)
L
H
H
H
NO OPERATION (NOP / continue previous operation)
1) to 6)
L
L
H
H
ACTIVE (select and activate row)
1) to 6)
L
L
L
H
AUTO REFRESH
1) to 7)
L
L
L
L
MODE REGISTER SET
1) to 7)
L
L
H
L
PRECHARGE
1) to 6), 8)
L
H
L
H
READ (select column and start READ burst)
1) to 6), 9)
L
H
L
L
WRITE (select column and start WRITE burst)
1) to 6), 9)
L
L
H
L
PRECHARGE (deactivate row in bank or banks)
1) to 6), 10)
L
H
L
H
READ (select column and start new READ burst)
1) to 6), 9)
L
H
L
L
WRITE (select column and start new WRITE burst)
1) to 6), 9)
L
L
H
L
PRECHARGE (truncate READ burst, start precharge)
1) to 6), 10)
L
H
H
L
BURST TERMINATE
1) to 6), 11)
43
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
Table 14
Current State Bank n - Command to Bank n (cont’d)
Current State
Write
(AutoPrecharge
Disabled)
CS
RAS CAS WE Command / Action
Notes
L
H
L
H
READ (select column and start READ burst)
1) to 6), 9)
L
H
L
L
WRITE (select column and start WRITE burst)
1) to 6), 9)
L
L
H
L
PRECHARGE (truncate WRITE burst, start precharge)
1) to 6), 10)
L
H
H
L
BURST TERMINATE
1) to 6), 11)
1) This table applies when CKEn-1 was HIGH and CKEn is HIGH and after tRC has been met (if the previous state was self
refresh).
2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are
those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
3) Current state definitions:
Idle:
The bank has been precharged, and tRP has been met.
Row Active:
A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register
accesses are in progress.
Read:
A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been
terminated.
Write:
A WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been
terminated.
4) The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands, or
allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable
commands to the other bank are determined by its current state and according to Table 15.
Precharging:
Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank
is in the “idle” state.
Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank
is in the “row active” state.
Read with AP
Enabled:
Starts with registration of a READ command with Auto Precharge enabled and ends when tRP has been
met. Once tRP is met, the bank is in the idle state.
Write with AP
Enabled:
Starts with registration of a WRITE command with Auto Precharge enabled and ends when tRP has been
met. Once tRP is met, the bank is in the idle state.
5) The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied
on each positive clock edge during these states.
Refreshing:
Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the
SDRAM is in the “all banks idle” state.
Accessing Mode
Register:
Starts with registration of a MODE REGISTER SET command and ends when tMRD has been met. Once
tMRD is met, the SDRAM is in the “all banks idle” state.
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all
banks are in the idle state.
6) All states and sequences not shown are illegal or reserved.
7) Not bank-specific; requires that all banks are idle and no bursts are in progress.
8) Same as NOP command in that state.
9) READs or WRITEs listed in the Command/Action column include READs or WRITEs with Auto Precharge enabled and
READs or WRITEs with Auto Precharge disabled.
10) May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging.
11) Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
Table 15
Current State Bank n - Command to Bank m (different bank)
Current State
Any
Data Sheet
CS
RAS CAS WE Command / Action
Notes
H
X
X
X
DESELECT (NOP / continue previous operation)
1)2)3)4)5)6)
L
H
H
H
NO OPERATION (NOP / continue previous operation)
1) to 6)
44
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
Table 15
Current State Bank n - Command to Bank m (different bank) (cont’d)
Current State
CS
RAS CAS WE Command / Action
Notes
Idle
X
X
X
X
Any command otherwise allowed to bank n
1) to 6)
Row Activating,
Active, or
Precharging
L
L
H
H
ACTIVE (select and activate row)
1) to 6)
L
H
L
H
READ (select column and start READ burst)
1) to 7)
L
H
L
L
WRITE (select column and start WRITE burst)
1) to 7)
L
L
H
L
PRECHARGE (deactivate row in bank or banks)
1) to 6)
L
L
H
H
ACTIVE (select and activate row)
1) to 6)
L
H
L
H
READ (select column and start READ burst)
1) to 7)
L
H
L
L
WRITE (select column and start WRITE burst)
1) to 8)
L
L
H
L
PRECHARGE (deactivate row in bank or banks)
1) to 6)
L
L
H
H
ACTIVE (select and activate row)
1) to 6)
L
H
L
H
READ (select column and start READ burst)
1) to 7)
L
H
L
L
WRITE (select column and start WRITE burst)
1) to 7)
L
L
H
L
PRECHARGE (deactivate row in bank or banks)
1) to 6)
L
L
H
H
ACTIVE (select and activate row)
1) to 6)
L
H
L
H
READ (select column and start READ burst)
1) to 7), 9)
L
H
L
L
WRITE (select column and start WRITE burst)
1) to 9)
L
L
H
L
PRECHARGE (deactivate row in bank or banks)
1) to 6)
L
L
H
H
ACTIVE (select and activate row)
1) to 6)
L
H
L
H
READ (select column and start READ burst)
1) to 7), 9)
L
H
L
L
WRITE (select column and start WRITE burst)
1) to 7), 9)
L
L
H
L
PRECHARGE (deactivate row in bank or banks)
1) to 6)
Read (AutoPrecharge
Disabled)
Write (AutoPrecharge
Disabled)
Read
(with AutoPrecharge)
Write
(with AutoPrecharge)
1) This table applies when CKEn-1 was HIGH and CKEn is HIGH and after tRC has been met (if the previous state was Self
Refresh).
2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands
shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is
allowable). Exceptions are covered in the notes below.
3) Current state definitions:
Idle:
The bank has been precharged, and tRP has been met.
Row Active:
A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register
accesses are in progress.
Read:
A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been
terminated.
Write:
A WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been
terminated.
Read with AP
Enabled:
Starts with registration of a READ command with Auto Precharge enabled and ends when tRP has been
met. Once tRP is met, the bank is in the idle state.
Write with AP
Enabled:
Starts with registration of a WRITE command with Auto Precharge enabled and ends when tRP has been
met. Once tRP is met, the bank is in the idle state.
4) AUTO REFRESH, SELF REFRESH and MODE REGISTER SET commands may only be issued when all banks are idle.
5) A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state
only.
6) All states and sequences not shown are illegal or reserved.
7) READs or WRITEs listed in the Command/Action column include READs or WRITEs with Auto Precharge enabled and
READs or WRITEs with Auto Precharge disabled.
8) Requires appropriate DQM masking.
Data Sheet
45
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
9) Concurrent Auto Precharge: bank n will start precharging when its burst has been interrupted by a READ or WRITE
command to bank m.
Table 16
CKEn-1
L
L
H
H
Truth Table - CKE
CKEn
L
H
L
H
Current State
Command
Action
Notes
Power Down
X
Maintain Power Down
1)2)3)4)
Self Refresh
X
Maintain Self Refresh
1) to 4)
Clock Suspend
X
Maintain Clock Suspend
1) to 4)
Deep Power Down
X
Maintain Deep Power
Down
1) to 4)
Power Down
DESELECT or NOP
Exit Power Down
1) to 4)
Self Refresh
DESELECT or NOP
Exit Self Refresh
1) to 5)
Clock Suspend
X
Exit Clock Suspend
1) to 4)
Deep Power Down
X
Exit Deep Power Down
1) to 4), 6)
All Banks Idle
DESELECT or NOP
Enter Precharge Power
Down
1) to 4)
Bank(s) Active
DESELECT or NOP
Enter Active Power Down
1) to 4)
All Banks Idle
AUTO REFRESH
Enter Self Refresh
1) to 4)
Read / Write burst
(valid)
Enter Clock Suspend
1) to 4)
1) to 4)
see Table 14 and Table 15
1) CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
2) Current state is the state immediately prior to clock edge n.
3) COMMAND n is the command registered at clock edge n; ACTION n is a result of COMMAND n.
4) All states and sequences not shown are illegal or reserved.
5) DESELECT or NOP commands should be issued on any clock edges occurring during tRC period.
6) Exit from DEEP POWER DOWN requires the same command sequence as for power-up initialization.
Data Sheet
46
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Electrical Characteristics
3
Electrical Characteristics
3.1
Operating Conditions
Table 17
Absolute Maximum Ratings
Parameter
Symbol
Power Supply Voltage
Power Supply Voltage for Output Buffer
Input Voltage
Output Voltage
Operation Case Temperature
Commercial
Extended
Storage Temperature
Power Dissipation
Short Circuit Output Current
VDD
VDDQ
VIN
VOUT
TC
TC
TSTG
PD
IOUT
Values
Unit
min.
max.
-0.3
2.7
V
-0.3
2.7
V
-0.3
V
-0.3
VDDQ + 0.3
VDDQ + 0.3
0
+70
°C
-25
+85
°C
-55
+150
°C
–
0.7
W
–
50
mA
V
Attention: Stresses above those listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Maximum ratings are absolute ratings; exceeding only one of these values may cause
irreversible damage to the integrated circuit.
Table 18
Pin Capacitances1)2)
Parameter
Symbol
CI1
CI2
CIO
Input capacitance: CLK
Input capacitance: all other input pins
Input/Output capacitance: DQ
Values
Unit
min.
max.
1.5
3.0
pF
1.5
3.0
pF
3.0
5.0
pF
1) These values are not subject to production test but verified by device characterization.
2) Input capacitance is measured according to JEP147 with VDD, VDDQ applied and all other pins (except the pin under test)
floating. DQ’s should be in high impedance state. This may be achieved by pulling CKE to low level.
Data Sheet
43
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Electrical Characteristics
Table 19
Electrical Characteristics1)
Parameter
Power Supply Voltage
Power Supply Voltage for DQ Output Buffer
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Input leakage current
Output leakage current
Symbol
VDD
VDDQ
VIH
VIL
VOH
VOL
IIL
IOL
Values
Unit
Notes
–
min.
max.
1.65
1.95
V
1.65
1.95
V
–
0.8 × VDDQ
VDDQ + 0.3
V
2)
-0.3
0.3
V
2)
VDDQ - 0.2
–
V
–
–
0.2
V
–
-1.0
1.0
µA
–
-1.5
1.5
µA
–
1) 0 °C ≤ TC ≤ 70 °C (comm.); -25 °C ≤ TC ≤ 85 °C (ext.); all voltages referenced to VSS. VSS and VSSQ must be at same potential.
2) VIH may overshoot to VDD + 0.8 V for pulse width < 4 ns; VIL may undershoot to -0.8 V for pulse width < 4 ns.
Pulse width measured at 50% with amplitude measured between peak voltage and DC reference level.
Data Sheet
44
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Electrical Characteristics
3.2
AC Characteristics
Table 20
AC Characteristics1)2)3)4)
Parameter
Symbol
Clock cycle time
CL = 3
CL = 3
CL = 3
Clock low-level width
Address, data and command input setup time
Address, data and command input hold time
MODE REGISTER SET command period
DQ low-impedance time from CLK
DQ high-impedance time from CLK
Data out hold time
DQM to DQ High-Z delay (READ Commands)
DQM write mask latency
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE bank A to ACTIVE bank B delay
ACTIVE to PRECHARGE command period
WRITE recovery time
PRECHARGE command period
Refresh period (4096 rows)
Self refresh exit time
–
7.5
–
ns
9.5
–
ns
–
133
MHz
–
105
MHz
tAC
–
5.4
ns
–
6.0
ns
tCH
tCL
tIS
tIH
tMRD
tLZ
tHZ
tOH
tDQZ
tDQW
tRC
tRCD
tRRD
tRAS
tWR
tRP
tREF
tSREX
2.5
–
ns
2.5
–
ns
–
tCK
fCK
CL = 2
Clock high-level width
Notes
max.
CL = 2
Access time from CLK
Unit
min.
CL = 2
Clock frequency
- 7.5
–
5)6)
–
1.5
–
ns
7)
0.8
–
ns
7)
2
–
tCK
–
1.0
–
ns
–
3.0
7.0
ns
–
2.5
–
ns
5)6)
–
2
–
0
–
tCK
tCK
–
67
–
ns
8)
19
–
ns
8)
15
–
ns
8)
45
100k
ns
8)
14
–
ns
9)
19
–
ns
8)
–
64
ms
–
1
–
tCK
–
1) 0 °C ≤ TC ≤ 70 °C (comm.); -25 °C ≤ TC ≤ 85 °C (ext.); VDD = VDDQ = 1.8 V ± 0.15 V;
2) All parameters assumes proper device initialization.
3) AC timing tests measured at 0.9 V.
4) The transition time is measured between VIH and VIL; all AC characteristics assume tT = 1 ns.
5) Specified tAC and tOH parameters are measured with a 30 pF capacitive load only as shown below:
I/O
30 pF
6) If tT(CLK) > 1 ns, a value of (tT/2 - 0.5) ns has to be added to this parameter.
7) If tT > 1 ns, a value of (tT - 1) ns has to be added to this parameter.
8) These parameter account for the number of clock cycles and depend on the operating frequency, as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
9) The write recovery time of tWR = 14 ns allows the use of one clock cycle for the write recovery time when fCK ≤ 72 MHz.
With fCK > 72 MHz two clock cycles for tWR are mandatory. Infineon Technologies recommends to use two clock cycles for
the write recovery time in all applications.
Data Sheet
45
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Electrical Characteristics
3.3
Operating Currents
Table 21
Maximum Operating Currents1)
Parameter & Test Conditions
Symbol
Values
Unit
Notes
- 7.5
Operating current:
one bank: active / read / precharge, BL = 1, tRC = tRCmin
IDD1
60
mA
2)3)
Precharge power-down standby current:
all banks idle, CS ≥ VIHmin, CKE ≤ VILmax,
inputs changing once every two clock cycles
IDD2P
0.5
mA
2)
Precharge power-down standby current with clock stop:
all banks idle, CS ≥ VIHmin, CKE ≤ VILmax, all inputs stable
IDD2PS
0.35
mA
–
Precharge non power-down standby current:
all banks idle, CS ≥ VIHmin, CKE ≥ VIHmin,
inputs changing once every two clock cycles
IDD2N
13
mA
2)
Precharge non power-down standby current with clock stop:
all banks idle, CS ≥ VIHmin, CKE ≥ VIHmin, all inputs stable
IDD2NS
1.0
mA
–
Active power-down standby current:
one bank active, CS ≥ VIHmin, CKE ≤ VILmax,
inputs changing once every two clock cycles
IDD3P
1.0
mA
2)
Active power-down standby current with clock stop:
one bank active, CS ≥ VIHmin, CKE ≤ VILmax, all inputs stable
IDD3PS
0.5
mA
–
Active non power-down standby current:
one bank active, CS ≥ VIHmin, CKE ≥ VIHmin,
inputs changing once every two clock cycles
IDD3N
15
mA
2)
Active non power-down standby current with clock stop:
one bank active, CS ≥ VIHmin, CKE ≥ VIHmin, all inputs stable
IDD3NS
1.5
mA
–
Operating burst read current:
all banks active; continuous burst read,
inputs changing once every two clock cycles
IDD4
45
mA
2)3)
Auto-Refresh current:
tRC = tRCmin, “burst refresh”,
inputs changing once every two clock cycles
IDD5
90
mA
2)
Self Refresh current:
self refresh mode, CS ≥ VIHmin, CKE ≤ VILmax, all inputs stable
IDD6
see Table 22
Deep Power Down current
IDD7
20
µA
–
–
1) 0 °C ≤ TC ≤ 70 °C (comm.); -25 °C ≤ TC ≤ 85 °C (ext.); VDD = VDDQ = 1.8 V ± 0.15 V;
Recommended Operating Conditions unless otherwise noted
2) These values are measured with tCK = 7.5 ns
3) All parameters are measured with no output loads.
Data Sheet
46
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Electrical Characteristics
Self Refresh Currents1)2)
Table 22
Parameter & Test Conditions
Max.
Temperature
Symbol
85 °C
IDD6
Self Refresh Current:
Self refresh mode,
full array activation
(PASR = 000)
Self Refresh Current:
Self refresh mode,
half array activation
(PASR = 001)
Self Refresh Current:
Self refresh mode,
quarter array activation
(PASR = 010)
Values
typ.
max.
365
415
70 °C
260
–
45 °C
185
–
25 °C
165
–
85 °C
285
325
70 °C
210
–
45 °C
155
–
25 °C
140
–
85 °C
245
280
70 °C
190
–
45 °C
145
–
25 °C
130
–
Units
Notes
µA
–
1) 0 °C ≤ TC ≤ 70 °C (comm.); -25 °C ≤ TC ≤ 85 °C (ext.); VDD = VDDQ = 1.8 V ± 0.15 V
2) The On-Chip Temperature Sensor (OCTS) adjusts the refresh rate in self refresh mode to the component’s actual
temperature with a much finer resolution than supported by the 4 distinct temperature levels as defined by JEDEC for
TCSR. At production test the sensor is calibrated, and IDD6 max. current is measured at 85°C. Typ. values are obtained
from device characterization.
3.4
Pullup and Pulldown Characteristics
Table 23
Half Drive Strength (Default) and Full Drive Strength
Voltage
(V)
Full Drive Strength
Half Drive Strength (Default)
Pull-Down Current (mA) Pull-Up Current (mA) Pull-Down Current (mA) Pull-Up Current (mA)
Nominal
Low
Nominal
High
Nominal
Low
Nominal
High
Nominal
Low
Nominal
High
Nominal
Low
Nominal
High
0.00
0.0
0.0
-19.7
-33.4
0.0
0.0
-39.3
-66.7
0.40
15.1
20.5
-18.8
-32.0
30.2
41.0
-37.6
-63.9
0.65
20.3
28.5
-18.2
-31.0
40.5
57.0
-36.4
-61.9
0.85
22.0
32.0
-17.6
-29.9
43.9
64.0
-35.1
-59.8
1.00
22.6
33.5
-16.7
-28.7
45.2
67.0
-33.3
-57.3
1.40
23.5
35.0
-9.4
-20.4
46.9
70.0
-18.8
-40.7
1.50
23.6
35.3
-6.6
-17.1
47.2
70.5
-13.2
-34.1
1.65
23.8
35.5
-1.8
-11.4
47.5
71.0
-3.5
-22.7
1.80
23.9
35.7
3.8
-4.8
47.7
71.4
7.5
-9.6
1.95
24.0
35.9
9.8
2.5
48.0
71.8
19.6
5.0
The above characteristics are specified under nominal process variation / condition
Temperature (Tj): Nominal = 50 °C, VDDQ: Nominal = 1.80 V
Data Sheet
47
V1.4, 2004-04-30
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Package Outlines
4
Package Outlines
8 x 0.8 = 6.4
0.12 +0.01
-0.04
0.8
0.8
5)
1.7 ±0.03
D
4)
B
A
2)
4)
3)
8 x 0.8 = 6.4
0.3 D
20˚±5˚
1)
0.1 C
0.31±0.03
1.0 -0.2
0.1 C
0.41 ±0.03
54x
ø0.12
ø0.07
M
M
C
C SEATING PLANE
A B
1.5 2)
4.25
8
2.24
0.2
12
1) A1 Marking Ballside
2) Die Sort Fiducial
3) Bad Unit Marking (BUM)
4) Middle of Packages Edges
5) Middle of Ball Matrix
Figure 47
P-VFBGA-54-2 (Plastic Very Thin Fine Ball Grid Array Package)
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
SMD = Surface Mounted Device
Data Sheet
48
V1.4, 2004-04-30
www.infineon.com
Published by Infineon Technologies AG