Product Folder Sample & Buy Support & Community Tools & Software Technical Documents DS92LV2411, DS92LV2412 SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 DS92LV241x 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer 1 Features 3 Description • • • The DS92LV2411 (Serializer) and DS92LV2412 (Deserializer) chipset translates a parallel 24–bit LVCMOS data interface into a single high-speed CML serial interface with embedded clock information. This single serial stream eliminates skew issues between clock and data, reduces connector size and interconnect cost for transferring a 24-bit, or less, bus over FR-4 printed circuit board backplanes, differential or coax cables. 1 • • • • • • • • 24-Bit Data, 3–Bit Control, 5 to 50 MHz Clock Application Payloads up to 1.2 Gbps AC Coupled Interconnects: STP up to 10 m or Coax 20+ m 1.8 V or 3.3 V Compatible LVCMOS I/O Interface Integrated Terminations on Ser and Des AT-SPEED BIST Mode and Reporting Pin Configurable by Pins or I2C Compatible Serial Control Bus Power Down Mode Minimizes Power Dissipation >8 kV HBM ESD Rating SERIALIZER — DS92LV2411 – Supports Spread Spectrum Clocking (SSC) on Inputs – Data Scrambler for Reduced EMI – DC-Balance Encoder for AC Coupling – Selectable Output VOD and Adjustable Deemphasis DESERIALIZER — DS92LV2412 – Random Data Lock; no Reference Clock Required – Adjustable Input Receiver Equalization – LOCK (Real Time Link Status) Reporting Pin – Selectable Spread Spectrum Clock Generation (SSCG) and Output Slew Rate Control (OS) to Reduce EMI 2 Applications • • • • • • Embedded Video and Display Medical Imaging Factory Automation Office Automation — Printer, Scanner Security and Video Surveillance General Purpose Data Communication In addition to the 24-bit data bus interface, the DS92LV2411/12 also features a 3-bit control bus for slow speed signals. This allows implementing video and display applications with up to 24–bits per pixel (RGB888). Programmable transmit de-emphasis, receive equalization, on-chip scrambling and DC balancing enables long distance transmission over lossy cables and backplanes. The DS92LV2412 automatically locks to incoming data without an external reference clock or special sync patterns, providing easy “plugand-go” or “hot plug” operation. EMI is minimized by the use of low voltage differential signaling, receiver drive strength control, and spread spectrum clocking capability. The DS92LV2411/12 chipset is programmable though an I2C interface as well as through Pins. A built-in AT-SPEED BIST feature validates link integrity and may be used for system diagnostics. The DS92LV2411 is offered in a 48-Pin WQFN and the DS92LV2412 is offered in a 60-Pin WQFN package. Both devices operate over the full industrial temperature range of -40°C to +85°C. Device Information PART NUMBER PACKAGE BODY SIZE (NOM) DS92LV2411 WQFN (48) 7.00 mm × 7.00 mm DS92LV2412 WQFN (60) 9.00 mm × 9.00 mm 4 Typical Application Schematic VDDIO VDDn (1.8V or 3.3V) 1.8V DI[7:0] DI[15:8] DI[23:16] CI1 CI2 CI3 CLKIN Graphic Processor OR Video Imager OR ASIC/FPGA PDB Channel Link II 1 Pair / AC Coupled 0.1 PF 0.1 PF DOUT+ RIN+ DOUT- RIN100 ohm STP Cable DS92LV2411 Serializer BISTEN Optional VDDn VDDIO 1.8V (1.8V or 3.3V) CMF RFB VODSEL DeEmph SCL SDA ID[x] Optional DAP DS92LV2412 Deserializer PDB BISTEN DO[7:0] DO[15:8] DO[23:16] CO1 CO2 CO3 CLKOUT 24-bit RGB Display OR ASIC/FPGA LOCK PASS STRAP pins not shown SCL SDA ID[x] DAP 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DS92LV2411, DS92LV2412 SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. 1 Applications ........................................................... 1 Description ............................................................. 1 Typical Application Schematic............................. 1 Revision History..................................................... 2 Pin Configuration and Functions ......................... 3 Specifications....................................................... 10 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 8 Absolute Maximum Ratings .................................... ESD Ratings............................................................ Recommended Operating Conditions..................... Thermal Information ................................................ Serializer DC Electrical Characteristics .................. Deserializer DC Electrical Characteristics .............. DC and AC Serial Control Bus Characteristics....... Recommended Timing For The Serial Control Bus Recommended Serializer Timing For CLKIN.......... Serializer Switching Characteristics...................... Deserializer Switching Characteristics.................. Typical Characteristics .......................................... 10 10 10 11 11 12 13 14 18 19 20 21 Detailed Description ............................................ 22 8.1 8.2 8.3 8.4 8.5 8.6 9 Overview ................................................................. Functional Block Diagrams ..................................... Feature Description................................................. Device Functional Modes........................................ Programming........................................................... Register Maps ......................................................... 22 22 23 34 34 37 Applications and Implementation ...................... 40 9.1 Application Information............................................ 40 9.2 Typical Applications ................................................ 40 10 Power Supply Recommendations ..................... 44 11 Layout................................................................... 44 11.1 Layout Guidelines ................................................. 44 11.2 Layout Example .................................................... 44 12 Device and Documentation Support ................. 47 12.1 12.2 12.3 12.4 Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 47 47 47 47 13 Mechanical, Packaging, and Orderable Information ........................................................... 47 5 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (April 2014) to Revision E Page • Changed "Terminal" terminology back to "Pin" ..................................................................................................................... 1 • Added statement about checkerboard pattern from deserializer data output when in BIST mode ..................................... 32 • Added note that BISTEN pin must be high and REG = 0 to use BIST mode. .................................................................... 32 • Changed deserializer Reg 0x02[6] definition to match correct OSS_SEL behavior ............................................................ 38 Changes from Revision C (April 2013) to Revision D Page • Added Handling Ratings and Thermal Characteristics and updated datasheet to new layout. ............................................ 1 • Changed Serializer Supply current power down test condition from VDDIO from 13.6V to 3.6V .......................................... 12 • Added DC to "Deserializer Electrical Characteristics" .......................................................................................................... 12 • Changed typical value to 36mA instead of 37mA ............................................................................................................... 12 • Changed Test condition of VOUT for determining IOZ ........................................................................................................... 12 • Added max value for VIL when using 1.8V I/O LVCMOS .................................................................................................... 12 • Changed IOL from 3mA to 1.25mA ..................................................................................................................................... 13 • Changed parentheses location of UI equation for clarification ............................................................................................ 20 • Added characteristic graphics for serializer CML driver output and deserializer LVCMOS clock output ............................ 21 • Added applications graphics of the serializer output with and without de-emphasis .......................................................... 43 • Added layout example and stencil diagram graphics ........................................................................................................... 44 Changes from Revision B (April 2013) to Revision C • 2 Page Changed layout of National Data Sheet to TI format ........................................................................................................... 43 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 DS92LV2411, DS92LV2412 www.ti.com SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 6 Pin Configuration and Functions DI9 DI8 DI7 DI6 DI5 BISTEN VDDIO DI4 DI3 DI2 DI1 DI0 36 35 34 33 32 31 30 29 28 27 26 25 48-Pin WQFN Package RHS Top View DI10 37 24 VODSEL DI11 38 23 De-Emph DI12 39 22 VDDTX DI13 40 21 PDB DI14 41 20 DOUT+ 19 DOUT- 18 RES2 DI15 42 DI16 43 DS92LV2411 TOP VIEW DAP = GND DI17 44 17 VDDHS DI18 45 16 RES1 DI19 46 15 RES0 DI20 47 14 VDDP 13 CONFIG[1] 5 6 7 8 9 10 CI1 ID[x] VDDL SCL SDA CLKIN 12 4 CI3 CONFIG[0] 3 CI2 11 2 DI23 RFB 1 48 DI22 DI21 Pin Functions, DS92LV2411 Serializer (1) PIN NAME NO. TYPE DESCRIPTION LVCMOS PARALLEL INTERFACE CI1 5 I, LVCMOS w/ pull-down Control Signal Input For Display/Video Application: CI1 = Data Enable Input Control signal pulse width must be 3 clocks or longer to be transmitted when the Control Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00). The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter setting. CI2 3 I, LVCMOS w/ pull-down Control Signal Input For Display/Video Application: CI2 = Horizontal Sync Input Control signal pulse width must be 3 clocks or longer to be transmitted when the Control Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00). The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter setting. CI3 4 I, LVCMOS w/ pull-down Control Signal Input For Display/Video Application: CI3 = Vertical Sync Input CI3 is limited to 1 transition per 130 clock cycles. Thus, the minimum pulse width allowed is 130 clock cycle wide. (1) NOTE: 1 = HIGH, 0 = LOW The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on the PDB Pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage. Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 Submit Documentation Feedback 3 DS92LV2411, DS92LV2412 SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 www.ti.com Pin Functions, DS92LV2411 Serializer(1) (continued) PIN NAME NO. TYPE DESCRIPTION CLKIN 10 I, LVCMOS w/ pull-down Clock Input Latch/data strobe edge set by RFB Pin. DI[7:0] 34, 33, 32, 29, 28, 27, 26, 25 I, LVCMOS w/ pull-down Parallel Interface Data Input Pins For 8–bit RED Display: DI7 = R7 – MSB, DI0 = R0 – LSB. DI[15:8] 42, 41, 40, 39, 38, 37, 36, 35 I, LVCMOS w/ pull-down Parallel Interface Data Input Pins For 8–bit GREEN Display: DI15 = G7 – MSB, DI8 = G0 – LSB. DI[23:16] 2, 1, 48, 47, 46, 45, 44, 43 I, LVCMOS w/ pull-down Parallel Interface Data Input Pins For 8–bit BLUE Display: DI23 = B7 – MSB, DI16 = B0 – LSB. CONTROL AND CONFIGURATION BISTEN 31 I, LVCMOS w/ pull-down BIST Mode — Optional BISTEN = 0, BIST is disabled (normal operation) BISTEN = 1, BIST is enabled 13, 12 I, LVCMOS w/ pull-down 00: Control Signal Filter DISABLED. Interfaces with DS92LV2412 or DS92LV0412 01: Control Signal Filter ENABLED. Interfaces with DS92LV2412 or DS92LV0412 10: Reverse compatibility mode to interface with the DS90UR124 or DS99R124Q 11: Reverse compatibility mode to interface with the DS90C124 De-Emph 23 I, Analog w/ pull-up De-Emphasis Control De-Emph = open (float) - disabled To enable De-emphasis, tie a resistor from this Pin to GND or control via register. See Table 2. This can also be controlled by I2C register access. ID[x] 6 I, Analog I2C Serial Control Bus Device ID Address Select — Optional Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 11. PDB 21 I, LVCMOS w/ pull-down Power-down Mode Input PDB = 1, Ser is enabled (normal operation). Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section. PDB = 0, Ser is powered down When the Ser is in the power-down state, the driver outputs (DOUT+/-) are both logic high, the PLL is shutdown, IDD is minimized. Control Registers are RESET. 18, 16, 15 I, LVCMOS w/ pull-down Reserved - tie LOW RFB 11 I, LVCMOS w/ pull-down Clock Input Latch/Data Strobe Edge Select RFB = 1, parallel interface data and control signals are latched on the rising clock edge. RFB = 0, parallel interface data and control signals are latched on the falling clock edge. This can also be controlled by I2C register access. SCL 8 I, LVCMOS Open Drain I2C Serial Control Bus Clock Input - Optional SCL requires an external pull-up resistor to 3.3V. SDA 9 I/O, LVCMOS I2C Serial Control Bus Data Input / Output - Optional Open Drain SDA requires an external pull-up resistor 3.3V. VODSEL 24 I, LVCMOS w/ pull-down CONFIG[1: 0] RES[2:0] 4 Submit Documentation Feedback Differential Driver Output Voltage Select VODSEL = 1, CML VOD is ±420 mV, 840 mVp-p (typ) — long cable / De-Emph applications VODSEL = 0, CML VOD is ±280 mV, 560 mVp-p (typ) — short cable (no De-emph), low power mode. This is can also be control by I2C register. Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 DS92LV2411, DS92LV2412 www.ti.com SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 Pin Functions, DS92LV2411 Serializer(1) (continued) PIN NAME NO. TYPE DESCRIPTION CHANNEL-LINK II — CML SERIAL INTERFACE DOUT- 19 O, CML Inverting Output. The output must be AC Coupled with a 0.1 µF capacitor. DOUT+ 20 O, CML Non–Inverting Output. The output must be AC Coupled with a 0.1 µF capacitor. DAP Ground DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connect to the ground plane (GND) with at least 9 vias. VDDHS 17 Power TX High Speed Logic Power, 1.8 V ±5% VDDIO 30 Power LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10% VDDL 7 Power Logic Power, 1.8 V ±5% VDDP 14 Power PLL Power, 1.8 V ±5% VDDTX 22 Power Output Driver Power, 1.8 V ±5% POWER AND GROUND GND Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 Submit Documentation Feedback 5 DS92LV2411, DS92LV2412 SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 www.ti.com NC BISTEN VDDR PASS/OP_LOW DO0/MAP_SEL[0] DO1/MAP_SEL[1] DO2 VDDIO DO3/SSC0 DO4/SSC1 DO5/SSC2 DO6/SSC3 DO7 LOCK NC 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 60-Pin WQFN Package NKB Top View NC 46 30 NC RES 47 29 VDDL VDDIR 48 28 DO8/OSC_SEL0 RIN+ 49 27 DO9/OSC_SEL1 RIN- 50 26 DO10/OSC_SEL2 CMF 51 25 DO11 ROUT+ 52 DS92LV2412 ROUT- 53 TOP VIEW VDDCMLO 54 DAP = GND VDDR 55 ID[x] 56 BOLD PIN NAME ± indicates I/O strap pin associated with output pin VDDIO 23 DO12/EQ0 22 DO13/EQ1 21 DO14/EQ2 20 DO15/EQ3 19 DO16 PIN NO. 9 10 11 12 13 14 DO23/CONFIG[0] DO22/CONFIG[1] DO21/OS_CLKOUT DO20/LF_MODE VDDIO DO19/OS_DATA 15 8 CO2 TYPE NC 7 NC CO3 16 6 60 CO1 NC 5 DO18/OSS_SEL CLKOUT 17 4 59 VDDSC PDB 3 DO17/RFB SCL 18 2 58 SDA VDDSC 1 57 NC VDDPR Pin Functions, DS92LV2412 Deserializer NAME 24 (1) DESCRIPTION LVCMOS PARALLEL INTERFACE CLKOUT 5 O, LVCMOS Pixel Clock Output In power-down (PDB = 0), output is controlled by the OSS_SEL Pin (See Table 6). Data strobe edge set by RFB. CO1 6 O, LVCMOS Control Signal Output For Display/Video Application: CO1 = Data Enable Output Control signal pulse width must be 3 clocks or longer to be transmitted when the Control Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00). The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter setting. In power-down (PDB = 0), output is controlled by the OSS_SEL Pin (See Table 6). (1) 6 NOTE: 1 = HIGH, 0 = LOW The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on the PDB Pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 DS92LV2411, DS92LV2412 www.ti.com SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 Pin Functions, DS92LV2412 Deserializer PIN NAME NO. (1) (continued) TYPE DESCRIPTION CO2 8 O, LVCMOS Control Signal Output For Display/Video Application: CO2 = Horizontal Sync Output Control signal pulse width must be 3 clocks or longer to be transmitted when the Control Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00). The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter setting. In power-down (PDB = 0), output is controlled by the OSS_SEL Pin (See Table 6). CO3 7 O, LVCMOS Control Signal Output For Display/Video Application: CO3 = Vertical Sync Output CO3 is different than CO1 and CO2 because it is limited to 1 transition per 130 clock cycles. Thus, the minimum pulse width allowed is 130 clock cycle wide. The CONFIG[1:0] Pins have no affect on CO3 signal In power-down (PDB = 0), output is controlled by the OSS_SEL Pin (See Table 6). DO[7:0] 33, 34, 35, 36, 37, 39, 40, 41 I, STRAP, O, LVCMOS Parallel Interface Data Output Pins For 8–bit RED Display: DO7 = R7 – MSB, DO0 = R0 – LSB. In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 6). These Pins are inputs during power-up (See STRAP Inputs). DO[15:8] 20, 21, 22, 23, 25, 26, 27, 28 I, STRAP, O, LVCMOS Parallel Interface Data Output Pins For 8–bit GREEN Display: DO15 = G7 – MSB, DO8 = G0 – LSB. In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 6). These Pins are inputs during power-up (See STRAP Inputs). DO[23:16] 9, 10, 11, 12, 14, 17, 18, 19 I, STRAP, O, LVCMOS Parallel Interface Data Input Pins For 8–bit BLUE Display: DO23 = B7 – MSB, DO16 = B0 – LSB. In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 6). These Pins are inputs during power-up (See STRAP Inputs). LOCK 32 O, LVCMOS LOCK Status Output LOCK = 1, PLL is Locked, outputs are active LOCK = 0, PLL is unlocked, DO[23:0], CO1, CO2, CO3 and CLKOUT output states are controlled by OSS_SEL (See Table 6). May be used as Link Status or to flag when Video Data is active (ON/OFF). PASS 42 O, LVCMOS PASS Output (BIST Mode) PASS = 1, error free transmission PASS = 0, one or more errors were detected in the received payload Route to test point for monitoring, or leave open if unused. CONTROL AND CONFIGURATION — STRAP PINS (2) CONFIG[1:0] 10 [DO22], 9 [DO23] STRAP I, LVCMOS w/ pull-down 00: Control Signal Filter DISABLED. Interfaces with DS92LV2411 or DS92LV0411 01: Control Signal Filter ENABLED. Interfaces with DS92LV2411 or DS92LV0411 10: Reverse compatibility mode to interface with the DS90UR241 or DS99R241 11: Reverse compatibility mode to interface with the DS90C241 EQ[3:0] 20 [DO15], 21 [DO14], 22 [DO13], 23 [DO12] STRAP I, LVCMOS w/ pull-down Receiver Input Equalization (See Table 3). This can also be controlled by I2C register access. LF_MODE 12 [DO20] STRAP I, LVCMOS w/ pull-down SSCG Low Frequency Mode Only required when SSCG is enabled, otherwise LF_MODE condition is a DON’T CARE (X). LF_MODE = 1, SSCG in low frequency mode (CLK = 5-20 MHz) LF_MODE = 0, SSCG in high frequency mode (CLK = 20-50 MHz) This can also be controlled by I2C register access. 40[D], 41 [D] STRAP I, LVCMOS w/ pull-down Bit mapping reverse compatibility / DS90UR241 Options Pin or Register Control Default setting is b'00. MAP_SEL[1:0] (2) For a High State, use a 10 kΩ pull up to VDDIO; for a Low State, the IO includes an internal pull down. The STRAP Pins are read upon power-up and set device configuration. Pin Number listed along with shared data output name in square brackets. Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 Submit Documentation Feedback 7 DS92LV2411, DS92LV2412 SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 www.ti.com Pin Functions, DS92LV2412 Deserializer PIN NAME NO. TYPE (1) (continued) DESCRIPTION OP_LOW 42 [PASS] STRAP I, LVCMOS w/ pull-down Outputs held LOW when LOCK = 1 NOTE: Do not use any other strap options with this strap function enabled OP_LOW = 1: all outputs are held LOW during power up until released by programming OP_LOW release/set register HIGH. NOTE: Before the device is powered up, the outputs are in TRI-STATE See Figure 26 and Figure 27 OP_LOW = 0: all outputs toggle normally as soon as LOCK goes HIGH (default) This can also be controlled by I2C register access. OS_CLKOUT 11 [DO21] STRAP I, LVCMOS w/ pull-down Output CLKOUT Slew Select OS_CLKOUT = 1, Increased CLKOUT slew rate OS_CLKOUT = 0, Normal CLKOUT slew rate (default) This can also be controlled by I2C register access. OS_DATA 14 [DO19] STRAP I, LVCMOS w/ pull-down Output DO[23:0], CO1, CO2, CO3 Slew Select OS_DATA = 1, Increased DO slew rate OS_DATA = 0, Normal DO slew rate (default) This can also be controlled by I2C register access. OSS_SEL 17 [DO18] STRAP I, LVCMOS w/ pull-down Output Sleep State Select OSS_SEL is used in conjunction with PDB to determine the state of the outputs in Power Down (Sleep). (See Table 6). NOTE: OSS_SEL STRAP CANNOT BE USED IF OP_LOW = 1 This can also be controlled by I2C register access. RFB 18 [DO17] STRAP I, LVCMOS w/ pull-down Clock Output Strobe Edge Select RFB = 1, parallel interface data and control signals are strobed on the rising clock edge. RFB = 0, parallel interface data and control signals are strobed on the falling clock edge. This can also be controlled by I2C register access. OSC_SEL[2:0] 26 [DO10], 27 [DO9], 28 [DO8] STRAP I, LVCMOS w/ pull-down Oscillator Selectl (See Table 7 and Table 8). This can also be controlled by I2C register access. SSC[3:0] 34 [DO6], 35 [DO5], 36 [DO4], 37 [DO3] STRAP I, LVCMOS w/ pull-down Spread Spectrum Clock Generation (SSCG) Range Select (See Table 4 and Table 5). This can also be controlled by I2C register access. CONTROL AND CONFIGURATION BISTEN 44 I, LVCMOS w/ pull-down ID[x] 56 I, Analog NC 1, 15, 16, 30, 31, 45, 46, 60 BIST Enable Input — Optional BISTEN = 0, BIST is disabled (normal operation) BISTEN = 1, BIST is enabled I2C Serial Control Bus Device ID Address Select — Optional Resistor to Ground and 10 kΩ pull-up to 1.8V rail. (See Table 11). Not Connected Leave Pin open (float) PDB 59 I, LVCMOS w/ pull-down Power Down Mode Input PDB = 1, Des is enabled (normal operation). Refer to “Power Up Requirements and PDB Pin” in the Applications Information Section. PDB = 0, Des is in power-down. When the Des is in the power-down state, the LVCMOS output state is determined by Table 6. Control Registers are RESET. RES 47 I, LVCMOS w/ pull-down Reserved - tie LOW SCL 3 I, LVCMOS Open Drain I2C Serial Control Bus Clock Input - Optional SCL requires an external pull-up resistor to 3.3V. SDA 2 8 I/O, LVCMOS I2C Serial Control Bus Data Input / Output - Optional Open Drain SDA requires an external pull-up resistor to 3.3V. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 DS92LV2411, DS92LV2412 www.ti.com SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 Pin Functions, DS92LV2412 Deserializer PIN NAME NO. TYPE (1) (continued) DESCRIPTION CHANNEL-LINK II — CML SERIAL INTERFACE CMF 51 I, Analog Common-Mode Filter VCM center-tap is a virtual ground which may be AC coupled to ground to increase receiver common mode noise immunity. Recommended value is 4.7 μF or higher. RIN+ 49 I, CML True Input. The input must be AC Coupled with a 0.1 μF capacitor. RIN- 50 I, CML Inverting Input. The input must be AC Coupled with a 0.1 μF capacitor. ROUT+ 52 O, CML True Output — Receive Signal after the Equalizer NC if not used or connect to test point for monitor. Requires I2C control to enable. ROUT- 53 O, CML Inverting Output — Receive Signal after the Equalizer NC if not used or connect to test point for monitor. Requires I2C control to enable. DAP Ground DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connected to the ground plane (GND) with at least 9 vias. 54 Power RX High Speed Logic Power, 1.8 V ± 5% VDDIO 13, 24, 38 Power LVCMOS I/O Power, 1.8 V ± 5% OR 3.3 V ± 10% (VDDIO) VDDIR 48 Power Input Power, 1.8 V ±5% VDDL 29 Power Logic Power, 1.8 V ±5% POWER AND GROUND (3) GND VDDCMLO VDDPR 57 Power PLL Power, 1.8 V ±5% VDDR 43, 55 Power RX High Speed Logic Power, 1.8 V ±5% VDDSC 4, 58 Power SSCG Power, 1.8 V ±5% (3) Power must be supplied to all power Pins for normal operation Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 Submit Documentation Feedback 9 DS92LV2411, DS92LV2412 SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings (1) (2) (3) MIN MAX UNIT Supply Voltage – VDDn (1.8 V) −0.3 2.5 V Supply Voltage – VDDIO −0.3 4.0 V LVCMOS I/O Voltage −0.3 (VDDIO + 0.3) V Receiver Input Voltage −0.3 (VDD + 0.3) V Driver Output Voltage −0.3 (VDD + 0.3) V +150 °C +150 °C Junction Temperature −65 Storage Temperature Range (Tstg) (1) (2) (3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. For soldering specifications, see product folder at www.ti.com and http://www.ti.com/lit/SNOA549 7.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) Electrostatic discharge (1) UNIT ±8000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±1000 Machine Model (MM) ±250 V IEC61000–4–2), RD = 330Ω, CS = 150pF V(ESD) (1) (2) Electrostatic discharge Air Discharge (DOUT+, DOUT-) ±2500 Contact Discharge (DOUT+, DOUT-) ±800 Air Discharge (RIN+, DIN-) ±2500 Contact Discharge (RIN+, RIN-) ±800 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible if necessary precautions are taken. Pins listed as DOUT+, DOUT- or RIN+, DIN- may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible if necessary precautions are taken. Pins listed as DOUT+, DOUT- or RIN+, DIN- may actually have higher performance. 7.3 Recommended Operating Conditions MIN TYP MAX UNIT Supply Voltage (VDDn) 1.71 1.8 1.89 V LVCMOS Supply Voltage (VDDIO) 1.71 1.8 1.89 V OR LVCMOS Supply Voltage (VDDIO) Operating Free Air Temperature (TA) Clock Frequency 3.0 3.3 3.6 V −40 +25 +85 °C 5 Supply Noise (1) (1) 10 50 MHz 50 mVP-P Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8V) supply with amplitude = 100 mVp-p measured at the device VDDn Pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 750 kHz. The Des on the other hand shows no error when the noise frequency is less than 400 kHz. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 DS92LV2411, DS92LV2412 www.ti.com SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 7.4 Thermal Information THERMAL METRIC (1) RHS (2) NKB (3) 48 PINS 60 PINS RθJA Junction-to-ambient thermal resistance 27.1 24.6 RθJC(top) Junction-to-case (top) thermal resistance 4.5 2.8 (1) (2) (3) UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Ratings for maximum dissipation capacity (215 mW). Ratings for maximum dissipation capacity (478 mW). 7.5 Serializer DC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3) PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT LVCMOS INPUT DC SPECIFICATIONS VIH High Level Input Voltage VIL Low Level Input Voltage IIN Input Current VDDIO = 3.0 to 3.6V VDDIO = 1.71 to 1.89V VDDIO = 3.0 to 3.6V VDDIO = 1.71 to 1.89V VIN = 0V or VDDIO VDDIO = 3.0 to 3.6V DI[23:0], CI1,CI2,CI3, CLKIN, PDB, VODSEL, RFB, BISTEN, CONFIG[1:0] 2.2 VDDIO 0.65* VDDIO VDDIO GND 0.8 GND 0.35* VDDIO –15 ±1 +15 –15 ±1 +15 VODSEL = 0 ±205 ±280 ±355 VODSEL = 1 ±320 ±420 ±520 V V μA VDDIO = 1.71 to 1.89V CML DRIVER DC SPECIFICATIONS VOD Differential Output Voltage VODp-p Differential Output Voltage (DOUT+) – (DOUT-) RL = 100Ω, Deemph = disabled, Figure 2 VODSEL = 0 560 mVp-p VODSEL = 1 840 mVp-p RL = 100Ω, Deemph = disabled, VODSEL = L ΔVOD 1 VOS Offset Voltage – Single-ended At TP A and B, Figure 1 RL = 100Ω, Deemph = disabled RL = 100Ω, De-emph = disabled ΔVOS Offset Voltage Unbalance Singleended At TP A and B, Figure 1 IOS Output Short Circuit Current RTO Internal Output Termination Resistor (1) (2) (3) DOUT+/- = 0V, De-emph = disabled mV VODSEL = 0 VODSEL = 1 DOUT+, DOUT- VODSEL = 0 80 50 mV 0.65 V 1.575 V 1 mV –36 mA 100 120 Ω The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Typical values represent most likely parametric norms at VDD = 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. Current into device Pins is defined as positive. Current out of a device Pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD, VTH and VTL which are differential voltages. Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 Submit Documentation Feedback 11 DS92LV2411, DS92LV2412 SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 www.ti.com Serializer DC Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3) PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT 75 85 mA 3 5 mA 11 15 mA 65 75 mA 3 5 mA 11 15 mA 40 1000 µA 5 10 µA 10 20 µA TYP MAX UNIT 2.2 VDDIO V GND 0.8 V +15 μA SUPPLY CURRENT IDDT1 IDDIOT1 Serializer Supply Current (includes load current) RL = 100 Ω, CLKIN = 50 MHz IDDT2 IDDIOT2 Serializer Supply Current Power-down IDDZ Checker Board VDD = 1.89V Pattern, De-emph VDDIO = 1.89V = 3kΩ, VODSEL VDDIO = 3.6V = H, Figure 9 All VDD Pins Checker Board VDD33 = 1.89V Pattern, De-emph VDDIO = 1.89V = 6kΩ, VODSEL VDDIO = 3.6V = L, Figure 9 All VDD Pins PDB = 0V , (All other LVCMOS Inputs = 0V) All VDD Pins IDDIOZ VDD33 = 1.89V VDDIO = 1.89V VDDIO = 3.6V VDDIO VDDIO VDDIO 7.6 Deserializer DC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (1) PARAMETER TEST CONDITIONS PIN/FREQ. (2) (3) MIN 3.3 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 3.0 to 3.6V VIH High Level Input Voltage VIL Low Level Input Voltage IIN Input Current VIN = 0V or VDDIO VOH High Level Output Voltage IOH = −0.5 mA, RDS = L VOL Low Level Output Voltage IOL = +0.5 mA, RDS = L IOS Output Short Circuit Current IOZ TRI-STATE Output Current PDB, BISTEN DO[23:0], CO1, CO2, CO3, CLKOUT, LOCK, PASS VDDIO = 3.3V, VOUT = 0V, OS_PCLK/DATA = L/H CLKOUT VDDIO = 3.3V, VOUT = 0V, OS_PCLK/DATA = L/H Outputs –15 ±1 2.4 VDDIO GND V V 0.4 36 PDB = 0V, OSS_SEL = 0V, VOUT = H Outputs V mA –15 +15 μA 1.235 VDDIO V GND 0.595 V +15 µA 1.8 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 1.71 to 1.89V VIH High Level Input Voltage VIL Low Level Input Voltage IIN Input Current VIN = 0V or VDDIO VOH High Level Output Voltage IOH = −0.5 mA, RDS = L VOL Low Level Output Voltage IOL = +0.5 mA, RDS = L IOS Output Short Circuit Current (1) (2) (3) 12 PDB, BISTEN DO[23:0], CO1, CO2, CO3, CLKOUT, LOCK, PASS –15 ±1 VDDIO – 0.45 VDDIO GND V 0.45 V VDDIO = 1.8V, VOUT = 0V, OS_PCLK/DATA = L/H CLKOUT 18 mA VDDIO = 1.8V, VOUT = 0V, OS_PCLK/DATA = L/H Outputs 18 mA The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Typical values represent most likely parametric norms at VDD = 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. Current into device Pins is defined as positive. Current out of a device Pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD, VTH and VTL which are differential voltages. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 DS92LV2411, DS92LV2412 www.ti.com SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 Deserializer DC Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3) PARAMETER TRI-STATE Output Current IOZ TEST CONDITIONS PIN/FREQ. MIN PDB = 0V, OSS_SEL = 0V, VOUT = H Outputs TYP –15 MAX UNIT +15 µA CML RECEIVER DC SPECIFICATIONS VTH Differential Input VCM = +1.2V (Internal VBIAS) Threshold High Voltage VTL Differential Input Threshold Low Voltage VCM Common Mode Voltage, Internal VBIAS IIN Input Current RTI Internal Input Termination Resistor RIN+, RIN- +50 mV –50 mV 12 VIN = 0V or VDDIO –15 RIN+, RIN- 80 100 V +15 µA 120 Ω LOOP THROUGH CML DRIVER OUTPUT DC SPECIFICATIONS – EQ TEST PORT Differential Output Voltage RL = 100Ω VOS Offset Voltage Singleended RL = 100Ω RT Internal Termination Resistor VOD 542 mV 1.4 V ROUT+/- ROUT+/- 80 100 120 Ω 93 110 mA 33 45 mA 62 75 mA 40 3000 µA SUPPLY CURRENT Checker Board Pattern, RDS = H, CL = 4pF, Figure 9 VDD = 1.89V IDDIO1 Deserializer Supply Current (includes load current) CLKOUT = 50 MHz IDDZ Deserializer Supply Current Power Down PDB = 0V, All other LVCMOS Inputs = 0V VDD = 1.89V IDD1 IDDIOZ VDDIO = 1.89V VDDIO = 3.6V VDDIO = 1.89V VDDIO = 3.6V All VDD Pins VDDIO All VDD Pins VDDIO 5 50 µA 10 100 µA TYP MAX UNIT 7.7 DC and AC Serial Control Bus Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. PARAMETER TEST CONDITIONS MIN VIH Input High Level SDA and SCL 2.2 VDD 3.3V VIL Input Low Level Voltage SDA and SCL GND 0.8 VHY Input Hysteresis VOL Output Low Voltage (1) Iin tR SDA RiseTime – READ tF tSU;DAT >50 V V mV SDA, IOL = 1.25mA, VDDIO = 3.3V 0 0.4 V SDA or SCL, Vin = VDDIO or GND -15 +15 µA SDA, RPU = X, Cb ≤ 400pF 40 ns SDA Fall Time – READ 25 ns Set Up Time — READ 520 ns tHD;DAT Hold Up Time — READ 55 ns tSP Input Filter 50 ns Cin Input Capacitance <5 pF (1) SDA or SCL Specification is ensured by characterization and is not tested in production. Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 Submit Documentation Feedback 13 DS92LV2411, DS92LV2412 SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 www.ti.com 7.8 Recommended Timing For The Serial Control Bus Over recommended operating supply and temperature ranges unless otherwise specified. PARAMETER fSCL tLOW tHIGH tHD;STA tSU:STA tHD;DAT tSU;DAT tSU;STO tBUF tr tf TEST CONDITIONS SCL Clock Frequency SCL Low Period MIN TYP MAX UNIT Standard Mode 100 kHz Fast Mode 400 kHz Standard Mode 4.7 µs Fast Mode 1.3 µs Standard Mode 4.0 µs Fast Mode 0.6 µs Hold time for a start or a repeated start condition, Figure 18 Standard Mode 4.0 µs Fast Mode 0.6 µs Set Up time for a start or a repeated start condition, Figure 18 Standard Mode 4.7 µs Fast Mode 0.6 µs Data Hold Time, Figure 18 Standard Mode 0 3.45 µs Fast Mode 0 0.9 µs Data Set Up Time, Figure 18 Standard Mode 250 Fast Mode 100 ns Set Up Time for STOP Condition, Figure 18 Standard Mode 4.0 µs Fast Mode 0.6 µs Bus Free Time Between STOP and START, Figure 18 Standard Mode 4.7 µs Fast Mode 1.3 µs SCL and SDA Rise Time, Figure 18 Standard Mode 1000 ns Fast Mode 300 ns SCL and SDA Fall Time, Figure 18 Standard Mode 300 ns Fast mode 300 ns SCL High Period A A' CA ns Scope 50: 50: CB B B' 50: 50: Single-Ended Figure 1. Serializer Test Circuit DOUT+ VOD- VOD+ DOUT- VOS VOD+ (DOUT+) - (DOUT+) VODp-p 0V VOD- Differential GND Figure 2. Serializer Output Waveforms 14 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 DS92LV2411, DS92LV2412 www.ti.com SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 +VOD 80% (DOUT+) - (DOUT-) 0V 20% -VOD tLLHT tLHLT Figure 3. Serializer Output Transition Times tTCIH tTCP CLKIN w/ RFB = L tTCIL 80% 20% 1/2 VDDIO tCLKT GND tCLKT VDDIO VIHmin VILmax DI[23:0], CI1,CI2,CI3 VDDIO GND tDIS tDIH Figure 4. Serializer Input CLKIN Waveform And Set And Hold Times PDB CLKIN 1/2 VDDIO "X" active tPLD DOUT (Diff.) Driver On Driver OFF, VOD = 0V Figure 5. Serializer Lock Time 1/2 VDDIO PDB CLKIN active "X" tXZD DOUT (Diff.) active Driver OFF, VOD = 0V Figure 6. Serializer Disable Time Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 Submit Documentation Feedback 15 DS92LV2411, DS92LV2412 SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 DIN[23:0], CI1,CI2,CI3 SYMBOL N www.ti.com SYMBOL N+1 tSD CLKIN (RFB = L) START BIT STOP START BIT BIT STOP BIT DOUT (Diff.) SYMBOL N-1 SYMBOL N Figure 7. Serializer Latency Delay tDJIT tDJIT VOD (+) DOUT (Diff.) TxOUT_E_O 0V VOD (-) tBIT (1 UI) Figure 8. Serializer Output Jitter VDDIO CLKIN/ CLKOUT w/ RFB = L GND VDDIO DI/DO (odd), CI2/CO2, CI3/CO3 GND VDDIO DI/DO (even), CI1/CO1 GND Figure 9. Checkerboard Data Pattern VDDIO 80% 20% GND tCLH tCHL Figure 10. Deserializer LVCMOS Transition Times START BIT STOP START BIT BIT STOP BIT RIN (Diff.) SYMBOL N SYMBOL N+1 tDD CLKOUT (RFB = L) DO[23:0], CO1,CO2,CO3 SYMBOL N-2 SYMBOL N-1 SYMBOL N Figure 11. Deserializer Delay – Latency 16 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 DS92LV2411, DS92LV2412 www.ti.com SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 1/2 VDDIO PDB RIN (Diff.) active "X" tXZR CLKOUT, DO[23:0], CO1,CO2,CO3 PASS, LOCK active Z (TRI-STATE) Figure 12. Deserializer Disable Time (OSS_SEL = 0) PDB 2.0V 0.8V RIN (Diff.) 'RQ¶W&DUH tDDLT LOCK TRI-STATE or LOW Z or L tRxZ DO[23:0], CO1,CO2,CO3 TRI-STATE or LOW or Pulled Up CLKOUT (RFB = L) Z or L or PU TRI-STATE or LOW OFF IN LOCK TIME Z or L ACTIVE OFF Figure 13. Deserializer PLL Lock Times And PDB Tri-State Delay VDDIO CLKOUT w/RFB = H 1/2 VDDIO GND VDDIO DO[23:0], CO1,CO2,CO3 1/2 VDDIO 1/2 VDDIO GND tROS tROH Figure 14. Deserializer Output Data Valid (Setup And Hold) Times With SSCG = Off VDDIO CLKOUT w/RFB = H 1/2 VDDIO GND DO[23:0], CO1,CO2,CO3 1/2 VDDIO tROS 1/2 VDDIO tROH VDDIO GND Figure 15. Deserializer Output Data Valid (Setup And Hold) Times With SSCG = On Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 Submit Documentation Feedback 17 DS92LV2411, DS92LV2412 SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 www.ti.com Ideal Data Bit End Sampling Window Ideal Data Bit Beginning RxIN_TOL Left VTH 0V VTL RxIN_TOL Right Ideal Center Position (tBIT/2) tBIT (1 UI) tRJIT = RxIN_TOL (Left + Right) - tRJIT Sampling Window = 1 UI Figure 16. Receiver Input Jitter Tolerance BISTEN 1/2 VDDIO tPASS PASS (w/ errors) 1/2 VDDIO Current BIST Test - Toggle on Error Prior BIST Result Result Held Figure 17. BIST Pass Waveform SDA tLOW tf tHD;STA tr tf tr tBUF tSP SCL tSU;STA tHD;STA tHIGH tHD;DAT tSU;STO tSU;DAT START STOP REPEATED START START Figure 18. Serial Control Bus Timing Diagram 7.9 Recommended Serializer Timing For CLKIN Over recommended operating supply and temperature ranges unless otherwise specified. PARAMETER MIN TYP MAX UNIT 20 T 200 ns Transmit Input CLKIN High Time 0.4T 0.5T 0.6T ns tTCIL Transmit Input CLKIN Low Time 0.4T 0.5T 0.6T ns tCLKT CLKIN Input Transition Time SSCIN CLKIN Input – Spread Spectrum at 50 MHz tTCP Transmit Input CLKIN Period tTCIH 18 Submit Documentation Feedback TEST CONDITIONS 5 MHz to 50 MHz, Figure 4 0.5 fmod fdev 2.4 ns 35 kHz ±0.02 fMOD kHz Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 DS92LV2411, DS92LV2412 www.ti.com SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 7.10 Serializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. PARAMETER tLHT Ser Output Low-to-High Transition Time, Figure 3 tHLT Ser Output High-to-Low Transition Time, Figure 3 TEST CONDITIONS MIN TYP MAX UNIT RL = 100Ω, De-emphasis = disabled, VODSEL = 0 200 ps RL = 100Ω, De-emphasis = disabled, VODSEL = 1 200 ps RL = 100Ω, De-emphasis = disabled, VODSEL = 0 200 ps RL = 100Ω, De-emphasis = disabled, VODSEL = 1 200 ps tDIS Input Data - Setup Time, Figure 4 DI[23:0], CI1, CI2, CI3 to CLKIN tDIH Input Data - Hold Time, Figure 4 CLKIN to DI[23:0], CI1, CI2, CI3 tXZD Ser Output Active to OFF Delay, Figure 6 tPLD Serializer PLL Lock Time (1), RL = 100Ω Figure 5 tSD Serializer Delay - Latency, Figure 7 RL = 100Ω tDJIT Ser Output Total Jitter, Figure 8 RL = 100Ω, De-Emph = disabled, RANDOM pattern, CLKIN = 50 MHz 0.28 UI RL = 100Ω, De-Emph = disabled, RANDOM pattern, CLKIN = 43MHz 0.27 UI RL = 100Ω, De-Emph = disabled, RANDOM pattern, CLKIN = 5MHz 0.35 UI λSTXBW δSTX (1) Serializer Jitter Transfer Function -3 dB Bandwidth Serializer Jitter Transfer Function Peaking 2 ns 2 ns 8 15 ns 1.4 10 ms 144*T 145*T ns CLKIN = 50 MHz 3 MHz CLKIN = 43 MHz 2.3 MHz CLKIN = 20 MHz 1.3 MHz CLKIN = 5MHz 650 kHz CLKIN = 50 MHz 0.84 dB CLKIN = 43 MHz 0.83 dB CLKIN = 20 MHz 0.83 dB CLKIN = 5MHz 0.28 dB When the Serializer output is at TRI-STATE the Deserializer will lose PLL lock. Resynchronization / Relock must occur before data transfer require tPLD Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 Submit Documentation Feedback 19 DS92LV2411, DS92LV2412 SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 www.ti.com 7.11 Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. PARAMETER TEST CONDITIONS PIN/FREQ. TYP MAX UNIT tRCP CLK Output Period tRCP = tTCP 20 T 200 ns tRDC CLK Output Duty Cycle SSCG = OFF, 5 – 50MHz 0.43T 0.50T 0.57T ns SSCG = ON, 5 – 20 MHz 0.35T 0.59T 0.65T ns SSCG = ON, 20 – 50 MHz 0.40T 0.53T 0.60T ns tCLH LVCMOS Low-to-High Transition Time, Figure 10 tCHL LVCMOS High-to-Low Transition Time, Figure 10 tROS tROH tDDLT VDDIO = 1.8V, CL = 4pF, OS_CLKOUT/DATA = L CLKOUT MIN CLKOUT/DO[23:0], CO1, CO2, CO3 VDDIO = 3.3V CL = 4pF, OS_CLKOUT/DATA = H VDDIO = 1.8V CL = 4pF, OS_CLKOUT/DATA = L CLKOUT/DO[23:0], CO1, CO2, CO3 VDDIO = 3.3V CL = 8 pF, OS_CLKOUT/DATA = H 2.0 ns 1.6 ns 1.5 ns VDDIO = 1.71 to 1.89V or VDDIO = 3.0 to 3.6V CL = 4pF (lumped load) DO[23:0], CO1, CO2, CO3 0.27 0.45 T Data Valid after CLKOUT – Hold Time, Figure 14 VDDIO = 1.71 to 1.89V or VDDIO = 3.0 to 3.6V CL = 4pF (lumped load) DO[23:0], CO1, CO2, CO3 0.4 0.55 T Deserializer Lock Time, Figure 13 SSC[3:0] = OFF, See (1) CLKOUT = 5MHz SSC[3:0] = OFF, See (1) CLKOUT = 50MHz SSC[3:0] = ON, See (1) CLKOUT = 5MHz SSC[3:0] = ON, See (1) CLKOUT = 50MHz Des Delay - Latency, Figure 11 SSC[3:0] = ON, See (2) CLKOUT = 5 to 50 MHz tDPJ Des Period Jitter SSC[3:0] = OFF, See (3) Des Cycle-to-Cycle Jitter tIIT ns Data Valid before CLKOUT – Set Up Time, Figure 14 tDD tDCCJ 2.1 Des Input Jitter Tolerance, Figure 16 SSC[3:0] = OFF, See (2) EQ = OFF, SSCG = OFF, CLKOUT = 50 MHz 3 ms 4 ms 30 ms 6 ms 139*T 140*T ns CLKOUT = 5MHz 975 1700 ps CLKOUT = 10MHz 500 1000 ps CLKOUT = 50MHz 550 1250 ps CLKOUT = 5MHz 675 1150 ps CLKOUT = 10MHz 375 900 ps CLKOUT = 50MHz 500 1150 jitter freq <2MHz 0.9 UI (4) jitter freq >6MHz 0.5 UI (4) ps BIST MODE tPASS BIST PASS Valid Time, BISTEN = 1, Figure 17 1 10 µs SSCG MODE fDEV fMOD (1) (2) (3) (4) 20 Spread Spectrum Clocking Deviation Frequency Under typical conditions Spread Spectrum Clocking Modulation Frequency Under typical conditions CLKOUT = 5 to 50 MHz, SSC[3:0] = ON CLKOUT = 5 to 50 MHz, SSC[3:0] = ON ±0.005 fMOD ±0.02 fMOD KHz 8 100 kHz tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active clock. tDCCJ is the maximum amount of jitter between adjacent clock cycles. tDPJ is the maximum amount the period is allowed to deviate over many samples. UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / (28*CLK) ). The UI scales with clock frequency. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 DS92LV2411, DS92LV2412 www.ti.com SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 7.12 Typical Characteristics 50 MHz TX Pixel Clock Input (2 V/DIV) CML Serializer Data Throughput (100 mV/DIV) 50 MHz RX Pixel Clock Input (2 V/DIV) Time (1 ns/DIV) Time (20 ns/DIV) Note: On the rising edge of each clock period, the CML driver outputs Note: When both devices are locked and the scope is triggered from a low Stop bit, high Start bit, and 28 DC-scrambled data bits. the TX pixel clock, the RX clock is genlocked to the TX pixel clock and does not drift. Figure 19. Serializer CML Driver Output with 50 MHz TX Figure 20. Comparison of Deserializer LVCMOS RX Clock Pixel Clock. Output locked to a 50 MHz TX Pixel Clock. Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 Submit Documentation Feedback 21 DS92LV2411, DS92LV2412 SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 www.ti.com 8 Detailed Description 8.1 Overview The DS92LV2411 / DS92LV2412 chipset transmits and receives 24-bits of data and 3 control signals over a single serial CML pair operating at 140 Mbps to 1.4 Gbps. The serial stream also contains an embedded clock, video control signals and the DC-balance information which enhances signal quality and supports AC coupling. The Des can attain lock to a data stream without the use of a separate reference clock source, which greatly simplifies system complexity and overall cost. The Des also synchronizes to the Ser regardless of the data pattern, delivering true automatic “plug and lock” performance. It can lock to the incoming serial stream without the need of special training patterns or sync characters. The Des recovers the clock and data by extracting the embedded clock information, validating and then deserializing the incoming data stream providing a parallel LVCMOS video bus to the display or ASIC/FPGA. The DS92LV2411 / DS92LV2412 chipset can operate in 24-bit color depth (with DE, HS, VS encoded within the serial data stream). In 18–bit color applications, the three video control signals maybe sent encoded within the serial bit stream (restrictions apply) along with six additional general purpose signals. 8.2 Functional Block Diagrams RFB CLKIN PLL Parallel to Serial Input Latch DI[23:0] CI1/DE CI2/HS CI3/VS DC Balance Encoder VODSEL De-Emph DOUT+ DOUT- Pattern Generator CONFIG[1:0] PDB SCL SCA ID[x] Timing and Control BISTEN DS92LV2411 ± SERIALIZER 22 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 DS92LV2411, DS92LV2412 www.ti.com SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 Functional Block Diagrams (continued) SSCG RIN+ EQ RIN- Output Latch CMF DC Balance Decoder ROUT- Serial to Parallel ROUT+ Error Detector BISTEN PDB SCL SCA ID[x] Timing and Control Clock and Data Recovery DO[23:0] CO1/DE CO2/HS CO3/VS PASS STRAP INPUT LF_MODE OS_CLKOUT OS_DATA OSS_SEL RFB EQ [3:0] OSC_SEL [2:0] SSC [3:0] CONFIG [1:0] MAP_SEL [1:0] STRAP INPUT OP_LOW CLKOUT LOCK DS92LV2412 ± DESERIALIZER 8.3 Feature Description 8.3.1 Serializer Functional Description The Ser converts a wide parallel input bus to a single serial output data stream, and also acts as a signal generator for the chipset Built In Self Test (BIST) mode. The device can be configured via external Pins or through the optional serial control bus. The Ser features enhance signal quality on the link by supporting: a selectable VOD level, a selectable de-emphasis signal conditioning and also the Channel Link II data coding that provides randomization, scrambling, and DC Balancing of the data. The Ser includes multiple features to reduce EMI associated with display data transmission. This includes the randomization and scrambling of the data and also the system spread spectrum clock support. The Ser features power saving features with a sleep mode, auto stop clock feature, and optional LVCMOS (1.8 V) parallel bus compatibility. 8.3.1.1 EMI Reduction Features 8.3.1.1.1 Data Randomization and Scrambling Channel Link II Ser / Des feature a 3 step encoding process which enables the use of AC coupled interconnects and also helps to manage EMI. The serializer first passes the parallel data through a scrambler which randomizes the data. The randomized data is then DC balanced. The DC balanced and randomized data then goes through a bit shuffling circuit and is transmitted out on the serial line. This encoding process helps to prevent static data patterns on the serial stream. The resulting frequency content of the serial stream ranges from the parallel clock frequency to the nyquist rate. For example, if the Ser / Des chip set is operating at a parallel clock frequency of 50 MHz, the resulting frequency content of serial stream ranges from 50 MHz to 700 MHz ( 50 MHz *28 bits = 1.4 Gbps / 2 = 700 MHz ). 8.3.1.1.2 Ser — Spread Spectrum Compatibility The Ser CLKIN is capable of tracking spread spectrum clocking (SSC) from a host source. The CLKIN will accept spread spectrum tracking up to 35 kHz modulation and ±0.5, ±1 or ±2% deviations (center spread). The maximum conditions for the CLKIN input are: a modulation frequency of 35 kHz and amplitude deviations of ±2% (4% total). Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 Submit Documentation Feedback 23 DS92LV2411, DS92LV2412 SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 www.ti.com Feature Description (continued) 8.3.1.2 Integrated Signal Conditioning Features — Ser 8.3.1.2.1 Ser — VOD Select (VODSEL) The Ser differential output voltage may be increased by setting the VODSEL Pin High. When VODSEL is Low, the VOD is at the standard (default) level. When VODSEL is High, the VOD is increased in level. The increased VOD is useful in extremely high noise environments and also on extra long cable length applications. When using de-emphasis it is recommended to set VODSEL = H to avoid excessive signal attenuation especially with the larger de-emphasis settings. This feature may be controlled by the external Pin or by register. Table 1. Differential Output Voltage INPUT EFFECT VODSEL VOD mV VOD mVp-p H ±420 840 L ±280 560 8.3.1.2.2 Ser — De-Emphasis (De-Emph) The De-Emph Pin controls the amount of de-emphasis beginning one full bit time after a logic transition that the Ser drives. This is useful to counteract loading effects of long or lossy cables. This Pin should be left open for standard switching currents (no de-emphasis) or if controlled by register. De-emphasis is selected by connecting a resistor on this Pin to ground, with R value between 0.5 kΩ to 1 MΩ, or by register setting. When using DeEmphasis it is recommended to set VODSEL = H. Table 2. De-Emphasis Resistor Value RESISTOR VALUE (kΩ) DE-EMPHASIS SETTING Open Disabled 0.6 - 12 dB 1.0 - 9 dB 2.0 - 6 dB 5.0 - 3 dB 0.00 VDD = 1.8V, -2.00 TA = 25oC DE-EMPH (dB) -4.00 -6.00 -8.00 -10.00 -12.00 -14.00 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 R VALUE - LOG SCALE (:) Figure 21. De-Emph vs. R Value 24 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 DS92LV2411, DS92LV2412 www.ti.com SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 8.3.1.3 Power Saving Features 8.3.1.3.1 Ser — Power Down Feature (PDB) The Ser has a PDB input Pin to ENABLE or POWER DOWN the device. This Pin is controlled by the host and is used to save power, disabling the link when the it is not needed. In the POWER DOWN mode, the high-speed driver outputs are both pulled to VDD and present a 0V VOD state. Note – in POWER DOWN, the optional Serial Bus Control Registers are RESET. 8.3.1.3.2 Ser — Stop Clock Feature The Ser will enter a low power SLEEP state when the CLKIN is stopped. A STOP condition is detected when the input clock frequency is less than 3 MHz. The clock should be held at a static Low or high state. When the CLKIN starts again, the Ser will then lock to the valid input clock and then transmits the serial data to the Des. Note – in STOP CLOCK SLEEP, the optional Serial Bus Control Registers values are RETAINED. 8.3.1.3.3 1.8 V or 3.3 V VDDIO Operation The Ser parallel bus and Serial Bus Interface can operate with 1.8 V or 3.3 V levels (VDDIO) for host compatibility. The 1.8 V levels will offer lower noise (EMI) and also a system power savings. 8.3.1.4 Ser — Pixel Clock Edge Select (RFB) The RFB Pin determines the edge that the data is latched on. If RFB is High, input data is latched on the Rising edge of the CLKIN. If RFB is Low, input data is latched on the Falling edge of the CLKIN. Ser and Des maybe set differently. This feature may be controlled by the external Pin or by register. 8.3.1.5 Optional Serial Bus Control Please see the following section on the optional Serial Bus Control Interface. 8.3.1.6 Optional BIST Mode Please see the following section on the chipset BIST mode for details. 8.3.2 Deserializer Functional Description The Des converts a single input serial data stream to a wide parallel output bus, and also provides a signal check for the chipset Built In Self Test (BIST) mode. The device can be configured via external Pins and strap Pins or through the optional serial control bus. The Des features enhance signal quality on the link with an integrated equalizer on the serial input and Channel Link II data encoding which provides randomization, scrambling, and DC balancing of the data. The Des includes multiple features to reduce EMI associated with data transmission. This includes the randomization and scrambling of the data, the output spread spectrum clock generation (SSCG) support and output clock and data slew rate select. The Des features power saving features with a power down mode, and optional LVCMOS (1.8 V) interface compatibility. 8.3.2.1 Integrated Signal Conditioning Features — Des 8.3.2.1.1 Des — Input Equalizer Gain (Eq) The Des can enable receiver input equalization of the serial stream to increase the eye opening to the Des input. Note this function cannot be seen at the RxIN+/- input but can be observed at the serial test port (ROUT+/-) enabled via the Serial Bus control registers. The equalization feature may be controlled by the external Pin or by register. Table 3. Receiver Equalization Configuration INPUTS EFFECT EQ3 EQ2 EQ1 EQ0 L L L H L L H H ~3 dB L H L H ~4.5 dB L H H H ~6 dB Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 ~1.5 dB Submit Documentation Feedback 25 DS92LV2411, DS92LV2412 SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 www.ti.com Table 3. Receiver Equalization Configuration (continued) INPUTS EQ3 EQ2 H H EFFECT EQ1 EQ0 L L H L H H ~9 dB H H L H ~10.5 dB H H H H ~12 dB X X X L OFF* ~7.5 dB * Default Setting is EQ = Off 8.3.2.2 EMI Reduction Features 8.3.2.2.1 Des — Output Slew Rate Select (OS_CLKOUT/OS_DATA) The parallel data outputs and clock outputs of the deserializer feature selectable output slew rates. The slew rate of the CLKOUT Pin is controlled by the strap Pin or register OS_CLKOUT, while the data outputs (DO[23:0] and CO[3:1]) are controlled by the strap Pin or register OS_DATA. When OS_CLKOUT/DATA = HIGH, the maximum slew rate is selected. When the OS_CLKOUT/DATA = LOW, the minimum slew rate is selected. Use the higher slew rate when driving longer traces or a heavier capacitive load. 8.3.2.2.2 Des — Common Mode Filter Pin (CMF) — Optional The Des provides access to the center tap of the internal termination. A capacitor may be placed on this Pin for additional common-mode filtering of the differential pair. This can be useful in high noise environments for additional noise rejection capability. A 4.7 µF capacitor may be connected to this Pin to Ground. 8.3.2.2.3 Des — SSCG Generation — Optional The Des provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both clock and data outputs are modulated. This will aid to lower system EMI. Output SSCG deviations to ±2% (4% total) at up to 100 kHz modulations is available. See Table 4. This feature may be controlled by external STRAP Pins or by register. Table 4. SSCG Configuration (LF_MODE = L) — Des Output SSC[3:0] INPUTS LF_MODE = L (20 - 50 MHz) 26 RESULT SSC3 SSC2 SSC1 SSC0 fdev (%) fmod (kHz) L L L L NA Disable L L L H ±0.5 L L H L ±1.0 L L H H ±1.5 L H L L ±2.0 L H L H ±0.5 L H H L ±1.0 L H H H ±1.5 H L L L ±2.0 H L L H ±0.5 H L H L ±1.0 H L H H ±1.5 H H L L ±2.0 H H L H ±0.5 H H H L ±1.0 H H H H ±1.5 Submit Documentation Feedback CLK/2168 CLK/1300 CLK/868 CLK/650 Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 DS92LV2411, DS92LV2412 www.ti.com SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 Table 5. SSCG Configuration (Lf_mode = H) — Des Output SSC[3:0] INPUTS LH_MODE = H (5 - 20 MHz) RESULT SSC3 SSC2 SSC1 SSC0 fdev (%) fmod (kHz) L L L L L L L NA Disable H ±0.5 L L H L ±1.0 L L H H ±1.5 L H L L ±2.0 L H L H ±0.5 L H H L ±1.0 L H H H ±1.5 H L L L ±2.0 H L L H ±0.5 H L H L ±1.0 H L H H ±1.5 H H L L ±2.0 H H L H ±0.5 H H H L ±1.0 H H H H ±1.5 CLK/620 CLK/370 CLK/258 CLK/192 Frequency fdev(max) FCLKOUT+ FCLKOUT FCLKOUT- fdev(min) Time 1/fmod Figure 22. SSCG Waveform 8.3.2.2.4 1.8 V or 3.3 V VDDIO Operation The Des parallel bus and Serial Bus Interface can operate with 1.8 V or 3.3 V levels (VDDIO) for target host compatibility. The 1.8 V levels will offer a lower noise (EMI) and also a system power savings. 8.3.2.3 Power Saving Features 8.3.2.3.1 Des — Powerdown Feature (PDB) The Des has a PDB input Pin to ENABLE or POWER DOWN the device. This Pin can be controlled by the system to save power, disabling the Des when the display is not needed. An auto detect mode is also available. In this mode, the PDB Pin is tied High and the Des will enter POWER DOWN when the serial stream stops. When the serial stream starts up again, the Des will lock to the input stream and assert the LOCK Pin and output valid data. In POWER DOWN mode, the Data and CLKOUT output states are determined by the OSS_SEL status. Note – in POWER DOWN, the optional Serial Bus Control Registers are RESET. 8.3.2.3.2 Des — Stop Stream Sleep Feature The Des will enter a low power SLEEP state when the input serial stream is stopped. A STOP condition is detected when the embedded clock bits are not present. When the serial stream starts again, the Des will then lock to the incoming signal and recover the data. Note – in STOP STREAM SLEEP, the optional Serial Bus Control Registers values are RETAINED. Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 Submit Documentation Feedback 27 DS92LV2411, DS92LV2412 SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 www.ti.com 8.3.2.4 Des — Clock-Data Recovery Status Flag (Lock) And Output State Select (OSS_SEL) When PDB is driven HIGH, the CDR PLL begins locking to the serial input and LOCK goes from TRI-STATE to LOW (depending on the value of the OSS_SEL setting). After the DS92LV2412 completes its lock sequence to the input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial input is available on the parallel bus and clock outputs. The CLKOUT output is held at its current state at the change from OSC_CLK (if this is enabled via OSC_SEL) to the recovered clock (or vice versa). If there is a loss of clock from the input serial stream, LOCK is driven Low and the state of the outputs are based on the OSS_SEL setting (STRAP Pin configuration or register). 8.3.2.5 Des — Oscillator Output — Optional The Des provides an optional clock output when the input clock (serial stream) has been lost. This is based on an internal oscillator. The frequency of the oscillator may be selected. This feature may be controlled by the external Pin or by register. See Table 7 and Table 8. Table 6. OSS_SEL And PDB Configuration — Des Outputs INPUTS SERIAL INPUT PDB X X OUTPUTS OSS_SEL CLKOUT DO[23:0], CO1, CO2, CO3 LOCK PASS L L Z Z Z Z L H Z Z Z Z Static H L L L L L Static H H Z Z* L L Active H X Active Active H H *NOTE — If Pin is strapped HIGH the output will be pulled up Table 7. OSC (Oscillator) Mode — Des Output INPUTS OUTPUTS EMBEDDED CLK CLKOUT DO[23:0]/CO1/CO2/CO3 LOCK PASS NOTE * OSC Output L L H Present Toggling Active H H * NOTE — Absent and OSC_SEL ≠ 000 28 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 DS92LV2411, DS92LV2412 www.ti.com SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 PDB (DES) RIN (Diff.) LOCK DO[23:0], CO1,CO2,CO3 CLKOUT* (DES) active serial stream X H Z H L L L L L L Z Z Z Z Z Locking OFF Active C0 or C1 Error In Bit Stream (Loss of LOCK) Active OFF CONDITIONS: * RFB = L, and OSS_SEL Strap = L Figure 23. Des Outputs With Output State Select Low (OSS_SEL = L) PDB (DES) RIN (Diff.) active serial stream Z LOCK X H L H Z L DO[23:0], CO1,CO2,CO3 Z Z Z CLKOUT* (DES) Z Z Z OFF Locking Active C0 or C1 Error In Bit Stream (Loss of LOCK) Active OFF CONDITIONS: * RFB = L, and OSS_SEL Strap = H Figure 24. Des Outputs With Output State Select High (OSS_SEL = H) Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 Submit Documentation Feedback 29 DS92LV2411, DS92LV2412 SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 www.ti.com Table 8. OSC_SEL (Oscillator) Configuration OSC_SEL[2:0] INPUTS CLKOUT OSCILLATOR FREQUENCY OSC_SEL2 OSC_SEL1 OSC_SEL0 L L L Off – Feature Disabled – Default L L H 50 MHz ±40% L H L 25 MHz ±40% L H H 16.7 MHz ±40% H L L 12.5 MHz ±40% H L H 10 MHz ±40% H H L 8.3 MHz ±40% H H H 6.3 MHz ±40% PDB (DES) RIN (Diff.) active serial stream LOCK Z DO[23:0], CO1,CO2,CO3 Z CLKOUT* (DES) Z X H H L L Z Z L L Z L f f H PASS Z OFF H Z L L Locking Active C0 or C1 Error In Bit Stream (Loss of LOCK) Active OFF CONDITIONS: * RFB = L, OSS_SEL = H , and OSC_SEL not equal to 000. Figure 25. Des Outputs With Output State High And Clk Output Oscillator Option Enabled 8.3.2.6 Des — OP_LOW — Optional The OP_LOW feature is used to hold the LVCMOS outputs, except for the LOCK output, at a LOW state. When the OP_LOW feature is enabled, the LVCMOS outputs will be held at logic LOW while LOCK = LOW. The user must toggle the OP_LOW Set/Reset register bit to release the outputs to the normal toggling state. Note that the release of the outputs can only occur when LOCK is HIGH. The OP_LOW strap option is assigned to the PASS Pin, at Pin location 42. Restrictions on other straps: 1. Other strap options should not be used in order to keep the data and clock outputs at a true logic LOW state. Other features should be selected through the I2C register interface. 2. The OSS_SEL feature is not available when OP_LOW is enabled. Outputs DO[23:0], CO[3:1] and CLKOUT are in TRI-STATE before PDB toggles HIGH because the OP-LOW strap value has not been recognized until the DS92LV2412 powers up. Figure 26 shows the user controlled release of the OP_LOW and automatic reset of OP_LOW set on the falling edge of LOCK. Figure 27 shows the user controlled release of OP_LOW and manual reset of OP_LOW set. Note manual reset of OP_LOW can only occur when LOCK is HIGH. 30 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 DS92LV2411, DS92LV2412 www.ti.com SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 PDB 2.0V LOCK OP_ LOW SET (Strap pin) User controlled User controlled OP_ LOW RELEASE/SET (Register) DO[23:0], CO3, CO2, CO1 TRISTATE ACTIVE ACTIVE CLKOUT TRISTATE ACTIVE ACTIVE Figure 26. OP_LOW Auto Set PDB 2.0V LOCK OP_LOW SET (Strap pin) User controlled User controlled OP_ LOW RELEASE/SET (Register) DO[23:0], CO3, CO2, CO1 TRISTATE ACTIVE CLKOUT TRISTATE ACTIVE Figure 27. OP_LOW Manual Set/Reset 8.3.2.7 Des — Clock Edge Select (RFB) The RFB Pin determines the edge that the data is strobed on. If RFB is High, output data is strobed on the Rising edge of the CLKOUT. If RFB is Low, data is strobed on the Falling edge of the CLKOUT. This allows for inter-operability with downstream devices. The Des output does not need to use the same edge as the Ser input. This feature may be controlled by the external Pin or by register. 8.3.2.8 Des — Control Signal Filter — Optional The deserializer provides an optional Control Signal (C3, C2, C1) filter that monitors the three control signals and eliminates any pulses or glitches that are 1 or 2 parallel clock periods wide. Control signals must be 3 parallel clock periods wide (in its HIGH or LOW state, regardless of which state is active). This is set by the CONFIG[1:0] strap option or by I2C register control. Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 Submit Documentation Feedback 31 DS92LV2411, DS92LV2412 SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 www.ti.com 8.3.2.9 Des — SSCG Low Frequency Optimization (Lf_mode) Text to come. This feature may be controlled by the external Pin or by Register. 8.3.2.10 Des — Strap Input Pins Configuration of the device maybe done via configuration input Pins and the STRAP input Pins, or via the Serial Control Bus. The STRAP input Pins share select parallel bus output Pins. They are used to load in configuration values during the initial power up sequence of the device. Only a pull-up on the Pin is required when a HIGH is desired. By default the pad has an internal pull down, and will bias Low by itself. The recommended value of the pull up is 10 kΩ to VDDIO; open (NC) for Low, no pull-down is required (internal pull-down). If using the Serial Control Bus, no pull ups are required. 8.3.3 Built In Self Test (BIST) An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high-speed serial link. This is useful in the prototype stage, equipment production, in-system test and also for system diagnostics. In the BIST mode only a input clock is required along with control to the Ser and Des BISTEN input Pins. The Ser outputs a test pattern (PRBS7) and drives the link at speed. The Des detects the PRBS7 pattern and monitors it for errors. A PASS output Pin toggles to flag any payloads that are received with 1 to 24 errors. Upon completion of the test, the result of the test is held on the PASS output until reset (new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width applied to the Des BISTEN Pin. During the BIST duration, the deserializer data outputs toggle with a checkerboard pattern. Inter-operability is supported between this Channel Link II device and all Channel Link II generations (Gen 1/2/3). Note: In order to use BIST mode, the BISTEN Pin must be pulled high and REG = 0. The serializer cannot be placed in BIST mode if REG = 1, as this will cause the DS92LV2411 to ignore the pin input voltage. 8.3.3.1 Sample BIST Sequence See Figure 28 for the BIST mode flow diagram. Step 1: Place the DS92LV2411 Ser in BIST Mode by setting Ser BISTEN = H. For the DS92LV2411 Ser or DS99R421 Channel Link II Ser BIST Mode is enabled via the BISTEN Pin. A CLKIN is required for BIST. When the Des detects the BIST mode pattern and command (DCA and DCB code) the data and control signal outputs are shut off. Step 2: Place the DS92LV2412 Des in BIST mode by setting the BISTEN = H. The Des is now in the BIST mode and checks the incoming serial payloads for errors. If an error in the payload (1 to 24) is detected, the PASS Pin will switch low for one half of the clock period. During the BIST test, the PASS output can be monitored and counted to determine the payload error rate. Step 3: To Stop the BIST mode, the Des BISTEN Pin is set Low. The Des stops checking the data and the final test result is held on the PASS Pin. If the test ran error free, the PASS output will be High. If there was one or more errors detected, the PASS output will be Low. The PASS output state is held until a new BIST is run, the device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the BISTEN signal. Step 4: To return the link to normal operation, the Ser BISTEN input is set Low. The Link returns to normal operation. Figure 29 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the link (differential data transmission etc.), thus they may be introduced by greatly extending the cable length, faulting the interconnect, reducing signal condition enhancements (De-Emphasis, VODSEL, or Rx Equalization). 32 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 DS92LV2411, DS92LV2412 www.ti.com SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 Normal Step 1: SER in BIST BIST Wait Step 2: Wait, DES in BIST BIST start Step 3: DES in Normal Mode - check PASS BIST stop Step 4: SER in Normal Figure 28. BIST Mode Flow Diagram 8.3.3.2 BER Calculations It is possible to calculate the approximate Bit Error Rate (BER). The following is required: • Clock Frequency (MHz) • BIST Duration (seconds) • BIST test Result (PASS) The BER is less than or equal to one over the product of 24 times the CLK rate times the test duration. If we assume a 50 MHz clock, a 10 minute (600 second) test, and a PASS, the BERT is ≤ 1.39 X 10E-12 The BIST mode runs a check on the data payload bits. The LOCK Pin also provides a link status. It the recovery of the C0 and C1 bits does not reconstruct the expected clock signal, the LOCK Pin will switch Low. The combination of the LOCK and At-Speed BIST PASS Pin provides a powerful tool for system evaluation and performance monitoring. SER BISTEN (SER) DES Outputs BISTEN (DES) Case 1 - Pass CLKOUT (RFB = L) DO[23:0] CO1,CO2,CO3 DATA (internal) PASS Prior Result PASS PASS X X X FAIL Prior Result Normal Case 2 - Fail X = bit error(s) DATA (internal) PRBS BIST Test BIST Duration BIST Result Held Normal Figure 29. BIST Waveforms Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 Submit Documentation Feedback 33 DS92LV2411, DS92LV2412 SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 www.ti.com 8.4 Device Functional Modes 8.4.1 Data Transfer The DS92LV2411 / DS92LV2412 chipset will transmit and receive a pixel of data in the following format: C1 and C0 represent the embedded clock in the serial stream. C1 is always HIGH and C0 is always LOW. The remaining 26 bit spaces contain the scrambled, encoded and DC-Balanced serial data. 8.4.2 Serializer and Deserializer Operating Modes and Reverse Compatibility (Config[1:0]) The DS92LV2411 / DS92LV2412 chipset is compatible with other single serial lane Channel Link II or FPD-Link II devices. Configuration modes are provided for reverse compatibility with the DS90C241 / DS90C124 and also the DS90UR241 / DS90UR124 by setting the respective mode with the CONFIG[1:0] Pins on the Ser or Des as shown in Table and Table. This selection also determines whether the Control Signal Filter feature is enabled or disabled in the Normal mode. These configuration modes are selectable the control Pins only. Table 9. DS92LV2411 Serializer Modes CONFIG1 CONFIG0 L L L H MODE DES DEVICE Normal Mode, Control Signal Filter disabled DS92LV2412, DS92LV2412, DS92LV0422, DS92LV0412 Normal Mode, Control Signal Filter enabled DS92LV2412, DS92LV2412, DS92LV0422, DS92LV0412 H L Reverse Compatibility Mode DS90UR124, DS99R124 H H Reverse Compatibility Mode DS90C124 Table 10. DS92LV2412 Serializer Modes CONFIG1 CONFIG0 L L L H MODE SER DEVICE Normal Mode, Control Signal Filter disabled DS92LV2411, DS92LV2411, DS92LV0421, DS92LV0411 Normal Mode, Control Signal Filter enabled DS92LV2411, DS92LV2411, DS92LV0421, DS92LV0411 H L Reverse Compatibility Mode DS90UR241 H H Reverse Compatibility Mode DS90C241 8.4.3 Video Control Signal Filter — Serializer and Deserializer When operating the devices in Normal Mode, the Control Signals have the following restrictions: • Normal Mode with Control Signal Filter Enabled: Control Signal 1 and Control Signal 2 — Only 2 transitions per 130 clock cycles are transmitted, the transition pulse must be 3 parallel clocks or longer. • Normal Mode with Control Signal Filter Disabled: Control Signal 1 and Control Signal 2 — Only 2 transitions per 130 clock cycles are transmitted, no restriction on minimum transition pulse. • Control Signal 3 — Only 1 transition per 130 clock cycles is transmitted , minimum pulse width is 130 clock cycles. Control Signals are defined as low frequency signals with limited transition. Glitches of a control signal can cause a visual error in display applications. This feature allows for the chipset to validate and filter out any high frequency noise on the control signals. See Figure. 8.5 Programming 8.5.1 Optional Serial Bus Control The Ser and Des may also be configured by the use of a serial control bus that is I2C protocol compatible. By default, the I2C reg_0x00'h is set to 00'h and all configuration is set by control/strap Pins. A write of 01'h to reg_0x00'h will enable/allow configuration by registers; this will override the control/strap Pins. Multiple devices may share the serial control bus since multiple addresses are supported. See Figure 30. 34 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 DS92LV2411, DS92LV2412 www.ti.com SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 Programming (continued) The serial bus is comprised of three Pins. The SCL is a Serial Bus Clock Input. The SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external pull up resistor to VDDIO. For most applications a 4.7 k pull up resistor to VDDIO may be used. The resistor value may be adjusted for capacitive loading and data rate requirements. The signals are either pulled High, or driven Low. 1.8V 10 k VDDIO ID[X] 4.7k HOST 4.7k RID SCL SCL SDA SDA SER or DES To other Devices Figure 30. Serial Control Bus Connection The third Pin is the ID[X] Pin. This Pin sets one of four possible device addresses. As shown in Figure 30 , Table 11 and Table 12 different Resistor values could be used to set different SMBUS addresses. The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when SDA transitions Low while SCL is High. A STOP occurs when SDA transition High while SCL is also HIGH. See Figure 31 SDA SCL S START condition, or START repeat condition P STOP condition Figure 31. Start and Stop Conditions To communicate with a remote device, the host controller (master) sends the slave address and listens for a response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after every data byte is successfully received. When the master is reading data, the master ACKs after every data byte is received to let the slave know it wants to receive another data byte. When the master wants to stop reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop condition. A READ is shown in Figure 32 and a WRITE is shown in Figure 33. If the Serial Bus is not required, the three Pins may be left open (NC). Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 Submit Documentation Feedback 35 DS92LV2411, DS92LV2412 SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 www.ti.com Programming (continued) Table 11. Id[X] Resistor Value – DS92LV2411 Serializer RESISTOR RID kΩ ADDRESS 7'b ADDRESS 8'b 0 APPENDED (WRITE) 0.47 7b' 110 1001 (h'69) 8b' 1101 0010 (h'D2) 2.7 7b' 110 1010 (h'6A) 8b' 1101 0100 (h'D4) 8.2 7b' 110 1011 (h'6B) 8b' 1101 0110 (h'D6) Open 7b' 110 1110 (h'6E) 8b' 1101 1100 (h'DC) Table 12. Id[X] Resistor Value – DS92LV2412 Deserializer RESISTOR RID kΩ ADDRESS 7'b ADDRESS 8'b 0 APPENDED (WRITE) 0.47 7b' 111 0001 (h'71) 8b' 1110 0010 (h'E2) 2.7 7b' 111 0010 (h'72) 8b' 1110 0100 (h'E4) 8.2 7b' 111 0011 (h'73) 8b' 1110 0110 (h'E6) Open 7b' 111 0110 (h'76) 8b' 1110 1100 (h'EC) Register Address Slave Address S A 2 A 1 A 0 0 Slave Address a c k a c k A 2 S A 1 A 0 Data 1 a c k a c k P Figure 32. Serial Control Bus — Read Register Address Slave Address S A 2 A 1 A 0 0 a c k Data a c k a c k P Figure 33. Serial Control Bus — Write 36 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 DS92LV2411, DS92LV2412 www.ti.com SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 8.6 Register Maps Table 13. Serializer — Serial Bus Control Registers ADD ADD (dec) (hex) 0 1 2 0 1 2 REGISTER NAME Ser Config 1 Device ID De-Emphasis Control Bit(s) R/W DEFAULT (bin) 7 R/W 0 Reserved Reserved 6 R/W 0 Reserved Reserved 5 R/W 0 VODSEL 0: Low 1: High 4 R/W 0 RFB 0: Data latched on Falling edge of CLKIN 1: Data latched on Rising edge of CLKIN 3:2 R/W 00 CONFIG 00: Control Signal Filter Disabled 01: Control Signal Filter Enabled 10: Reserved 11: Reserved 1 R/W 0 SLEEP Note – not the same function as PowerDown (PDB) 0: normal mode 1: Sleep Mode – Register settings retained. 0 R/W 0 REG 0: Configurations set from control Pins 1: Configuration set from registers (except I2C_ID) 7 R/W 0 REG ID 0: Address from ID[X] Pin 1: Address from Register 6:0 R/W 1101000 ID[X] Serial Bus Device ID, Four IDs are: 7b '1101 001 (h'69) 7b '1101 010 (h'6A) 7b '1101 011 (h'6B) 7b '1101 110 (h'6E) All other addresses are Reserved. 7:5 R/W 000 De-E Setting 000: 001: 010: 011: 100: 101: 110: 111: 4 R/W 0 De-E EN 0: De-Emphasis Enabled 1: De-Emphasis Disabled 3:0 R/W 000 Reserved Reserved FUNCTION DESCRIPTION set by external Resistor -1 dB -2 dB -3.3 dB -5 dB -6.7 dB -9 dB -12 dB Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 Submit Documentation Feedback 37 DS92LV2411, DS92LV2412 SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 www.ti.com Table 14. Deserializer — Serial Bus Control Registers ADD ADD (dec) (hex) 0 1 2 38 0 1 2 REGISTER NAME Des Config 1 Slave ID Des Features 1 Bit(s) R/W DEFAULT (bin) 7 R/W 0 LF_MODE 0: 20 to 50 MHz SSCG Operation 1: 5 to 20 MHz SSCG Operation 6 R/W 0 OS_CLKOUT 0: Normal CLKOUT Slew Rate 1: Increased CLKOUT Slew Rate 5 R/W 0 OS_DATA 0: Normal DATA Slew Rate 1: Increased DATA Slew Rate 4 R/W 0 RFB 0: Data strobed on Falling edge of CLKOUT 1: Data strobed on Rising edge of CLKOUT 3:2 R/W 00 CONFIG 00: Normal Mode, Control Signal Filter Disabled 01: Normal Mode, Control Signal Filter Enabled 10: Reserved 11: Reserved 1 R/W 0 SLEEP Note – not the same function as PowerDown (PDB) 0: Normal Mode 1: Sleep Mode – Register settings retained. 0 R/W 0 REG Control 0: Configurations set from control Pins / STRAP Pins 1: Configurations set from registers (except I2C_ID) 7 R/W 0 6:0 R/W 1110000 7 R/W 6 FUNCTION DESCRIPTION 0: Address from ID[X] Pin 1: Address from Register ID[X] Serial Bus Device ID, Four IDs are: 7b '1110 001 (h'71) 7b '1110 010 (h'72) 7b '1110 011 (h'73) 7b '1110 110 (h'76) All other addresses are Reserved. 0 OP_LOW 0: Set outputs state LOW (except LOCK) 1: Release output LOW state, outputs toggling normally Note: This register only works during LOCK = 1 R/W 0 OSS_SEL Output Sleep State Select 0: CLKOUT, DO[23:0], CO1, CO2, CO3 = L, LOCK = Normal, PASS = H 1: CLKOUT, DO[23:0], CO1, CO2, CO3 = Tri-State, LOCK = Normal, PASS = H 5:4 R/W 00 Reserved Reserved 3 R/W 0 OP_LOW Strap Bypass 0: Strap will determine whether OP_LOW feature is ON or OFF 1: Turns OFF OP_LOW feature 2:0 R/W 00 OSC_SEL 000: 001: 010: 011: 100: 101: 110: 111: Submit Documentation Feedback disable 50 MHz ±40% 25 MHz ±40% 16.7 MHz ±40% 12.5 MHz ±40% 10 MHz ±40% 8.3 MHz ±40% 6.3 MHz ±40% Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 DS92LV2411, DS92LV2412 www.ti.com SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 Table 14. Deserializer — Serial Bus Control Registers (continued) ADD ADD (dec) (hex) 3 4 3 4 REGISTER NAME Des Features 2 ROUT Config Bit(s) R/W DEFAULT (bin) 7:5 R/W 000 4 R/W 0 3:0 R/W 0000 7 R/W 0 6:0 R/W 0000000 FUNCTION DESCRIPTION EQ Gain 000: 001: 010: 011: 100: 101: 110: 111: ~1.625 dB ~3.25 dB ~4.87 dB ~6.5 dB ~8.125 dB ~9.75 dB ~11.375 dB ~13 dB EQ Enable 0: EQ = disable 1: EQ = enable SSC IF LF_MODE = 0, then: 000: SSCG disable 0001: fdev = ±0.5%, fmod 0010: fdev = ±1.0%, fmod 0011: fdev = ±1.5%, fmod 0100: fdev = ±2.0%, fmod 0101: fdev = ±0.5%, fmod 0110: fdev = ±1.0%, fmod 0111: fdev = ±1.5%, fmod 1000: fdev = ±2.0%, fmod 1001: fdev = ±0.5%, fmod 1010: fdev = ±1.0%, fmod 1011: fdev = ±1.5%, fmod 1100: fdev = ±2.0%, fmod 1101: fdev = ±0.5%, fmod 1110: fdev = ±1.0%, fmod 1111: fdev = ±1.5%, fmod IF LF_MODE = 1, then: 000: SSCG disable 0001: fdev = ±0.5%, fmod 0010: fdev = ±1.0%, fmod 0011: fdev = ±1.5%, fmod 0100: fdev = ±2.0%, fmod 0101: fdev = ±0.5%, fmod 0110: fdev = ±1.0%, fmod 0111: fdev = ±1.5%, fmod 1000: fdev = ±2.0%, fmod 1001: fdev = ±0.5%, fmod 1010: fdev = ±1.0%, fmod 1011: fdev = ±1.5%, fmod 1100: fdev = ±2.0%, fmod 1101: fdev = ±0.5%, fmod 1110: fdev = ±1.0%, fmod 1111: fdev = ±1.5%, fmod = CLK/2168 = CLK/2168 = CLK/2168 = CLK/2168 = CLK/1300 = CLK/1300 = CLK/1300 = CLK/1300 = CLK/868 = CLK/868 = CLK/868 = CLK/868 = CLK/650 = CLK/650 = CLK/650 = CLK/620 = CLK/620 = CLK/620 = CLK/620 = CLK/370 = CLK/370 = CLK/370 = CLK/370 = CLK/258 = CLK/258 = CLK/258 = CLK/258 = CLK/192 = CLK/192 = CLK/192 Repeater Enable 0: Output ROUT+/- = disable 1: Output ROUT+/- = enable Reserved Reserved Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 Submit Documentation Feedback 39 DS92LV2411, DS92LV2412 SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 www.ti.com 9 Applications and Implementation 9.1 Application Information The DS92LV2411/DS92LV2412 chipset is intended for interface between a host (graphics processor) and a Display. It supports an 24-bit color depth (RGB888). In a RGB888 application, 24 color bits (D[23:0), Pixel Clock (CLKIN) and three control bits (C1, C2, C3) are supported across the serial link with CLK rates from 5 to 50 MHz. The chipset may also be used in 18-bit color applications. In this application three to six general purpose signals may also be sent from host to display. The Des is expected to be located close to its target device. The interconnect between the Des and the target device is typically in the 1 to 3 inch separation range. The input capacitance of the target device is expected to be in the 5 to 10 pF range. Care should be taken on the CLK output trace as this signal is edge sensitive and strobes the data. It is also assumed that the fanout of the Des is one. If additional loads need to be driven, a logic buffer or mux device is recommended. 9.2 Typical Applications VDDIO VDDn (1.8V or 3.3V) 1.8V DI[7:0] DI[15:8] DI[23:16] CI1 CI2 CI3 CLKIN Graphic Processor OR Video Imager OR ASIC/FPGA PDB DO[7:0] DO[15:8] DO[23:16] CO1 CO2 CO3 CLKOUT Channel Link II 1 Pair / AC Coupled 0.1 PF 0.1 PF DOUT+ RIN+ DOUT- RIN100 ohm STP Cable DS92LV2411 Serializer BISTEN Optional VDDn VDDIO 1.8V (1.8V or 3.3V) CMF PDB BISTEN RFB VODSEL DeEmph SCL SDA ID[x] DS92LV2412 Deserializer Optional LOCK PASS STRAP pins not shown SCL SDA ID[x] DAP 24-bit RGB Display OR ASIC/FPGA DAP Figure 34. Typical Application Schematic for DS92LV2411, DS92LV2412 Ser/Des Pair 9.2.1 Design Requirements For this typical design application, use the following as input parameters. Table 15. Design Parameters DESIGN PARAMETER EXAMPLE VALUE VDDIO 1.8 V or 3.3 V VDDn 1.8 V AC Coupling Capacitor for DOUT± and RIN± 0.1 µF CLK Frequency 50 MHz 9.2.2 Detailed Design Procedure 9.2.2.1 Typical Application Connection Figure 35 shows a typical connection diagram of the DS92LV2411 Ser in Pin control mode for a 24-bit application. The CML outputs require 0.1 µF AC coupling capacitors to the line. The line driver includes internal termination. Bypass capacitors are placed near the power supply Pins. At a minimum, four 0.1 µF capacitors and a 4.7 µF capacitor should be used for local device bypassing. System GPO (General Purpose Output) signals control the PDB and BISTEN Pins. In this application the RFB Pin is tied Low to latch data on the falling edge of 40 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 DS92LV2411, DS92LV2412 www.ti.com SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 the CLKIN. In this example the cable is long, therefore the VODSEL Pin is tied High and a De-Emphasis value is selected by the resistor R1. The interface to the host is with 1.8 V LVCMOS levels, thus the VDDIO Pin is connected also to the 1.8V rail. The optional Serial Bus control is not used in this example, thus the SCL, SDA and ID[x] Pins are left open. A delay cap is placed on the PDB signal to delay the enabling of the device until power is stable. DS92LV2411 (SER) VDDIO VDDIO C9 C7 FB1 C3 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI9 DI10 DI11 DI12 DI13 DI14 DI15 LVCMOS Parallel Video Interface CI1 CI2 CI3 LVCMOS Control Interface BISTEN PDB C12 CONFIG1 CONFIG0 RFB C4 FB2 C5 FB3 C6 FB4 C8 C10 VDDP C11 VDDL C1 Serial Channel Link II Interface DOUT+ DOUTC2 DI16 DI17 DI18 DI19 DI20 DI21 DI22 DI23 CLKIN 1.8V VDDTX VDDHS VDDIO VODSEL De-Emph 1.8V R1 10k ID[X] SCL SDA RID RES2 RES1 RES0 DAP (GND) NOTE: C1-C2 = 0.1 PF C3-C8 = 0.1 PF C9-11 = 4.7 PF C12 = >10 PF R1 (cable specific) RID (see ID[x] Resistor Value Table 12) FB1-FB4: Impedance = 1 k:, low DC resistance (<1:) Figure 35. DS92LV2411 Typical Connection Diagram — Pin Control Figure 36 shows a typical connection diagram of the DS92LV2412 Des in Pin/strap control mode for a 24-bit application. The CML inputs utilize 0.1 µF coupling capacitors to the line and the receiver provides internal termination. Bypass capacitors are placed near the power supply Pins. At a minimum, seven 0.1 µF capacitors and two 4.7 µF capacitors should be used for local device bypassing. System GPO (General Purpose Output) signals control the PDB and the BISTEN Pins. In this application the RFB Pin is tied Low to strobe the data on the falling edge of the CLKOUT. Since the device in the Pin/STRAP mode, four 10 kΩ pull up resistors are used on the parallel output bus to select the desired device features. CFEN is set to 1 for Normal Mode with Control Signal Filter enabled, this is accomplished with the STRAP pull-up on DO23. The receiver input equalizer is also enabled and set to provide 7.5 dB of gain, this is accomplished with EQ[3:0] set to 1001'b with STRAP pull ups on DO12 and DO15. To reduce parallel bus EMI, the SSCG feature is enabled and set to fmod = CLK/2168 and ±1% with SSC[3:0] set to 0010'b and a STRAP pull-up on DO4. The desired features are set with the use of the four pull up resistors. The interface to the target display is with 3.3V LVCMOS levels, thus the VDDIO Pin is connected to the 3.3 V rail. The optional Serial Bus Control is not used in this example, thus the SCL, SDA and ID[x] Pins are left open. A delay cap is placed on the PDB signal to delay the enabling of the device until power is stable. Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 Submit Documentation Feedback 41 DS92LV2411, DS92LV2412 SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 www.ti.com DS92LV2412 (DES) 1.8V VDDL C13 C11 VDDIO VDDIO C8 C3 VDDSC C12 C14 VDDIO C9 C4 VDDPR VDDIO C10 C5 VDDR C15 C6 VDDIR VDDIO EXAMPLE: STRAP Input Pull-Ups (10k) VDDCMLO C16 C7 C1 Serial Channel Link II Interface RIN+ RINCMF C2 C17 TP_A ROUT+ ROUT- TP_B Host Control BISTEN PDB C18 1.8V 10k ID[X] SCL SDA RID C1 - C2 = 0.1 PF C3 - C12 = 0.1 PF C13, C16 = 4.7 PF C17 = 4.7 PF C18 = >10 PF RID (see ID[x] Resistor Value Table 13) FB1-FB4: Impedance = 1 k:, low DC resistance (<1:) 8 NC DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 DO9 DO10 DO11 DO12 DO13 DO14 DO15 LVCMOS Parallel Video Interface DO16 DO17 DO18 DO19 DO20 DO21 DO22 DO23 CO1 CO2 CO3 CLKOUT RES DAP (GND) LOCK PASS Figure 36. DS92LV2412 Typical Connection Diagram — Pin Control 9.2.2.2 Power Up Requirements and PDB Pin The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on the PDB Pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage. When PDB Pin is pulled to VDDIO, it is recommended to use a 10 kΩ pull-up and a 22 uF cap to GND to delay the PDB input signal. 42 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 DS92LV2411, DS92LV2412 www.ti.com SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 9.2.2.3 Transmission Media The Ser/Des chip set is intended to be used in a point-to-point configuration, through a PCB trace, through twisted pair cable or through 50Ω coaxial cables. The Ser and Des provide internal terminations providing a clean signaling environment. The interconnect for the differential serial interface should present a differential impedance of 100Ω. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Shielded or un-shielded cables may be used depending upon the noise environment and application requirements. For 50Ω coaxial cable serial interfaces, any unused input or output Pin must be terminated with an 0.1 µF AC coupling capacitor and a 50Ω resistor to ground. The PCB traces and serial interconnect should have a single ended impedance of 50Ω. 9.2.2.4 Live Link Insertion The Ser and Des devices support live pluggable applications. The automatic receiver lock to random data “plug and go” hot insertion capability allows the DS92LV2412 to attain lock to the active data stream during a live insertion event. 9.2.2.5 Serial Interconnect Guidelines See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details. • Use 100Ω coupled differential pairs • Use the S/2S/3S rule in spacings – S = space between the pair – 2S = space between pairs – 3S = space to LVCMOS signal • Minimize the number of Vias • Use differential connectors when operating above 500Mbps line speed • Maintain balance of the traces • Minimize skew within the pair • Terminate as close to the TX outputs and RX inputs as possible Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the Texas Instruments web site at: http://www.ti.com/ww/en/analog/interface/lvds.shtml 9.2.3 Application Curves CML Serializer Data Throughput (100 mV/DIV) CML Serializer Data Throughput (100 mV/DIV) 50 MHz TX Pixel Clock Input (2 V/DIV) 50 MHz TX Pixel Clock Input (2 V/DIV) Time (4 ns/DIV) Time (4 ns/DIV) Figure 37. Serializer Output with 50 MHz TX Pixel Clock, De-emphasis Disabled Figure 38. Serializer Output with 50 MHz TX Pixel Clock, De-emphasis Enabled Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 Submit Documentation Feedback 43 DS92LV2411, DS92LV2412 SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 www.ti.com 10 Power Supply Recommendations The devices are designed to operate from an input voltage supply of 1.8V. Some devices provide separate power and ground Pins for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power Pin pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits such as PLLs. 11 Layout 11.1 Layout Guidelines Circuit board layout and stack-up for the Ser/Des devices should be designed to provide low-noise power feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the tantalum capacitors should be at least 5X the power supply voltage being used. Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per supply Pin, locate the smaller value closer to the Pin. A large bulk capacitor is recommend at the point of power entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is recommended to connect power and ground Pins directly to the power and ground planes with bypass capacitors connected to the plane with via on both ends of the capacitor. Connecting power or ground Pins to an external bypass capacitor will increase the inductance of the path. A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At high frequency, it is also a common practice to use two vias from power and ground Pins to the planes, reducing the impedance at high frequency. Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the CML lines to prevent coupling from the LVCMOS lines to the CML lines. Closely-coupled differential lines of 100 Ohms are typically recommended for differential interconnect. The closely coupled lines help to ensure that coupled noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also radiate less. Information on the WQFN style package is provided in TI Application Note: AN-1187 (SNOA401). 11.2 Layout Example Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste deposition. Inspection of the stencil prior to placement of the LLP package is highly recommended to improve board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown below: 44 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 DS92LV2411, DS92LV2412 www.ti.com SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 Layout Example (continued) Figure 39. No Pullback LLP, Single Row Reference Diagram Table 16. No Pullback LLP Stencil Aperture Summary for DS92LV2411 and DS92LV2412 Device Pin MKT Dwg PCB I/O Count Pad Size (mm) PCB Pitch (mm) PCB DAP size (mm) Stencil I/O Aperture (mm) Stencil DAP Aperture (mm) Number of DAP Aperture Openings Gap Between DAP Aperture (Dim A mm) DS92LV2411 48 SQA48A 0.25 x 0.6 0.5 5.1 x 5.1 0.25 x 0.7 1.1 x 1.1 16 0.2 DS92LV2412 60 SQA60B 0.25 x 0.8 0.5 7.2 x 7.2 0.25 x 0.9 1.16 x 1.16 25 0.3 Figure 40. 48-Pin WQFN Stencil Example of Via and Opening Placement The following PCB layout examples are derived from the layout design of the DS9LV2411 and DS92LV2412 in the LV24EVK01 Evaluation Module User's Guide (SNLU006). These graphics and additional layout description are used to demonstrate both proper routing and proper solder techniques when designing in the Ser/Des pair. Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 Submit Documentation Feedback 45 DS92LV2411, DS92LV2412 SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 www.ti.com Figure 41. DS92LV2411 Serializer Example Layout Figure 42. DS92LV2412 Deserializer Example Layout 46 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 DS92LV2411, DS92LV2412 www.ti.com SNLS302E – MAY 2010 – REVISED FEBRUARY 2015 12 Device and Documentation Support 12.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 17. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY DS92LV2411 Click here Click here Click here Click here Click here DS92LV2412 Click here Click here Click here Click here Click here 12.2 Trademarks All trademarks are the property of their respective owners. 12.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DS92LV2411 DS92LV2412 Submit Documentation Feedback 47 PACKAGE OPTION ADDENDUM www.ti.com 5-Feb-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) DS92LV2411SQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LV2411SQ DS92LV2411SQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LV2411SQ DS92LV2411SQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LV2411SQ DS92LV2412SQ/NOPB ACTIVE WQFN NKB 60 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LV2412SQ DS92LV2412SQE/NOPB ACTIVE WQFN NKB 60 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LV2412SQ DS92LV2412SQX/NOPB ACTIVE WQFN NKB 60 2000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LV2412SQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 5-Feb-2015 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 5-Feb-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DS92LV2411SQ/NOPB WQFN RHS 48 DS92LV2411SQE/NOPB WQFN RHS DS92LV2411SQX/NOPB WQFN RHS DS92LV2412SQ/NOPB WQFN DS92LV2412SQE/NOPB DS92LV2412SQX/NOPB SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 NKB 60 1000 330.0 16.4 9.3 9.3 1.3 12.0 16.0 Q1 WQFN NKB 60 250 178.0 16.4 9.3 9.3 1.3 12.0 16.0 Q1 WQFN NKB 60 2000 330.0 16.4 9.3 9.3 1.3 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Feb-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS92LV2411SQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 DS92LV2411SQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 DS92LV2411SQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 DS92LV2412SQ/NOPB WQFN NKB 60 1000 367.0 367.0 38.0 DS92LV2412SQE/NOPB WQFN NKB 60 250 213.0 191.0 55.0 DS92LV2412SQX/NOPB WQFN NKB 60 2000 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA NKB0060B SQA60B (Rev B) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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