Fairchild FAH4830MPX Haptic driver for dc motors (erms) and linear resonant actuators (lras) Datasheet

FAH4830
Haptic Driver for DC Motors (ERMs) and Linear
Resonant Actuators (LRAs)
Features
Description
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Direct Drive of ERM and LRA Motors
The FAH4830 is a high-performance enhanced haptic
drive for mobile phone and other hand-held devices.
The haptic driver takes a single-ended PWM input
signal to control a DC motor. It can drive both Eccentric
Rotating Mass (ERM) and Linear Resonant Actuator
(LRA) motors. The device utilizes an external 10 kHz to
50 kHz PWM signal capable of meeting the wide range
of resonant frequencies.
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Settable Filter and External Gain Control
External PWM Input (10 kHz to 50 kHz)
External Motor Enable/Disable Input
Internal Mode-Select Register: ERM or LRA
Low Standby Current: <500 nA
Fast Wake-up Time
Nearly Rail-to-Rail Output Swing
Register-Based Control by I2C
Over Driving Motor Control
Under-Voltage, Over-Current, and OverTemperature Protections
The FAH4830 has its own register maps accessible via
I2C serial communication. A gain control setting can be
used to help prevent PWM noise from getting into the
motor and to control the maximum output voltage on the
motor. For ERM motors, the over-drive control block is
designed to control the inertial momentum of the motor.
Package: 10-Lead MLP
Applications
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Mobile Phones
Handheld Devices
Any Key-Pad Interface
Related Resources
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AN-5067 — PCB Land Pattern Design and SurfaceMount Guidelines for MLP Packages
Figure 1.
Block Diagram
Ordering Information
Part Number
Operating Temperature Range
Package
Packing Method
FAH4830MPX
-40°C to +85°C
10-Lead, Dual, JEDEC MO-229,
3mm Square, Molded Leadless
Package (MLP)
3000 Units on
Tape & Reel
© 2012 Fairchild Semiconductor Corporation
FAH4830 • 1.0.1
www.fairchildsemi.com
FAH4830 — Haptic Driver for DC Motors (ERMs) and Linear Resonant Actuators (LRAs)
January 2013
Figure 2.
Pin Assignments (Top View)
Pin Definitions
Name
Pin #
Type
Description
VDD
1
Power
Power
GND
2, 7
Power
Ground
MDP
3
Output
Positive motor driver output
MDN
4
Output
Negative motor driver output
GAIN
5
Input
Gain control for motor driving (39 nF capacitor required to tied to MDN)
PWM
6
Input
PWM input
HEN
8
Input
Haptic motor enable/disable (HIGH: enable, LOW: disable)
SDA
9
Input
I2C data input
SCL
10
Input
I2C clock input
Note:
1. The exposed DAP should be connected to ground.
© 2012 Fairchild Semiconductor Corporation
FAH4830 • 1.0.1
FAH4830 — Haptic Driver for DC Motors (ERMs) and Linear Resonant Actuators (LRAs)
Pin Configuration
www.fairchildsemi.com
2
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VDD
DC Supply Voltage
-0.3
6.0
V
VIO
Analog and Digital I/O (All Input and Output Pins)
-0.3
VCC+0.3
V
Reliability Information
Symbol
TJ
Parameter
Min.
Typ.
Junction Temperature
TSTG
Storage Temperature Range
-65
JA
Thermal Resistance, JEDEC Standard, Multilayer Test Boards, Still Air
Max.
Unit
+150
°C
+150
°C
200
°C/W
Electrostatic Discharge Information
Symbol
ESD
Parameter
Max.
Human Body Model, JESD22-A114
8
Charged Device Model, JESD22-C101
2
Unit
kV
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
TA
Operating Temperature Range
-40
VDD
Supply Voltage Range
2.7
© 2012 Fairchild Semiconductor Corporation
FAH4830 • 1.0.1
Typ.
3.3
Max.
Unit
+85
°C
5.5
V
FAH4830 — Haptic Driver for DC Motors (ERMs) and Linear Resonant Actuators (LRAs)
Absolute Maximum Ratings
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3
Typical values are at TA = 25°C, VDD = 3.3 V, and VLDO = 3.0 V unless otherwise noted.
Symbol
IfQY
IIHPWM
Parameter
Conditions
PWM Input
Frequency
Square Wave Input
Input Current
PWM = 3.3 V
Min.
Typ.
10
0.1
Max.
Unit
50
kHz
1.0
µA
IIHHEN
Input Current
HEN = 3.3 V
0.1
1.0
µA
IILPWM
Input Current
PWM = 0.0 V
0.1
1.0
µA
IILHEN
Input Current
HEN = 0.0 V
0.1
1.0
µA
IIHSCL
Input Current
SCL = 3.3 V
0.1
1.0
µA
IIHSDA
Input Current
SDA = 3.3 V
0.1
1.0
µA
IILSCL
Input Current
SCL = 0.0 V
0.1
1.0
µA
IILSDA
Input Current
SDA = 0.0 V
0.1
1.0
µA
0.3 X VDD
V
VIH
Input Logic high
VIL
Input Logic Low
0.7 X VDD
ICAP
Input Capacitance
PWM Capacitance to GND or
VDD
19
VOL
Output Voltage
VDD = 3.3 V, RL = 10 Ω
100
200
mV
VOH
Output Voltage
VDD = 3.3 V, RL = 10 Ω
2.9
3.1
V
IOUT
Short-Circuit
Protection
VDD = 3.3 V, MDP to MDN Short
to Each Other & Short to GND
tWU
Wake-up Time
tSD
Shutdown Time
RIN
VLDO-0.3
V
pF
500
mA
30
50
µs
PWM = 50% Duty Cycle, CF =
39.0 nF, HEN HIGH to LOW
1
3
µs
Input Resistance
Gain Input – Default Register
Setting
10
kΩ
CIN
Input Capacitance
Gain Input
10
pF
IDD
Supply Current
PWM = 22.4 kHz 50% Duty,
LRA/ERM Mode, RL = 10 Ω
4
7
mA
IPO
Power-Down Supply VPWM = 0 V, VDD = 2.7 V,
Current
VLDO = 2.4 V, Reg 0x20 bit 7=0
100
400
nA
3.0
3.6
V
1
%
VOUT
Output Voltage
Range
2.4
VREG
Output Voltage
Accuracy
-1
Figure 3.
© 2012 Fairchild Semiconductor Corporation
FAH4830 • 1.0.1
FAH4830 — Haptic Driver for DC Motors (ERMs) and Linear Resonant Actuators (LRAs)
Electrical Characteristics
Haptic Enable/Disable Functional Timing
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4
TA = 25°C, VDD = 3.3 V, and VLDO = 3.0 V unless otherwise noted.
Symbol
Fast Mode (400kHz)
Parameter
Min.
Max.
Unit
0.6
V
VIL
Low-Level Input Voltage
-0.3
VIH
High-Level Input Voltage
1.3
VOL
Low-Level Output Voltage at 3 mA Sink Current
(Open-Drain or Open-Collector)
V
0
0.4
V
IIH
High-Level Input Current of Each I/O Pin, Input Voltage = VDD
-1
1
µA
IIL
Low-Level Input Current of Each I/O Pin, Input Voltage = 0 V
-1
1
µA
I2C AC Electrical Characteristics
Symbol
fSCL
tHD;STA
Fast Mode (400kHz)
Parameter
SCL Clock Frequency
Min.
Max.
Unit
0
400
kHz
Hold Time (Repeated) START Condition
0.6
µs
tLOW
Low Period of SCL Clock
1.3
µs
tHIGH
High Period of SCL Clock
0.6
µs
tSU;STA
Set-up Time for Repeated START Condition
0.6
tHD;DAT
Data Hold Time
tSU;DAT
0
(2)
100
Data Set-up Time
(3)
tr
Rise Time of SDA and SCL Signals
tf
Fall Time of SDA and SCL Signals
tSU;STO
tBUF
µs
0.9
(3)
µs
ns
20+0.1Cb
300
ns
20+0.1Cb
300
ns
Set-up Time for STOP Condition
0.6
µs
Bus-Free Time between STOP and START Conditions
1.3
µs
tSP
Pulse Width of Spikes that Must Be Suppressed by the Input Filter
0
50
ns
Notes:
2. A Fast-Mode I2C Bus® device can be used in a Standard-Mode I2C bus system, but the requirement tSU;DAT
≥250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the
2
Serial Data (SDA) line tr_max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I C Bus
specification) before the SCL line is released.
3. Cb equals the total capacitance of one bus line in pf. If mixed with High-Speed Mode devices, faster fall times are
2
allowed according to the I C specification.
FAH4830 — Haptic Driver for DC Motors (ERMs) and Linear Resonant Actuators (LRAs)
I2C DC Electrical Characteristics
Figure 4. Definition of Timing for Full-Speed Mode Devices on the I2C Bus
© 2012 Fairchild Semiconductor Corporation
FAH4830 • 1.0.1
www.fairchildsemi.com
5
I2C Control
Setting the Pointer
For all operations, a “pointer” stored in the command
register must be indicating the register to be written or
read. To change the pointer value in the command
register, the read/write bit following the address must be
0. This indicates that the master writes new information
into the command register.
After the FAH4830 sends an ACK in response to
receiving the address and read/write bit, the master
must transmit an appropriate 8-bit pointer value, as
explained in the I2C Registers section. The FAH4830
sends an ACK after receiving the new pointer data.
The pointer-set operation is illustrated in Figure 7 and
Figure 8. Any time a pointer-set is performed, it must be
immediately followed by a read or write operation. The
command register retains the pointer between
operations; once a register is indicated, subsequent
read operations do not require a pointer set cycle. Write
operations always require the pointer be reset.
Reading
If the pointer is already pointing to the desired register,
the master can read from that register by setting the
read/write bit (following the slave address) to 1. After
sending an ACK, data transmission begins during the
following clock cycle. The master should respond with a
NACK, followed by a STOP condition (see Figure 5).
The master can read multiple bytes by responding to the
data with an ACK instead of a NACK and continuing to
send SCL pulses, as shown in Figure 6. The FAH4830
increments the pointer by one and sends the data from
the next register. The master indicates the last data byte
by responding with a NACK, followed by a STOP.
To read from a register other than the one currently
indicated by the command register, a pointer to the
desired register must be set. Immediately following the
pointer-set, the master must perform a REPEAT START
condition (see Figure 8), which indicates to the
FAH4830 that a new operation is about to occur. If the
REPEAT START condition does not occur, the
FAH4830 assumes that a write is taking place and the
selected register is overwritten by the upcoming data on
the data bus. After the START condition, the master
must again send the device address and read/write bit.
This time, the read/write bit must be set to 1 to indicate
a read. The rest of the read cycle is the same as
described for reading from a preset pointer location.
Writing
All writes must be preceded by a pointer set, even if the
pointer is already pointing to the desired register.
Immediately following the pointer-set, the master must
begin transmitting the data to be written. After
transmitting each byte of data, the master must release
the Serial Data (SDA) line for one clock cycle to allow
the FAH4830 to acknowledge receiving the byte. The
write operation should be terminated by a STOP
condition from the master (see Figure 7).
As with reading, the master can write multiple bytes by
continuing to send data. The FAH4830 increments the
pointer by one and accepts data for the next register.
The master indicates the last data byte by issuing a
STOP condition.
Writing to and reading from registers is accomplished
2
2
via the I C interface. The I C protocol requires that one
device on the bus initiates and controls all read and
write operations. This device is called the “master”
device. The master device generates the SCL signal,
which is the clock signal for all other devices on the bus.
All other devices on the bus are called “slave” devices.
The FAH4830 is a slave device. Both the master and
slave devices can send and receive data on the bus.
During I2C operations, one data bit is transmitted per
clock cycle. All I2C operations follow a repeating nineclock-cycle pattern that consists of eight bits (one byte)
of transmitted data followed by an acknowledge (ACK)
or not acknowledge (NACK) from the receiving device.
Note that there are no unused clock cycles during any
operation; therefore, there must be no breaks in the
stream of data and ACKs/NACKs during data transfers.
For most operations, I2C protocol requires the SDA line
remain stable (unmoving) whenever SCL is HIGH. For
example, transitions on the SDA line can only occur
when SCL is LOW. The exceptions are when the master
device issues a START or STOP condition. The slave
device cannot issue a START or STOP condition.
START Condition: This condition occurs when the SDA
line transitions from HIGH to LOW while SCL is HIGH.
The master device uses this condition to indicate that a
data transfer is about to begin.
STOP Condition: This condition occurs when the SDA
line transitions from LOW to HIGH while SCL is HIGH.
The master device uses this condition to signal the end
of a data transfer.
Acknowledge and Not Acknowledge: When data is
transferred to the slave device, the slave device sends
acknowledge (ACK) after receiving every byte of data.
The receiving device sends an ACK by pulling SDA
LOW for one clock cycle.
When the master device is reading data from the slave
device, the master sends an ACK after receiving every
byte of data. Following the last byte, a master device
sends a “not acknowledge” (NACK) instead of an ACK,
followed by a STOP condition. A NACK is indicated by
leaving SDA HIGH during the clock after the last byte.
Slave Address
Each slave device on the bus must have a unique
address so the master can identify which device is
sending or receiving data. The FAH4830 slave address
is 0000110X binary, where “X” is the read/write bit.
Master write operations are indicated when X = 0.
Master read operations are indicated when X = 1.
Writing to and Reading from the FAH4830
All read and write operations must begin with a START
condition generated by the master. After the START
condition, the master must immediately send a slave
address (7 bits), followed by a read/write bit. If the slave
address matches the address of the FAH4830, the
FAH4830 sends an ACK after receiving the read/write
bit by pulling the SDA line LOW for one clock cycle.
© 2012 Fairchild Semiconductor Corporation
FAH4830 • 1.0.1
FAH4830 — Haptic Driver for DC Motors (ERMs) and Linear Resonant Actuators (LRAs)
Functional Description
www.fairchildsemi.com
6
Read / Write Diagrams
Figure 5.
Figure 6.
2
I C Multiple Byte Read
Figure 7.
Figure 8.
I2C Read
I2C Write
I2C Write Followed by Read
Digital Interface
The I2C-compatible interface is used to program the FAH4830 as listed in the below register configurations. The I2C
address of the FAH4830 is 0x06.
Binary
Hex
00000110
0x06
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Table 1.
Control Registers and Default Values
Address
Register Name
Type
Reset Value
0x20
CONTROL0
R/W
10010000
0x21
CONTROL1
R/W
00101100
0x22
Haptic_STAT
R
00001110
Table 2.
Control Register MAP (Control0, Control1, Status)
Bit7
Bit6
Bit5
Bit4
Haptic_En
ODRV_EN
ODRVEN_HL
MOT_TYP
Input Resistance[7:5]
Bit3
Bit2
Reserved
Reserved[7:4]
VDD_G




Reserved
VREG_G
Control 0
Address: 20h
Reset Value: 1001_0000
Type: Read/Write
BOLD is default state
Bit #
Name
Size (Bits)
7
Haptic_En
1
Haptic Drive Enable Mode
0: Power-Down Mode
1: Normal Operation Mode
6
ODRV_EN
1
Haptic Over-Drive Enable Mode (for ERM)
0: Disable Over Drive
1: Enable Over Drive
5
ODRVEN_HL
1
Selection of Over-Drive
0: Over-Drive LOW (GND RAIL)
1: Over-Drive HIGH (VDD RAIL)
4
MOT_TYP
1
Select Motor Type
0: LRA (Linear Resonant Actuator)
1: ERM (Eccentric Rotation Mass)
3:2
Reserved
2
Not used
2
Select PWM Divide
00: 1/1
01: 1/128
10: 1/256
11: 1/512
1:0
PWM_DIV
© 2012 Fairchild Semiconductor Corporation
FAH4830 • 1.0.1
Bit0
PWM_DIV
VLDO_OUT
Notes:
4. Connect the bottom DAP to ground.
Table 3.
Bit1
Description
OT
Reserved
FAH4830 — Haptic Driver for DC Motors (ERMs) and Linear Resonant Actuators (LRAs)
Register Definitions
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8

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
Control 1
Address: 21h
Reset Value: 0010_1100
Type: Read/Write
BOLD is default state
Bit #
Name
Size (Bits)
7:5
Input Resistance
3
4:2
VLDO_OUT
3
1:0
Reserved
2
Table 5.



Description
000: 8 kΩ
001: 10 kΩ
010: 12 kΩ
011: 14 kΩ
100: 16 kΩ
101: 18 kΩ
110: 20 kΩ
111: 22 kΩ
000: 2.4 V
001: 2.6 V
010: 2.8 V
011: 3.0 V
100: 3.2 V
101 :3.4 V
110: 3.6 V
Not used
Status
Address: 22h
Reset Value: 0000_1110
Type: Read Only
Bit #
Name
Size (Bits)
7:4
Reserved
4
Not used
3
VDD_G
1
0: Input voltage is not valid (under UVLO); input voltage is less than 2.3 V
(rising) / 2.1 V (falling)
1: Input voltage is valid (over UVLO)
2
VLDO_OUT_G
1
0: Regulator output is not valid (VLDO_OUT is less than 70% of VLDO_OUT
programmed)
1: Regulator output is valid
1
OT
1
0: Over-temperature protection is tripped
1: Over-temperature protection is not tripped
0
Reserved
1
Not used, default is 0
Table 6.
Description
FAH4830 — Haptic Driver for DC Motors (ERMs) and Linear Resonant Actuators (LRAs)
Table 4.
VDD vs. VLDO_OUT
VDD (V)
VLDO_OUT
(Programmed Voltage)
© 2012 Fairchild Semiconductor Corporation
FAH4830 • 1.0.1
2.7
2.4
2.6
3.0
2.4
2.6
2.8
3.3
2.4
2.6
2.8
3.0
3.2
4.5
2.4
2.6
2.8
3.0
3.2
3.4
3.6
5.0
2.4
2.6
2.8
3.0
3.2
3.4
3.6
5.5
2.4
2.6
2.8
3.0
3.2
3.4
3.6
www.fairchildsemi.com
9
user flexibility to obtain the correct resonant frequency
for the chosen LRA device.
The FAH4830 has the external PWM input pin for the
motor driver block. In ERM Mode, the device uses the
39 nF external capacitor as an integrator. This converts
the PWM output to differential DC levels on the
MDP / MDN outputs.
The input signal’s duty cycle changes the amplitude of
the positive and negative outputs for the motor drive.
The LRA and ERM motor vibration strength depends on
the PWM duty cycle. When the duty cycle is 50/50, the
device stops. The vibration is maximum when the duty
ratio is 1% to 99% or 99% to 1%. The regulator voltage
level controls the amplitude of the signal at the motor.
In the LRA Mode, to control the 10 kHz to 50 kHz
frequency range of the PWM input signal; the device
incorporates an internal clock-dividing feature that can
2
be modified via the I C register settings. This allows the
Figure 9.
LRA Motor Drive (MDN, MDP)
Figure 10.
© 2012 Fairchild Semiconductor Corporation
FAH4830 • 1.0.1
FAH4830 — Haptic Driver for DC Motors (ERMs) and Linear Resonant Actuators (LRAs)
Applications Information
System Block Diagram
www.fairchildsemi.com
10
Table 7.
ERM System Block Diagram
ERM Motor Function
PWM Duty Cycle
ERM Drive Voltage
VDD
90/10%
PWM
Duty
Cycle
GND
VDD
50/50%
PWM
Duty
Cycle
GND
10/90%
PWM
Duty
Cycle
© 2012 Fairchild Semiconductor Corporation
FAH4830 • 1.0.1
FAH4830 — Haptic Driver for DC Motors (ERMs) and Linear Resonant Actuators (LRAs)
Figure 11.
www.fairchildsemi.com
11
Table 8.
LRA System Block Diagram
LRA Resonant Actuator Function
LRA Drive Voltage at Resonant
Frequency
PWM Duty Cycle (1)
90/10% PWM
Duty Cycle
50/50% PWM
Duty Cycle
FAH4830 — Haptic Driver for DC Motors (ERMs) and Linear Resonant Actuators (LRAs)
Figure 12.
10/90% PWM
Duty Cycle
Note:
5. PWM frequency is a multiple of the LRA resonant frequency, which is controlled by I2C register control 0 bit zero
and one. For example, if the LRA resonant frequency is 175 Hz, the PWM frequency would be 22.4 kHz and the
I2C Divide By register would be programmed to 1/128.
© 2012 Fairchild Semiconductor Corporation
FAH4830 • 1.0.1
www.fairchildsemi.com
12
Over-Drive Motor Control for ERM
Low-Pass Filter
The Cf in Figure 1 (low-pass filter) is used to reduce the
high-frequency harmonics caused by the PWM signal
when the internal clock processing block operates. If Cf
is increased, the lower-frequency harmonics are
reduced. If the value is decreased, the higher-frequency
harmonics are decreased. Usually, 39 nF is
recommended for ERM devices. Verify that the cut-off
frequency is higher than the resonant frequency of the
haptic device. Cf Is a required component for the circuit
to operate properly. The low-pass filter cut-off frequency
may be determined as fC= 1 / (2π Rf C). At default
settings and Cf = 39 nF, the cut-off freqency is 408 Hz.
A common approach to driving DC motors is to overdrive a voltage that overcomes the inertia of the motor's
mass. The motor is often overdriven for a short time
before returning to the motor's rated voltage to sustain
rotation. The FAN4830 haptic block can over-drive a
motor up to the VDD voltage. Over-drive can also be
used to stop (or brake) a motor quickly. The haptic
driver can brake down to a voltage of GND. Reference
the motor datasheet for safe and reliable over-drive
voltage and duration. Normally, an ERM motor’s rated
voltage is 1.5 V, but it can be driven up to VDD for an
over-drive condition. The over-drive function should be
used during start and stop ONLY because it can
damage the ERM motor if it is used for longer than the
time guaranteed in the motor datasheet. The over-drive
feature also helps to eliminate long vibration tails, which
are undesirable in haptic feedback systems.
Gain Control
The gain of the FAH4830 is permanently set to a value
of 1 with the internal resistors, at any programmable
resistor value setting. If a motor requires a voltage less
than is programmable with the LDO, an external resistor
may be placed in parallel with capacitor Cf. The
resultant gain is the parallel combination of external Rf
and Internal Rf, divided by the Ri resistor.
This function could be used in the following steps:
1.
HEN = LOW
2.
PWM = 90%-10% (example)
Internal LDO
3.
ORDRVEN_HL = 1 (HIGH drive)
The internal LDO is designed for an I2C seven-step
adjustable output voltage. This provides flexibility for
various motor voltages and configurations for low-power
consumption. The LDO includes an internal circuit for
short-circuit current protection.
4.
ORDVEN = 1 (enabled) apply +VREG to motor (start)
5.
HEN = 1 (enabled motor drive)
6.
ORDVEN = 0 (disabled)
7.
PWM = signal (example “3 clicks”)
8.
ORDRVEN_HL = Low
9.
ORDVEN = 1 (enabled) apply –VREG to motor
(brake)
Serial Interface
On power-up, the device default values are invoked.
The FAH4830 allows programming through the
registers: the motor type, PWM dividing ratio, power
down, and others functions. The device functions
2
without any I C input signals connected.
10. HEN = 0 (disable motor drive)
Thermal Shutdown
11. ORDVEN = 0 (disabled)
The device has thermal shutdown capability. If the
junction temperature is above 150°C, the temperature
control block shuts down and stays off until the
temperature is below 134°C. The register values are
kept as written so that it’s not required to initialize again.
Over-Drive Duration
It is important that over-drive time not damage motors.
The over-drive duration time must be dependent on the
motor datasheet and care taken not to assert an overvoltage condition over the rated time limit of the motor.
Over-Current Limitation
Status Registers
The driver includes a current-limitation block to protect
against an over-current condition, mainly caused by a
stuck-rotor condition. Over-current protection limitation
is 500 mA typical.
© 2012 Fairchild Semiconductor Corporation
FAH4830 • 1.0.1
FAH4830 — Haptic Driver for DC Motors (ERMs) and Linear Resonant Actuators (LRAs)
Filter and Gain Control
The FAH4830 has a status register set that monitors
LDO input voltage, regulator output voltage, and overtemperature status.
www.fairchildsemi.com
13
3.0
0.15 C
10
A
2X
6
1.55
2.00
3.10
2.33
0.78
0.55
B
2.25
2.20
2.00
3.0
0.15 C
2X
TOP VIEW
0.8 MAX
0.23
0.02
D
1
0.50
0.25
5
RECOMMENDED LAND PATTERN
0.10 C
(0.20)
0.08 C
0.05
0.00
C
SIDE VIEW
SEATING
PLANE
(3.00±0.10)
2.25±0.05
PIN #1 IDENT
(0.38)
1
5
(3.00±0.10)
1.55±0.05
0.40±0.05
0.5
10
0.30
0.20
6
2.0
0.10
0.05
C A B
C
BOTTOM VIEW
A. CONFORMS TO JEDEC REGISTRATION MO-229,
VARIATION WEED-5
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994
D. LAND PATTERN DIMENSIONS ARE NOMINAL
REFERENCE VALUES ONLY
FAH4830 — Haptic Driver for DC Motors (ERMs) and Linear Resonant Actuators (LRAs)
Physical Dimensions
MLP10BrevA
Figure 13.
10-Lead, JEDEC MO-229, 3 mm Square, Molded Leadless Package (MLP)
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without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
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warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2012 Fairchild Semiconductor Corporation
FAH4830 • 1.0.1
www.fairchildsemi.com
14
FAH4830 — Haptic Driver for DC Motors (ERMs) and Linear Resonant Actuators (LRAs)
15
www.fairchildsemi.com
© 2012 Fairchild Semiconductor Corporation
FAH4830 • 1.0.1