Zarlink MT88E45BS 4-wire calling number identification circuit 2 Datasheet

MT88E45B
4-Wire Calling Number Identification Circuit 2
(4-Wire CNIC2)
Features
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Compatible with:
• Bellcore GR-30-CORE, SR-TSV-002476,
ANSI/TIA/EIA-716, TIA/EIA-777;
• ETSI ETS 300 778-1 (FSK only variant) & -2;
• BT (British Telecom) SIN227 & SIN242
Bellcore ‘CPE Alerting Signal’ (CAS), ETSI
‘Dual Tone Alerting Signal’ (DT-AS), BT Idle
State and Loop State ‘Tone Alert Signal’
detection
1200 baud Bell 202 and CCITT V.23 FSK
demodulation
Separate differential input amplifiers with
adjustable gain for Tip/Ring and telephone
hybrid or speech IC connections
Selectable 3-wire FSK data interface (bit
stream or 1 byte buffer)
Facility to monitor the stop bit for framing error
check
FSK Carrier detect status output
3 to 5V +/- 10% supply voltage
Uses 3.579545MHz crystal or ceramic
resonator
Low power CMOS with power down
Applications
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Bellcore CID (Calling Identity Delivery) and
CIDCW (Calling Identity Delivery on Call
Waiting) telephones and adjuncts
ETSI, BT CLIP (Calling Line Identity
Presentation) and CLIP with Call Waiting
telephones and adjuncts
Fax and answering machines
Computer Telephony Integration (CTI) systems
Ordering Information
MT88E45BS
20 Pin SOIC
MT88E45BN
20 Pin SSOP
-40°C to 85°C
Description
The MT88E45B is a low power CMOS integrated
circuit suitable for receiving the physical layer
signals used in North American (Bellcore) Calling
Identity Delivery on Call Waiting (CIDCW) and
Calling Identity Delivery (CID) services. It is also
suitable for ETSI and BT Calling Line Identity
Presentation (CLIP) and CLIP with Call Waiting
services.
The MT88E45B contains a 1200 baud Bell 202/
CCITT V.23 FSK demodulator and a CAS/DT-AS
detector. Two input op-amps allow the MT88E45B to
be connected to both Tip/Ring and the telephone
hybrid or speech IC receive pair for optimal CIDCW
telephone
architectural
implementation.
FSK
demodulation is always on Tip/Ring, while CAS
detection can be on Tip/Ring or Hybrid Receive. Tip/
Ring CAS detection is required for the Bellcore/TIA
Multiple Extension Interworking (MEI) and BT’s onhook CLIP. A selectable FSK data interface allows
the data to be processed as a bit stream or extracted
from a 1 byte on chip buffer. Power management has
been incorporated to power down the FSK or CAS
section when not required. Full chip power down is
also available. The MT88E45B is suitable for
applications using a fixed power source (with a +/10% variation) between 3 and 5V.
MODE
FSKen+Tip/Ring CASen
IN1+
+
IN1-
-
Anti-Alias
Filter
PWDN
GS1
+
IN2-
-
Carrier
Detector
Hybrid CASen
PWDN
MODE
Bias
Generator
PWDN
FSKen
OSC2
2130Hz
Bandpass
CASen
Control Bit
Decode
Oscillator
OSC1
DATA
Data Timing
Recovery
DCLK
FSKen
CASen
GS2
VREF
FSK
Demodulator
PWDN
PWDN
IN2+
FSK
Bandpass
2750Hz
Bandpass
CD
DR
STD
Tone
Detection
Algorithm
CASen
Guard
Time
Mux
•
May 2003
DR/STD
ST/GT
EST
Vdd
Vss
CB0 CB1 CB2
Figure 1 - Functional Block Diagram
1
MT88E45B
Data Sheet
VREF
1
20
IN2+
IN1+
2
19
IN2-
IN1-
3
18
GS2
GS1
4
17
CB2
Vss
5
16
CB1
OSC1
6
15
Vdd
OSC2
7
14
CD
CB0
8
13
ST/GT
DCLK
9
12
EST
DATA
10
11
DR/STD
MT88E45B
Figure 2 - Pin Connections
Pin Description
Pin # Name
1
VREF
Voltage Reference (Output). Nominally Vdd/2. It is used to bias the Tip/Ring and Hybrid input opamps.
2
IN1+
Tip/Ring Op-amp Non-inverting (Input).
3
IN1-
Tip/Ring Op-amp Inverting (Input).
4
GS1
Tip/Ring Gain Select (Output). This is the output of the Tip/Ring connection op-amp. The opamp should be used to connect the MT88E45B to Tip and Ring. The Tip/Ring signal can be
amplified or attenuated at GS1 via selection of the feedback resistor between GS1 and IN1-. FSK
demodulation (which is always on Tip/Ring) or CAS detection (for MEI or BT on-hook CLIP) of the
GS1 signal is enabled via the CB1 and CB2 pins. See Tables 1 and 2.
5
Vss
Power supply ground.
6
OSC1 Oscillator (Input). Crystal connection. This pin can also be driven directly from an external clock
source.
7
OSC2 Oscillator (Output). Crystal connection. When OSC1 is driven by an external clock, this pin
should be left open.
8
9
2
Description
CB0
Control Bit 0 (CMOS Input). This pin is used primarily to select the 3-wire FSK data interface
mode. When it is low, interface mode 0 is selected where the FSK bit stream is output directly.
When it is high, interface mode 1 is selected where the FSK byte is stored in a 1 byte buffer which
can be read serially by the application’s microcontroller.
The FSK interface is consisted of the DATA, DCLK and DR/STD pins. See the 3 pin descriptions
to understand how CB0 affects the FSK interface.
When CB0 is high and CB1, CB2 are both low the MT88E45B is put into a power down state
consuming minimal power supply current. See Tables 1 and 2.
DCLK 3-wire FSK Interface Data Clock (Schmitt Input/CMOS Output). In mode 0 (when the CB0 pin
is logic low) this is a CMOS output which denotes the nominal mid-point of a FSK data bit.
In mode 1 (when the CB0 pin is logic high) this is a Schmitt trigger input used to shift the FSK data
byte out to the DATA pin.
MT88E45B
Data Sheet
Pin Description
Pin # Name
10
11
12
13
DATA
Description
3-wire FSK Interface Data (CMOS Output). Mark frequency corresponds to logical 1. Space
frequency corresponds to logical 0.
In mode 0 (when the CB0 pin is logic low) the FSK serial bit stream is output to the DATA pin
directly.
In mode 1 (when the CB0 pin is logic high) the start bit is stripped off, the data byte and the trailing
stop bit are stored in a 9 bit buffer. At the end of each word signalled by the DR/STD pin, the
microcontroller should shift the byte out onto the DATA pin by applying 8 read pulses to the DCLK
pin. A 9th DCLK pulse will shift out the stop bit for framing error checking.
DR/STD 3-wire FSK Interface Data Ready/CAS Detection Delayed Steering (CMOS Output). Active
low.
When FSK demodulation is enabled via the CB1 and CB2 pins this pin is the Data Ready output.
It denotes the end of a word. In both FSK interface modes 0 and 1, it is normally hi and goes low
for half a bit time at the end of a word. But in mode 1 if DCLK starts during DR low, the first rising
edge of the DCLK input will return DR to high. This feature allows an interrupt requested by a low
going DR to be cleared upon reading the first DATA bit.
When CAS detection is enabled via the CB1 and CB2 pins this pin is the Delayed Steering output.
It goes low to indicate that a time qualified CAS has been detected.
EST
CAS Detection Early Steering (CMOS Output). Active high. This pin is the raw CAS detection
output. It goes high to indicate the presence of a signal meeting the CAS accept frequencies and
signal level. It is used in conjunction with the ST/GT pin and external components to time qualify
the detection to determine whether the signal is a real CAS.
ST/GT CAS Detection Steering/Guard Time (CMOS Output/Analog Input). It is used in conjunction
with the EST pin and external components to time qualify the detection to determine whether the
signal is a real CAS.
A voltage greater than VTGt at this pin causes the MT88E45B to indicate that a CAS has been
detected by asserting the DR/STD pin low. A voltage less than VTGt frees up the MT88E45B to
accept a new CAS and returns DR/STD to high.
14
CD
Carrier Detect (CMOS Output). Active low.
A logic low indicates that an FSK signal is present. A time hysteresis is provided to allow for
momentary signal discontinuity. The demodulated FSK data is ignored by the MT88E45B until
carrier detect has been activated.
15
Vdd
Positive power supply.
16
CB1
Control Bit 1 (CMOS Input). Together with CB2 this pin selects the MT88E45B’s functionality
between FSK demodulation, Tip/Ring CAS detection and Hybrid CAS detection.
When CB0 is high and CB1, CB2 are both low the MT88E45B is put into a power down state
consuming minimal power supply current. See Tables 1 and 2.
17
CB2
Control Bit 2 (CMOS Input). Together with CB1 this pin selects the MT88E45B’s functionality
between FSK demodulation, Tip/Ring CAS detection and Hybrid CAS detection.
When CB0 is high and CB1, CB2 are both low the MT88E45B is put into a power down state
consuming minimal power supply current. See Tables 1 and 2.
18
GS2
Hybrid Gain Select (Output). This is the output of the hybrid receive connection op-amp. The opamp should be used to connect the MT88E45B to the telephone hybrid or speech IC receive pair.
The hybrid receive signal can be amplified or attenuated at GS2 via selection of the feedback
resistor between GS2 and IN2-. When the CPE is off-hook CAS detection of the GS2 signal
should be enabled via the CB1 and CB2 pins. See Tables 1 and 2.
19
IN2-
Hybrid Op-amp Inverting (Input).
20
IN2+
Hybrid Op-amp Non-Inverting (Input).
3
MT88E45B
CB0 CB1 CB2
Data Sheet
FSK
Interface
Function
0/1
1
1
Set by CB0 FSK Demodulation. Tip/Ring input (GS1) selected. DR/STD is DR.
0/1
1
0
Set by CB0 Hybrid CAS Detection. Hybrid Receive input (GS2) selected. DR/STD is STD.
0/1
0
1
Set by CB0 Tip/Ring CAS Detection. Tip/Ring input (GS1) selected. DR/STD is STD.
When the line is off-hook, a Bellcore/TIA Multiple Extension Interworking (MEI)
compatible Type 2 CPE should be able to detect CAS from Tip/Ring while the
CPE is on-hook because it may be the ACK sender. Tip/Ring CAS detection is
also required for BT’s on-hook CLIP.
1
0
0
Mode 1
Power Down. The MT88E45B is disabled and draws virtually no power supply
current.
0
0
0
Mode 0
Reserved for factory testing.
Table 1 - CB0/1/2 Functionality
The number of control bits (CB) required to interface the MT88E45B with the microcontroller depends on the
functionality of the application, as shown in Table 2.
Control
s
Functionality Group
Description
FSK (mode 0 or 1) and
Hybrid CAS only
(Non MEI compatible)
CB2
CB0 is hardwired to Vdd or Vss to select the FSK
interface.
CB1 hardwired to Vdd.
The microcontroller uses CB2 to select between the 2
functions.
FSK (mode 0 or 1),
Hybrid CAS,
Tip/Ring CAS
(MEI compatible or BT on-hook CLIP)
CB1
CB2
CB0 is hardwired to Vdd or Vss to select the FSK
interface.
The microcontroller uses CB1 and CB2 to select between
the 3 functions.
FSK (mode 1),
Hybrid CAS,
Tip/Ring CAS,
Power Down
(MEI compatible or BT on-hook CLIP)
CB1
CB2
CB0 is hardwired to Vdd to select FSK interface mode 1.
The microcontroller uses CB1 and CB2 to select between
the 4 functions.
FSK (mode 0), Hybrid CAS,
Tip/Ring CAS, Power Down
(MEI compatible or BT on-hook CLIP)
CB0
CB1
CB2
All 3 pins are required.
Table 2 - Control Bit Functionality Groups
Functional Overview
The MT88E45B is compatible with FSK and FSK
plus CAS (CPE Alerting Signal) based Caller ID
services around the world. Caller ID is the generic
name for a group of services offered by telephone
operating companies whereby information about the
calling party is delivered to the subscriber. In Europe
and some other countries Caller ID is known as
Calling Line Identity Presentation (CLIP). ETSI calls
CAS ‘Dual Tone Alerting Signal’ (DT-AS), BT calls it
‘Tone Alert Signal’.
Depending on the service, data delivery can occur
when the line is in the on-hook or off-hook state. In
most countries the data is modulated in either Bell
4
202 or CCITT V.23 FSK format and transmitted at
1200 baud from the serving end office to the
subscriber’s terminal. Additionally in off-hook
signalling, the special dual tone CAS is used to alert
the terminal before FSK data transmission. BT uses
CAS to alert the terminal prior to FSK in both onhook (Idle State) and off-hook (Loop State)
signalling.
In North America, Caller ID uses the voiceband data
transmission interface defined in the Bellcore
document GR-30-CORE. The terminal or CPE
(Customer Premises Equipment) requirements are
defined in Bellcore document SR-TSV-002476.
Typical services are CND (Calling Number Delivery),
CNAM (Calling Name Delivery), VMWI (Visual
Data Sheet
Message Waiting Indicator) and CIDCW (Calling
Identity Delivery on Call Waiting).
In Europe, Caller ID requirements are defined by
ETSI. The CPE documents are ETS 300 778-1 for
on-hook, ETS 300 778-2 for off-hook. The end office
requirements are ETS 300 659-1 (on-hook) and ETS
300 659-2 (off-hook). ETSI has defined services
such as CLIP and CLIP with Call Waiting which are
similar to those of Bellcore. Some European
countries produce their own national specifications.
For example, in the UK BT’s standards are SIN227
and SIN242, the UK CCA (Cable Communications
Association) standard is TW/P&E/312.
In on-hook Caller ID, such as CND, CNAM and CLIP,
the information is typically transmitted (in FSK) from
the end office before the subscriber picks up the
phone. There are various methods such as between
the first and second rings (North America), between
an abbreviated ring and the first true ring (Japan,
France and Germany). On-hook Caller ID can also
occur without ringing for services such as VMWI. In
BT’s on-hook CLIP, the signalling begins with a line
polarity reversal, followed by CAS and then FSK.
Bellcore calls an on-hook capable Caller ID CPE a
‘Type 1 CPE’.
In off-hook Caller ID, such as CIDCW and CLIP with
Call Waiting, information about a new calling party is
sent to the subscriber who is already engaged in a
call. Bellcore’s method uses CAS to alert the CPE.
When the CPE detects CAS and there are no offhook extensions, the CPE should mute its
transmission path and send an acknowledgment to
the end office via a DTMF digit called ACK. Upon
receiving ACK, the end office will send the FSK data.
Bellcore calls an off-hook capable CPE a ‘Type 2
CPE’. A Type 2 CPE is capable of off-hook and Type
1 functionalities and should ACK with a DTMF ‘D’.
The ETSI and BT off-hook signalling protocols are
similar to Bellcore’s but with timing and signal
parametric differences. ETSI has no requirement for
off-hook extension checking before ACK.
One factor affecting the quality of the CIDCW service
is the CPE’s CAS speech immunity. Although the
end office has muted the far end party before and
after it sends CAS, the near end (the end which is to
receive the information) user may be still talking.
Therefore the CPE must be able to detect CAS
successfully in the presence of near end speech.
This is called the talkdown immunity. The CPE must
also be immune to imitation of CAS by speech from
both ends of the connection because the CAS
detector is continuously exposed to speech
throughout the call. This is called the talkoff
immunity.
MT88E45B
If the CPE is a telephone, one way to achieve good
CAS speech immunity is to put CAS detection on the
telephone hybrid or speech IC receive pair instead of
on Tip and Ring. Talkdown immunity improves
because the near end speech has been attenuated
while the CAS level is the same as on Tip/Ring,
resulting in improved signal to speech ratio. Talkoff
immunity is also improved because the near end
speech has been attenuated.
In the Bellcore SR-TSV-002476 Issue 1 off-hook
protocol, the CPE should not ACK if it detected an
off-hook extension. The FSK will not be sent and the
customer will not receive the Call Waiting ID.
Bellcore, together with the TIA (Telecommunications
Industry Association) TR41.3.1 working group, has
defined a CPE capability called Multiple Extension
Interworking (MEI) which overcomes this problem.
In the MEI scheme, all MEI compatible CPEs must
be capable of detecting CAS when the line is offhook, even though the CPE itself may be on-hook.
This is because under some conditions an on-hook
CPE may become the ACK sender. Another reason
for the on-hook CPE to detect CAS is to maintain
synchronous call logs between on and off-hook
CPEs. When CAS is received and all off-hook CPEs
are MEI compatible, one of the CPEs will ACK and
all compatible CPEs will receive FSK.
A problem arises in a CPE where the CAS detector
is connected only to the hybrid or speech IC receive
pair: it cannot detect CAS when it is on-hook. The
reason is that when the CPE is on-hook either the
hybrid/speech IC is non functional or the signal level
is severely attenuated. Therefore an on-hook Type 2
CPE must be capable of detecting CAS from Tip/
Ring, in addition to detecting CAS from the hybrid/
speech IC receive signal when it is off-hook.
The MT88E45B offers an optimal solution which
combines good speech immunity and MEI
compatibility. Two input op-amps allow the
MT88E45B to be connected both to Tip/Ring and to
the hybrid/speech IC receive pair. Both connections
can be differential or single ended. FSK
demodulation is always on the Tip/Ring signal. CAS
detection can be from the Tip/Ring or hybrid/speech
IC receive signal. Being able to detect CAS on Tip/
Ring also makes the MT88E45B suitable for BT onhook CLIP applications.
For applications such as those in most European
countries where Tip/Ring CAS detection is not
needed, then the Tip/Ring and Hybrid op-amp gains
can be tailored independently to meet country
specific FSK and CAS signal level requirements
5
MT88E45B
respectively. Note that since the Hybrid op-amp is for
CAS detection only, its gain can always be tailored
specifically for the CAS signal level.
The FSK demodulator is compatible with Bellcore,
ETSI and BT standards. The demodulated FSK data
is either output directly (bit stream mode) or stored in
a one byte buffer (buffer mode). In the buffer mode,
the stop bit immediately following a byte is also
stored and can be shifted out after the data byte.
This facility allows for framing error checking
required in Type 2 CPEs. In the bit stream mode, two
timing signals are provided. One indicates the bit
sampling instants of the data byte, the other the end
of byte. A carrier detector indicates presence of
signal and shuts off the data stream when there is no
signal.
The entire chip can be put into a virtually zero
current power down mode. The input op-amps, FSK
demodulator, CAS detector and the oscillator are all
shut off. Furthermore, power management has been
incorporated to minimize operating current. When
FSK is selected the CAS detector is powered down.
When CAS is selected the FSK demodulator is
powered down.
Functional Description
3 to 5V Operation
The MT88E45B’s FSK and CAS reject levels are
proportional to Vdd. When operated at Vdd equal 3V
+/- 10%, to keep the FSK and CAS reject levels as at
5V (nominal) the Tip/Ring and Hybrid op-amp gains
should be reduced from those of 5V. Gains for
nominal Vdd (with a +/- 10% variation) other than 3
or 5V can be chosen as interpolation between the 3
and 5V settings.
Input Configuration
The MT88E45B provides an input arrangement
comprised of two op-amps and a bias source (VREF).
VREF is a low impedance voltage source which is
used to bias the op-amp inputs at Vdd/2. The Tip/
Ring op-amp (IN1+, IN1-, GS1 pins) is for connecting
to Tip and Ring. The Hybrid op-amp (IN2+, IN2-,
GS2 pins) is for connecting to the telephone hybrid
or speech IC receive pair.
Either FSK or CAS detection can be selected for the
Tip/Ring connection, while the hybrid connection is
for CAS detection only. Phrased in another way, FSK
demodulation is always on Tip/Ring, while CAS
detection can be on Tip/Ring or Hybrid Receive. Tip/
Ring CAS detection is required for MEI and BT onhook CLIP, while Hybrid CAS detection is needed for
optimal CAS speech immunity.
6
Data Sheet
The feedback resistor connected between GS1 and
IN1- can be used to adjust the Tip/Ring signal gain.
The feedback resistor connected between GS2 and
IN2- can be used to adjust the hybrid receive signal
gain. When the Tip/Ring op-amp is selected, the
GS2 signal is ignored. When the Hybrid op-amp is
selected, the GS1 signal is ignored.
Either or both op-amps can be configured in the
single ended input configuration shown in Figure 3,
or in the differential input configuration shown in
Figure 4.
IN+
C
IN-
RIN
Voltage Gain
(AV) = RF / RIN
Highpass Corner Frequency
f-3dB = 1/(2πRINC)
RF
GS
VREF
Figure 3 - Single Ended Input Configuration
C1
R1
IN+
IN-
C2
R4
R5
GS
R3
R2
VREF
Differential Input Amplifier
C1 = C2
R1 = R4 (For unity gain R5= R4)
R3 = (R2R5) / (R2 + R5)
Voltage Gain
Highpass Corner Frequency
(AVdiff) = R5/R1
f-3dB = 1/(2πR1C1)
Input Impedance
(ZINdiff) = 2
R12 + (1/ωC)2
Figure 4 - Differential Input Configuration
CAS Detection
In North America, CAS is used in off-hook signalling
only. In Europe (ETSI) it is used in off-hook
signalling, and by BT in both on and off-hook
signalling. ETSI calls it the Dual Tone Alerting Signal
(DT-AS). Although the ETSI on-hook standard
contains a DT-AS specification, BT is the only
administration known to employ CAS in on-hook
signalling. (BT calls it Tone Alert Signal.) The CAS/
DT-AS characteristics are summarized in Table 3.
MT88E45B
Data Sheet
BTc
(Off-hook = ‘Loop State’)
(On-hook = ‘Idle State’)
Bellcorea
(Off-hook only)
ETSIb
(Off-hook)
+/-0.5%
+/-0.5%
Off-hook: +/-0.6%
On-hook: +/-1.1%
Signal Level (per tone)
-14 to -32 dBmd
-9.78 to -32.78 dBm
(-12 to -35 dBVe)
+0.22 to -37.78 dBm
(-2 to -40 dBV)
Reject Level (per tone)
-45 dBm
Maximum Twist (V2130Hz/V2750Hz)
+/-6 dB
+/-6 dB
+/-7 dB
75 to 85 ms
75 to 85 ms
Off-hook: 80 to 85 ms
On-hook: 88 to 110 ms
2130 Hz and 2750 Hz
CAS/DT-AS Characteristics
Frequency Tolerance
Duration
On-hook: -43.78 dBm
(-46 dBV)
Reject Duration
Signal to Noise Ratio
Off-hook: <=70 ms
On-hook: <=20 ms
Speech
Speech
Off-hook: Speech
On-hook: >= 20 dB
(300-3400 Hz)
Hybrid Op-amp (GS2) Gain
Vdd = 5V +/- 10%
0 to -5 dB
0 to -5 dB
0 dB
Hybrid Op-amp (GS2) Gain
Vdd = 3V +/- 10%
-3.5 to -8.5 dB
-3.5 to -8.5 dB
-3.5 dB
a. SR-TSV-002476, Issue 1 Dec 1992
b. ETS 300 778-2 Jan 98. The DT-AS plus FSK variant of ETSI on-hook signalling described in ETS 300 778-1 is not supported
because on-hook DT-AS uses the GS1 op-amp. With the GS1 gain in Table 4, the DT-AS minimum level will be below the
MT88E45B’s minimum accept level.
c. SIN227 Issue 3 Nov 97, SIN242 Issue 2 Nov 96
d. dBm - Decibels above or below a reference power of 1 mW into 600 ohms. 0 dBm = 0.7746 Vrms.
e. dBV - Decibels above or below a reference voltage of 1 Vrms. 0 dBV = 1 Vrms
Table 3 - CAS/DT-AS Characteristics
Table 3 shows the Hybrid op-amp (GS2) gain for
operation at 3V and 5V nominal Vdd, with a ± 10%
Vdd variation. For 3V operation, the Hybrid op-amp
gain should be reduced from the 5V setting to
maintain the CAS reject level and to maintain the
talkoff immunity: the CAS threshold is directly
proportional to Vdd, when Vdd is reduced the
threshold becomes lower, hence lower level CAS are
accepted. If the gain is not reduced, the MT88E45B
will be more talkoff prone. In Table 3, the GS2 gain is
shown as a range. By adopting the lower gain, talkoff
immunity can be improved.
When CAS detection is selected, the dual purpose
output pin DR/STD is STD. STD goes low when CAS
has been detected, and returns high after CAS has
ended.
CAS Guard Time
The guard time circuit shown in Figure 5 implements
a timing algorithm which determines whether the
signal is a CAS. Proper selection of the guard time(s)
is key to good speech immunity. The first indication
that there might be a CAS is when EST goes high.
EST high indicates that both tones are present. EST
low indicates that one or both tones is not present.
STD low indicates that CAS has been detected.
When STD returns high it indicates that CAS has
ended.
The timing algorithm consists of 2 components: a
tone present guard time (tGP) and a tone absent
guard time (tGA). tGP sets the minimum accept
duration for CAS. That is, both tones must be
detected continuously for tGP for STD to go low to
indicate that CAS has been detected. For STD to
return high to indicate that CAS has ended, one or
both tones must have disappeared for tGA. The
purpose of tGA is to bridge over momentary EST
dropouts once EST has met the minimum tone
duration so as to decrease the likelihood of a long
talkoff being broken up into several talkoffs. Usually
tGA is set very short or removed altogether because
there is another way to deal with the problem (by
ignoring further detections for 2 seconds after every
detection).
7
MT88E45B
Data Sheet
MT88E45B
Both Tones Present
Vdd
P Q1
C
+
ST/GT
-
VTGt
Vdiode
Comparator
R1
R2
N Q2
Rp=R1 || R2
= Vss
EST
DR/STD
Indicates STD in CAS
detection mode
CAS
tDP
tDA
tABS
EST
tREC
tGP
tGA
tGP=R1C ln [Vdd / (Vdd-VTGt)]
tGA=RpC ln
Vdd - Vdiode (Rp/R2)
VTGt - Vdiode (Rp/R2)
Rp=R1 || R2
ST/GT
tGA=0 if R2=0
STD
Figure 5 - CAS Guard Time Circuit Operation
Tone present guard time (tGP) operation: In Figure 5
initially there is no CAS, EST is low so Q1 is off. C
has been fully charged applying 0V to ST/GT so Q2
is on. When both tones are detected EST goes high
and turns off Q2. Because C has been fully charged
(ST/GT=0V), the comparator output is low and Q1
stays off. With both Q1 and Q2 off the high at EST
discharges C through R1 and the ST/GT voltage
increases from 0V. When the voltage exceeds the
comparator threshold VTGt, which is typically 0.5
Vdd, the comparator output goes high; Q1 turns on
and accelerates the discharge of C (ST/GT goes
quickly to Vdd); STD goes low to indicate that a valid
CAS has been received. If one or both tones
disappeared before tGP has been reached (i.e. when
ST/GT voltage is still below VTGt), Q2 turns back on
and charges C quickly to bring the ST/GT voltage
back to 0V. Then if EST goes high again the tGP
duration must start over.
Tone absent guard time (tGA) operation: In Figure 5
initially both tones have been detected for tGP so C is
fully discharged and ST/GT is at Vdd. While both
tones continue to be detected EST stays high; ST/GT
8
is at Vdd (the comparator output is high); so Q1 is on
and Q2 is off. When one or both tones stop EST
goes low and turns off Q1. Because C is fully
discharged (ST/GT=Vdd), the comparator output is
high and Q2 stays off. With both Q1 and Q2 off the
low at EST charges C through Rp=(R1 || R2) and the
ST/GT voltage falls towards 0V. When the voltage
has fallen below VTGt, the comparator output goes
low. Since EST is also low Q2 turns on and
accelerates the charging of C so that ST/GT goes
quickly to 0V. STD goes high to indicate that the CAS
has ended. If EST goes back to high before tGA has
been reached (i.e. when ST/GT voltage is still above
VTGt), Q1 turns back on and discharges C quickly to
bring the ST/GT voltage back to Vdd. Then if EST
goes low again the tGA duration must start over. To
set tGA=0, set R2 to 0.
In Figure 5, tDP is the delay from the start of CAS to
EST responding, tDA is the delay from the end of CAS
to EST responding. The total delay from the start of
CAS to STD responding is tREC=tDP+tGP. The total
delay from the end of CAS to STD responding is
tABS=tDA+tGA.
MT88E45B
Data Sheet
Parameter
North America: Bellcorea
Europe: ETSIb
UK: BTc
Mark (Logical 1) Frequency
1200 Hz +/- 1%
1300 Hz +/- 1.5%
Space (Logical 0) Frequency
2200 Hz +/- 1%
2100 Hz +/- 1.5%
-4.23 to -36.20 dBm
(476 to 12 mVrms)d
-5.78 to -33.78 dBme
(-8 to -36 dBV)f,g
Signal Reject Level
-48.24 dBm (3mVrms) for
On-hook No Ring Signalling
such as VMWI
On-hook only:
-47.78 dBm
(-50dBV)
Transmission Rate
1200 baud +/- 1%
1200 baud +/- 1%
Twist (VMARK/VSPACE)
-6 to +10 dB
-6 to +6 dB
Signal to Noise Ratio
Single Tone (f):
-18 dB (f<=60Hz)
-12 dB (60<f<=120Hz)
-6 dB (120<f<=200Hz)
+25 dB (200<f<3200Hz)
+6 dB (f>=3200Hz)
>= 25 dB
(300 to 3400 Hz)
>= 20 dB
(300 to 3400 Hz)
Tip/Ring Op-Amp (GS1) Gain
Vdd = 5V +/- 10%
0 dB
-2 dBh
0 dB
Tip/Ring Op-Amp (GS1) Gain
Vdd = 3V +/- 10%
-3.5 dB
-5.5 dBi
-3.5 dB
Received Signal Level
a.
b.
c.
d.
e.
f.
g.
h.
i.
-5.78 to -37.78 dBm
(-8 to -40 dBV)
ANSI/TIA/EIA-716 and TIA/EIA-777. Bellcore has agreed to the values and will synchronize its requirements.
ETS 300 778-1 (On-hook) Sep 97, ETS 300 778-2 (Off-hook) Jan 98.
SIN 227 Issue 3 Nov 97, SIN242 Issue 2 Nov 96.
North American on-hook signalling range. The off-hook range is inside the on-hook range: 190mVrms to 12mVrms.
dBm - Decibels above or below a reference power of 1 mW into 600 ohms. 0 dBm = 0.7746 Vrms
dBV - Decibels above or below a reference voltage of 1 Vrms. 0 dBV = 1 Vrms.
ETSI on-hook signalling range. The off-Hook signalling levels are inside this range: -8.78 to -30.78 dBm (-11 to -33 dBV).
The 5V ETSI Tip/Ring op-amp gain can be 0 dB if there is no FSK reject level requirement.
The 3V ETSI Tip/Ring op-amp gain can be -3.5dB if there is no FSK reject level requirement.
Table 4 - FSK Signal Characteristics
FSK Demodulation
The FSK characteristics are shown in Table 4. In
North America, TIA (Telecommunications Industry
Association) also sets standards. The Type 1 Caller
ID CPE standard is ANSI/TIA/EIA-716. The Type 2
standard is TIA/EIA-777. The North American FSK
characteristics in Table 4 are from ANSI/TIA/EIA716. They differ from those Bellcore published in SRTSV-002476 and SR-3004. Bellcore is represented
in TR41.3.1 and will synchronize to the TIA
requirements in its future documents.
The TIA Type 1 standard includes an FSK reject
level:
•
•
if data is not preceded by ringing (e.g. VMWI),
FSK signals below 3mVrms (-48.24 dBm) shall
be rejected
if data is preceded by ringing, FSK detection
may be extended below 3mVrms
The MT88E45B is compliant with the Bellcore/TIA,
ETSI and BT requirements with the Tip/Ring op-amp
gains in Table 4. In Europe if the country specific
FSK requirements do not incorporate ETSI’s FSK
reject level then the Tip/Ring op-amp gain can also
be 0dB at 5V and -3.5dB at 3V to meet the ETSI
minimum CAS level for on-hook signalling (-40 dBV).
For 3V operation, the FSK receiver becomes more
sensitive and lower level signals will be accepted
than at 5V. To maintain the FSK reject level, the Tip/
Ring input op-amp gain should be reduced. Note that
since the Tip/Ring op-amp is also used for Tip/Ring
CAS detection, the CAS level will also be reduced for
on-hook detection.
FSK Data Interface
The MT88E45B provides a powerful dual mode 3wire interface so that the data bytes in the
demodulated FSK bit stream can be extracted
without the need either for an external UART or for
the CPE’s microcontroller to perform the function in
9
MT88E45B
software. The interface is specifically designed for
the 1200 baud rate and is consisted of 3 pins: DATA,
DCLK (Data Clock) and DR (Data Ready). DR/STD
is a dual purpose output pin. When FSK is selected it
is DR.
Two modes (modes 0 and 1) are selectable via the
CB0 pin. In mode 0, the FSK bit stream is output
directly. In mode 1, the data byte and the trailing stop
bit are stored in a 9 bit buffer. If mode 1 is desired,
the CB0 pin can be hardwired to Vdd. If mode 0 is
desired and full chip power down is not required, the
CB0 pin can be hardwired to Vss.
In Bellcore’s off-hook protocol, a Type 2 CPE should
restore the voicepath within 50ms after the end of
the FSK signal. Due to noise, end of carrier detection
is not always reliable. The TIA Type 2 standard
stipulates that the CPE must detect the end of FSK
when any one of the following occurs:
•
•
•
absence of carrier signal or,
more than five framing errors (trailing stop bit a
0 instead of a 1) have been detected in the FSK
message or,
more than 150ms of continuous mark signal or
space signal has been detected.
Mode 0 - Bit Stream Mode
This mode is selected when the CB0 pin is low. In
this mode the FSK data is output directly to the DATA
pin. DCLK and DR pins are timing signal outputs
(see Figure 13).
For each received stop and start bit sequence, the
MT88E45B outputs a fixed frequency clock string of
8 pulses at the DCLK pin. Each DCLK rising edge
occurs in the middle of a DATA bit cell. DCLK is not
generated for the start and stop bits. Consequently,
DCLK will clock only valid data into a peripheral
device such as a serial to parallel shift register or a
microcontroller. The MT88E45B also outputs an end
of word pulse (Data Ready) at the DR pin. DR goes
low for half a nominal bit time at the beginning of the
trailing stop bit. It can be used to interrupt a
microcontroller or cause a serial to parallel converter
to parallel load its data into the microcontroller. Since
the DR rising edge occurs in the middle of the stop
bit, it can also be used to read the stop bit to check
for framing error.
Alternatively, DCLK and DATA may occupy 2 bits of a
microcontroller’s input port. The microcontroller polls
the input port and saves the DATA bit whenever
DCLK changes from low to high. When DR goes low,
10
Data Sheet
the word may then be assembled from the last 8
saved bits.
DATA may also be connected to a personal
computer’s serial communication port after
conversion from CMOS to RS-232 voltage levels.
Mode 1 - Buffer Mode
This mode is selected when the CB0 pin is high. In
this mode the received byte is stored on chip. At the
end of a byte DR goes low to indicate that a new byte
has become available. The microcontroller applies
DCLK pulses to read the register contents serially
out of the DATA pin (see Figure 14).
Internal to the MT88E45B, the start bit is stripped off,
the data bits and the trailing stop bit are sampled and
stored. Midway through the stop bit, the 8 data bits
and the stop bit are parallel loaded into a 9 bit shift
register and DR goes low. The register’s contents
are shifted out to the DATA pin on the supplied
DCLK’s rising edges in the order they were received.
The last bit must be shifted out and DCLK returned
to low before the next DR. DCLK must be low for tDDS
before DR goes low and must remain low for tDDH
after DR has gone low (see Figure 14).
If DCLK begins while DR is low, DR will return to high
upon the first DCLK rising edge. If DR interrupts a
microcontroller then this feature allows the interrupt
to be cleared by the first read pulse. Otherwise DR is
low for half a nominal bit time (1/2400 sec).
Reading the stop bit allows the software to check for
framing errors. When framing error is not checked
the microcontroller only needs to send 8 DCLK
pulses to shift the data byte out.
Carrier Detect
The carrier detector provides an indication of the
presence of a signal in the FSK frequency band. It
detects the presence of a signal of sufficient
amplitude at the output of the FSK bandpass filter.
The signal is qualified by a frequency aware digital
algorithm before the CD output is set low to indicate
carrier detection. A 10ms hysteresis is provided to
allow for momentary signal dropout once CD has
been activated. CD is released when there is no
activity at the FSK bandpass filter output for 10ms.
When CD is inactive (high), the raw output of the
FSK demodulator is ignored by the internal data
timing recovery circuit. In mode 0 the DATA, DCLK
and DR pins are forced high. In mode 1 the output
shift register is not updated and DR is high; if DCLK
is clocked, DATA is undefined.
MT88E45B
Data Sheet
Note that signals such as speech, CAS and DTMF
tones also lie in the FSK frequency band and the
carrier detector may be activated by these signals.
They will be demodulated and presented as data. To
avoid the false data, the MT88E45B should be put
into CAS or power down mode when FSK is not
expected. Ringing, on the other hand, does not pose
a problem as it is ignored by the carrier detector.
Interrupt
The DR/STD output can be used to interrupt a
microcontroller. When the MT88E45B is the only
interrupt source, DR/STD can be connected directly
to the microcontroller’s interrupt input. Figure 9
shows the necessary connections when the
MT88E45B is one of many interrupt sources. The
diodes and resistors implement a wired-or so that the
microcontroller is interrupted (INT low active or
falling edge triggered) when one or more of INT1,
INT2 or DR/STD is low. The microcontroller can
determine which one of DR/STD, INT1 or INT2
caused the interrupt by reading them into an input
port.
When system power is first applied and CB0/1/2
have already been configured to select CAS
detection, DR/STD will power up as logic low. This is
because there is no charge across the ST/GT
capacitor in Figure 5, hence ST/GT is at Vdd which
causes STD to be low. If DR/STD is used to interrupt
a microcontroller the interrupt will not clear until the
capacitor has charged up. Therefore upon initial
power up the microcontroller should ignore this
interrupt source until there is sufficient time to charge
the capacitor. Alternatively, the MT88E45B can be
put into power down mode: DR/STD goes high and
clears the interrupt, ST/GT goes low and the
capacitor will charge up quickly.
Power Down
selected, the CAS detector is powered down. When
CAS is selected the FSK demodulator is powered
down. The two input op-amps are not affected and
both will remain operational.
Oscillator
The MT88E45B requires a 3.579545MHz crystal or
ceramic resonator to generate its oscillator clock. To
meet the CAS detection frequency tolerance
specifications the crystal or resonator must have a
0.1% frequency tolerance. The crystal specification
is as follows: (e.g. CTS MP036S)
Frequency:
Frequency Tolerance:
Resonance Mode:
Load Capacitance:
Maximum Series
Resistance:
Maximum Drive Level:
3.579545MHz
± 0.1% (over temperature
range of the application)
Parallel
18pF
150Ω
2mW
Alternatively an external clock source can be used.
In which case the OSC1 pin should be driven directly
from a CMOS buffer and the OSC2 pin left open.
For 5V+/-10% applications any number of
MT88E45B’s can be connected as shown in Figure
6 so that only one crystal is required.
MT88E45B
OSC1
OSC2
3.579545 MHz
MT88E45B
OSC1
OSC2
MT88E45B
OSC1
OSC2
to the
next MT88E45B
(For 5V+/-10% applications only)
Figure 6 - Common Crystal Connection
The MT88E45B can be powered down to consume
virtually no power supply current via a state of the
CB0/1/2 pins. Momentary transition of CB0/1/2 into
the power down code will not activate power down.
In power down mode both input op-amps, VREF and
the oscillator are non functional. DCLK becomes an
input because to select the power down state CB0 is
1 which will select FSK interface mode 1. If the
application uses FSK interface mode 0 and the
MT88E45B needs to be powered down then a pull
down resistor should be added at the DCLK pin to
define its state during power down (R15 in Figure 7).
When the MT88E45B is powered down DATA, DR/
STD, CD are high; EST and ST/GT are low.
To reduce the operating current an Intelligent Power
Down feature has been incorporated. When FSK is
11
MT88E45B
Data Sheet
Application Circuits
Tx+
TIP
TIP
RING
RING
Telephone
Hybrid
or
Speech IC
(Symbolic)
Microphone
Tx-
Rx+
Speaker
Rx-
R5
C1
R1
D1
R6
R3
D2
D3
C2 R2
R11
MT88E45B
R7
VREF
IN2+
IN1+
IN2-
IN1-
GS2
GS1
CB2
Vss
CB1
OSC1
Vdd
OSC2
CD
R10
R8 C3
R9 C4
R12
R4
D4
= To Microcontroller
Vss Xtal
= From Microcontroller
(FSK Interface Mode 1 selected)
R15 is required only if both FSK
interface mode 0 and power
down features are used.
R15
Vdd
C5
ST/GT
CB0
DCLK
EST
DATA
DR/STD
C6
R13
R14
D5
Unless stated otherwise, resistors are 1%, 0.1Watt; capacitors are 5%, 6.3V.
C6 should be
connected directly
across Vdd and Vss
pins
For 1000Vrms, 60Hz isolation from Tip to Earth and Ring to Earth:
R1,R2
430K, 0.5W, 5%, 475V min. C1,C2
2n2, 1332V min.
(e.g. IRC type GS-3)
If the 1000Vrms is handled by other methods then this circuit has to meet the FCC Part 68 Type B Ringer requirements:
R1,R2
432K, 0.1W, 1%, 56V min. C1,C2
2n2, 212V min.
Common to both sets of R1,R2:
R3,R4
34K
R8,R9
464K
R13
825K
R14
226K or 26K1
R15
100K, 20%
C3,C4
C5
C6
D1-D4
D5
Xtal
2n2
100n
100n, 20%
Diodes. 1N4148 or equivalent
Diode. 1N4148 or equivalent
3.579545MHz, 0.1% crystal
or ceramic resonator
R5,R10
R6,R11
R7,R12
5V, 0dB gain
53K6
60K4
464K
3V, -3.5dB gain
35K7
40K2
309K
Figure 7 - Application Circuit: Bellcore MEI Compatible Type 2 Telephone
12
MT88E45B
Data Sheet
1.00
0.95
Gain ratio for
Bellcore GS1, GS2
ETSI GS2 op amps
0.90
0.85
0.794
Gain Ratio
0.80
0.75
0.70
0.65
Gain ratio for ETSI
GS1 op amp
0.668
0.60
0.55
0.531
0.50
3.0
3.5
4.0
4.5
5.0
Nominal Vdd (Volts)
Figure 8 - Gain Ratio as a Function of Nominal Vdd
Gain Setting Resistor Calculation Example for Figure 8:
•
•
•
For the desired nominal Vdd, use Figure 8 to determine approximate Av.
For the GS1 op-amp, start with the 0dB gain setting resistor values of R50dB, R6 0dB and R7 0dB. In
Figure 7 these values are 53K7, 60K4 and 464K respectively. Keep C1,C2,R1,R2,R3,R4 as in Figure 7
to maintain the highpass corner frequency constant for all gain settings.
For the desired gain setting of Av:
R7Av= R70dB x AV
Scaled for desired gain. Choose
the closest standard resistor value as R7Av.
Actual Av from now on is R7Av/R70db
R5Av= R50dB x AV
Scaled for good common mode range. Choose
the closest standard resistor value as R5Av.
1/R6Av = 1/R5Av - 1/R7Av
•
Calculate R6Av so that R5Av=R6Av || R7Av. Choose
the closest standard resistor value as R6Av.
Repeat for R 10, R 11, R 12 for the GS2 op-amp.
Example:
•
•
•
For a gain of -3.5dB, Av=10 -3.5/20 = 0.668
R7 -3.5dB= 464K x 0.668 = 309K9, the closest standard resistor value is 309K.
Av is now 309K/464K = 0.666
R5 -3.5dB= 53K6 x 0.666 = 35K7, the closest standard resistor value is 35K7.
Therefore R6 -3.5dB is calculated to be 40K4, the closest standard resistor value is 40K2.
13
MT88E45B
Data Sheet
Vdd
Interrupt Source 1
INT1
(Open Drain)
Interrupt Source 2
Resistor (R1)
Vdd
Resistor (R2)
Microcontroller
D1
R1 can be opened and
D1 shorted if the
microcontroller does not
read the INT1 pin.
INT2
(CMOS)
INT(input)
MT88E45B
DR/STD
(CMOS)
Input Port Bit
Figure 9 - Application Circuit: Multiple Interrupt Source
14
MT88E45B
Data Sheet
Absolute Maximum Ratings* - Voltages are with respect to VSS unless otherwise stated
Parameter
Symbol
Min
Max
Units
1
Supply voltage with respect to Vss
VDD
-0.3
6
V
2
Voltage on any pin other than supplies **
VPIN
Vss-0.3
VDD+0.3
V
3
Current at any pin other than supplies
IPIN
10
mA
4
Storage Temperature
TST
-65
150
o
C
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
**
Under normal operating conditions voltage on any pin except supplies can be minimum VSS-1V to maximum VDD+1V for an input current
limited to less than 200µΑ
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
2.7
1
Power Supplies
VDD
2
Clock Frequency
fOSC
3
Tolerance on Clock Frequency
4
Operating Temperature
‡ Typical figures are at 25
oC
Typ‡
Max
Units
5.5
V
3.579545
MHz
∆fOSC
-0.1
+0.1
%
TOP
-40
85
oC
and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics†
Characteristics
1
2
Standby Supply
Current
S
U
P
P
L
Y
Sym
IDDQ
Operating Supply
Current
VDD = 5V ±10%
VDD = 3V ±10%
IDD
3
Power
Consumption
PO
4
Schmitt Input High
Threshold
VT+
Schmitt Input Low
Threshold
DCLK
5
6
CB0
CB1
CB2
7
DCLK
DATA
DR/STD
CD, EST
ST/GT
Min
Typ‡
Max
Units
Test Conditions
0.1
15
µA
All inputs are
VDD/VSS except
for oscillator pins.
No analog input.
outputs unloaded.
CB0/1/2 = 1/0/0
2.8
1.5
8
4.5
mA
mA
44
mW
0.44*VDD
0.64*VDD
V
VT-
0.27*VDD
0.47*VDD
V
Schmitt Hysteresis
VHYS
0.2
CMOS Input High
Voltage
VIH
0.7*VDD
VDD
V
CMOS Input Low
Voltage
VIL
VSS
0.3*VDD
V
Output High Source
Current
IOH
0.8
All inputs are
VDD/VSS except
for oscillator pins.
No analog input.
outputs unloaded.
V
mA
VOH=0.9*VDD
15
MT88E45B
Data Sheet
DC Electrical Characteristics† (continued)
Characteristics
8
DCLK
DATA
DR/STD
CD, EST
ST/GT
9
IN1+
IN1IN2+
IN2-
Sym
Min
Output Low Sink
Current
IOL
2
Input Current
Iin1
ST/GT
11
VREF
12
13
ST/GT
Max
Units
Test Conditions
mA
VOL=0.1*VDD
1
µA
Vin=VDD to VSS
Iin2
10
µA
Vin=VDD to VSS
Output HighImpedance Current
Ioz1
5
µA
Vout =VDD to VSS
Output Voltage
VREF
0.5VDD+0.1
V
Output Resistance
RREF
2
kΩ
Comparator
Threshold Voltage
VTGt
0.5VDD+0.05
V
DCLK
CB0
CB1
CB2
10
Typ‡
0.5VDD -0.1
0.5VDD-0.05
No Load
† DC Electrical Characteristics are over recommended operating conditions, unless otherwise stated.
‡ Typical figures are at 25oC and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - CAS Detection
Characteristic
Sym
Min
Typ‡
Max
Unit
Notes*
1
Lower Tone Frequency
fL
2130
Hz
2
Upper Tone Frequency
fH
2750
Hz
3
Frequency Deviation: Accept
1.1%
range within which
tones are
accepted
4
Frequency Deviation: Reject
3.5%
range outside of
which tones are
rejected
5
Accept Signal Level (per
tone)
-40
-37.78
6
-2
0.22
dBV
dBm
1, 5, 6
Reject Signal Level (per tone)
Vdd=5V +/-10% only
-46
-43.78
dBV
dBm
2, 5, 6
7
Reject Signal Level (per tone)
Vdd=3V+/-10% or 5V+/-10%
-47.22
-45
dBV
dBm
1, 5, 6
8
Twist: 20 log (V2130Hz/V2750Hz)
+7
dB
9
Signal to Noise Ratio
-7
SNRCAS
20
dB
3,4
† AC Electrical Characteristics are over recommended operating conditions, unless otherwise stated.
‡ Typical figures are at 25oC and are for design aid only: not guaranteed and not subject to production testing
*Notes:
1. Tip/Ring signal level. Input op-amp configured to 0dB gain at Vdd=5V+/-10%, -3.5dB at Vdd=3V+/-10%.
2. Tip/Ring signal level. Input op-amp configured to 0dB gain at Vdd=5V+/-10%.
3. Both tones have the same amplitude.
4. Band limited random noise 300-3400Hz. Measurement valid only when tone is present.
5. dBV - Decibels above or below a reference voltage of 1 Vrms. 0 dBV = 1 Vrms. Signal level is per tone.
6. dBm - Decibels above or below a reference power of 1 mW into 600 ohms. 0 dBm = 0.7746 Vrms. Signal level is per tone.
16
MT88E45B
Data Sheet
AC Electrical Characteristics† - FSK Demodulation
Characteristics
Sym
Min
Typ‡
-40
-37.78
10.0
Max
Units
-6.45
-4.23
476
dBV
dBm
mVrms
1, 2, 4, 5
-48.24
-50.46
3
dBm
dBV
mVrms
1, 2, 4, 5
1
Accept Signal Level Range
2
Bell 202 Format Reject Signal Level
3
Transmission Rate
1188
1200
1212
baud
4
Mark and Space Frequencies
Bell 202 1 (Mark)
Bell 202 0 (Space)
1188
2178
1200
2200
1212
2222
Hz
Hz
1280.5
2068.5
1300
2100
1319.5
2131.5
Hz
Hz
+10
dB
CCITT V.23 1 (Mark)
CCITT V.23 0 (Space)
5
Twist: 20 log (VMARK/VSPACE)
6
Signal to Noise Ratio
-6
SNRFSK
20
dB
Notes*
1,3
† AC Electrical Characteristics are over recommended operating conditions, unless otherwise stated.
‡ Typical figures are nominal values and are for design aid only: not guaranteed and not subject to production testing.
*Notes:
1. Both mark and space have the same amplitude.
2. Tip/Ring signal level. Input op-amp configured to 0dB gain at Vdd=5V+/-10%, -3.5dB at Vdd=3V+/-10%.
3. Band limited random noise (200-3400Hz). Present when FSK signal is present. Note that the BT band is 300-3400Hz, the Bellcore
band is 0-4kHz.
4. dBV - Decibels above or below a reference voltage of 1 Vrms. 0 dBV = 1 Vrms.
5. dBm - Decibels above or below a reference power of 1 mW into 600 ohms. 0 dBm = 0.7746 Vrms.
Electrical Characteristics† - Gain Setting Amplifiers
Characteristics
Sym
Min
Max
Units
1
µA
Test Conditions
VSS ≤ VIN ≤ VDD
1
Input Leakage Current
IIN
2
Input Resistance
Rin
3
Input Offset Voltage
VOS
4
Power Supply Rejection Ratio
PSRR
30
dB
1kHz ripple on VDD
5
Common Mode Rejection Ratio
CMRR
40
dB
VCMmin ≤ VIN ≤ VCMmax
6
DC Open Loop Voltage Gain
AVOL
40
dB
7
Unity Gain Bandwidth
fC
0.3
MHz
8
Output Voltage Swing
VO
0.5
9
Capacitive Load (GS1,GS2)
CL
10
Resistive Load (GS1,GS2)
RL
100
11
Common Mode Range Voltage
VCM
1.0
10
MΩ
25
mV
VDD-0.5
V
50
pF
Load ≥ 100kΩ
kΩ
VDD-1.0
V
† Electrical characteristics are over recommended operating conditions, unless otherwise stated.
17
MT88E45B
Data Sheet
AC Electrical Characteristics† - CAS Detection Timing
Characteristics
Sym
Min
Max
Units
tDP
0.5
10
ms
See Figures 16, 17
2
Tone absent detect time
tDA
0.1
8
ms
† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
See Figures 16, 17
1
Tone present detect time
Notes
AC Electrical Characteristics† - Oscillator and Carrier Detect Timing
Characteristics
1
2
OSC2
3
4
CD
5
Sym
Min
Max
Units
Power-up time
tPU
50
ms
Power-down time
tPD
10
ms
Input FSK to CD low delay
tCP
25
ms
Input FSK to CD high delay
tCA
Hysteresis
10
ms
10
ms
Notes
† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
AC Electrical Characteristics† - 3-Wire FSK Data Interface Timing (Mode 0)
Characteristics
1
Sym
Min
Typ‡
Max
Units
Notes*
Rise time
tRR
200
ns
into 50pF Load
Fall time
tRF
200
ns
into 50pF Load
3
Low time
tRL
4
Rate
2
5
DR/STD
DATA
6
7
DATA
DCLK
Input FSK to DATA
delay
415
416
417
µs
2
1188
1200
1212
baud
1
1
5
ms
tIDD
Rise time
tR
200
ns
into 50pF Load
Fall time
tF
200
ns
into 50pF Load
DATA to DCLK delay
tDCD
6
416
µs
1, 2, 3
9
DCLK to DATA delay
tCDD
6
416
µs
1, 2, 3
10
Frequency
fDCLK0
1201.6
1202.8
1204
Hz
2
High time
tCH
415
416
417
µs
2
Low time
tCL
415
416
417
µs
2
tCRD
415
416
417
µs
2
8
11
DCLK
12
13
DCLK
DR/STD
DCLK to DR delay
† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25oC and are for design aid only: not guaranteed and not subject to production testing.
*Notes:
1. FSK input data at 1200 ±12 baud.
2. OSC1 at 3.579545 MHz ±0.1%.
3. Function of signal condition.
18
MT88E45B
Data Sheet
AC Electrical Characteristics† - 3-Wire FSK Data Interface Timing (Mode 1)
Characteristics
1
Frequency
2
DCLK
3
4
DCLK
DR/STD
5
Sym
Min
Max
Units
1
MHz
70
%
100
ns
fDCLK1
Duty cycle
30
Rise time
tR1
DCLK low set up before DR
tDDS
500
ns
DCLK low hold time after DR
tDDH
500
ns
Notes
† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels
Characteristics
Sym
Level
Units
1
CMOS Threshold Voltage
VCT
0.5*VDD
V
2
Rise/Fall Threshold Voltage High
VHM
0.7*VDD
V
3
Rise/Fall Threshold Voltage Low
VLM
0.3*VDD
V
Notes
19
MT88E45B
Data Sheet
tCDD
tDCD
VHM
VCT
VLM
DATA
tF
tR
VHM
VCT
VLM
DCLK
tCL
tCH
tR
tF
Figure 10 - DATA and DCLK Mode 0 Output Timing
tRR
tRF
VHM
VCT
VLM
DR
tRL
Figure 11 - DR Output Timing
VHM
DCLK
VLM
tR1
Figure 12 - DCLK Mode 1 Input Timing
20
MT88E45B
Data Sheet
start
TIP/RING
(A/B) WIRES
b7
stop
start
b0 b1 b2 b3 b4 b5 b6 b7
stop
tIDD
DATA
(Output)
b6 b7
start
b0 b1 b2 b3 b4 b5 b6 b7
stop
start
start
b0 b1 b2 b3 b4 b5 b6 b7
stop
b0 b1 b2 b3 b4 b5
start
b0 b1 b2 b3 b4 b5 b6 b7
stop
b0 b1 b2 b3
stop
DCLK
(Output)
tCL
tCH
tCRD
1/fDCLK0
DR
(Output)
tRL
Figure 13 - 3-Wire FSK Data Interface Timing (Mode 0)
Demodulated Data
(Internal Signal)
DR (Data Ready)
(Output)
Word N+1
Word N
stop
7
1
0
start
2
3
4
5
6
Note 1
7
stop
tRL
Note 2
>tDDS
>tDDH
1/fDCLK1
DCLK (Data Clock)
(Schmitt Input)
DATA
(Output)
7
stop 0
Word N-1
1
2
3
4
5
6
7
stop
0
Word N
The DCLK input must be low before and after DR falling edge.
Note 1: DCLK occurs during DR low and returns DR to high.
Note 2: DCLK occurs after DR, so DR is low for half a nominal bit time.
Figure 14 - 3-Wire FSK Data Interface Timing (Mode 1)
21
MT88E45B
TIP/RING
Data Sheet
1st Ring
PWDN
Note 1
Ch. seizure
B
A
C
Mark
D
Data
2nd Ring
F
E
Note 2
Note 3
tPU
Note 2
Note 4
tPD
OSC2
FSKen
Note 1
tCP
tCA
CD
DR
Note 5
DCLK
DATA
..101010..
Data
A = 2sec typical
B = 250-500ms
C = 250ms
D = 150ms
E = feature specific
Max C+D+E = 2.9 to 3.7sec
F ≥ 200ms
Figure 15 - Application Timing for Bellcore On-hook Data Transmission Associated with Ringing,
e.g., CID
Notes:
This on-hook case application is included because a CIDCW (off-hook) CPE must be also capable of receiving on-hook data
transmission (with ringing) from the end office.
1) PWDN and FSKen are internal signals decoded from CB0/1/2.
2) The CPE designer may choose to enable the MT88E45B only after the end of ringing to conserve power in a battery operated CPE.
CD is not activated by ringing.
3) The microcontroller in the CPE powers down the MT88E45B after CD has become inactive.
4) The microcontroller times out if CD is not activated.
5) This signal represents the mode of the DR/STD pin.
22
MT88E45B
Data Sheet
CPE goes off-hook
CPE unmutes handset
and enables keypad
CPE mutes handset & disables keypad
CPE sends
TIP/RING
CAS
A
Note 1
B
ACK
Note 5
C
D
Mark
E
Data
F
G
PWDN
Note 8
Hybrid CASen
Note 8
FSKen
Note 8
Note 2
Note 3
Note 4
tPU
OSC2
EST
ST/GT
tDP
tDA
tGA
VTGt
tGP
tREC
tABS
STD
Note 9
Note 6
Note 7
tCP
tCA
CD
DR
Note 9
DCLK
DATA
Data
A = 75-85ms
B = 0-100ms
C = 55-65ms
D = 0-500ms
E = 58-75ms
F = feature specific
G ≤ 50ms
Figure 16 - Application Timing for Bellcore Off-hook Data Transmission, e.g., CIDCW
Notes:
1) In a CPE where AC power is not available, the designer may choose to switch over to line power when the CPE goes off-hook and
use battery power while on-hook. The CPE must also be CID (on-hook) capable because a CIDCW CPE includes CID functionality.
2) Non-FSK signals such as CAS, speech and DTMF tones are in the same frequency band as FSK. They will be demodulated and
give false data. Therefore the MT88E45B should be taken out of FSK mode when FSK is not expected.
3) The MT88E45B may be put into FSK mode as soon as the CPE has finished sending the acknowledgment signal ACK. TR-NWT000575 specifies that ACK = DTMF ‘D’ for non-ADSI CPE, ‘A’ for ADSI CPE.
4) The MT88E45B should be taken out of FSK mode when CD has become inactive, or after 5 framing errors have been detected, or
after 150ms of continuous mark signal or space signal has been received. The framing errors need not be consecutive.
5) In an unsuccessful attempt where the end office does not send the FSK signal, the CPE should unmute the handset and enable the
keypad after interval D has expired.
6) The total recognition time is t REC = tGP + tDP , where t GP is the tone present guard time and t DP is the tone present detect time. V TGt
is the comparator threshold (refer to Figure 5 for details).
7) The total tone absent time is t ABS = tGA + tDA , where tGA is the tone absent guard time and tDA is the tone absent detect time. V TGt
is the comparator threshold (refer to Figure 5 for details).
8) PWDN, Hybrid CASen and FSKen are internal signals decoded from CB0/1/2.
9) This signal represents the mode of the DR/STD pin.
23
MT88E45B
Data Sheet
Line Reversal
A/B Wires
‘Idle State Tone Alert Signal’
Ch. seizure
DT-AS
A
B
C
Mark
D
E
Data
G
F
PWDN
Note 4
Note 6
Tip/Ring
CASen
Note 6
Ring
50-150ms
tDP
tDA
EST
Note 1
tGP
tGA
Note 2
VTGt
ST/GT
tREC
tABS
Note 3
STD
Note 7
TE DC load
15±1ms
< 0.5mA (optional)
<120µAµ
20±5ms
TE AC load
Current wetting pulse (see SIN227)
Note 4
Zss (Refer to SIN227)
FSKen
Note 5
Note 6
tCP
tCA
CD
DR
Note 7
DCLK
..101010..
DATA
tPU
OSC2
Data
tPD
A ≥ 100ms
B = 88-110ms
C ≥ 45ms (up to 5sec)
D = 80-262ms
E = 45-75ms
F ≤ 2.5sec (typ. 500ms)
G > 200ms
Note:
All
values
obtained from SIN227
Issue 1
Figure 17 - Application Timing for BT Caller Display Service (CDS), e.g., CLIP
Notes:
1) The total recognition time is tREC = tGP + tDP , where t GP is the tone present guard time and tDP is the tone present detect time. V TGt
is the comparator threshold (refer to Figure 5 for details).
2) The total tone absent time is t ABS = tGA + tDA , where t GA is the tone absent guard time and tDA is the tone absent detect time. V TGt
is the comparator threshold (refer to Figure 5 for details).
3) By choosing t GA=15ms, tABS will be 15-25ms so that the current wetting pulse and AC load can be applied right after the STD rising
edge.
4) SIN227 specifies that the AC and DC loads should be removed between 50-150ms after the end of the FSK signal, indicated by CD
returning to high. The MT88E45B may also be powered down at this time.
5) The MT88E45B should be taken out of FSK mode when FSK is not expected to prevent the FSK demodulator from reacting to other
in-band signals such as speech, DT-AS/CAS and DTMF tones.
6) PWDN, Tip/Ring CASen, FSKen are internal signals decoded from CB0/1/2.
7) This signal represents the mode of the DR/STD pin.
24
MT88E45B
Data Sheet
Line Reversal (Optionally sent)
A/B Wires
PWDN
Note 3
Ch. seizure
Ring Burst
A
First Complete
Ring Cycle
B
C
Mark
D
Data
E
F
Note 2
50-150ms
Note 1
250-400ms
TE DC load
TE AC load
FSKen
Note 3
tCP
tCA
CD
DR
Note 4
DCLK
..101010..
DATA
tPU
OSC2
Data
tPD
A = 200-450ms
B ≥ 500ms
C = 80-262ms
D = 45-262ms
E ≤ 2.5s (typ. 500ms)
F >200ms
Note: Parameter F
from "CCA Exceptions
Document Issue 3"
Figure 18 - Application Timing for UK’s CCA Caller Display Service (CDS), e.g., CLIP
Notes:
1) From TW/P&E/312. Start time: The CPE should enter the signalling state by applying the DC and AC terminations within this time
after the end of the ring burst.
2) End time: The CPE should leave the signalling state by removing the DC and AC terminations within this time after the end of Data,
indicated by CD returning to high. The MT88E45B should also be taken out of FSK mode at this time to prevent the FSK
demodulator from reacting to other in-band signals such as speech, and DTMF tones.
3) PWDN and FSKen are internal signals decoded from CB0/1/2.
4) This signal represents the mode of the DR/STD pin.
25
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