Cypress CY7C4211-25AC 64/256/512/1k/2k/4k/8k x 9 synchronous fifo Datasheet

CY7C4421/4201/4211/4221
CY7C4231/4241/4251
64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
Features
Functional Description
• High-speed, low-power, First-In, First-Out (FIFO)
memories
— 64 × 9 (CY7C4421)
— 256 × 9 (CY7C4201)
— 512 × 9 (CY7C4211)
— 1K × 9 (CY7C4221)
— 2K × 9 (CY7C4231)
— 4K × 9 (CY7C4241)
— 8K × 9 (CY7C4251)
• High-speed 100-MHz operation (10 ns Read/Write cycle
time)
• Low power (ICC = 35 mA)
• Fully asynchronous and simultaneous Read and Write
operation
• Empty, Full, and Programmable Almost Empty and
Almost Full status flags
• TTL-compatible
• Expandable in width
• Output Enable (OE) pin
• Independent Read and Write enable pins
• Center power and ground pins for reduced noise
• Width-expansion capability
• Space saving 7 mm × 7 mm 32-pin TQFP
• 32-pin PLCC
• Pin-compatible and functionally equivalent to
IDT72421, 72201, 72211, 72221, 72231, and 72241
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and two
Write-enable pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a free-running Read clock (RCLK) and two
Read-enable pins (REN1, REN2). In addition, the CY7C42X1
has an output enable pin (OE). The Read (RCLK) and Write
(WCLK) clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
Read/Write applications. Clock frequencies up to 100 MHz are
achievable.
Depth expansion is possible using one enable input for system
control, while the other enable is controlled by expansion logic
to direct the flow of data.
D0- 8
Pin Configuration
D1
D0
PAF
PAE
GND
REN1
RCLK
REN2
OE
WCLK WEN1 WEN2/LD
FLAG
PROGRAM
REGISTER
Write
CONTROL
Dual Port
RAM Array
64 x 9
Read
POINTER
RESET
LOGIC
THREE-STATE
OUTPUTREGISTER
Read
CONTROL
Cypress Semiconductor Corporation
Document #: 38-06016 Rev. *A
PAF
PAE
GND
REN1
RCLK
REN2
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
WEN1
WCLK
WEN2/LD
VCC
Q8
Q7
Q6
Q5
9 10 11 12 13 14 15 16
OE
EF
RCLK REN1 REN2
•
TQFP
Top View
32 31 30 29 28 27 26 25
D1
D0
OE
Q0- 8
RS
WEN1
WCLK
WEN2/LD
VCC
Q8
Q7
Q6
Q5
3901 North First Street
•
San Jose
•
Q3
Q4
8k x 9
Q2
RS
EF
PAE
PAF
FF
4 3 2 1 32 3130
29
5
28
6
27
7
26
8
9
25
10
24
11
23
12
22
21
13
14151617181920
D2
D 3 EF
D 4 FF
Q
D5 0
Q1
D6 Q
2
D7 Q
3
D8 Q4
RS
FLAG
LOGIC
Write
POINTER
PLCC
Top View
D2
D3
D4
D5
D6
D7
D8
INPUT
REGISTER
FF
Q0
Q1
Logic Block Diagram
The CY7C42X1 are high-speed, low-power FIFO memories
with clocked Read and Write interfaces. All are 9 bits wide. The
CY7C42X1 are pin-compatible to IDT722X1. Programmable
features include Almost Full/Almost Empty flags. These FIFOs
provide solutions for a wide variety of data buffering needs,
including high-speed data acquisition, multiprocessor interfaces, and communications buffering.
CA 95134 • 408-943-2600
Revised March 6, 2202
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Selection Guide
-10
-15
-25
Unit
100
66.7
40
MHz
Maximum Access Time
8
10
15
ns
Minimum Cycle Time
10
15
25
ns
Minimum Data or Enable Set-up
3
4
6
ns
0.5
1
1
ns
8
10
15
ns
Commercial
35
35
35
ICC1
Industrial
40
40
40
Maximum Frequency
Minimum Data or Enable Hold
Maximum Flag Delay
Active Power Supply Current
Density
CY7C4421
CY7C4201
CY7C4211
CY7C4221
CY7C4231
CY7C4241
CY7C4251
64 × 9
256 × 9
512 × 9
1K × 9
2K × 9
4K × 9
8K × 9
Functional Description
The CY7C42X1 provides four status pins: Empty, Full, Almost Empty,
Almost Full. The Almost Empty/Almost Full flags are programmable
to single word granularity. The programmable flags default to
Empty – 7 and Full – 7.
The flags are synchronous, i.e., they change state relative to
either the Read clock (RCLK) or the Write clock (WCLK).
When entering or exiting the Empty and Almost Empty states,
the flags are updated exclusively by the RCLK. The flags
denoting Almost Full, and Full states are updated exclusively
by WCLK. The synchronous flag architecture guarantees that
the flags maintain their status for at least one cycle.
All configurations are fabricated using advanced 0.65µ N-Well
CMOS technology. Input ESD protection is greater than 2001V, and
latch-up is prevented by the use of guard rings.
Architecture
The CY7C42X1 consists of an array of 64 to 8K words of 9 bits
each (implemented by a dual-port array of SRAM cells), a
Read pointer, a Write pointer, control signals (RCLK, WCLK,
REN1, REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF, FF).
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition
signified by EF being LOW. All data outputs (Q0–8) go LOW
tRSF after the rising edge of RS. In order for the FIFO to reset
to its default state, a falling edge must occur on RS and the
user must not read or Write while RS is LOW. All flags are
guaranteed to be valid tRSF after RS is taken LOW.
active. REN1 and REN2 must set up tENS before RCLK for it
to be a valid Read function. WEN1 and WEN2 must occur tENS
before WCLK for it to be a valid Write function.
An output enable (OE) pin is provided to three-state the Q0–8
outputs when OE is asserted. When OE is enabled (LOW),
data in the output register will be available to the Q0–8 outputs
after tOE.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid Read on its Q0–8 outputs
even after additional reads occur.
Write Enable 1 (WEN1). If the FIFO is configured for programmable flags, Write Enable 1 (WEN1) is the only Write enable
control pin. In this configuration, when Write Enable 1 (WEN1)
is LOW, data can be loaded into the input register and RAM
array on the LOW-to-HIGH transition of every Write clock
(WCLK). Data is stored is the RAM array sequentially and
independently of any on-going Read operation.
Write Enable 2/Load (WEN2/LD). This is a dual-purpose pin.
The FIFO is configured at Reset to have programmable flags
or to have two Write enables, which allows for depth
expansion. If Write Enable 2/Load (WEN2/LD) is set active
HIGH at Reset (RS = LOW), this pin operates as a second
Write enable pin.
If the FIFO is configured to have two Write enables, when
Write Enable (WEN1) is LOW and Write Enable 2/Load
(WEN2/LD) is HIGH, data can be loaded into the input register
and RAM array on the LOW-to-HIGH transition of every Write
clock (WCLK). Data is stored in the RAM array sequentially
and independently of any on-going Read operation.
FIFO Operation
Programming
When the WEN1 signal is active LOW and WEN2 is active HIGH,
data present on the D0–8 pins is written into the FIFO on each
rising edge of the WCLK signal. Similarly, when the REN1 and
REN2 signals are active LOW, data in the FIFO memory will
be presented on the Q0–8 outputs. New data will be presented
on each rising edge of RCLK while REN1 and REN2 are
When WEN2/LD is held LOW during Reset, this pin is the load
(LD) enable for flag offset programming. In this configuration,
WEN2/LD can be used to access the four 8-bit offset registers
contained in the CY7C42X1 for writing or reading data to these
registers.
Document #: 38-06016 Rev. *A
Page 2 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
When the device is configured for programmable flags and
both WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH
transition of WCLK writes data from the data inputs to the
empty offset least significant bit (LSB) register. The second,
third, and fourth LOW-to-HIGH transitions of WCLK store data
in the empty offset most significant bit (MSB) register, full offset
LSB register, and full offset MSB register, respectively, when
WEN2/LD and WEN1 are LOW. The fifth LOW-to-HIGH
transition of WCLK while WEN2/LD and WEN1 are LOW
writes data to the empty LSB register again. Figure 1 shows
the registers sizes and default values for the various device
types.
64 × 9
8
It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written; then by bringing
the WEN2/LD input HIGH, the FIFO is returned to normal
Read and Write operation. The next time WEN2/LD is brought
LOW, a Write operation stores data in the next offset register
in sequence.
The contents of the offset registers can be read to the data
outputs when WEN2/LD is LOW and both REN1 and REN2
are LOW. LOW-to-HIGH transitions of RCLK Read register
contents to the data outputs. Writes and reads should not be
preformed simultaneously on the offset registers.
256 × 9
0
6 5
8
Empty Offset (LSB) Reg.
Default Value = 007h
8
Empty Offset (LSB) Reg.
Default Value = 007h
0
8
512 × 9
0
7
8
Empty Offset (LSB) Reg.
Default Value = 007h
0
1
0
7
8
Empty Offset (LSB) Reg.
Default Value = 007h
0
8
1K × 9
0
7
8
(MSB)
0
8
0
6 5
8
Full Offset (LSB) Reg
Default Value = 007h
0
7
8
Full Offset (LSB) Reg
Default Value = 007h
0
8
8
Full Offset (LSB) Reg
Default Value = 007h
0
8
(MSB)
00
0
7
0
7
Full Offset (LSB) Reg
Default Value = 007h
0
1
8
8
0
7
8
0
7
8
Full Offset (LSB) Reg
Default Value = 007h
8
(MSB)
000
(MSB)
00000
0
7
8
8
0
7
Full Offset (LSB) Reg
Default Value = 007h
0
3
0
4
8
Full Offset (LSB) Reg
Default Value = 007h
0
2
0
7
(MSB)
0000
0
7
8
Empty Offset (LSB) Reg.
Default Value = 007h
0
3
8
(MSB)
000
8
8K × 9
Empty Offset (LSB) Reg.
Default Value = 007h
0
2
8
(MSB)
00
4K × 9
Empty Offset (LSB) Reg.
Default Value = 007h
0
1
8
(MSB)
0
2K × 9
0
1
8
(MSB)
0000
0
4
(MSB)
00000
Figure 1. Offset Register Location and Default Values
Document #: 38-06016 Rev. *A
Page 3 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Programmable Flag (PAE, PAF) Operation
(256 – m), CY7C4211 (512 – m), CY7C4221 (1K – m),
CY7C4231 (2K – m), CY7C4241 (4K – m), and CY7C4251
(8K – m). PAF is set HIGH by the LOW-to-HIGH transition of
WCLK when the number of available memory locations is
greater than m.
Whether the flag offset registers are programmed as
described in Table 1 or the default values are used, the
programmable almost-empty flag (PAE) and programmable
almost-full flag (PAF) states are determined by their corresponding offset registers and the difference between the Read
and Write pointers.
Table 1. Writing the Offset Registers
The number formed by the empty offset least significant bit
register and empty offset most significant register is referred
to as n and determines the operation of PAE. PAE is synchronized to the LOW-to-HIGH transition of RCLK by one flip-flop
and is LOW when the FIFO contains n or fewer unread words.
PAE is set HIGH by the LOW-to-HIGH transition of RCLK when
the FIFO contains (n + 1) or greater unread words.
WCLK[1]
LD
WEN
0
0
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
0
1
No Operation
1
0
Write Into FIFO
1
1
No Operation
The number formed by the full offset least significant bit
register and full offset most significant bit register is referred to
as m and determines the operation of PAF. PAE is synchronized to the LOW-to-HIGH transition of WCLK by one flip-flop
and is set LOW when the number of unread words in the FIFO
is greater than or equal to CY7C4421. (64 – m), CY7C4201
Selection
Table 2. Status Flags
Number of Words in FIFO
CY7C4421
CY7C4201
0
1 to n
CY7C4211
0
[2]
FF
PAF
PAE
EF
H
H
L
L
[2]
0
1 to n
[2]
H
H
L
H
(n + 1) to 32
(n + 1) to 128
1 to n
(n + 1) to 256
H
H
H
H
33 to (64 – (m + 1))
129 to (256 – (m + 1))
257 to (512 – (m + 1))
H
H
H
H
(64 – m)[3] to 63
(256 – m)[3] to 255
(512 – m)[3] to 511
H
L
H
H
64
256
512
L
L
H
H
Number of Words in FIFO
CY7C4221
0
1 to n
CY7C4231
0
[2]
1 to n
(n + 1) to 512
CY7C4241
0
[2]
0
[2]
(n + 1) to 1024
CY7C4251
[2]
1 to n
1 to n
(n + 1) to 2048
(n + 1) to 4096
513 to (1024 – (m + 1)) 1025 to (2048 – (m + 1)) 2049 to (4096 – (m + 1)) 4097 to (8192 – (m + 1))
(1024 – m)
1024
[3]
to 1023
(2048 – m)
2048
[3]
to 2047
(4096 – m)
4096
[3]
to 4095
(8192 – m)
8192
[3]
to 8191
FF
PAF
PAE
EF
H
H
L
L
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
H
H
Notes:
1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a Read is performed on the LOW-to-HIGH transition of
RCLK.
2. n = Empty Offset (n = 7 default value).
3. m = Full Offset (m = 7 default value).
Document #: 38-06016 Rev. *A
Page 4 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Width Expansion Configuration
Flag Operation
Word width may be increased simply by connecting the corresponding input controls signals of multiple devices. A
composite flag should be created for each of the end-point
status flags (EF and FF). The partial status flags (PAE and
PAF) can be detected from any one device. Figure 2 demonstrates a 18-bit word width by using two CY7C42X1s. Any
word width can be attained by adding additional CY7C42X1s.
The CY7C42X1 devices provide four flag pins to indicate the
condition of the FIFO contents. Empty, Full, PAE, and PAF are
synchronous.
Full Flag
The Full Flag (FF) will go LOW when device is full. Write operations are inhibited whenever FF is LOW regardless of the state
of WEN1 and WEN2/LD. FF is synchronized to WCLK, i.e., it
is exclusively updated by each rising edge of WCLK.
When the CY7C42X1 is in a Width Expansion Configuration,
the Read Enable (REN2) control input can be grounded (See
Figure 2). In this configuration, the Write Enable 2/Load
(WEN2/LD) pin is set to LOW at Reset so that the pin operates
as a control to load and read the programmable flag offsets.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW,
regardless of the state of REN1 and REN2. EF is synchronized
to RCLK, i.e., it is exclusively updated by each rising edge of
RCLK.
RESET (RS)
DATA IN (D) 18
Write
Write
Write
RESET (RS)
9
9
Read CLOCK (RCLK)
CLOCK (WCLK)
Read ENABLE 1 (REN1)
ENABLE 1 (WEN1)
OUTPUT ENABLE (OE)
ENABLE 2/LOAD
(WEN2/LD)
CY7C42X1
PROGRAMMABLE (PAF)
CY7C42X1
EF EMPTY FLAG (EF) #2
EF
FULL FLAG (FF) # 1
PROGRAMMABLE (PAE)
EMPTY FLAG (EF) #1
FF
FF
9
FULL FLAG (FF) # 2
DATA OUT (Q)
18
9
Read Enable 2 (REN2)
Read Enable 2 (REN2)
42X1–16
Figure 2. Block Diagram of 64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9 Synchronous FIFO Memory
Used in a Width Expansion Configuration
Document #: 38-06016 Rev. *A
Page 5 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ...................................–65°C to +150°C
Ambient Temperature with
Power Applied...............................................–55°C to +125°C
Static Discharge Voltage .......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA
Operating Range
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
Range
Ambient
Temperature
VCC
DC Voltage Applied to Outputs
in High-Z State ............................................... –0.5V to +7.0V
Commercial
0°C to +70°C
5V ±10%
–40°C to +85°C
5V ±10%
DC Input Voltage............................................ –3.0V to +7.0V
Industrial
[4]
Pin Definitions
Pin
Name
I/O
Description
D0–8
Data Inputs
I
Data Inputs for 9-bit Bus
Q0–8
Data Outputs
O
Data Outputs for 9-bit Bus
WEN1
Write Enable 1
I
The only Write enable to have programmable flags when device is configured. Data is
written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH.
If the FIFO is configured to have two Write enables, data is written on a LOW-to-HIGH
transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
WEN2/LD Dual Write Enable 2
Mode Pin
Load
I
If HIGH at reset, this pin operates as a second Write enable. If LOW at reset, this pin
operates as a control to Write or Read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO
if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW
to write or read the programmable flag offsets.
REN1, REN2
Read Enable
Inputs
I
Enables Device for Read Operation
WCLK
Write Clock
I
The rising edge clocks data into the FIFO when WEN1 is LOW, WEN2/LD is HIGH, and the
FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-offset
register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the FIFO
is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag-offset
register.
EF
Empty Flag
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF
Full Flag
O
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
PAE
Programmable
Almost Empty
O
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value programmed into the FIFO.
PAF
Programmable
Almost Full
O
When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed into
the FIFO.
RS
Reset
I
Resets device to empty condition. A reset is required before an initial Read or Write
operation after power-up.
OE
Output Enable
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If OE is
HIGH, the FIFO’s outputs are in High-Z (high-impedance) state.
I
Note:
4. TA is the “instant on” case temperature.
Document #: 38-06016 Rev. *A
Page 6 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Electrical Characteristics Over the Operating Range[5]
-10
Parameter
Description
Test Conditions
Min.
-15
Max.
VOH
Output HIGH Voltage
VCC = Min.,
IOH = –2.0 mA
VOL
Output LOW Voltage
VCC = Min.,
IOL = 8.0 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input Leakage
Current
VCC = Max.
IOS[6]
Output Short
Circuit Current
VCC = Max.,
VOUT = GND
–90
IOZL
IOZH
Output OFF,
High-Z Current
OE > VIH,
VSS < VO < VCC
–10
ICC1[7]
Active Power Supply
Current
Commercial
35
Industrial
ICC2[8]
Average Standby
Current
Commercial
Industrial
Min.
2.4
-25
Max.
2.4
Max.
V
0.4
VCC
2.2
–3.0
0.8
–10
+10
Unit
2.4
0.4
2.2
Min.
0.4
V
VCC
V
VCC
2.2
–3.0
0.8
–3.0
0.8
V
–10
+10
–10
+10
µA
–90
+10
–90
–10
+10
mA
–10
+10
mA
35
35
mA
40
40
40
mA
10
10
10
mA
15
15
15
mA
Capacitance[9]
Parameter
Description
Input Capacitance
Output Capacitance
CIN
COUT
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
5
7
Unit
pF
pF
AC Test Loads and Waveforms[10, 11]
R1 1.1 KΩ
ALL INPUT PULSES
5V
OUTPUT
3.0V
R2
680Ω
CL
INCLUDING
JIG AND
SCOPE
Equivalent to:
GND
≤ 3 ns
THÉVENIN EQUIVALENT
420Ω
OUTPUT
90%
10%
90%
10%
≤ 3 ns
1.91V
Switching Characteristics Over the Operating Range
-10
Parameter
Description
Min.
-15
Max.
Min.
100
-25
Max.
Min.
Unit
40
MHz
15
ns
tS
Clock Cycle Frequency
tA
Data Access Time
tCLK
Clock Cycle Time
10
15
25
ns
tCLKH
Clock HIGH Time
4.5
6
10
ns
tCLKL
Clock LOW Time
4.5
6
10
ns
tDS
Data Set-up Time
3
4
6
ns
2
8
66.7
Max.
2
10
2
Notes:
5. See the last page of this specification for Group A subgroup testing information.
6. Test no more than one output at a time for not more than one second.
7. Outputs open. Tested at Frequency = 20 MHz.
8. All inputs = VCC – 0.2V, except WCLK and RCLK, which are switching at 20 MHz.
9. Tested initially and after any design or process changes that may affect these parameters.
10. CL = 30 pF for all AC parameters except for tOHZ.
11. CL = 5 pF for tOHZ.
Document #: 38-06016 Rev. *A
Page 7 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Switching Characteristics Over the Operating Range
-10
Parameter
Description
Min.
-15
Max.
Min.
-25
Max.
Min.
Max.
Unit
tDH
Data Hold Time
tENS
Enable Set-up Time
0.5
1
1
ns
3
4
6
ns
tENH
Enable Hold Time
0.5
tRS
Reset Pulse Width[12]
10
1
1
ns
15
25
ns
tRSS
Reset Set-up Time
8
tRSR
Reset Recovery Time
8
10
15
ns
10
15
ns
tRSF
Reset to Flag and Output Time
tOLZ
Output Enable to Output in Low-Z[13]
0
tOE
Output Enable to Output Valid
3
7
3
8
3
12
ns
tOHZ
Output Enable to Output in High-Z[13]
3
7
3
8
3
12
ns
tWFF
Write Clock to Full Flag
8
10
15
ns
tREF
Read Clock to Empty Flag
8
10
15
ns
tPAF
Clock to Programmable Almost-Full Flag
8
10
15
ns
tPAE
Clock to Programmable Almost-Full Flag
8
10
15
ns
tSKEW1
Skew Time between Read Clock and Write Clock
for Empty Flag and Full Flag
5
6
10
ns
tSKEW2
Skew Time between Read Clock and Write Clock
for Almost-Empty Flag and Almost-Full Flag
10
15
18
ns
10
15
0
25
0
ns
ns
Switching Waveforms
Write Cycle Timing
tCLK
tCLKH
tCLKL
WCLK
tDS
tDH
D0 –D8
tENS
tENH
WEN1
NO OPERATION
NO OPERATION
WEN2
(if applicable)
tWFF
tWFF
FF
tSKEW1
[14]
RCLK
REN1,REN2
Notes:
12. Pulse widths less than minimum values are not allowed.
13. Values guaranteed by design, not currently tested.
Document #: 38-06016 Rev. *A
Page 8 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Switching Waveforms (continued)
Read Cycle Timing
tCKL
tCLKH
tCLKL
RCLK
tENS
tENH
REN1,REN2
NO OPERATION
tREF
tREF
EF
tA
Q0 –Q8
VALID DATA
tOLZ
tOHZ
tOE
OE
tSKEW1
[15]
WCLK
WEN1
WEN2
Reset Timing[16]
tRS
RS
tRSS
tRSR
tRSS
tRSR
tRSS
tRSR
REN1,
REN2
WEN1
WEN2/LD
[17]
tRSF
EF,PAE
tRSF
FF,PAF,
tRSF
OE=1 [18]
Q0 - Q8
OE=0
Notes:
14. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time
between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.
15. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time
between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF may not change state until the next RCLK rising edge.
Document #: 38-06016 Rev. *A
Page 9 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Switching Waveforms (continued)
First Data Word Latency after Reset with Simultaneous Read and Write
WCLK
t DS
D0–D8
D0 (FIRSTVALID Write)
D1
tENS
D2
D3
[20]
tA
D4
[19]
tFRL
WEN1
WEN2
(if applicable)
tSKEW1
RCLK
tREF
EF
tA
REN1,
REN2
Q0 –Q8
D0
D1
tOLZ
tOE
OE
Empty Flag Timing
WCLK
tDS
tDS
DATAWRITE2
DATAWRITE1
D0 –D8
tENH
tENS
tENH
tENS
WEN1
WEN2
(if applicable)
tENS
tENH
tFRL
tENS
[19]
tENH
tFRL
[19]
RCLK
tSKEW1
tREF
tREF
tREF
tSKEW1
EF
REN1,
REN2
LOW
OE
tA
Q0 –Q8
DATA IN OUTPUT REGISTER
DATA Read
Notes:
16. The clocks (RCLK, WCLK) can be free-running during reset.
17. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable
for the programmable flag offset registers.
18. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.
19. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or
tCLK + tSKEW1. The Latency Timing applies only at the Empty Boundary (EF = LOW).
20. The first word is available the cycle after EF goes HIGH, always.
Document #: 38-06016 Rev. *A
Page 10 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Switching Waveforms (continued)
Full Flag Timing
NO Write
NO Write
NO Write
WCLK
tSKEW1 [14]
tSKEW1 [14]
tDS
DATA Write
DATA Write
D0 –D8
tWFF
tWFF
tWFF
FF
WEN1
WEN2
(if applicable)
RCLK
tENH
OE
tENH
tENS
REN1,
REN2
tENS
LOW
tA
Q0 –Q8
tA
DATA Read
DATA IN OUTPUT REGISTER
NEXT DATA Read
Programmable Almost Empty Flag Timing
tCLKL
tCLKH
WCLK
tENS tENH
WEN1
WEN2
(if applicable)
tENS tENH
PAE
tSKEW2 [21]
Note
22
N + 1 WORDS
INFIFO
tPAE
Note
23
tPAE
RCLK
tENS
tENS tENH
REN1,
REN2
Document #: 38-06016 Rev. *A
Page 11 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Switching Waveforms (continued)
Programmable Almost Full Flag Timing
Note
24
tCLKL
tCLKH
WCLK
tENS tENH
WEN1
Note
25
WEN2
(if applicable)
tPAF
tENS tENH
PAF
FULL − M WORDS
IN FIFO [26]
FULL − M+1 WORDS
IN FIFO
tSKEW2 [27]
tPAF
RCLK
tENS
tENS tENH
REN1,
REN2
Write Programmable Registers
tCLK
tCLKL
tCLKH
WCLK
tENS
tENH
WEN2/LD
tENS
WEN1
tDS
tDH
D0 –D8
PAE OFFSET
LSB
PAE OFFSET
MSB
PAF OFFSET
LSB
PAF OFFSET
MSB
Notes:
21. tSKEW2 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of
WCLK and the rising RCLK is less than tSKEW2, then PAE may not change state until the next RCLK.
22. PAE offset = n.
23. If a Read is performed on this rising edge of the Read clock, there will be Empty + (n – 1) words in the FIFO when PAE goes LOW.
24. If a Write is performed on this rising edge of the Write clock, there will be Full – (m – 1) words of the FIFO when PAF goes LOW.
25. PAF offset = m.
26. 64-m words for CY7C4421, 256 – m words in FIFO for CY7C4201, 512 – m words for CY7C4211, 1024 – m words for CY7C4221, 2048 – m words for CY7C4231,
4096 – m words for CY7C4241, 8192 – m words for CY7C4251.
27. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK.
Document #: 38-06016 Rev. *A
Page 12 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Switching Waveforms (continued)
Read Programmable Registers
tCLK
tCLKL
tCLKH
RCLK
tENS
tENH
WEN2/LD
tENS
PAF OFFSET
MSB
REN1,
REN2
tA
Q0 –Q8
Document #: 38-06016 Rev. *A
UNKNOWN
PAE OFFSET LSB
PAE OFFSET MSB
PAF OFFSET
LSB
Page 13 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Typical AC and DC Characteristics
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
1.20
1.2
1.0
VIN = 3.0V
TA = 25°C
f = 100 MHz
0.8
0.6
4
4.5
5.5
5
1.10
1.00
0.90
25
NORMALIZED tA vs. SUPPLY
VOLTAGE
0
1.0
0.9
5.5
35
25
0
1
2
3
OUTPUT VOLTAGE (V)
Document #: 38-06016 Rev. *A
4
OUTPUT SINK CURRENT (mA)
45
100
TYPICAL t A CHANGE vs.
OUTPUT LOADING
40
1.00
0.75
25
10
VCC = 5.0V
TA = 25°C
25
125
AMBIENT TEMPERATURE (°C)
55
75
1.25
SUPPLY VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
50
VCC = 5.0V
0.50
−55
6
25
FREQUENCY (MHz)
Delta t A (ns)
NORMALIZED tA
NORMALIZED t A
1.1
0.8
OUTPUT SOURCE CURRENT (mA)
0.60
125
1.50
5
0.80
NORMALIZED tA vs.
AMBIENT TEMPERATURE
1.2
4.5
0.90
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
4
VCC = 5.0V
TA = 25°C
VIN = 3.0V
1.00
0.70
0.80
−55
6
1.10
VIN = 3.0V
VCC = 5.0V
f = 100 MHz
NORMALIZED I CC
NORMALIZED I CC
NORMALIZED I CC
1.4
NORMALIZED SUPPLY CURRENT
vs. FREQUENCY
0
0
200
400
600
800 1000
CAPACITANCE (pF)
OUTPUT SINK CURRENT vs.
OUTPUT VOLTAGE
160
140
120
100
80
60
40
20
0
0
1
2
3
4
OUTPUT VOLTAGE (V)
Page 14 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Ordering Information
64 x 9 Synchronous FIFO
Speed
(ns)
10
15
Ordering Code
CY7C4421-10AC
Package
Name
Package
Type
A32
32-lead Thin Quad Flatpack
CY7C4421-10JC
J65
32-lead Plastic Leaded Chip Carrier
CY7C4421-15AC
A32
32-lead Thin Quad Flatpack
CY7C4421-15JC
J65
32-lead Plastic Leaded Chip Carrier
Operating
Range
Commercial
Commercial
256 x 9 Synchronous FIFO
Speed
(ns)
10
15
25
Ordering Code
Package
Name
Package
Type
CY7C4201-10AC
A32
32-lead Thin Quad Flatpack
CY7C4201-10JC
J65
32-lead Plastic Leaded Chip Carrier
CY7C4201-15AC
A32
32-lead Thin Quad Flatpack
CY7C4201-15JC
J65
32-lead Plastic Leaded Chip Carrier
CY7C4201-25AC
A32
32-lead Thin Quad Flatpack
CY7C4201-25JC
J65
32-lead Plastic Leaded Chip Carrier
CY7C4201-25AI
A32
32-lead Thin Quad Flatpack
Operating
Range
Commercial
Commercial
Commercial
Industrial
512 x 9 Synchronous FIFO
Speed
(ns)
10
15
25
Ordering Code
CY7C4211-10AC
Package
Name
Package
Type
Operating
Range
A32
32-lead Thin Quad Flatpack
Commercial
CY7C4211-10JC
J65
32-lead Plastic Leaded Chip Carrier
CY7C4211-10AI
A32
32-lead Thin Quad Flatpack
CY7C4211-10JI
J65
32-lead Plastic Leaded Chip Carrier
CY7C4211-15AC
A32
32-lead Thin Quad Flatpack
CY7C4211-15JC
J65
32-lead Plastic Leaded Chip Carrier
CY7C4211-15AI
A32
32-lead Thin Quad Flatpack
Industrial
CY7C4211-25AC
A32
32-lead Thin Quad Flatpack
Commercial
CY7C4211-25JC
J65
32-lead Plastic Leaded Chip Carrier
Industrial
Commercial
1K x 9 Synchronous FIFO
Speed
(ns)
10
15
25
Ordering Code
CY7C4221-10AC
Package
Name
Package
Type
A32
32-lead Thin Quad Flatpack
CY7C4221-10JC
J65
32-lead Plastic Leaded Chip Carrier
CY7C4221-15AC
A32
32-lead Thin Quad Flatpack
CY7C4221-15JC
J65
32-lead Plastic Leaded Chip Carrier
CY7C4221-25AC
A32
32-lead Thin Quad Flatpack
CY7C4221-25JC
J65
32-lead Plastic Leaded Chip Carrier
Operating
Range
Commercial
Commercial
Commercial
2K x 9 Synchronous FIFO
Speed
(ns)
10
15
Ordering Code
CY7C4231-10AC
Package
Name
Package
Type
A32
32-lead Thin Quad Flatpack
CY7C4231-10JC
J65
32-lead Plastic Leaded Chip Carrier
CY7C4231-15AC
A32
32-lead Thin Quad Flatpack
Document #: 38-06016 Rev. *A
Operating
Range
Commercial
Commercial
Page 15 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
2K x 9 Synchronous FIFO (continued)
Speed
(ns)
25
Ordering Code
Package
Name
Package
Type
CY7C4231-15JC
J65
32-lead Plastic Leaded Chip Carrier
CY7C4231-25AC
A32
32-lead Thin Quad Flatpack
CY7C4231-25JC
J65
32-lead Plastic Leaded Chip Carrier
Operating
Range
Commercial
4K x 9 Synchronous FIFO
Speed
(ns)
10
15
25
Ordering Code
Package
Name
Package
Type
Operating
Range
CY7C4241-10AC
A32
32-lead Thin Quad Flatpack
CY7C4241-10JC
J65
32-lead Plastic Leaded Chip Carrier
Commercial
CY7C4241-10JI
J65
32-lead Plastic Leaded Chip Carrier
Industrial
CY7C4241-15AC
A32
32-lead Thin Quad Flatpack
Commercial
CY7C4241-15JC
J65
32-lead Plastic Leaded Chip Carrier
CY7C4241-25AC
A32
32-lead Thin Quad Flatpack
CY7C4241-25JC
J65
32-lead Plastic Leaded Chip Carrier
CY7C4241-25JI
J65
32-lead Plastic Leaded Chip Carrier
Commercial
Industrial
8K x 9 Synchronous FIFO
Speed
(ns)
10
15
25
Ordering Code
CY7C4251-10AC
Package
Name
Package
Type
Operating
Range
A32
32-lead Thin Quad Flatpack
CY7C4251-10JC
J65
32-lead Plastic Leaded Chip Carrier
CY7C4251-10AI
A32
32-lead Thin Quad Flatpack
Industrial
CY7C4251-15AC
A32
32-lead Thin Quad Flatpack
Commercial
CY7C4251-15JC
J65
32-lead Plastic Leaded Chip Carrier
CY7C4251-25AC
A32
32-lead Thin Quad Flatpack
CY7C4251-25JC
J65
32-lead Plastic Leaded Chip Carrier
CY7C4251-25AI
A32
32-lead Thin Quad Flatpack
Document #: 38-06016 Rev. *A
Commercial
Commercial
Industrial
Page 16 of 18
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Package Diagrams
32-lead Thin Plastic Quad Flatpack 7 × 7 × 1.0 mm A32
51-85063-B
32-Lead Plastic Leaded Chip Carrier J65
51-85002-B
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-06016 Rev. *A
Page 17 of 18
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Document Title: CY7C4421/4201/4211/4221, CY7C4231/4241/4251 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
Document Number: 38-06016
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
106477
09/10/01
SZV
Change from Spec number: 38-00419 to 38-06016
*A
110725
03/20/02
FSG
Change Input Leakage current IIX unit from mA to µA (typo)
Document #: 38-06016 Rev. *A
Description of Change
Page 18 of 18