240pin Registered DDR2 SDRAM DIMMs based on 512 Mb 1st ver. This Hynix registered Dual In-Line Memory Module (DIMM) series consists of 512Mb 1st ver. DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 512Mb 1st ver. based Registered DDR2 DIMM series provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition. FEATURES • JEDEC standard Double Data Rate2 Synchronous • Fully differential clock operations (CK & CK) DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power • Programmable Burst Length 4 / 8 with both sequen- Supply • tial and interleave mode All inputs and outputs are compatible with SSTL_1.8 interface • 4 Bank architecture • Posted CAS • Programmable CAS Latency 3 , 4 , 5 • OCD (Off-Chip Driver Impedance Adjustment) • ODT (On-Die Termination) • Auto refresh and self refresh supported • 8192 refresh cycles / 64ms • Serial presence detect with EEPROM • DDR2 SDRAM Package: 60ball FBGA • 133.35 x 30.00 mm form factor • Lead-free Products are RoHS compliant ORDERING INFORMATION Part Name Density Organization # of DRAMs # of ranks Materials HYMP564R728-E3/C4 512MB 64Mx72 9 1 Leaded HYMP512R728-E3/C4 1GB 128Mx72 18 2 Leaded HYMP512R724-E3/C4 1GB 128Mx72 18 1 Leaded HYMP125R72M4-E3/C4 2GB 256Mx72 36 2 Leaded HYMP564R72P8-E3/C4 512MB 64Mx72 9 1 Lead free HYMP512R72P8-E3/C4 1GB 128Mx72 18 2 Lead free HYMP512R72P4-E3/C4 1GB 128Mx72 18 1 Lead free HYMP125R72MP4-E3/C4 2GB 256Mx72 36 2 Lead free This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / Apr. 2005 1 1240pin Registered DDR2 SDRAM DIMMs SPEED GRADE & KEY PARAMETERS E3 (DDR2-400) C4 (DDR2-533) Unit Speed@CL3 400 400 Mbps Speed@CL4 400 533 Mbps Speed@CL5 - - Mbps CL-tRCD-tRP 3-3-3 4-4-4 tCK ADDRESS TABLE Density Organization Ranks SDRAMs # of DRAMs # of row/bank/column Address Refresh Method 512MB 64M x 72 1 64Mb x 8 9 14(A0~A13)/2(BA0~BA1)/10(A0~A9) 8K / 64ms 1GB 128M x 72 2 64Mb x 8 18 14(A0~A13)/2(BA0~BA1)/10(A0~A9) 8K / 64ms 1GB 128M x 72 1 128Mb x 4 18 14(A0~A13)/2(BA0~BA1)/11(A0~A9,A11) 8K / 64ms 2GB 256M x 72 2 128Mb x 4 36 14(A0~A13)/2(BA0~BA1)/11(A0~A9,A11) 8K / 64ms Rev. 1.0 / Apr. 2005 2 1240pin Registered DDR2 SDRAM DIMMs Input/Output Functional Description Symbol Type Polarity Pin Description CK0 IN Positive Edge Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL. CK0 IN Negative Negative line of the differential pair of system clock inputs that drives input to the on-DIMM PLL. Edge CKE[1:0] IN Active High Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. S[1:0] IN Active Low Enables the associated DDR2 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1 ODT[1:0] IN Active High On-Die Termination signals. RAS, CAS, WE IN Active Low When sampled at the positive rising edge of the clock. RAS,CAS and WE(ALONG WITH S) define the command being entered. Vref Supply Reference voltage for SSTL18 inputs VDDQ Supply Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity. For all current DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins. BA[1:0] IN - Selects which DDR2 SDRAM internal bank of four is activated. During a Bank Activate command cycle, Address input difines the row address(RA0~RA13) A[9:0], A10/AP A[13:11] IN - DQ[63:0], CB[7:0] IN - DM[8:0] IN Active High VDD,VSS Supply During a Read or Write command cycle, Address input defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high., autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge. Data and Check Bit Input/Output pins. DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Power and ground for the DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to VDD/VDDQ planes on these modules. DQS[17:0] I/O Positive Edge DQS[17:0] I/O Negative Negative line of the differential data strobe for input and output data Edge SA[2:0] IN - These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range. SDA I/O - This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister may be connected from the SDA bus line to VDDSPD on the system planar to act as a pull up. SCL IN - This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from SCL to VDDSPD to act as a pull up on the system board. VDDSPD Supply Positive line of the differential data strobe for input and output data Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane. EEPROM supply is operable from 1.7V to 3.6V. RESET IN The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low level (the PLL will remain synchronized with the input clock) Par_In IN Parity bit for the Address and Control bus(“1”. Odd, “0”.Even) Err_Out OUT TEST Rev. 1.0 / Apr. 2005 Parity error found in the Address and Control bus Used by memory bus analysis tools(unused on memory DIMMs) 3 1240pin Registered DDR2 SDRAM DIMMs PIN DESCRIPTION Pin Pin Description Pin CK0 Clock Input,positive line ODT[1:0] CK0 Clock input,negative line VDDQ CKE0~CKE1 Clock Enable Input Pin Description On Die Termination Inputs DQs Power Supply DQ0~DQ63 Data Input/Output RAS Row Address Strobe CB0~CB7 Data check bits Input/Output CAS Column Address Strobe DQS(0~8) Data strobes WE Write Enable DQS(0~8) Data strobes,negative line Chip Select Input DM(0~8), Data Maskes/Data strobes DQS(9~17) Address input DQS(9~17) Data strobes,negative line S0,S1 A0~A9, A11~A13 A10/AP Address input/Autoprecharge RFU Reserved for Future Use BA0,BA1 SDRAM Bank Address NC No Connect SCL Serial Presence Detect(SPD) Clock Input TEST Memory bus test tool (Not Connected and Not Usable on DIMMs) SDA SPD Data Input/Output VDD Core Power VDDQ I/O Power SA0~SA2 2 E PROM Address Inputs Par_In Parity bit for the Address and Control bus VSS Ground Err_Out Parity error found on the Address VREF Input/Output Reference RESET Reset Enable CB0~CB7 VDDSPD SPD Power Data Check bit Inputs/Outputs PIN LOCATION 1 pin 121 pin Rev. 1.0 / Apr. 2005 Front Side Back Side 64 pin 65 pin 184 pin 185 pin 120 pin 240 pin 4 1240pin Registered DDR2 SDRAM DIMMs PIN ASSIGNMENT Pin Name Pin Name Pin Name Pin Name Pin Name Pin 1 VREF 41 VSS 81 DQ33 121 VSS 161 CB4 201 Name VSS 2 VSS 42 CB0 82 VSS 122 DQ4 162 CB5 202 DM4/DQS13 3 DQ0 43 CB1 83 DQS4 123 DQ5 163 VSS 203 DQS13 4 DQ1 44 VSS 84 DQS4 124 VSS 164 DM8,DQS17 204 VSS 5 VSS 45 DQS8 85 VSS 125 DM0/DQS9 165 DQS17 205 DQ38 6 DQS0 46 DQS8 86 DQ34 126 DQS9 166 VSS 206 DQ39 7 DQS0 47 VSS 87 DQ35 127 VSS 167 CB6 207 VSS 8 VSS 48 CB2 88 VSS 128 DQ6 168 CB7 208 DQ44 9 DQ2 49 CB3 89 DQ40 129 DQ7 169 VSS 209 DQ45 10 DQ3 50 VSS 90 DQ41 130 VSS 170 VDDQ 210 VSS 11 VSS 51 VDDQ 91 VSS 131 DQ12 171 NC,CKE1 211 DM5/DQS14 DQS14 12 DQ8 52 CKE0 92 DQS5 132 DQ13 172 VDD 212 13 DQ9 53 VDD 93 DQS5 133 VSS 173 A15,NC 213 VSS 14 VSS 54 BA2,NC 94 VSS 134 DM1/DQS10 174 A14,NC 214 DQ46 15 DQS1 55 NC,Err_Out 95 DQ42 135 DQS10 175 VDDQ 215 DQ47 16 DQS1 56 VDDQ 96 DQ43 136 VSS 176 A12 216 VSS 17 VSS 57 A11 97 VSS 137 RFU 177 A9 217 DQ52 18 RESET 58 A7 98 DQ48 138 RFU 178 VDD 218 DQ53 19 NC 59 VDD 99 DQ49 139 VSS 179 A8 219 VSS 20 VSS 60 A5 100 VSS 140 DQ14 180 A6 220 RFU 21 DQ10 61 A4 101 SA2 141 DQ15 181 VDDQ 221 RFU 22 DQ11 62 VDDQ 102 NC(TEST) 142 VSS 182 A3 222 VSS 23 VSS 63 A2 103 VSS 143 DQ20 183 A1 223 DM6/DQS15 64 184 VDD 224 NC,DQS15 104 DQS6 144 DQ21 105 DQS6 145 VSS VSS 106 VSS 146 DM2/DQS11 185 VSS 107 DQ50 147 DQS11 VDD 108 DQ51 148 NC,Err_Out 109 VSS 149 VDD 110 DQ56 150 A10/AP 111 DQ57 151 112 VSS 113 DQS7 WE 114 CAS 115 24 DQ16 25 DQ17 VDD 26 VSS 65 27 DQS2 66 28 DQS2 67 29 VSS 68 30 DQ18 69 31 DQ19 70 32 VSS 71 BA0 33 DQ24 72 VDDQ 34 DQ25 73 35 VSS 74 Key Key 225 VSS CK0 226 DQ54 186 CK0 227 DQ55 VSS 187 VDD 228 VSS DQ22 188 A0 229 DQ60 DQ23 189 VDD 230 DQ61 VSS 190 BA1 231 VSS 152 DQ28 191 VDDQ 232 DM7/DQS16 153 DQ29 192 RAS 233 NC,DQS16 DQS7 154 VSS 193 S0 234 VSS VSS 155 DM3/DQS12 194 VDDQ 235 DQ62 DQ63 36 DQS3 75 VDDQ 116 DQ58 156 DQS12 195 ODT0 236 37 DQS3 76 NC, S1 117 DQ59 157 VSS 196 A13,NC 237 VSS 38 VSS 77 NC, ODT1 118 VSS 158 DQ30 197 VDD 238 VDDSPD 39 DQ26 78 VDDQ 119 SDA 159 DQ31 198 VSS 239 SA0 40 DQ27 79 VSS 120 SCL 160 VSS 199 DQ36 240 SA1 80 DQ32 200 DQ37 NC= No Connect, RFU= Reserved for Future Use. Note: 1. RESET(Pin 18) is connected to both OE of PLL and Reset of register. 2. NC/Err_out (Pin 55) and NC/Par_In(Pin68) are for optional function to check address and command parity. 3. The Test pin(Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules(DIMMs) Rev. 1.0 / Apr. 2005 5 1240pin Registered DDR2 SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM 512MB(64Mbx72) : HYMP564R728 /RS0 DQS4 /DQS4 DM4,DQS13 /DQS13 DQS0 /DQS0 DM0,DQS9 /DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM RDQS I/O 0 I/O 1 I/O 2 I/O I/O I/O I/O I/O 3 4 5 6 7 NU /RDQS /CS DQS DM RDQS I/O 0 I/O 1 I/O 2 /DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D0 I/O I/O I/O I/O I/O NU /RDQS /CS DQS /DQS DQS /DQS DQS /DQS DQS /DQS D4 3 4 5 6 7 DQS5 /DQS5 DM5,DQS14 /DQS14 DQS1 /DQS1 DM1,DQS10 /DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM RDQS I/O 0 I/O 1 I/O 2 I/O I/O I/O I/O I/O 3 4 5 6 7 NU /RDQS /CS DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D1 DM RDQS I/O 0 I/O 1 I/O 2 I/O I/O I/O I/O I/O 3 4 5 6 7 NU /RDQS /CS DQS D5 3 4 5 6 7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D2 NU /RDQS DM RDQS I/O 0 I/O 1 I/O 2 /DQS I/O I/O I/O I/O I/O /CS D6 3 4 5 6 7 DQS7 /DQS7 DM7,DQS16 /DQS16 DQS3 /DQS3 DM3,DQS12 /DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O I/O I/O I/O I/O /CS DQS6 /DQS6 DM6,DQS15 /DQS15 DQS2 /DQS2 DM2,DQS11 /DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 NU /RDQS DM RDQS I/O 0 I/O 1 I/O 2 /DQS DM RDQS I/O 0 I/O 1 I/O 2 I/O I/O I/O I/O I/O 3 4 5 6 7 NU /RDQS /CS DQS DM RDQS I/O 0 I/O 1 I/O 2 /DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D3 DQS8 /DQS8 DM8DQS17 /DQS17 I/O I/O I/O I/O I/O NU /RDQS /CS D7 3 4 5 6 7 Serial PD VDD SPD CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM RDQS I/O 0 I/O 1 I/O 2 I/O I/O I/O I/O I/O 3 4 5 6 7 R E G I S T E R /CS0* BA0 to BA1 A0 to A13 /RAS /CAS CKE0 NU /RDQS /CS DQS /DQS SCL SDA SCL W P D8 /RS0 to /CS ==> /CS: SDRAMs D0 to D8 VDD / VDDQ A0 A1 A2 SA0 SA1 SA2 CK0 RBA0 to RBA1 ==> BA0 to BA1: SDRAMs D0 to D8 /CK0 Serial PD SDA U0 DO-D8 VREF DO-D8 VSS DO-D8 P L L PCK0 to PCK6, PCK8,PCK9 ==> CK: SDRAMs D0 toD8 OE /PCK7 ==> /CK: Register /PCK0 to /PCK6, /PCK8, /PCK9 ==> /CK: SDRAMs D0 toD8 /RA0 to RA13 ==> A0 to A13: SDRAMs D0 to D8 /RRAS ==>/RAS: SDRAMs D0 to D8 /RCAS ==>/CAS: SDRAMs D0 to D8 PCK7 ==> CK: Register /RESET RCKE0 ==> CKE: SDRAMs D0 to D8 /RWE ==> /WE: SDRAMs D0 to D8 /WE ODT0 RODT0 ==> ODT0: SDRAMs D0 to D8 /RESET PCK7 /RST Notes : 1. Register values are 22 Ohms. /PCK7 * : /S0 connects to D/CS and VDD connects to /CSR on register. Rev. 1.0 / Apr. 2005 6 1240pin Registered DDR2 SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM 1GB(128Mbx72) : HYMP512R728 / RS1 / RS0 DQS0 / DQS0 DM0, DQS9 /DQS9 DQS4 / DQS4 DM4, DQS13 /DQS13 DM NU / CS RDQS / RDQS I/ O 0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS / DQS I/ O 1 DM NU / CS RDQS / RDQS I/ O 0 DQS / DQS I/ O 1 D0 I/ O 2 I/ O 2 I/ O 3 I/ O 3 I/ O 4 I/ O 4 I/ O 5 I/ O 5 I/ O 6 I/ O 7 I/ O 6 I/ O 7 DM NU / CS RDQS / RDQS I/ O 0 DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 DQ39 D9 DQ1 / DQ1 DM1,DQS10 /DQS10 DQS / DQS I/ O 1 DM NU / CS RDQS / RDQS I/ O 0 DQS / DQS I/ O 1 D4 I/ O 2 I/ O 2 I/ O 3 I/ O 3 I/ O 4 I/ O 4 I/ O 5 I/ O 5 I/ O 6 I/ O 7 I/ O 6 I/ O 7 D 13 DQS5 / DQS5 DM5, DQS14 /DQS14 DM NU / CS RDQS / RDQS I/ O 0 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 / DQS2 DM 2,DQS11 /DQS11 DQS / DQS I/ O 1 I/ O 2 I/ O 3 I/ O 3 I/ O 4 I/ O 4 I/ O 5 I/ O 5 I/ O 6 I/ O 7 I/ O 6 I/ O 7 DM / CS NU RDQS / RDQS I/ O 0 DQS / DQS I/ O 1 z DM NU / CS RDQS / RDQS I/ O 0 I/ O 2 I/ O 3 I/ O 3 I/ O 4 I/ O 4 I/ O 5 I/ O 5 I/ O 6 I/ O 7 I/ O 6 I/ O 7 DM / CS NU RDQS / RDQS I/ O 0 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 D 10 DQS / DQS I/ O 1 D 11 DM NU / CS RDQS / RDQS I/ O 0 DQ 40 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 DQ47 DQS6 / DQS6 DM6, DQS15 /DQS15 I/ O 2 I/ O 3 I/ O 3 I/ O 4 I/ O 4 I/ O 5 I/ O 5 I/ O 6 I/ O 7 I/ O 6 I/ O 7 DQS8 / DQS8 DM8,DQS17 /DQS17 SCL DM NU / CS RDQS / RDQS I/ O 0 DQS / DQS I/ O 1 DM NU / CS RDQS / RDQS I/ O 0 I/ O 4 I/ O 4 I/ O 5 I/ O 5 I/ O 6 I/ O 7 I/ O 6 I/ O 7 DQS / DQS D8 I/ O 2 I/ O 3 I/ O 3 I/ O 4 I/ O 4 I/ O 5 I/ O 5 I/ O 6 I/ O 7 I/ O 6 I/ O 7 D 14 DM NU / CS RDQS / RDQS I/ O 0 I/ O 2 I/ O 3 I/ O 3 I/ O 4 I/ O 4 I/ O 5 I/ O 5 I/ O 6 I/ O 7 I/ O 6 I/ O 7 DM NU / CS RDQS / RDQS I/ O 0 DQS / DQS I/ O 1 DQS / DQS D 15 DM NU / CS RDQS / RDQS I/ O 0 DQS / DQS I/ O 1 D7 I/ O 2 I/ O 2 I/ O 3 I/ O 3 I/ O 4 I/ O 4 I/ O 5 I/ O 5 I/ O 6 I/ O 7 I/ O 6 I/ O 7 SCL D 16 V DD SPD Serial PD V DD /V DDQ DO-D 17 V REF DO-D 17 V SS DO-D 17 SDA Serial PD DQS / DQS A0 A1 A1 SA0 SA1 SA2 I/ O 1 I/ O 2 DQS / DQS I/ O 1 D6 I/ O 2 WP CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 I/ O 3 I/ O 1 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ 63 D 12 I/ O 2 I/ O 3 DM NU / CS RDQS / RDQS I/ O 0 DQS / DQS DM NU / CS RDQS / RDQS I/ O 0 I/ O 1 D5 I/ O 2 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ 55 DQS7 / DQS7 DM7, DQS16 /DQS16 I/ O 1 D3 I/ O 2 DQS / DQS I/ O 1 DQS / DQS I/ O 1 D2 I/ O 2 DM NU / CS RDQS / RDQS I/ O 0 DQS / DQS I/ O 1 D1 I/ O 2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 / DQS3 DM3,DQS12 /DQS12 DM NU / CS RDQS / RDQS I/ O 0 D 17 CK0 /CK0 PCK0 to PCK6, PCK8,PCK9 = > CK : SDRAMx D0-D17 P L L /PCK0 to /PCK6, /PCK8,/PCK9 = > /CK : SDRAMx D0-D17 PCK7 = > CK: Register /S0 /S1 BA0 to BA1 A0 to A13 /RAS /CAS /WE CKE0 CKE1 ODT0 ODT1 /RESET PCK7 Rev. 1.0 / Apr. 2005 1:2 R E G I S T E R /RS0 to /CS : SDRAMs D0 - D8 /RESET OE /PCK7 = > /CK: Register /RS1 to /CS : SDRAMs D9 - D17 /RBA0 to RBA1 = > BA0 -BA1 : SDRAMs D0-D17 /RA0 to RA12 = > A0 -A12 : SDRAMs D0-D17 /RRAS = > /RAS: SDRAMs D0-D17 Notes: /RCAS = > /CAS: SDRAMs D0-D17 1. Register values are 22 Ohms +/- 5%. 2. /RS0 and /RS1 alternate between the back and front sides of the DIMM /RWE = > /WE: SDRAMs D0-D17 RCKE0 = > CKE0: SDRAMs D0-D8 RCKE1 = > CKE1: SDRAMs D9-D17 RODT0 = > ODT0: SDRAMs D0-D8 RODT1 = > ODT1: SDRAMs D9-D17 / RST /PCK7 7 1240pin Registered DDR2 SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM 1GB(64Mbx72) : HYMP512R724 VSS / RS0 / D Q S9 D Q S9 / D QS0 DQ S0 D Q S / D QS / C S I/ O0 I/O1 D0 I/O2 I/O3 DQ0 D Q1 D Q2 D Q3 DM D Q4 D Q5 D Q6 D Q7 Serial PD DM D Q S / DQ S / C S I/O0 I/O1 D1 I/O2 I/O3 D Q8 DQ9 DQ10 D Q11 DM D Q12 DQ13 DQ14 D Q15 D Q S / D QS / CS I/O0 I/O1 D 10 I/O2 I/O3 D Q S / DQ S / C S I/O0 I/O1 D2 I/O2 I/O3 D Q16 D Q17 D Q18 D Q19 DM DQ20 D Q21 D Q22 DQ23 SD A U0 W P A0 A1 A2 SA0 SA1 SA 2 DM V DD SPD Serial PD V D D /V DD Q DO-D 17 / D QS11 D Q S11 / D Q S2 D Q S2 SD A SC L SC L / D QS10 D Q S10 / D Q S1 D Q S1 D Q S / D QS / CS I/O0 I/O1 D 11 I/O2 I/O3 DM D Q S / D QS / CS I/O0 I/O1 D 12 I/O2 I/O3 DM D Q S / D QS / CS I/O0 I/O1 D 13 I/O2 I/O3 DM D Q S / D QS / CS I/O0 I/O1 D 14 I/O2 I/O3 DM D Q S / D QS / CS I/O0 I/O1 D 15 I/O2 I/O3 DM D Q S / D QS / CS I/O0 I/O1 D 16 I/O2 I/O3 DM D Q S / D QS / CS I/O0 I/O1 D 17 I/O2 I/O3 DM V REF DO-D 17 V SS DO-D 17 / D QS12 D Q S12 / D Q S3 D Q S3 D Q24 D Q25 D Q26 D Q27 D Q S / DQ S / C S I/O0 I/O1 D3 I/O2 I/O3 DM D Q S / DQ S / C S I/O0 I/O1 D4 I/O2 I/O3 DM D Q S / DQ S / C S I/O0 I/O1 D5 I/O2 I/O3 DM D Q28 D Q29 D Q30 D Q31 / D QS13 D Q S13 / D Q S4 D Q S4 DQ32 D Q33 D Q34 DQ35 D Q36 D Q37 D Q38 D Q39 / D QS14 D Q S14 / D Q S5 D Q S5 D Q40 D Q41 D Q42 D Q43 DQ44 D Q45 D Q46 D Q47 / DQ S15 D Q S15 / D Q S6 D Q S6 D Q48 D Q49 D Q50 D Q51 D Q S / DQ S / C S I/O0 I/O1 D6 I/O2 I/O3 DM D Q S / DQ S / C S I/O0 I/O1 D7 I/O2 I/O3 DM D Q S / DQ S / C S I/O0 I/O1 D8 I/O2 I/O3 DM D Q52 D Q53 D Q54 D Q55 / DQ S16 D Q S16 / D Q S7 D Q S7 D Q56 D Q57 D Q58 D Q59 DQ60 D Q61 D Q62 DQ63 / D QS17 D Q S17 / D Q S8 D Q S8 C B0 CB1 CB2 C B3 R E G I S T E R /C S0* BA0 to BA 1 A0 to A13 /RAS /C AS C KE0 C B4 C B5 C B6 C B7 CK 0 /RS0 to /C S ==> /CS: SD R AM s D 0 to D 17 PC K 0 to PC K 6, PC K 8,PC K9 = > C K : SD R AM x D0-D17 P L L /C K0 /PC K 0 to /PC K 6, /PC K 8,/PC K9 = > /C K : SD R AM x D0-D 17 R BA0 to R BA1 ==> BA0 to BA1: SD R AM s D 0 to D 17 PCK 7 = > CK : R egister /R A0 to R A13 ==> A0 to A13: SD R AM s D 0 to D 17 /R R AS ==>/R AS: SDR AM s D 0 to D 17 /R ESET OE /PC K7 = > /C K : Register /R C AS ==>/C AS: SDR AM s D 0 to D 17 R C KE0 ==> C KE: SD RAM s D 0 to D 17 /R W E ==> /W E: SD R AM s D 0 to D 17 /W E O D T0 R O D T0 ==> O D T0: SDR AM s D 0 to D 17 /R ESET D Q S / DQ S / C S I/O0 I/O1 D9 I/O2 I/O3 Notes: 1. Resistor values are 22 Ohm s +/- 5% . /R ST PC K7 /PCK 7 * /S0 connects to D/CS of Register1 and /CSR of Register2. /CSR of register and D/CS of register2 connects to VDD. ** /RESET,PCK 7 connect to both Registers. Other signals connect to one of two Registers. /S1,CKE1 and ODT1 are NC. Rev. 1.0 / Apr. 2005 8 1240pin Registered DDR2 SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM 2GB(256Mbx72) : HYMP125R72M4 VSS / RS0 / RS1 Serial PD D QS0 / D QS0 D Q0 DQ1 DQ2 D Q3 D QS9 / D QS9 DM / CS DQS / DQS DM / CS DQS / DQ S I/O0 I/O1 D0,D 18( DDP) I/O2 I/O3 D QS1 / D QS1 DQ8 DQ9 D Q10 D Q11 / RS0 / RS1 / RS0 / RS1 / RS0 / RS1 D Q12 D Q13 D Q14 DQ15 DM / CS DQ S / DQ S DM / CS DQS I/O0 I/O1 D 10,D 28( DDP) I/O2 I/O3 D Q20 D Q21 D Q22 DQ23 Serial PD V DD SPD V DD /V DDQ DO to D 35 V REF DO to D 35 V SS DO to D 35 DM / CS DQ S / DQ S DM / CS DQS / DQS I/O0 I/O1 D 11,D 29( DDP) I/O2 I/O3 D Q28 D Q29 D Q30 DQ31 DM / CS DQ S / DQ S DM / CS DQS I/O0 I/O1 D 12,D 30( DDP) I/O2 I/O3 CB4 CB5 CB6 CB7 DM / CS DQ S / DQ S DM / CS DQS I/O0 I/O1 D 17,D 35( DDP) I/O2 I/O3 D Q36 D Q37 D Q38 DQ39 DM / CS DQ S / DQ S DM / CS DQS / DQS I/O0 I/O1 D 13,D 31( DDP) I/O2 I/O3 D Q44 D Q45 D Q46 DQ47 DM / CS DQ S / DQ S DM / CS DQS I/O0 I/O1 D 14,D 32( DDP) I/O2 I/O3 DQS15 / D QS15 DM / CS DQS / DQS DM / CS DQS / DQ S I/O0 I/O1 D6,D 24( DDP) I/O2 I/O3 D Q52 D Q53 D Q54 DQ55 DM / CS DQ S / DQ S DM / CS DQS / DQS I/O0 I/O1 D 15,D 33( DDP) I/O2 I/O3 D QS9 / D QS9 D QS7 / D QS7 D Q56 DQ57 DQ58 D Q59 A2 SA 2 DQS14 / D QS14 DM / CS DQS / DQS DM / CS DQS I/O0 I/O1 D5,D 23( DDP) I/O2 I/O3 D QS6 / D QS6 DQ48 DQ49 DQ50 D Q51 A1 SA 1 DQS13 / D QS13 DM / CS DQS / DQS DM / CS DQS / DQ S I/O0 I/O1 D4,D2( DDP) I/O2 I/O3 D QS5 / D QS5 D Q40 DQ41 DQ42 D Q43 A0 SA 0 DQS17 / D QS17 DM / CS DQS / DQS DM / CS DQS I/O0 I/O1 D8,D 26( DDP) I/O2 I/O3 D QS4 / D QS4 D Q32 DQ33 DQ34 D Q35 SDA U0 DQS12 / D QS12 DM / CS DQS / DQS DM / CS DQS I/O0 I/O1 D3,D 21( DDP) I/O2 I/O3 D QS8 / D QS8 C B0 CB1 CB2 C B3 W P DM / CS DQ S / DQ S DM / CS DQS / DQS I/O0 I/O1 D9,D 27( DDP) I/O2 I/O3 DQS11 / D QS11 DM / CS DQS / DQS DM / CS DQS / DQ S I/O0 I/O1 D2,D 20( DDP) I/O2 I/O3 D QS3 / D QS3 DQ24 DQ25 DQ26 D Q27 D Q4 DQ5 DQ6 D Q7 SD A SCL DQS10 / D QS10 DM / CS DQS / DQS DM / CS DQS I/O0 I/O1 D1,D 19( DDP) I/O2 I/O3 D QS2 / D QS2 D Q16 DQ17 DQ18 D Q19 SC L DM / CS DQS / DQS DM / CS DQS I/O0 I/O1 D7,D 25( DDP) I/O2 I/O3 /S0* /S1* BA0 ? BA 1 A0?A13 /RAS /CAS /W E CKE0 CKE1 1:2 R E G I S T E R O DT0 ODT1 /RESET** PCK7** D Q60 D Q61 D Q62 DQ63 DM / CS DQ S / DQ S DM / CS DQS I/O0 I/O1 D9,D 34( DDP) I/O2 I/O3 /RS0 to /CS : SDRAM s D 0 ? D 17 /RS 1 to /CS : SDRAM s D 18 ? D35 CK0 /RBA0 ? RBA1 = > BA0 -BA1 : SDRAM s D 0-D35 /CK0 /RA0 ? RA 12 = > A0 -A12 : SDRAM s D 0-D 35 PCK0 to PCK6, PCK8,PCK9 = > CK : SDRAMx D0-D35 P L L /PCK0 to /PCK6, /PCK8,/PC K9 = > /CK : SD RAMx D0-D35 /RRAS = > /RAS: SDRAM s D 0-D 35 PCK7 = > CK: Register /RCAS = > /CAS: SDRAM s D 0-D35 /RW E = > /W E : SDRAM s D 0-D35 /RESET OE /PCK7 = > /CK: Register RCKE0 = > CKE 0: SDRAM s D 0-D17 RCKE 1 = > CKE1: SDRAM s D 18-D 35 RO DT0 = > O DT0: SDRAM s D 0-D17 RO DT1 = > O DT1: SDRAM s D 18-D35 / RST /PCK7** Notes: 1. Register values are 22 O hm s +/- 5% . 2. /RS 0 and /RS1 alternate between the back and front sides of the DIM M * /S0 connects to D/CS0 and /S1 connects to D/CS1 on both Registers. ** /RESET,PCK7 and /PCK7 connect to both Registers. Other signals connect to two Registers. Rev. 1.0 / Apr. 2005 9 1240pin Registered DDR2 SDRAM DIMMs ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Note VDD - 1.0 V ~ 2.3 V V 1 Voltage on VDDL pin relative to Vss VDDL -0.5V ~ 2.3 V V 1 Voltage on VDDQ pin relative to Vss VDDQ - 0.5 V ~ 2.3 V V 1 VIN, VOUT - 0.5 V ~ 2.3 V V 1 Storage Temperature TSTG -50 ~ +100 Storage Humidity(without condensation) HSTG 5 to 95 Voltage on VDD pin relative to Vss Voltage on any pin relative to Vss C 1 % 1 o Note : 1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating con ditions for extended periods may affect reliablility. OPERATING CONDITIONS Parameter Symbol Rating Units DIMM Operating temperature(ambient) TOPR 0 ~ +55 oC DIMM Barometric Pressure(operating & storage) PBAR 105 to 69 K Pascal DRAM Component Case Temperature Range TCASE 0 ~+95 o C Notes 1 2 Note : 1. Up to 9850 ft. 2. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to tREFI=3.9us. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2. DC OPERATING CONDITIONS (SSTL_1.8) Parameter Min Max Unit VDD 1.7 1.9 V VDDL 1.7 1.9 V VDDQ 1.7 1.9 V 1 Input Reference Voltage VREF 0.49 x VDDQ 0.51 x VDDQ V 2 EEPROM Supply Voltage VDDSPD 1.7 3.6 V Termination Voltage VTT VREF-0.04 VREF+0.04 V Power Supply Voltage Symbol Note 3 Note : 1. 2. 3. VDDQ must be less than or equal to VDD. Peak to peak ac noise on VREF may not exeed +/-2% VREF(dc) VTT of transmitting device must track VREF of receiving device. Rev. 1.0 / Apr. 2005 10 1240pin Registered DDR2 SDRAM DIMMs INPUT DC LOGIC LEVEL Parameter Symbol Min Max Unit Input High Voltage VIH(DC) VREF + 0.125 VDDQ + 0.3 V Input Low Voltage VIL(DC) -0.30 VREF - 0.125 V Min Max Unit Notes INPUT AC LOGIC LEVEL Parameter Symbol AC Input logic High VIH(AC) VREF + 0.250 - V AC Input logic Low VIL(AC) - VREF - 0.250 V Notes AC INPUT TEST CONDITIONS Symbol Condition Value Units Notes 0.5 * VDDQ V 1 VREF Input reference voltage VSWING(MAX) Input signal maximum peak to peak swing 1.0 V 1 SLEW Input signal minimum slew rate 1.0 V/ns 2, 3 Notes: 1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device 2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges and the range from VREF to VIL(ac) max for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions under test. and VIH(ac) to VIL(ac) on the negative transitions. VDDQ VIH(ac) min VIH(dc) min VSWING(MAX) VREF VIL(dc) max VIL(ac) max VSS delta TF Falling Slew = delta TR VREF - VIL(ac) max delta TF Rising Slew = VIH(ac)min - VREF delta TR < Figure : AC Input Test Signal Waveform> Rev. 1.0 / Apr. 2005 11 1240pin Registered DDR2 SDRAM DIMMs Differential Input AC logic Level Symbol Parameter Min. Max. Units Note VID (ac) ac differential input voltage 0.5 VDDQ + 0.6 V 1 VIX (ac) ac differential cross point voltage 0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175 V 2 1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS and UDQS. 2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to VIH(DC) - VIL(DC). VDDQ VTR VID Crossing point VIX or VOX VCP VSSQ < Differential signal levels > Notes: 1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH(AC) - VIL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ . VIX(AC) indicates the voltage at whitch differential input signals must cross. DIFFERENTIAL AC OUTPUT PARAMETERS Symbol Parameter Min. Max. Units Note VOX (ac) ac differential cross point voltage 0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125 V 1 Note: 1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross. Rev. 1.0 / Apr. 2005 12 1240pin Registered DDR2 SDRAM DIMMs OUTPUT BUFFER LEVELS OUTPUT AC TEST CONDITIONS Symbol Parameter SSTL_18 Units Notes VOTR Output Timing Measurement Reference Level 0.5 * VDDQ V 1 Notes: 1. The VDDQ of the device under test is referenced. OUTPUT DC CURRENT DRIVE Symbol Parameter SSTl_18 Units Notes IOH(dc) Output Minimum Source DC Current - 13.4 mA 1, 3, 4 IOL(dc) Output Minimum Sink DC Current 13.4 mA 2, 3, 4 Notes: 1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280 mV. 2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV. 3. The dc value of VREF applied to the receiving device is set to VTT 4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point along a 21 ohm load line to define a convenient driver current for measurement. Rev. 1.0 / Apr. 2005 13 1240pin Registered DDR2 SDRAM DIMMs PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25℃. f=1MHz ) 512MB : HYMP564R72[P]8 Pin Symbol Min Max Unit CK0, CK0 CCK 7 11 pF CKE, ODT CI1 8 12 pF CS CI2 8 12 pF Address, RAS, CAS, WE CI3 8 12 pF DQ, DM, DQS, DQS CIO 6 9 pF Symbol Min Max Unit CK0, CK0 CCK 7 11 pF CKE, ODT CI1 8 12 pF CS CI2 10 15 pF Address, RAS, CAS, WE CI3 8 12 pF DQ, DM, DQS, DQS CIO 8 13 pF Symbol Min Max Unit CK0, CK0 CCK 7 11 pF CKE, ODT CI1 8 12 pF CS CI2 10 15 pF Address, RAS, CAS, WE CI3 8 12 pF DQ, DM, DQS, DQS CIO 6 9 pF Symbol Min Max Unit CK0, CK0 CCK 9.5 14 pF CKE, ODT CI1 10.5 16 pF CS CI2 10.5 16 pF Address, RAS, CAS, WE CI3 10.5 16 pF DQ, DM, DQS, DQS CIO 17 21 pF 1GB : HYMP512R72[P]8 Pin 1GB : HYMP512R72[P]4 Pin 2GB : HYMP125R72M[P]4 Pin Note : 1. Pins not under test are tied to GND. 2. These value are guaranteed by design and tested on a sample basis only. Rev. 1.0 / Apr. 2005 14 1240pin Registered DDR2 SDRAM DIMMs IDD SPECIFICATIONS (TCASE : 0 to 95oC) 512MB, 64M x 72 Registered DIMM : HYMP564R72[P]8 Symbol E3(DDR2 400@CL 3) C4(DDR2 533@CL 4) Unit IDD0 1370 1460 mA IDD1 1460 1550 mA IDD2P 704 713 mA IDD2Q 965 1010 mA IDD2N 1010 1055 mA IDD3P(F) 830 875 mA IDD3P(S) 695 704 mA IDD3N 1145 1235 mA IDD4R 1820 2090 mA IDD4W 2000 2270 mA IDD5B 2135 2225 mA IDD6 500 500 mA IDD7 2630 2630 mA Notes 1 1GB, 128M x 72 Registered DIMM : HYMP512R72[P]8 Symbol E3(DDR2 400@CL3) C4(DDR2 533@CL 4) Unit IDD0 1865 2045 mA IDD1 1955 2135 mA IDD2P 758 776 mA IDD2Q 1280 1370 mA IDD2N 1370 1460 mA IDD3P(F) 1010 1100 mA IDD3P(S) 740 758 mA IDD3N 1640 1820 mA IDD4R 2315 2675 mA IDD4W 2495 2855 mA IDD5B 2630 2810 mA IDD6 549 549 mA IDD7 3125 3215 mA Notes 1 Notes : 1. IDD6 current alues are guaranted up to Tcase of 85oC max. Rev. 1.0 / Apr. 2005 15 1240pin Registered DDR2 SDRAM DIMMs 1GB, 128M x 72 Registered DIMM : HYMP512R72[P]4 Symbol E3(DDR2 400@CL 3) C4(DDR2 533@CL 4) Unit IDD0 2090 2270 mA IDD1 2270 2450 mA IDD2P 758 776 mA IDD2Q 1280 1370 mA IDD2N 1370 1460 mA IDD3P(F) 1010 1100 mA IDD3P(S) 740 758 mA IDD3N 1640 1820 mA IDD4R 2990 3530 mA IDD4W 2990 3170 mA IDD5B 3620 3800 mA IDD6 549 549 mA IDD7 4610 4610 mA note 1 2GB, 256M x 72 Registered DIMM : HYMP125R72M[P]4 Symbol E3(DDR2 400@CL 3) C4(DDR2 533@CL 4) Unit IDD0 3080 3400 mA IDD1 3260 3620 mA IDD2P 866 902 mA IDD2Q 1910 2090 mA IDD2N 2090 2270 mA IDD3P(F) 1370 1550 mA IDD3P(S) 830 866 mA IDD3N 2630 2990 mA IDD4R 3980 4700 mA IDD4W 4340 5060 mA IDD5B 4610 4970 mA IDD6 648 648 mA IDD7 5600 5780 mA note 1 Note : 1. IDD6 current alues are guaranted up to Tcase of 85℃ max. Rev. 1.0 / Apr. 2005 16 1240pin Registered DDR2 SDRAM DIMMs IDD Meauarement Conditions Symbol Conditions Units IDD0 Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD);CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus inputs are SWITCHING mA IDD1 Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD) ; CKE is HIGH, CS is HIGH between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W mA IDD2P Precharge power-down current ; All banks idle ; tCK = tCK(IDD) ; CKE is LOW ; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING mA IDD2Q Precharge quiet standby current;All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING mA IDD2N Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD3P Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Fast PDN Exit MRS(12) = 0 Other control and address bus inputs are STABLE; Data bus inputs are FLOATSlow PDN Exit MRS(12) = 1 ING IDD3N Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD4W Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD4R Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W mA IDD5B Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD6 Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING. IDD6 current values are guaranted up to Tcase of 85℃ max. mA IDD7 Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for detailed timing conditions mA mA mA Notes: 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD LOW is defined as Vin ≤ VILAC(max) HIGH is defined as Vin ≥ VIHAC(min) STABLE is defined as inputs stable at a HIGH or LOW level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes. Rev. 1.0 / Apr. 2005 17 1240pin Registered DDR2 SDRAM DIMMs Electrical Characteristics & AC Timings Speed Bins and CL,tRCD,tRP,tRC and tRAS for Corresponding Bin Speed DDR2-533 (C4) DDR2-400 (E3) Unit Bin(CL-tRCD-tRP) 4-4-4 3-3-3 Parameter min min CAS Latency 4 3 tCK tRCD 15 15 ns tRP 15 15 ns tRC 60 55 ns tRAS 45 40 ns AC Timing Parameters by Speed Grade Parameter Symbol DDR2-400 DDR2-533 Min Max Min Max Unit Note Data-Out edge to Clock edge Skew tAC -600 600 -500 500 ps DQS-Out edge to Clock edge Skew tDQSCK -500 500 -450 450 ns Clock High Level Width tCH 0.45 0.55 0.45 0.55 CK Clock Low Level Width tCL 0.45 0.55 0.45 0.55 CK Clock Half Period tHP min (tCL,tCH) - min (tCL,tCH) - ns System Clock Cycle Time tCK 5000 8000 3750 8000 ps DQ and DM input setup time tDS 150 - 100 - ps 1 DQ and DM input hold time tDH 275 - 225 - ps 1 DQ and DM input setup time(single-ended strobe) tDS1 25 - -25 - ps 1 DQ and DM input hold time(single-ended strobe) tDH1 25 - -25 - ps 1 Control & Address input Pulse Width for each input tIPW 0.6 - 0.6 - tCK DQ and DM input pulse witdth for each input pulse width for each input tDIPW 0.35 - 0.35 - tCK tHZ - tAC max - tAC max ps Data-out high-impedance window from CK, /CK DQS low-impedance time from CK/CK tLZ(DQS) tAC min tAC max tAC min tAC max ps DQ low-impedance time from CK/CK tLZ(DQ) 2*tAC min tAC max 2*tAC min tAC max ps DQS-DQ skew for DQS and associated DQ signals tDQSQ - 350 - 300 ps DQ hold skew factor tQHS - 450 - 400 ps DQ/DQS output hold time from DQS tQH tHP - tQHS - tHP - tQHS - ps First DQS latching transition to associated clock edge tDQSS -0.25 +0.25 -0.25 +0.25 tCK DQS input high pulse width tDQSH 0.35 - 0.35 - tCK DQS input low pulse width tDQSL 0.35 - 0.35 - tCK DQS falling edge to CK setup time tDSS 0.2 - 0.2 - tCK DQS falling edge hold time from CK tDSH 0.2 - 0.2 - tCK Mode register set command cycle time tMRD 2 - 2 - tCK Write postamble tWPST 0.4 0.6 0.4 0.6 tCK Write preamble tWPRE 0.35 - - tCK Rev. 1.0 / Apr. 2005 0.35 18 1240pin Registered DDR2 SDRAM DIMMs - Continued Parameter Symbol DDR2-400 DDR2-533 Min Max Min Max Unit Note Address and control input setup time tIS 350 - 250 - Address and control input hold time tIH 475 - 375 - ps ps Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK Read postamble tRPST 0.4 0.6 0.4 0.6 tCK - 105 - ns Auto-Refresh to Active/Auto-Refresh command period Row Active to Row Active Delay for 1KB page size tRFC 105 tRRD 7.5 - 7.5 - ns Row Active to Row Active Delay for 2KB page size tRRD 10 - 10 - ns Four Activate Window for 1KB page size tFAW 37.5 - 37.5 - ns Four Activate Window for 2KB page size tFAW 50 - 50 - ns CAS to CAS command delay tCCD 2 Write recovery time Auto Precharge Write Recovery + Precharge Time tWR tDAL 15 tWR+tRP - 15 tWR+tRP - ns tCK Write to Read Command Delay tWTR 10 - 7.5 - ns Internal read to precharge command delay 2 tCK tRTP 7.5 7.5 Exit self refresh to a non-read command tXSNR tRFC + 10 tRFC + 10 Exit self refresh to a read command tXSRD 200 - 200 - tCK tXP 2 - 2 - tCK tXARD 2 2 tCK tXARDS 6 - AL 6 - AL tCK tCKE 3 3 tCK Exit precharge power down to any non-read command Exit active power down to read command Exit active power down to read command (Slow exit, Lower power) CKE minimum pulse width (high and low pulse width) ODT turn-on delay tAOND tAON ODT turn-on ODT turn-on(Power-Down mode) tAONPD tAOFD ODT turn-off delay tAOF ODT turn-off ODT turn-off (Power-Down mode) ODT to power down entry latency ODT power down exit latency OCD drive mode output delay Minimum time clocks remains ON after CKE asynchronously drops LOW Average periodic Refresh Interval t AOFPD tANPD tAXPD tOIT tDelay tREFI tREFI 2 2 2 ns ns 2 tAC(min) tAC(max)+1 tAC(min) tAC(max)+1 tAC(min)+ 2tCK+ tAC(min)+ 2tCK+ 2 tAC(max)+1 2 tAC(max)+1 2.5 2.5 2.5 2.5 tAC(max) tAC(max) tAC(min) tAC(min) + 0.6 + 0.6 tAC(min)+ 2.5tCK+tAC tAC(min)+ 2.5tCK+tAC 2 (max)+1 2 (max)+1 3 3 8 8 0 12 0 12 tIS+tCK+tI tIS+tCK+tI H H 7.8 7.8 3.9 3.9 tCK ns ns tCK ns ns tCK tCK ns ns us us 2 3 Notes : 1. For details and notes, please refer to the relevant HYNIX component datasheet(HY5PS12[4/8]21(L)F). 2. 0°C ≤ TCASE ≤ 85°C 3. 85°C ＜ TCASE ≤ 95°C Rev. 1.0 / Apr. 2005 19 1240pin Registered DDR2 SDRAM DIMMs PACKAGE OUTLINE 64Mx72 (1 rank) - HYMP564R72[P]8 Front Side 2. 7 max 133.35 R E G I S T E R 4.0±0.1 ( Front) 30.0 PLL Detail-A Detail-B 1. 27 ± 0.10 5.175 63.0 5.0 55.0 5.175 10.0 17.80 Back 3.0 3.0 1.0 Detail of Contacts B 2.50 3.80 2.50 ± 0.20 0.20 Detail of Contacts A 0.8 ± 0.05 1.50 ± 0.10 5.00 Note) All dimensions are typical millimeter scale unless otherwise stated. Rev. 1.0 / Apr. 2005 20 1240pin Registered DDR2 SDRAM DIMMs PACKAGE OUTLINE 128Mx72 (2 ranks) - HYMP512R72[P]8 Front Side 133.35 4.0 max R E G I S T E R 4.0±0.1 30.0 PLL Detail-A Detail-B 1.27 ± 0.10 5.175 63.0 5.0 55.0 5.175 17.80 10.0 Back R E G I S T E R 3.0 3.0 1.0 Detail of Contacts B 2.50 3.80 2.50 ± 0.20 0.20 Detail of Contacts A 0.8± 0.05 1.50 ± 0.10 5.00 Note) All dimensions are typical millimeter scale unless otherwise stated. Rev. 1.0 / Apr. 2005 21 1240pin Registered DDR2 SDRAM DIMMs PACKAGE OUTLINE 128Mx72 (1 rank) - HYMP512R72[P]4 Front Side 133.35 4.0 max R E G I S T E R 4.0±0.1 30.0 PLL Detail-A Detail-B 1.27 ± 0.10 5.175 63.0 5.0 55.0 5.175 17.80 10.0 Back R E G I S T E R 3.0 3.0 1.0 Detail of Contacts B 2.50 3.80 2.50 ± 0.20 0.20 Detail of Contacts A 0.8± 0.05 1.50 ± 0.10 5.00 Note) All dimensions are typical millimeter scale unless otherwise stated. Rev. 1.0 / Apr. 2005 22 1240pin Registered DDR2 SDRAM DIMMs PACKAGE OUTLINE 256Mx72 (2 ranks) - HYMP125R72M[P]4 Front Side 133.35 4. 0 max R E G I S T E R 4.0±0.1 30.0 PLL Detail-A Detail-B 1. 27 ± 0.10 5.175 63.0 5.0 55.0 5.175 10.0 17.80 Back R E G I S T E R 3.0 3.0 1.0 Detail of Contacts B 2.50 3.80 2.50 ± 0.20 0.20 Detail of Contacts A 0.8 ± 0.05 1.50 ± 0.10 5.00 Note) All dimensions are typical millimeter scale unless otherwise stated. Rev. 1.0 / Apr. 2005 23 1240pin Registered DDR2 SDRAM DIMMs REVISION HISTORY Revision 1.0 History Date First Version Release - Data sheet coverage changed from an individual module part to a component based module family. Dec. 2004 Added VDDL spec, corrected tDS & tDH spec values. Apr. 2005 Rev. 1.0 / Apr. 2005 Remark 24