Preliminary GS81302Q20/38AGD-500/450/400 144Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.5 clock Latency • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs • Burst of 2 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • Data Valid Pin (QVLD) Support • IEEE 1149.1 JTAG-compliant Boundary Scan • RoHS-compliant 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package SigmaQuad™ Family Overview The GS81302Q20/38AGD are built in compliance with the SigmaQuad-II+ SRAM pinout standard for Separate I/O synchronous SRAMs. They are 150,994,944-bit (144Mb) SRAMs. The GS81302Q20/38AGD SigmaQuad SRAMs are 500 MHz–400 MHz 1.8 V VDD 1.8 V and 1.5 V I/O just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Clocking and Addressing Schemes The GS81302Q20/38AGD SigmaQuad-II+ SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. Each internal read and write operation in a SigmaQuad-II+ B2 RAM is two times wider than the device I/O bus. An input data bus de-multiplexer is used to accumulate incoming data before it is simultaneously written to the memory array. An output data multiplexer is used to capture the data produced from a single memory array read and then route it to the appropriate output drivers as needed. Therefore the address field of a SigmaQuad-II+ B2 RAM is always one address pin less than the advertised index depth (e.g., the 16M x 8 has an 8M addressable index). Parameter Synopsis Rev: 1.00a 5/2017 -500 -450 -400 tKHKH 2.0 ns 2.2 ns 2.5 ns tKHQV 0.45 ns 0.45 ns 0.45 ns 1/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2017, GSI Technology Preliminary GS81302Q20/38AGD-500/450/400 8M x 18 SigmaQuad-II+ SRAM—Top View 1 2 3 4 5 6 7 8 9 10 11 A CQ SA SA W BW1 K NC (288Mb) R SA SA CQ B NC Q9 D9 SA NC K BW0 SA NC NC Q8 C NC NC D10 VSS SA SA SA VSS NC Q7 D8 D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7 E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6 F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5 G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5 H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4 K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3 L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2 M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2 N NC D17 Q16 VSS SA SA SA VSS NC NC D1 P NC NC Q17 SA SA QVLD SA SA NC D0 Q0 R TDO TCK SA SA SA ODT SA SA SA TMS TDI 11 x 15 Bump BGA—15 x 17 mm Body—1 mm Bump Pitch Notes: 1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17. 2. A7 is the expansion address. Rev: 1.00a 5/2017 2/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2017, GSI Technology Preliminary GS81302Q20/38AGD-500/450/400 4M x 36 SigmaQuad-II+ SRAM—Top View 1 2 3 4 5 6 7 8 9 10 11 A CQ NC (288Mb) SA W BW2 K BW1 R SA SA CQ B Q27 Q18 D18 SA BW3 K BW0 SA D17 Q17 Q8 C D27 Q28 D19 VSS SA SA SA VSS D16 Q7 D8 D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7 E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6 F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5 G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5 H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4 K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3 L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2 M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2 N D34 D26 Q25 VSS SA SA SA VSS Q10 D9 D1 P Q35 D35 Q26 SA SA QVLD SA SA Q9 D0 Q0 R TDO TCK SA SA SA ODT SA SA SA TMS TDI 11 x 15 Bump BGA—15 x 17 mm Body—1 mm Bump Pitch Notes: 3. BW0 controls writes to D0:D8; BW1 controls writes to D9:D17; BW2 controls writes to D18:D26; BW3 controls writes to D27:D35 4. Pin A2 is the Expansion Address. Rev: 1.00a 5/2017 3/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2017, GSI Technology Preliminary GS81302Q20/38AGD-500/450/400 Pin Description Table Symbol Description Type Comments SA Synchronous Address Inputs Input — R Synchronous Read Input Active Low W Synchronous Write Input Active Low BW0–BW3 Synchronous Byte Writes Input Active Low K Input Clock Input Active High K Input Clock Input Active Low TMS Test Mode Select Input — TDI Test Data Input Input — TCK Test Clock Input Input — TDO Test Data Output Output — VREF HSTL Input Reference Voltage Input — ZQ Output Impedance Matching Input Input — Qn Synchronous Data Outputs Output — Dn Synchronous Data Inputs Input — Doff Disable PLL when low Input Active Low CQ Output Echo Clock Output — CQ Output Echo Clock Output — VDD Power Supply Supply 1.8 V Nominal VDDQ Isolated Output Buffer Supply Supply 1.8 V or 1.5 V Nominal VSS Power Supply: Ground Supply — QVLD Q Valid Output Output — ODT On-Die Termination Input Active High NC No Connect — — Notes: 1. NC = Not Connected to die or any other pin 2. When ZQ pin is directly connected to VDDQ, output impedance is set to minimum value and it cannot be connected to ground or left unconnected. 3. K and K cannot be set to VREF voltage. Rev: 1.00a 5/2017 4/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2017, GSI Technology Preliminary GS81302Q20/38AGD-500/450/400 Background Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are needed. Therefore, the SigmaQuad-II+ SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from Separate I/O SRAMs can cut the RAM’s bandwidth in half. SigmaQuad-II B2 SRAM DDR Read The read port samples the status of the Address Input and R pins at each rising edge of K. A low on the Read Enable-bar pin, R, begins a read cycle. Clocking in a high on the Read Enable-bar pin, R, begins a read port deselect cycle. SigmaQuad-II B2 SRAM DDR Write The write port samples the status of the W pin at each rising edge of K and the Address Input pins on the following rising edge of K. A low on the Write Enable-bar pin, W, begins a write cycle. The first of the data-in pairs associated with the write command is clocked in with the same rising edge of K used to capture the write command. The second of the two data in transfers is captured on the rising edge of K along with the write address. Clocking in a high on W causes a write port deselect cycle. Special Functions Byte Write Control Byte Write Enable pins are sampled at the same time that Data In is sampled. A High on the Byte Write Enable pin associated with a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven High or Low during the data in sample times in a write sequence. Each write enable command and write address loaded into the RAM provides the base address for a 2beat data transfer. The x18 version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any write sequence. Example x18 RAM Write Sequence using Byte Write Enables Data In Sample Time BW0 BW1 D0–D8 D9–D17 Beat 1 0 1 Data In Don’t Care Beat 2 1 0 Don’t Care Data In Resulting Write Operation Byte 1 D0–D8 Byte 2 D9–D17 Byte 3 D0–D8 Byte 4 D9–D17 Written Unchanged Unchanged Written Beat 1 Rev: 1.00a 5/2017 Beat 2 5/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2017, GSI Technology Preliminary GS81302Q20/38AGD-500/450/400 FLXDrive-II Output Driver Impedance Control HSTL I/O SigmaQuad-II+ SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is between 175 and 350. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is implemented with discrete binary weighted impedance steps. Input Termination Impedance Control These SigmaQuad-II+ SRAMs are supplied with programmable input termination on Data (D), Byte Write (BW), and Clock (K/K) input receivers. Input termination can be enabled or disabled via the ODT pin (6R). When the ODT pin is tied Low (or left floating —the pin has a small pull-down resistor), input termination is disabled. When the ODT pin is tied High, input termination is enabled. Termination impedance is programmed via the same RQ resistor (connected between the ZQ pin and VSS) used to program output driver impedance, and is nominally RQ*0.6 Thevenin-equivalent when RQ is between 175 and 250. Periodic readjustment of the termination impedance occurs to compensate for drifts in supply voltage and temperature, in the same manner as for driver impedance (see above). Note: When ODT = 1, Data (D), Byte Write (BW), and Clock (K, K) input termination is always enabled. Consequently, D, BW, K, K inputs should always be driven High or Low; they should never be tri-stated (i.e., in a High-Z state). If the inputs are tri-stated, the input termination will pull the signal to VDDQ/2 (i.e., to the switch point of the diff-amp receiver), which could cause the receiver to enter a meta-stable state, resulting in the receiver consuming more power than it normally would. This could result in the device’s operating currents being higher. Rev: 1.00a 5/2017 6/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2017, GSI Technology Preliminary GS81302Q20/38AGD-500/450/400 Separate I/O SigmaQuad-II B2 SigmaQuad-II SRAM Read Truth Table A R Output Next State Q Q K (tn) K (tn) K (tn) K (tn+2) K (tn+2½) X 1 Deselect Hi-Z Hi-Z V 0 Read Q0 Q1 Notes: 1. X = Don’t Care, 1 = High, 0 = Low, V = Valid. 2. R is evaluated on the rising edge of K. 3. Q0 and Q1 are the first and second data output transfers in a read. Separate I/O SigmaQuad-II B2 SigmaQuad-II SRAM Write Truth Table A W BWn BWn Input Next State D D K (tn + ½) K (tn) K (tn) K (tn + ½) K K (tn), (tn + ½) K (tn) K (tn + ½) V 0 0 0 Write Byte Dx0, Write Byte Dx1 D0 D1 V 0 0 1 Write Byte Dx0, Write Abort Byte Dx1 D0 X V 0 1 0 Write Abort Byte Dx0, Write Byte Dx1 X D1 X 0 1 1 Write Abort Byte Dx0, Write Abort Byte Dx1 X X X 1 X X Deselect X X Notes: 1. X = Don’t Care, H = High, L = Low, V = Valid. 2. W is evaluated on the rising edge of K. 3. D0 and D1 are the first and second data input transfers in a write. 4. BWn represents any of the Byte Write Enable inputs (BW0, BW1, etc.). Rev: 1.00a 5/2017 7/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2017, GSI Technology Preliminary GS81302Q20/38AGD-500/450/400 x36 Byte Write Enable (BWn) Truth Table BW0 BW1 BW2 BW3 D0–D8 D9–D17 D18–D26 D27–D35 1 1 1 1 Don’t Care Don’t Care Don’t Care Don’t Care 0 1 1 1 Data In Don’t Care Don’t Care Don’t Care 1 0 1 1 Don’t Care Data In Don’t Care Don’t Care 0 0 1 1 Data In Data In Don’t Care Don’t Care 1 1 0 1 Don’t Care Don’t Care Data In Don’t Care 0 1 0 1 Data In Don’t Care Data In Don’t Care 1 0 0 1 Don’t Care Data In Data In Don’t Care 0 0 0 1 Data In Data In Data In Don’t Care 1 1 1 0 Don’t Care Don’t Care Don’t Care Data In 0 1 1 0 Data In Don’t Care Don’t Care Data In 1 0 1 0 Don’t Care Data In Don’t Care Data In 0 0 1 0 Data In Data In Don’t Care Data In 1 1 0 0 Don’t Care Don’t Care Data In Data In 0 1 0 0 Data In Don’t Care Data In Data In 1 0 0 0 Don’t Care Data In Data In Data In 0 0 0 0 Data In Data In Data In Data In x18 Byte Write Enable (BWn) Truth Table BW0 BW1 D0–D8 D9–D17 1 1 Don’t Care Don’t Care 0 1 Data In Don’t Care 1 0 Don’t Care Data In 0 0 Data In Data In Rev: 1.00a 5/2017 8/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2017, GSI Technology Preliminary GS81302Q20/38AGD-500/450/400 Absolute Maximum Ratings (All voltages reference to VSS) Symbol Description Value Unit VDD Voltage on VDD Pins –0.5 to 2.9 V VDDQ Voltage in VDDQ Pins –0.5 to VDD V VREF Voltage in VREF Pins –0.5 to VDDQ V VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 ( 2.9 V max.) V VIN Input Voltage (Address, Control, Data, Clock) –0.5 to VDDQ +0.5 ( 2.9 V max.) V VTIN Input Voltage (TCK, TMS, TDI) –0.5 to VDDQ +0.5 ( 2.9 V max.) V IIN Input Current on Any Pin +/–100 mA dc IOUT Output Current on Any I/O Pin +/–100 mA dc TJ Maximum Junction Temperature 125 oC TSTG Storage Temperature –55 to 125 oC Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component. Recommended Operating Conditions Power Supplies Parameter Symbol Min. Typ. Max. Unit Supply Voltage VDD 1.7 1.8 1.9 V I/O Supply Voltage VDDQ 1.4 — VDD V Reference Voltage VREF VDDQ/2 – 0.05 — VDDQ/2 + 0.05 V Note: The power supplies need to be powered up simultaneously or in the following sequence: VDD, VDDQ, VREF, followed by signal inputs. The power down sequence must be the reverse. VDDQ must not exceed VDD. For more information, read AN1021 SigmaQuad and SigmaDDR Power-Up. Operating Temperature Parameter Symbol Min. Typ. Max. Unit Junction Temperature (Commercial Range Versions) TJ 0 25 85 C Junction Temperature (Industrial Range Versions)* TJ –40 25 100 C Note: * The part numbers of Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. Rev: 1.00a 5/2017 9/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2017, GSI Technology Preliminary GS81302Q20/38AGD-500/450/400 Thermal Impedance Package Test PCB Substrate JA (C°/W) Airflow = 0 m/s JA (C°/W) Airflow = 1 m/s JA (C°/W) Airflow = 2 m/s JB (C°/W) JC (C°/W) 165 BGA 4-layer TBD TBD TBD TBD TBD Notes: 1. Thermal Impedance data is based on a number of of samples from mulitple lots and should be viewed as a typical number. 2. Please refer to JEDEC standard JESD51-6. 3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to the PCB can result in cooling or heating of the RAM depending on PCB temperature. HSTL I/O DC Input Characteristics Parameter Symbol Min Max Units Notes Input Reference Voltage VREF VDDQ /2 – 0.05 VDDQ /2 + 0.05 V — Input High Voltage VIH1 VREF + 0.1 VDDQ + 0.3 V 1 Input Low Voltage VIL1 –0.3 VREF – 0.1 V 1 Input High Voltage VIH2 0.7 * VDDQ VDDQ + 0.3 V 2,3 Input Low Voltage VIL2 –0.3 0.3 * VDDQ V 2,3 Notes: 1. Parameters apply to K, K, SA, D, R, W, BW during normal operation and JTAG boundary scan testing. 2. Parameters apply to Doff, ODT during normal operation and JTAG boundary scan testing. 3. Parameters apply to ZQ during JTAG boundary scan testing only. HSTL I/O AC Input Characteristics Parameter Symbol Min Max Units Notes Input Reference Voltage VREF VDDQ /2 – 0.08 VDDQ /2 + 0.08 V — Input High Voltage VIH1 VREF + 0.2 VDDQ + 0.5 V 1,2,3 Input Low Voltage VIL1 –0.5 VREF – 0.2 V 1,2,3 Input High Voltage VIH2 VDDQ – 0.2 VDDQ + 0.5 V 4,5 Input Low Voltage VIL2 –0.5 0.2 V 4,5 Notes: 1. VIH(MAX) and VIL(MIN) apply for pulse widths less than one-quarter of the cycle time. 2. Input rise and fall times must be a minimum of 1 V/ns, and within 10% of each other. 3. Parameters apply to K, K, SA, D, R, W, BW during normal operation and JTAG boundary scan testing. 4. Parameters apply to Doff, ODT during normal operation and JTAG boundary scan testing. 5. Parameters apply to ZQ during JTAG boundary scan testing only. Rev: 1.00a 5/2017 10/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2017, GSI Technology Preliminary GS81302Q20/38AGD-500/450/400 Capacitance (TA = 25oC, f = 1 MHZ, VDD = 1.8 V) Parameter Symbol Test conditions Typ. Max. Unit Input Capacitance CIN VIN = 0 V 4 5 pF Output Capacitance COUT VOUT = 0 V 6 7 pF Clock Capacitance CCLK VIN = 0 V 5 6 pF Note: This parameter is sample tested. AC Test Conditions Parameter Conditions Input high level 1.25 Input low level 0.25 V Max. input slew rate 2 V/ns Input reference level 0.75 Output reference level VDDQ/2 Note: Test conditions as specified with output loading as shown unless otherwise noted. AC Test Load Diagram DQ 50 RQ = 250 (HSTL I/O) VREF = 0.75 V VT == 0.75 V Input and Output Leakage Characteristics Parameter Symbol Test Conditions Min. Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD –2 uA 2 uA Doff IILDOFF VIN = 0 to VDD –2 uA 100 uA ODT IIL ODT VIN = 0 to VDD –2 uA 100 uA Output Leakage Current IOL Output Disable, VOUT = 0 to VDDQ –2 uA 2 uA Rev: 1.00a 5/2017 11/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2017, GSI Technology Preliminary GS81302Q20/38AGD-500/450/400 Programmable Impedance HSTL Output Driver DC Electrical Characteristics Parameter Symbol Min. Max. Units Notes Output High Voltage VOH1 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V 1, 3 Output Low Voltage VOL1 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V 2, 3 Output High Voltage VOH2 VDDQ – 0.2 VDDQ V 4, 5 Output Low Voltage VOL2 Vss 0.2 V 4, 6 Notes: 1. IOH = (VDDQ/2) / (RQ/5) +/– 15% @ VOH = VDDQ/2 (for: 175 RQ 350 2. IOL = (VDDQ/2) / (RQ/5) +/– 15% @ VOL = VDDQ/2 (for: 175 RQ 350. 3. Parameter tested with RQ = 250 and VDDQ = 1.5 V 4. 0RQ 5. IOH = –1.0 mA 6. IOL = 1.0 mA Operating Currents -500 Parameter Symbol Test Conditions Operating Current (x36): DDR IDD Operating Current (x18): DDR IDD Standby Current (NOP): DDR ISB1 -450 -400 Notes 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C VDD = Max, IOUT = 0 mA Cycle Time tKHKH Min TBD TBD TBD TBD TBD TBD 2, 3 VDD = Max, IOUT = 0 mA Cycle Time tKHKH Min TBD TBD TBD TBD TBD TBD 2, 3 TBD TBD TBD TBD TBD TBD 2, 4 Device deselected, IOUT = 0 mA, f = Max, All Inputs 0.2 V or VDD – 0.2 V Notes: 1. 2. 3. 4. Power measured with output pins floating. Minimum cycle, IOUT = 0 mA Operating current is calculated with 50% read cycles and 50% write cycles. Standby Current is only after all pending read and write burst operations are completed. Rev: 1.00a 5/2017 12/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2017, GSI Technology Preliminary GS81302Q20/38AGD-500/450/400 Symbol -500 -450 -400 Min Max Min Max Min Max Units Parameter Notes AC Electrical Characteristics Clock K, K Clock Cycle Time tKHKH 2.0 8.4 2.2 8.4 2.5 8.4 ns tK Variable tKVar — 0.15 — 0.15 — 0.2 ns K, K Clock High Pulse Width tKHKL 0.4 — 0.4 — 0.4 — cycle K, K Clock Low Pulse Width tKLKH 0.4 — 0.4 — 0.4 — cycle K to K High tKHKH 0.85 — 0.94 — 1.06 — ns K to K High tKHKH 0.85 — 0.94 — 1.06 — ns PLL Lock Time tKLock 20 — 20 — 20 — s K Static to PLL reset tKReset 30 — 30 — 30 — ns K, K Clock High to Data Output Valid tKHQV — 0.45 — 0.45 — 0.45 ns K, K Clock High to Data Output Hold tKHQX –0.45 — –0.45 — –0.45 — ns K, K Clock High to Echo Clock Valid tKHCQV — 0.33 — 0.37 — 0.45 ns K, K Clock High to Echo Clock Hold tKHCQX –0.33 — –0.37 — –0.45 — ns CQ, CQ High Output Valid tCQHQV — 0.15 — 0.15 — 0.2 ns CQ, CQ High Output Hold tCQHQX –0.15 — –0.15 — –0.2 — ns tQVLD –0.15 0.15 –0.15 0.15 –0.2 0.2 ns tCQHCQH tCQHCQH 0.75 — 0.85 — 1.0 — ns K Clock High to Data Output High-Z tKHQZ — 0.45 — 0.45 — 0.45 ns K Clock High to Data Output Low-Z tKHQX1 –0.45 — –0.45 — –0.45 — ns tAVKH 0.25 0.275 — 0.4 — ns 1 tIVKH 0.25 — 0.275 — 0.4 — ns 2 tIVKH 0.2 — 0.22 — 0.28 — ns 3 tDVKH 0.2 — 0.22 — 0.28 — ns tKHAX 0.25 — 0.275 — 0.4 — ns 1 tKHIX 0.25 — 0.275 — 0.4 — ns 2 tKHIX 0.2 — 0.22 — 0.28 — ns 3 tKHDX 0.2 — 0.22 — 0.28 — ns 4 5 Output Times CQ, CQ High to QVLD CQ Phase Distortion Setup Times Address Input Setup Time Control Input Setup Time (R, W) Control Input Setup Time (BWX) Data Input Setup Time Hold Times Address Input Hold Time Control Input Hold Time (R, W) Control Input Hold Time (BWX) Data Input Hold Time Notes: 1. All Address inputs must meet the specified setup and hold times for all latching clock edges. 2. Control signals are R, W. 3. Control signals are BW0, BW1 and (BW2, BW3 for x36). 4. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 5. VDD slew rate must be less than 0.1 V DC per 50 ns for PLL lock retention. PLL lock time begins once VDD and input clock are stable. Rev: 1.00a 5/2017 13/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2017, GSI Technology Rev: 1.00a 5/2017 CQ CQ Q QVLD W R Addr K K A0 tKHIX tIVKH tKHAX tAVKH Read A0 / Write NOP A1 tKHIX tIVKH Read A1 / Write NOP A2 tQVLD A3 tCQHQV Q1 tCQLQV tCQLQX tCQHQV Q0+1 Read A3 / Write NOP tCQLQV Q0 Read A2 / Write NOP Read NOP CQ-Based Timing Diagram tCQHQX Q1+1 NOOP Q2 tCQLQX Q2+1 NOOP tCQHQX Q3 tQV Q3 NOOP Preliminary GS81302Q20/38AGD-500/450/400 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 14/24 © 2017, GSI Technology Rev: 1.00a 5/2017 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 15/24 CQ CQ Q QVLD D BWx W R Addr K K D8 A0 D8+1 tIVKH tKHIX A8 tAVKH tKHAX Read A0/ Write A8 D7 A1 D7+1 tIVKH tKHIX A7 D6 A2 tQVLD D6+1 tDVKH tKHDX tIVKH tKHIX A6 tCQHQV tCQLQV Q0 D5 Q0+1 D5+1 A5 tCQHQX tCQLQX Q1 tCQLQV tCQHQV Q1+1 NOOP tDVKH tKHDX Read A3/ Write A5 A3 tKHIX tIVKH Read A2/ Write A6 tKHAX tAVKH Read A1/ Write A7 Read-Write CQ-Based Timing Diagram Q2 tCQLQX tCQHQX Q2+1 NOOP Q3 tQV Q3 NOOP Preliminary GS81302Q20/38AGD-500/450/400 © 2017, GSI Technology Rev: 1.00a 5/2017 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 16/24 D BWx W R Addr K K D0 D1+1 tKHIX tIVKH A1 Read No-op / Write A1 D1 tKHDX tDVKH tKHIX tIVKH D0+1 tKHDX tDVKH tIVKH tKHIX tKHIX tIVKH A0 tKHAX tAVKH Read No-op / Write A0 D2 D2+1 A2 Read No-op / Write A2 D3 D3+1 A3 Read No-op / Write A3 Write NOP Timing Diagram NO-OP NO-OP NO-OP Preliminary GS81302Q20/38AGD-500/450/400 © 2017, GSI Technology Preliminary GS81302Q20/38AGD-500/450/400 JTAG Port Operation Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDD. Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected. JTAG Pin Descriptions Pin Pin Name I/O Description TCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS Test Mode Select In The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. TDI Test Data In In The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level. TDO Test Data Out Out Output that is active depending on the state of the TAP state machine. Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up. JTAG Port Registers Overview The various JTAG registers, refered to as Test Access Port or TAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible. Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Rev: 1.00a 5/2017 17/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2017, GSI Technology Preliminary GS81302Q20/38AGD-500/450/400 Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. JTAG TAP Block Diagram · · · · · · · · Boundary Scan Register · · 1 · 108 0 0 Bypass Register 2 1 0 Instruction Register TDI TDO ID Code Register 31 30 29 · · ·· 2 1 0 Control Signals TMS Test Access Port (TAP) Controller TCK Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. GSI Technology JEDEC Vendor ID Code See BSDL Model Bit # Presence Register ID Register Contents 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X 1 X X Rev: 1.00a 5/2017 X X X X X X X X X X X X X X X X X 0 18/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 0 0 1 1 0 1 1 0 0 1 © 2017, GSI Technology Preliminary GS81302Q20/38AGD-500/450/400 Tap Controller Instruction Set Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. JTAG Tap Controller State Diagram 1 0 Test Logic Reset 0 Run Test Idle 1 Select DR 1 Select IR 0 0 1 1 Capture DR Capture IR 0 0 Shift DR 1 1 Shift IR 0 1 1 Exit1 DR 0 Exit1 IR 0 0 Pause DR 1 Exit2 DR 1 Update DR 1 1 0 0 Pause IR 1 Exit2 IR 0 1 0 0 Update IR 1 0 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is Rev: 1.00a 5/2017 19/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2017, GSI Technology Preliminary GS81302Q20/38AGD-500/450/400 loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins. Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. JTAG TAP Instruction Set Summary Instruction Code Description Notes EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1 IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2 SAMPLE-Z 010 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. 1 GSI 011 GSI private instruction. 1 SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. 1 GSI 101 GSI private instruction. 1 GSI 110 GSI private instruction. 1 BYPASS 111 Places Bypass Register between TDI and TDO. 1 Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.00a 5/2017 20/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2017, GSI Technology Preliminary GS81302Q20/38AGD-500/450/400 JTAG Port Recommended Operating Conditions and DC Characteristics Parameter Symbol Min. Max. Unit Notes Test Port Input Low Voltage VILJ –0.3 0.3 * VDD V 1 Test Port Input High Voltage VIHJ 0.7 * VDD VDD +0.3 V 1 TMS, TCK and TDI Input Leakage Current IINHJ –300 1 uA 2 TMS, TCK and TDI Input Leakage Current IINLJ –1 100 uA 3 TDO Output Leakage Current IOLJ –1 1 uA 4 Test Port Output High Voltage VOHJ VDD – 0.2 — V 5, 6 Test Port Output Low Voltage VOLJ — 0.2 V 5, 7 Test Port Output CMOS High VOHJC VDD – 0.1 — V 5, 8 Test Port Output CMOS Low VOLJC — 0.1 V 5, 9 Notes: 1. Input Under/overshoot voltage must be –1 V < Vi < VDDn +1 V not to exceed 2.9 V maximum, with a pulse width not to exceed 20% tTKC. 2. VILJ VIN VDDn 3. 0 V VIN VILJn 4. Output Disable, VOUT = 0 to VDDn 5. The TDO output driver is served by the VDD supply. 6. IOHJ = –2 mA 7. IOLJ = + 2 mA 8. IOHJC = –100 uA 9. IOLJC = +100 uA JTAG Port AC Test Conditions Parameter Conditions Input high level VDD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level VDD/2 Output reference level VDD/2 JTAG Port AC Test Load TDO 50 VDD/2 * Distributed Test Jig Capacitance Notes: 1. Include scope and jig capacitance. 2. Test conditions as shown unless otherwise noted. Rev: 1.00a 5/2017 30pF* 21/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2017, GSI Technology Preliminary GS81302Q20/38AGD-500/450/400 JTAG Port Timing Diagram tTKC tTKH tTKL TCK tTH tTS TDI tTH tTS TMS tTKQ TDO tTH tTS Parallel SRAM input JTAG Port AC Electrical Characteristics Parameter Symbol Min Max Unit TCK Cycle Time tTKC 50 — ns TCK Low to TDO Valid tTKQ — 20 ns TCK High Pulse Width tTKH 20 — ns TCK Low Pulse Width tTKL 20 — ns TDI & TMS Set Up Time tTS 10 — ns TDI & TMS Hold Time tTH 10 — ns Rev: 1.00a 5/2017 22/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2017, GSI Technology Preliminary GS81302Q20/38AGD-500/450/400 Package Dimensions—165-Bump FPBGA (Package D) A1 CORNER TOP VIEW BOTTOM VIEW Ø0.10 M C Ø0.25 M C A B Ø0.40~0.60 (165x) 1 2 3 4 5 6 7 8 9 10 11 A1 CORNER 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R 1.0 14.0 15±0.05 1.0 A B C D E F G H J K L M N P R A 1.0 1.0 10.0 0.15 C B Rev: 1.00a 5/2017 SEATING PLANE 0.20(4x) 0.36~0.46 1.40 MAX. C 13±0.05 23/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2017, GSI Technology Preliminary GS81302Q20/38AGD-500/450/400 Ordering Information—GSI SigmaQuad-II+ SRAM Org Part Number1 Type Package Speed (MHz) TJ2 8M x 18 GS81302Q20AGD-500 SigmaQuad-II+ B2 SRAM RoHS-compliant 165-bump BGA 500 C 8M x 18 GS81302Q20AGD-450 SigmaQuad-II+ B2 SRAM RoHS-compliant 165-bump BGA 450 C 8M x 18 GS81302Q20AGD-400 SigmaQuad-II+ B2 SRAM RoHS-compliant 165-bump BGA 400 C 8M x 18 GS81302Q20AGD-500I SigmaQuad-II+ B2 SRAM RoHS-compliant 165-bump BGA 500 I 8M x 18 GS81302Q20AGD-450I SigmaQuad-II+ B2 SRAM RoHS-compliant 165-bump BGA 450 I 8M x 18 GS81302Q20AGD-400I SigmaQuad-II+ B2 SRAM RoHS-compliant 165-bump BGA 400 I 4M x 36 GS81302Q38AGD-500 SigmaQuad-II+ B2 SRAM RoHS-compliant 165-bump BGA 500 C 4M x 36 GS81302Q38AGD-450 SigmaQuad-II+ B2 SRAM RoHS-compliant 165-bump BGA 450 C 4M x 36 GS81302Q38AGD-400 SigmaQuad-II+ B2 SRAM RoHS-compliant 165-bump BGA 400 C 4M x 36 GS81302Q38AGD-500I SigmaQuad-II+ B2 SRAM RoHS-compliant 165-bump BGA 500 I 4M x 36 GS81302Q38AGD-450I SigmaQuad-II+ B2 SRAM RoHS-compliant 165-bump BGA 450 I 4M x 36 GS81302Q38AGD-400I SigmaQuad-II+ B2 SRAM RoHS-compliant 165-bump BGA 400 I Notes: 1. For Tape and Reel add the character “T” to the end of the part number. Example: GS81302QxxAGD-400T. 2. C = Commercial Temperature Range. I = Industrial Temperature Range. SigmaQuad-II+ SRAM Revision History File Name Format/Content • Creation of datasheet • (Rev1.00a: Corrected erroneous information in Input and Output Leakage Characteristics table) 81302Q1937A_r1 Rev: 1.00a 5/2017 Description of changes 24/24 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2017, GSI Technology