ON EMC5DXV5T1 Dual common base-collector bias resistor transistor Datasheet

EMC2DXV5T1,
EMC5DXV5T1
Preferred Devices
Dual Common
Base−Collector Bias
Resistor Transistors
NPN and PNP Silicon Surface Mount
Transistors with Monolithic Bias
Resistor Network
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The BRT (Bias Resistor Transistor) contains a single transistor with
a monolithic bias network consisting of two resistors; a series base
resistor and a base−emitter resistor. These digital transistors are
designed to replace a single device and its external resistor bias
network. The BRT eliminates these individual components by
integrating them into a single device. In the EMC5DXV5T1 series,
two complementary BRT devices are housed in the SOT−553 package
which is ideal for low power surface mount applications where board
space is at a premium.
• Simplifies Circuit Design
• Reduces Board Space
• Reduces Component Count
• Available in 8 mm, 7 inch Tape and Reel
• Lead Free
2
R1
1
R2
Q2
R2
Q1
R1
4
5
MARKING
DIAGRAM
5
5
1
SOT−553
CASE 463B
xx D
1
MAXIMUM RATINGS (TA = 25°C unless otherwise noted, common for Q1
and Q2, − minus sign for Q1 (PNP) omitted)
Symbol
Value
Unit
Collector-Base Voltage
VCBO
50
Vdc
Collector-Emitter Voltage
VCEO
50
Vdc
IC
100
mAdc
Rating
Collector Current
THERMAL CHARACTERISTICS
Characteristic
(One Junction Heated)
Symbol
Total Device Dissipation
TA = 25°C
Derate above 25°C
Thermal Resistance −
Junction-to-Ambient
Characteristic
(Both Junctions Heated)
Junction and Storage Temperature
Unit
357 (Note 1)
2.9 (Note 1)
mW
mW/°C
350 (Note 1)
°C/W
PD
RJA
Symbol
Total Device Dissipation
TA = 25°C
Derate above 25°C
Thermal Resistance −
Junction-to-Ambient
Max
Max
Unit
PD
500 (Note 1)
4.0 (Note 1)
mW
mW/°C
RJA
250 (Note 1)
°C/W
TJ, Tstg
−55 to +150
°C
xx = Specific Device Code
D = Date Code
ORDERING INFORMATION
Device
Package
Shipping†
EMC2DXV5T1
SOT−553
4 mm pitch
4000/Tape & Reel
EMC2DXV5T5
SOT−553
2 mm pitch
8000/Tape & Reel
EMC5DXV5T1
SOT−553
4 mm pitch
4000/Tape & Reel
EMC5DXV5T5
SOT−553
2 mm pitch
8000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
1. FR−4 @ Minimum Pad
Preferred devices are recommended choices for future use
and best overall value.
 Semiconductor Components Industries, LLC, 2003
September, 2003 − Rev. 1
1
Publication Order Number:
EMC2DXV5T1/D
EMC2DXV5T1, EMC5DXV5T1
DEVICE MARKING AND RESISTOR VALUES
Transistor 1 − PNP
Device
EMC2DXV5T1
EMC5DXV5T1
Transistor 2 − NPN
Marking
R1 (K)
R2 (K)
R1 (K)
R2 (K)
UC
U5
22
4.7
22
10
22
47
22
47
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
Collector-Base Cutoff Current (VCB = 50 V, IE = 0)
ICBO
−
−
100
nAdc
Collector-Emitter Cutoff Current (VCB = 50 V, IB = 0)
ICEO
−
−
500
nAdc
Emitter-Base Cutoff Current
(VEB = 6.0, IC = 5.0 mA)
IEBO
−
−
−
−
0.2
1.0
mAdc
Collector-Base Breakdown Voltage (IC = 10 µA, IE = 0)
V(BR)CBO
50
−
−
Vdc
Collector-Emitter Breakdown Voltage (IC = 2.0 mA, IB = 0)
V(BR)CEO
50
−
−
Vdc
hFE
60
20
100
35
−
−
VCE(SAT)
−
−
0.25
Vdc
Output Voltage (on) (VCC = 5.0 V, VB = 2.5 V, RL = 1.0 k)
VOL
−
−
0.2
Vdc
Output Voltage (off) (VCC = 5.0 V, VB = 0.5 V, RL = 1.0 k)
VOH
4.9
−
−
Vdc
k
Q1 TRANSISTOR: PNP
OFF CHARACTERISTICS
EMC2DXV5T1
EMC5DXV5T1
ON CHARACTERISTICS
DC Current Gain
(VCE = 10 V, IC = 5.0 mA)
EMC2DXV5T1
EMC5DXV5T1
Collector−Emitter Saturation Voltage (IC = 10 mA, IB = 0.3 mA)
Input Resistor
EMC2DXV5T1
EMC5DXV5T1
R1
15.4
3.3
22
4.7
28.6
6.1
Resistor Ratio
EMC2DXV5T1
EMC5DXV5T1
R1/R2
0.8
0.38
1.0
0.47
1.2
0.56
Q2 TRANSISTOR: NPN
OFF CHARACTERISTICS
Symbol
Min
Typ
Max
Unit
Collector-Base Cutoff Current (VCB = 50 V, IE = 0)
Characteristic
ICBO
−
−
100
nAdc
Collector-Emitter Cutoff Current (VCB = 50 V, IB = 0)
ICEO
−
−
500
nAdc
Emitter-Base Cutoff Current
(VEB = 6.0, IC = 5.0 mA)
IEBO
−
−
−
−
0.2
0.1
mAdc
Collector-Base Breakdown Voltage (IC = 10 µA, IE = 0)
V(BR)CBO
50
−
−
Vdc
Collector-Emitter Breakdown Voltage (IC = 2.0 mA, IB = 0)
V(BR)CEO
50
−
−
Vdc
hFE
60
80
100
140
−
−
VCE(SAT)
−
−
0.25
Vdc
Output Voltage (on) (VCC = 5.0 V, VB = 2.5 V, RL = 1.0 k)
VOL
−
−
0.2
Vdc
Output Voltage (off) (VCC = 5.0 V, VB = 0.5 V, RL = 1.0 k)
EMC2DXV5T1
EMC5DXV5T1
ON CHARACTERISTICS
DC Current Gain
(VCE = 10 V, IC = 5.0 mA)
EMC2DXV5T1
EMC5DXV5T1
Collector−Emitter Saturation Voltage (IC = 10 mA, IB = 0.3 mA)
VOH
4.9
−
−
Vdc
Input Resistor
EMC2DXV5T1
EMC5DXV5T1
R1
15.4
33
22
47
28.6
61
k
Resistor Ratio
EMC2DXV5T1
EMC5DXV5T1
R1/R2
0.8
0.8
1.0
1.0
1.2
1.2
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EMC2DXV5T1, EMC5DXV5T1
PD , POWER DISSIPATION (MILLIWATTS)
250
200
150
100
50
0
−50
RJA = 833°C/W
0
50
100
TA, AMBIENT TEMPERATURE (°C)
Figure 1. Derating Curve
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150
EMC2DXV5T1, EMC5DXV5T1
1000
10
VCE = 10 V
IC/IB = 10
1
hFE, DC CURRENT GAIN
VCE(sat) , MAXIMUM COLLECTOR VOLTAGE (VOLTS)
TYPICAL ELECTRICAL CHARACTERISTICS — EMC2DXV5T1 PNP TRANSISTOR
25°C
TA=−25°C
75°C
0.1
0.01
0
40
20
IC, COLLECTOR CURRENT (mA)
TA=75°C
100
10
50
10
1
Figure 3. DC Current Gain
100
IC, COLLECTOR CURRENT (mA)
3
2
1
10
20
30
40
VR, REVERSE BIAS VOLTAGE (VOLTS)
TA=−25°C
10
1
0.1
0.01
0.001
50
Figure 4. Output Capacitance
100
25°C
75°C
f = 1 MHz
lE = 0 mA
TA = 25°C
V in , INPUT VOLTAGE (VOLTS)
Cob , CAPACITANCE (pF)
4
0
VO = 5 V
0
1
2
3
4
5
6
7
Vin, INPUT VOLTAGE (VOLTS)
VO = 0.2 V
10
25°C
75°C
1
0
10
8
9
Figure 5. Output Current versus Input Voltage
TA=−25°C
0.1
100
IC, COLLECTOR CURRENT (mA)
Figure 2. VCE(sat) versus IC
0
25°C
−25°C
20
30
IC, COLLECTOR CURRENT (mA)
40
Figure 6. Input Voltage versus Output Current
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50
10
EMC2DXV5T1, EMC5DXV5T1
1
1000
IC/IB = 10
VCE = 10 V
TA=−25°C
25°C
hFE, DC CURRENT GAIN
VCE(sat) , MAXIMUM COLLECTOR VOLTAGE (VOLTS)
TYPICAL ELECTRICAL CHARACTERISTICS — EMC2DXV5T1 NPN TRANSISTOR
0.1
75°C
0.01
0.001
0
20
40
IC, COLLECTOR CURRENT (mA)
TA=75°C
25°C
−25°C
100
10
50
1
10
IC, COLLECTOR CURRENT (mA)
Figure 7. VCE(sat) versus IC
Figure 8. DC Current Gain
100
IC, COLLECTOR CURRENT (mA)
2
1
0
0
10
20
30
40
VR, REVERSE BIAS VOLTAGE (VOLTS)
25°C
75°C
f = 1 MHz
IE = 0 mA
TA = 25°C
1
0.1
0.01
0.001
50
TA=−25°C
10
VO = 5 V
0
1
2
3
4
5
6
7
Vin, INPUT VOLTAGE (VOLTS)
10
VO = 0.2 V
TA=−25°C
25°C
75°C
1
0.1
0
10
8
9
10
Figure 10. Output Current versus Input Voltage
Figure 9. Output Capacitance
V in , INPUT VOLTAGE (VOLTS)
Cob , CAPACITANCE (pF)
4
3
100
20
30
IC, COLLECTOR CURRENT (mA)
40
Figure 11. Input Voltage versus Output
Current
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5
50
EMC2DXV5T1, EMC5DXV5T1
1000
1
VCE = 10 V
IC/IB = 10
TA=75°C
0.1
0.01
hFE, DC CURRENT GAIN
VCE(sat) , MAXIMUM COLLECTOR VOLTAGE (VOLTS)
TYPICAL ELECTRICAL CHARACTERISTICS — EMC5DXV5T1 PNP TRANSISTOR
25°C
−25°C
0
10
20
30
50
40
100
1
60
1
10
100
IC, COLLECTOR CURRENT (mA)
IC, COLLECTOR CURRENT (mA)
Figure 12. VCE(sat) versus IC
Figure 13. DC Current Gain
1000
100
IC, COLLECTOR CURRENT (mA)
f = 1 MHz
IE = 0 mA
TA = 25°C
10
Cob , CAPACITANCE (pF)
25°C
−25°C
10
12
8
6
4
SERIES 1
2
0
TA=75°C
0
5
10
20
30
15
25
35
VR, REVERSE BIAS VOLTAGE (VOLTS)
40
1
Figure 14. Output Capacitance
VO = 5 V
0.1
0.01
45
75°C
10
TA=−25°C
25°C
0
2
4
6
8
Vin, INPUT VOLTAGE (VOLTS)
10
12
Figure 15. Output Current versus Input Voltage
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EMC2DXV5T1, EMC5DXV5T1
10
1000
VCE = 10 V
IC/IB = 10
hFE, DC CURRENT GAIN
VCE(sat) , MAXIMUM COLLECTOR VOLTAGE (VOLTS)
TYPICAL ELECTRICAL CHARACTERISTICS — EMC5DXV5T1 NPN TRANSISTOR
1
25°C
TA=−25°C
75°C
0.1
0.01
0
TA=75°C
25°C
−25°C
100
10
50
20
40
IC, COLLECTOR CURRENT (mA)
10
IC, COLLECTOR CURRENT (mA)
1
Figure 16. VCE(sat) versus IC
1
100
IC, COLLECTOR CURRENT (mA)
0.4
0.2
0
0
25°C
75°C
0.6
TA=−25°C
10
1
0.1
0.01
0.001
50
10
20
30
40
VR, REVERSE BIAS VOLTAGE (VOLTS)
VO = 5 V
0
2
4
6
Vin, INPUT VOLTAGE (VOLTS)
100
VO = 0.2 V
TA=−25°C
10
25°C
75°C
1
0.1
0
10
8
10
Figure 19. Output Current versus Input Voltage
Figure 18. Output Capacitance
V in , INPUT VOLTAGE (VOLTS)
Cob , CAPACITANCE (pF)
Figure 17. DC Current Gain
f = 1 MHz
IE = 0 mA
TA = 25°C
0.8
100
20
30
40
50
IC, COLLECTOR CURRENT (mA)
Figure 20. Input Voltage versus Output Current
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EMC2DXV5T1, EMC5DXV5T1
INFORMATION FOR USING THE SOT−553 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages
must be the correct size to insure proper solder connection
interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.3
0.0118
0.45
0.0177
1.0
0.0394
1.35
0.0531
0.5
0.5
0.0197 0.0197
SCALE 20:1
mm inches
SOT−553
SOT−553 POWER DISSIPATION
SOLDERING PRECAUTIONS
The power dissipation of the SOT−553 is a function of
the pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature
of the die, RJA, the thermal resistance from the device
junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT−553
package, PD can be calculated as follows:
PD =
The melting temperature of solder is higher than the
rated temperature of the device. When the entire device is
heated to a high temperature, failure to complete soldering
within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied during cooling.
TJ(max) − TA
RJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature TA of 25°C,
one can calculate the power dissipation of the device which
in this case is 150 milliwatts.
PD =
150°C − 25°C
833°C/W
= 150 milliwatts
The 833°C/W for the SOT−553 package assumes the use
of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 150 milliwatts.
There are other alternatives to achieving higher power dissipation from the SOT−553 package. Another alternative
would be to use a ceramic substrate or an aluminum core
board such as Thermal Clad. Using a board material such
as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.
* Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage
to the device.
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EMC2DXV5T1, EMC5DXV5T1
PACKAGE DIMENSIONS
SOT−553
XV5 SUFFIX
5−LEAD PACKAGE
CASE 463B−01
ISSUE O
A
−X−
5
C
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
4
1
2
B
−Y−
3
D
G
S
J
5 PL
0.08 (0.003)
M
X Y
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DIM
A
B
C
D
G
J
K
S
MILLIMETERS
MIN
MAX
1.50
1.70
1.10
1.30
0.50
0.60
0.17
0.27
0.50 BSC
0.08
0.18
0.10
0.30
1.50
1.70
INCHES
MIN
MAX
0.059
0.067
0.043
0.051
0.020
0.024
0.007
0.011
0.020 BSC
0.003
0.007
0.004
0.012
0.059
0.067
EMC2DXV5T1, EMC5DXV5T1
Thermal Clad is a trademark of the Bergquist Company.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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Phone: 81−3−5773−3850
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For additional information, please contact your
local Sales Representative.
EMC2DXV5T1/D
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