Gennum GS9062 Hd-linx ii sd-sdi and dvb-asi serializer with clockcleaner Datasheet

GS9062 HD-LINX® II
SD-SDI and DVB-ASI Serializer
with ClockCleaner™
GS9062 Data Sheet
Key Features
Description
•
SMPTE 259M-C compliant scrambling and
NRZ → NRZI encoding (with bypass)
•
DVB-ASI sync word insertion and 8b/10b encoding
•
adjustable loop bandwidth
•
user selectable additional processing features
including:
The GS9062 is a dual-standard serializer with an
integrated cable driver. When used in conjunction with
the GO1555/GO1525* Voltage Controlled Oscillator, a
transmit solution can be realized for SD-SDI and
DVB-ASI applications.
•
ANC data checksum, and line number
calculation and insertion
•
TRS and EDH packet generation and insertion
•
illegal code remapping
•
internal flywheel for noise immune TRS generation
•
20-bit / 10-bit CMOS parallel input data bus
•
27MHz / 13.5MHz parallel digital input
•
automatic standards detection and indication
•
Pb-free and RoHS compliant
•
1.8V core power supply and 3.3V charge pump
power supply
•
3.3V digital I/O supply
•
JTAG test interface
•
small footprint compatible with GS1560A, GS1561,
GS1532, and GS9060
Applications
•
SMPTE 259M-C Serial Digital Interfaces
•
DVB-ASI Serial Digital Interfaces
The device features an internal PLL, which can be
configured for loop bandwidth as narrow as 100kHz.
Thus the GS9062 can tolerate in excess of 300ps jitter
on the input PCLK and still provide output jitter well
within SMPTE specification. Connect the output clocks
from Gennum’s GS4911 clock generator directly to the
GS9062’s PCLK input and configure the GS9062’s loop
bandwidth accordingly.
In addition to serializing the input, the GS9062 performs
NRZ-to-NRZI encoding and scrambling as per SMPTE
259M-C when operating in SMPTE mode. When
operating in DVB-ASI mode, the device will insert K28.5
sync characters and 8b/10b encode the data prior to
serialization.
Parallel data inputs are provided for 10-bit multiplexed
or 20-bit demultiplexed formats. An appropriate parallel
clock input signal is also required.
The integrated cable driver features an output mute on
loss of parallel clock, high impedance mode and
adjustable signal swing.
The GS9062 also includes a range of data processing
functions including automatic standards detection and
EDH support. The device can also insert TRS signals,
re-map illegal code words and insert SMPTE 352M
payload identifier packets. All processing features are
optional and may be enabled/disabled via external
control pin(s) and/or host interface programming.
The GS9062 is Pb-free, and the encapsulation
compound does not contain halogenated flame
retardant (RoHS compliant).
*For new designs use GO1555
22209 - 7
February 2007
1 of 46
www.gennum.com
GS9062 Data Sheet
Functional Block Diagram
VCO_GND
LF
VCO_VCC
LB_CONT
VCO
VCO
CP_CAP
PCLK
LOCKED
F
V
H
DETECT_TRS
DVB_ASI
IOPROC_EN/DIS
SMPTE_BYPASS
BLANK
20bit/10bit
Phase detector, charge pump,
VCO control & power supply
bypass
dvb-asi
ClockCleaner™
SDO_EN/DIS
DIN[19:0]
I/O
Buffer
&
demux
TRS insertion,
data blank, codere-map and
flywheel
DVB-ASI sync
word insert &
8b/10b encode
SMPTE
352M
generation
EDH
generation
& SMPTE
scramble
SDO
P -> S
SDO
RSET
HOST Interface /
JTAG test
Reset
RESET_TRST
SDOUT_TDO
SDIN_TDI
SCLK_TCK
CS_TMS
JTAG/HOST
GS9062 Functional Block Diagram
22209 - 7
February 2007
2 of 46
GS9062 Data Sheet
Contents
Key Features .................................................................................................................1
Applications...................................................................................................................1
Description ....................................................................................................................1
Functional Block Diagram .............................................................................................2
1. Pin Out .....................................................................................................................5
1.1 Pin Assignment ...............................................................................................5
1.2 Pin Descriptions ..............................................................................................6
2. Electrical Characteristics ........................................................................................12
2.1 Absolute Maximum Ratings ..........................................................................12
2.2 DC Electrical Characteristics ........................................................................12
2.3 AC Electrical Characteristics.........................................................................13
2.4 Solder Reflow Profiles...................................................................................15
2.5 Input/Output Circuits .....................................................................................16
2.6 Host Interface Maps......................................................................................18
2.6.1 Host Interface Map (Read only registers) ...........................................19
2.6.2 Host Interface Map (R/W configurable registers)................................20
3. Detailed Description ...............................................................................................21
3.1 Functional Overview .....................................................................................21
3.2 Parallel Data Inputs.......................................................................................21
3.2.1 Parallel Input in SMPTE Mode............................................................22
3.2.2 Parallel Input in DVB-ASI Mode..........................................................22
3.2.3 Parallel Input in Data-Through Mode ..................................................22
3.2.4 Parallel Input Clock (PCLK) ................................................................23
3.3 SMPTE Mode................................................................................................23
3.3.1 Internal Flywheel.................................................................................23
3.3.2 HVF Timing Signal Extraction .............................................................24
3.4 DVB-ASI Mode..............................................................................................25
3.4.1 Control Signal Inputs ..........................................................................25
3.5 Data-Through Mode ......................................................................................26
3.6 Additional Processing Functions...................................................................26
3.6.1 Input Data Blank .................................................................................26
3.6.2 Automatic Video Standard Detection..................................................26
3.6.3 Packet Generation and Insertion ........................................................28
3.7 Parallel-To-Serial Conversion .......................................................................34
3.8 Serial Digital Data PLL..................................................................................35
3.8.1 External VCO......................................................................................35
3.8.2 Lock Detect Output .............................................................................35
3.8.3 Loop Bandwidth Adjustment ...............................................................36
3.9 Serial Digital Output ......................................................................................36
3.9.1 Output Swing ......................................................................................37
22209 - 7
February 2007
3 of 46
GS9062 Data Sheet
3.9.2 Serial Digital Output Mute...................................................................37
3.10 GSPI Host Interface ....................................................................................37
3.10.1 Command Word Description.............................................................38
3.10.2 Data Read and Write Timing ............................................................39
3.10.3 Configuration and Status Registers ..................................................39
3.11 JTAG...........................................................................................................40
3.12 Device Power Up ........................................................................................41
3.13 Device Reset...............................................................................................41
4. Application Reference Design ................................................................................42
4.1 Typical Application Circuit .............................................................................42
5. References & Relevant Standards.........................................................................43
6. Package & Ordering Information............................................................................44
6.1 Package Dimensions ....................................................................................44
6.2 Packaging Data.............................................................................................45
6.3 Ordering Information .....................................................................................45
7. Revision History .....................................................................................................46
22209 - 7
February 2007
4 of 46
GS9062 Data Sheet
1. Pin Out
IO_VDD
DIN9
IO_GND
DIN8
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
IO_VDD
51 50
49
48
47
46
45
44
43
42
41
DIN10
56
DIN11
57
IO_VDD
DIN14
58
DIN13
DIN15
59
DIN12
DIN17
60
DIN16
IO_GND
1.1 Pin Assignment
55
54
53
52
61
40
IO_GND
DIN18
62
39
DIN1
DIN19
63
38
DIN0
CORE_VDD
64
37
CORE_VDD
NC
65
36
H
NC
66
35
V
DETECT_TRS
67
34
F
9062
33
CORE_GND
32
BLANK
70
31
NC
CORE_GND
68
PCLK
69
NC
NC
71
30
SCLK_TCK
LOCKED
72
29
SDIN_TDI
VCO
73
28
SDOUT_TDO
CS_TMS
JTAG/HOST
4
5
6
22209 - 7
7
8
9
10
11
12
13
14
15
16
17 18
February 2007
19
20
RSET
3
SMPTE_BYPASS
2
CD_VDD
SDO_EN/DIS
1
NC
CD_GND
21
NC
22
80
NC
79
CP_GND
NC
LB_CONT
IOPROC_EN/DIS
SDO
NC
23
20bit/10bit
78
NC
CP_CAP
DVB_ASI
LF
SDO
NC
RESET_TRST
24
NC
25
77
NC
76
NC
VCO_VCC
RSV
26
PD_VDD
75
PD_GND
74
VCO_GND
CP_VDD
VCO
27
5 of 46
GS9062 Data Sheet
1.2 Pin Descriptions
Table 1-1: Pin Descriptions
Pin
Number
Name
Timing
Type
Description
1
CP_VDD
–
Power
Power supply connection for the charge pump. Connect to +3.3V
DC analog.
2
PD_GND
–
Power
Ground connection for the phase detector. Connect to analog
GND.
3
PD_VDD
–
Power
Power supply connection for the phase detector. Connect to
+1.8V DC analog.
4, 6 – 8,
NC
–
–
No connect.
5
RSV
–
–
Reserved – connect to analog ground.
9
DVB_ASI
Non
Synchronous
Input
10 – 11,
14 – 17, 31,
70 – 71
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
When set HIGH in conjunction with SMPTE_BYPASS = LOW,
the device will be configured to operate in DVB-ASI mode.
When set LOW, the device will not support the encoding of
received DVB-ASI data.
12
20bit/10bit
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select the input data bus width in SMPTE or
Data-Through modes. This signal is ignored in DVB-ASI mode.
When set HIGH, the parallel input will be 20-bit demultiplexed
data.
When set LOW, the parallel input will be 10-bit multiplexed data.
13
IOPROC_EN/DIS
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable I/O processing features.
When set HIGH, the following I/O processing features of the
device are enabled:
• EDH Packet Generation and Insertion
• SMPTE 352M Packet Generation and Insertion
• ANC Data Checksum Calculation and Insertion
• TRS Generation and Insertion
• Illegal Code Remapping
To enable a subset of these features, keep IOPROC_EN/DIS
HIGH and disable the individual feature(s) in the
IOPROC_DISABLE register accessible via the host interface.
When set LOW, the I/O processing features of the device are
disabled, regardless of whether the features are enabled in the
IOPROC_DISABLE register.
22209 - 7
February 2007
6 of 46
GS9062 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
18
SMPTE_BYPASS
Non
Synchronous
Input
Description
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
When set HIGH in conjunction with DVB_ASI = LOW, the device
will be configured to operate in SMPTE mode. All I/O processing
features may be enabled in this mode.
When set LOW, the device will not support the scrambling or
encoding of received SMPTE data. No I/O processing features
will be available.
19
RSET
Analog
Input
20
CD_VDD
–
Power
21
SDO_EN/DIS
Non
Synchronous
Input
Used to set the serial digital output signal amplitude. Connect to
CD_VDD through 281Ω +/- 1% for 800mVp-p single-ended output
swing.
Power supply connection for the serial digital cable driver.
Connect to +1.8V DC analog.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable the serial digital output stage.
When set LOW, the serial digital output signals SDO and SDO
are disabled and become high impedance.
When set HIGH, the serial digital output signals SDO and SDO
are enabled.
22
CD_GND
–
Power
Ground connection for the serial digital cable driver. Connect to
analog GND.
23, 24
SDO, SDO
Analog
Output
Serial digital output signal operating at 270Mb/s.
The slew rate of these outputs is automatically controlled to meet
SMPTE 259M specifications.
25
RESET_TRST
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to reset the internal operating conditions to default settings
and to reset the JTAG test sequence.
Host Mode (JTAG/HOST = LOW)
When asserted LOW, all functional blocks will be set to default
conditions and all input and output signals become high
impedance, including the serial digital outputs SDO and SDO.
Must be set HIGH for normal device operation.
JTAG Test Mode (JTAG/HOST = HIGH)
When asserted LOW, all functional blocks will be set to default
and the JTAG test sequence will be held in reset.
When set HIGH, normal operation of the JTAG test sequence
resumes.
26
JTAG/HOST
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select JTAG Test Mode or Host Interface Mode.
When set HIGH, CS_TMS, SDOUT_TDO, SDI_TDI and
SCLK_TCK are configured for JTAG boundary scan testing.
When set LOW, CS_TMS, SDOUT_TDO, SDI_TDI and
SCLK_TCK are configured as GSPI pins for normal host
interface operation.
22209 - 7
February 2007
7 of 46
GS9062 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
27
CS_TMS
Synchronous
with
SCLK_TCK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Chip Select / Test Mode Select
Host Mode (JTAG/HOST = LOW)
CS_TMS operates as the host interface chip select, CS, and is
active LOW.
JTAG Test Mode (JTAG/HOST = HIGH)
CS_TMS operates as the JTAG test mode select, TMS, and is
active HIGH.
NOTE: If the host interface is not being used, tie this pin HIGH.
28
SDOUT_TDO
Synchronous
with
SCLK_TCK
Output
CONTROL SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data Output / Test Data Output
Host Mode (JTAG/HOST = LOW)
SDOUT_TDO operates as the host interface serial output,
SDOUT, used to read status and configuration information from
the internal registers of the device.
JTAG Test Mode (JTAG/HOST = HIGH)
SDOUT_TDO operates as the JTAG test data output, TDO.
29
SDIN_TDI
Synchronous
with
SCLK_TCK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data In / Test Data Input
Host Mode (JTAG/HOST = LOW)
SDIN_TDI operates as the host interface serial input, SDIN, used
to write address and configuration information to the internal
registers of the device.
JTAG Test Mode (JTAG/HOST = HIGH)
SDIN_TDI operates as the JTAG test data input, TDI.
NOTE: If the host interface is not being used, tie this pin HIGH.
30
SCLK_TCK
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data Clock / Test Clock.
Host Mode (JTAG/HOST = LOW)
SCLK_TCK operates as the host interface burst clock, SCLK.
Command and data read/write words are clocked into the device
synchronously with this clock.
JTAG Test Mode (JTAG/HOST = HIGH)
SCLK_TCK operates as the JTAG test clock, TCK.
NOTE: If the host interface is not being used, tie this pin HIGH.
32
BLANK
Synchronous
with PCLK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable input data blanking.
When set LOW, the luma and chroma input data is set to the
appropriate blanking levels. Horizontal and vertical ancillary
spaces will also be set to blanking levels.
When set HIGH, the luma and chroma input data pass through
the device unaltered.
22209 - 7
February 2007
8 of 46
GS9062 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
33, 68
CORE_GND
–
Power
Ground connection for the digital core logic. Connect to digital
GND.
34
F
Synchronous
with PCLK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the ODD / EVEN field of the video signal when
DETECT_TRS is set LOW. The device will set the F bit in all
outgoing TRS signals for the entire period that the F input signal
is HIGH (IOPROC_EN/DIS must also be HIGH).
The F signal should be set HIGH for the entire period of field 2
and should be set LOW for all lines in field 1 and for all lines in
progressive scan systems.
The F signal is ignored when DETECT_TRS = HIGH.
35
V
Synchronous
with PCLK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the portion of the video field / frame that is used
for vertical blanking when DETECT_TRS is set LOW. The device
will set the V bit in all outgoing TRS signals for the entire period
that the V input signal is HIGH (IOPROC_EN/DIS must also be
HIGH).
The V signal should be set HIGH for the entire vertical blanking
period and should be set LOW for all lines outside of the vertical
blanking interval.
The V signal is ignored when DETECT_TRS = HIGH.
36
H
Synchronous
with PCLK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the portion of the video line containing active
video data when DETECT_TRS is set LOW. The device will set
the H bit in all outgoing TRS signals for the entire period that the
H input signal is HIGH (IOPROC_EN/DIS must also be HIGH).
H signal timing is configurable via the H_CONFIG bit of the
IOPROC_DISABLE register, accessible via the host interface.
Active Line Blanking (H_CONFIG = 0h)
The H signal should be set HIGH for the entire horizontal
blanking period, including the EAV and SAV TRS words, and
LOW otherwise. This is the default setting.
TRS Based Blanking (H_CONFIG = 1h)
The H signal should be set HIGH for the entire horizontal
blanking period as indicated by the H bit in the received TRS ID
words, and LOW otherwise.
37, 64
CORE_VDD
–
22209 - 7
Power
February 2007
Power supply connection for the digital core logic. Connect to
+1.8V DC digital.
9 of 46
GS9062 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
38, 39, 42–
48, 50
DIN[0:9]
Synchronous
with PCLK
Input
PARALLEL DATA BUS
Signal levels are LVCMOS/LVTTL compatible.
DIN9 is the MSB and DIN0 is the LSB.
20-bit mode
20bit/10bit = HIGH
Chroma data input in SMPTE
mode SMPTE_BYPASS =
HIGH
DVB_ASI = LOW
Data input in Data-Through
mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
High impedance in DVB-ASI
mode
SMPTE_BYPASS = LOW
DVB_ASI = HIGH
10-bit mode
20bit/10bit = LOW
High impedance in all modes.
40, 49, 60
IO_GND
–
Power
Ground connection for digital I/O buffers. Connect to digital GND.
41, 53, 61
IO_VDD
–
Power
Power supply connection for digital I/O buffers. Connect to +3.3V
DC digital.
51, 52, 54–
59, 62, 63
DIN[10:19]
Synchronous
with PCLK
Input
PARALLEL DATA BUS
Signal levels are LVCMOS/LVTTL compatible.
DIN19 is the MSB and DIN10 is the LSB.
20-bit mode
20bit/10bit = HIGH
Luma data input in SMPTE
mode
SMPTE_BYPASS = HIGH
DVB_ASI = LOW
Data input in Data-Through
mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
DVB-ASI data input in
DVB-ASI mode
SMPTE_BYPASS = LOW
DVB_ASI = HIGH
10-bit mode
20bit/10bit = LOW
Multiplexed Luma and Chroma
data input in SMPTE mode
SMPTE_BYPASS = HIGH
DVB_ASI = LOW
Data input in data through
mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
DVB-ASI data input in
DVB-ASI mode
SMPTE_BYPASS = LOW
DVB_ASI = HIGH
22209 - 7
February 2007
10 of 46
GS9062 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
67
DETECT_TRS
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select the timing mode of the device.
When set HIGH, the device will lock the internal flywheel to the
embedded TRS timing signals in the parallel input data.
When set LOW, the device will lock the internal flywheel to the
externally supplied H, V, and F input signals.
69
72
PCLK
LOCKED
–
Synchronous
with PCLK
Input
Output
PARALLEL DATA BUS CLOCK
Signal levels are LVCMOS/LVTTL compatible.
SD 20-bit mode
PCLK = 13.5MHz
SD 10-bit mode
PCLK = 27MHz
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS / LVTTL compatible.
The LOCKED signal will be HIGH whenever the device has
correctly received and locked to SMPTE compliant data in
SMPTE mode or DVB-ASI compliant data in DVB-ASI mode.
It will be LOW otherwise.
73, 74
VCO, VCO
Analog
Input
Differential inputs for the external VCO reference signal. For
single ended devices such as the GO1555/GO1525*, VCO
should be AC coupled to VCO_GND.
*For new designs use GO1555
75
VCO_GND
–
Output Power
Ground reference for the external voltage controlled oscillator.
Connect to pins 2, 4, 6, and 8 of the GO1555/GO1525*. This pin
is an output.
Should be isolated from all other grounds.
*For new designs use GO1555
76
VCO_VCC
–
Output Power
Power supply for the external voltage controlled oscillator.
Connect to pin 5 of the GO1555/GO1525*. This pin is an output.
Should be isolated from all other power supplies.
*For new designs use GO1555
77
LF
Analog
Output
Control voltage to external voltage controlled oscillator. Nominally
+1.25V DC.
78
CP_CAP
Analog
Input
PLL lock time constant capacitor connection. Normally connected
to VCO_GND through 2.2nF.
79
LB_CONT
Analog
Input
Control voltage to set the loop bandwidth of the integrated
reclocker.
80
CP_GND
–
Power
Ground connection for the charge pump. Connect to analog
GND.
22209 - 7
February 2007
11 of 46
GS9062 Data Sheet
2. Electrical Characteristics
2.1 Absolute Maximum Ratings
Parameter
Value/Units
Supply Voltage Core
-0.3V to +2.1V
Supply Voltage I/O
-0.3V to +4.6V
Input Voltage Range (any input)
-2.0V to + 5.25V
Ambient Operating Temperature
-20°C < TA < 85°C
Storage Temperature
-40°C < TSTG < 125°C
Solder Reflow Temperature
230°C
ESD Protection On All Pins
1kV
1. NOTE: See reflow solder profiles (Solder Reflow Profiles on page 15)
2. MIL STD 883 ESD protection applied to all pins on the device.
2.2 DC Electrical Characteristics
Table 2-1: DC Electrical Characteristics
TA = 0°C to 70°C, unless otherwise specified.
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Test
Levels
Notes
System
Operation Temperature Range
TA
–
0
–
70
°C
–
1
Digital Core Supply Voltage
CORE_VDD
–
1.65
1.8
1.95
V
1
1
Digital I/O Supply Voltage
IO_VDD
–
3.0
3.3
3.6
V
1
1
Charge Pump Supply Voltage
CP_VDD
–
3.0
3.3
3.6
V
1
1
Phase Detector Supply Voltage
PD_VDD
–
1.65
1.8
1.95
V
1
1
Input Buffer Supply Voltage
BUFF_VDD
–
1.65
1.8
1.95
V
1
1
Cable Driver Supply Voltage
CD_VDD
–
1.71
1.8
1.89
V
1
1
External VCO Supply Voltage
Output
VCO_VCC
–
2.25
2.50
2.75
V
1
–
+1.8V Supply Current
I1V8
–
–
–
245
mA
1
3
+3.3V Supply Current
I3V3
–
–
–
45
mA
1
–
Total Device Power
PD
–
–
–
590
mW
5
3
22209 - 7
February 2007
12 of 46
GS9062 Data Sheet
Table 2-1: DC Electrical Characteristics (Continued)
TA = 0°C to 70°C, unless otherwise specified.
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Test
Levels
Notes
Digital I/O
Input Logic LOW
VIL
–
–
–
0.8
V
1
–
Input Logic HIGH
VIH
–
2.1
–
–
V
1
–
Output Logic LOW
VOL
8mA
–
0.2
0.4
V
1
–
Output Logic HIGH
VOH
8mA
IO_VDD - 0.4
–
–
V
1
–
Input
RSET Voltage
VRSET
RSET=281Ω
0.54
0.6
0.66
V
1
2
VCMOUT
75Ω load,
RSET=281Ω
0.8
1.0
1.2
V
1
–
Output
Output Common Mode Voltage
TEST LEVELS
NOTES
1. Production test at room temperature and nominal supply
voltage with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply
voltage with guardbands for supply and temperature ranges
using correlated test.
3. Production test at room temperature and nominal supply
voltage.
4. QA sample test.
5. Calculated result based on Level 1, 2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of
similar product.
9. Indirect test.
1. All DC and AC electrical parameters within specification.
2. Set by the value of the RSET resistor.
3. SDO outputs enabled.
2.3 AC Electrical Characteristics
Table 2-2: AC Electrical Characteristics
TA = 0°C to 70°C, unless otherwise shown
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Test
Levels
Notes
SMPTE and
Data-Through modes
–
21
–
PCLK
6
–
DVB-ASI mode
–
11
–
PCLK
6
–
1
–
–
ms
7
3
System
Device Latency
Reset Pulse Width
treset
22209 - 7
February 2007
13 of 46
GS9062 Data Sheet
Table 2-2: AC Electrical Characteristics (Continued)
TA = 0°C to 70°C, unless otherwise shown
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Test
Levels
Notes
Parallel Clock Frequency
fPCLK
–
13.5
–
27.0
MHz
1
–
Parallel Clock Duty Cycle
DCPCLK
–
40
50
60
%
1
–
Input Data Setup Time
tSU
–
2
–
–
ns
1
1
Input Data Hold Time
tIH
–
1.5
–
–
ns
1
1
Serial Output Data Rate
DRSDO
–
–
270
–
Mb/s
1
–
Serial Output Swing
∆VSDD
RSET = 281Ω
Load = 75Ω
–
800
–
mVp-p
1
–
Serial Output Rise Time
20% ~ 80%
trSDO
ORL compensation
using recommended
circuit
400
550
1500
ps
1
–
Serial Output Fall Time
20% ~ 80%
tfSDO
ORL compensation
using recommended
circuit
400
550
1500
ps
1
–
Serial Output Intrinsic Jitter
tIJ
Pseudorandom and
pathological signal
–
270
350
ps
1
–
Serial Output Duty Cycle
Distortion
DCDSDO
–
–
20
–
ps
1
2
GSPI Input Clock Frequency
fSCLK
–
–
–
6.6
MHz
1
–
GSPI Input Clock Duty Cycle
DCSCLK
–
40
50
60
%
6,7
–
–
0
–
–
ns
6,7
–
Parallel Input
Serial Digital Output
GSPI
GSPI Input Data Setup Time
GSPI Input Data Hold Time
–
1.43
–
–
ns
6,7
–
GSPI Output Data Hold Time
–
2.10
–
–
ns
6,7
–
GSPI Output Data Delay Time
–
–
–
7.27
ns
6,7
–
TEST LEVELS
NOTES
1. Production test at room temperature and nominal supply voltage with
guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with
guardbands for supply and temperature ranges using correlated test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1, 2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of similar
product.
9. Indirect test.
1. With 15pF load.
2. Serial Duty Cycle Distortion is defined here to be the
difference between the width of a ‘1’ bit, and the width of a
‘0’ bit.
3. See Device Power Up on page 41, Figure 3-13.
22209 - 7
February 2007
14 of 46
GS9062 Data Sheet
2.4 Solder Reflow Profiles
The device is manufactured with Matte-Sn terminations and is compatible with both
standard eutectic and Pb-free solder reflow profiles. The recommended standard
eutectic reflow profile is shown in Figure 2-1. MSL qualification was performed
using the maximum Pb-free reflow profile shown in Figure 2-2.
60-150 sec.
Temperature
10-20 sec.
230˚C
220˚C
3˚C/sec max
183˚C
6˚C/sec max
150˚C
100˚C
25˚C
Time
120 sec. max
6 min. max
Figure 2-1: Standard Eutectic Solder Reflow Profile
Temperature
60-150 sec.
20-40 sec.
260˚C
250˚C
3˚C/sec max
217˚C
6˚C/sec max
200˚C
150˚C
25˚C
Time
60-180 sec. max
8 min. max
Figure 2-2: Maximum Pb-free Solder Reflow Profile (Preferred)
22209 - 7
February 2007
15 of 46
GS9062 Data Sheet
2.5 Input/Output Circuits
All resistors in ohms, all capacitors in farads, unless otherwise shown.
SDO
SDO
Figure 2-3: Serial Digital Output
LF
CP_CAP
300
Figure 2-4: VCO Control Output & PLL Lock Time Capacitor
VDD
42K
63K
PCLK
Figure 2-5: PCLK Input
22209 - 7
February 2007
16 of 46
GS9062 Data Sheet
VCO
VDD
25
1.5K
5K
25
VCO
Figure 2-6: VCO Input
LB_CONT
865mV
7.2K
Figure 2-7: PLL Loop Bandwidth Control
22209 - 7
February 2007
17 of 46
IOPROC_DISABLE
EDH_FLAG
VIDEO_STANDARD
VIDEO_FORMAT_B
VIDEO_FORMAT_A
FF_LINE_END_F1
FF_LINE_START_F1
FF_LINE_END_F0
FF_LINE_START_F0
AP_LINE_END_F1
AP_LINE_START_F1
AP_LINE_END_F0
AP_LINE_START_F0
RASTER_STRUCTURE4
RASTER_STRUCTURE3
RASTER_STRUCTURE2
RASTER_STRUCTURE1
REGISTER NAME
LINE_352M_f2
LINE_352M_f1
ADDRESS
1Ch
1Bh
1Ah
19h
18h
17h
16h
15h
14h
13h
12h
11h
10h
0Fh
0Eh
0Dh
0Ch
0Bh
0Ah
09h
08h
07h
06h
05h
04h
03h
02h
01h
00h
Not Used
Not Used
Not Used
VF4-b7
VF2-b7
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
15
Not Used
Not Used
Not Used
ANC-IDA
VDS-b3
VF4-b5
VF2-b5
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
13
Not Used
Not Used
22209 - 7
Not Used
ANC-UES
VDS-b4
VF4-b6
VF2-b6
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
14
Not Used
Not Used
2.6 Host Interface Maps
Not Used
ANC-EDA
VDS-b1
VF4-b3
VF2-b3
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
b11
b11
11
Not Used
Not Used
February 2007
Not Used
ANC-IDH
VDS-b2
VF4-b4
VF2-b4
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
12
Not Used
Not Used
Not Used
ANC-EDH
VDS-b0
VF4-b2
VF2-b2
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
b10
b10
b10
b10
10
b10
b10
Not Used
FF-UES
INT_PROG
VF4-b1
VF2-b1
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
9
b9
b9
H_CONFIG
FF-IDA
STD_LOCK
VF4-b0
VF2-b0
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
8
b8
b8
Not Used
FF-IDH
Not Used
VF3-b7
VF1-b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
7
b7
b7
352M_INS
FF-EDA
Not Used
VF3-b6
VF1-b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
6
b6
b6
ILLEGAL_
REMAP
FF-EDH
Not Used
VF3-b5
VF1-b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
5
b5
b5
4
EDH_CRC_
INS
AP-UES
Not Used
VF3-b4
VF1-b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
3
AP-IDH
Not Used
VF3-b2
VF1-b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
2
b2
b2
ANC_CSUM_ Not Used
INS
AP-IDA
Not Used
VF3-b3
VF1-b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
Not Used
AP-EDA
Not Used
VF3-b1
VF1-b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
1
b1
b1
18 of 46
TRS_INS
AP-EDH
Not Used
VF3-b0
VF1-b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
0
b0
b0
GS9062 Data Sheet
VIDEO_STANDARD
RASTER_STRUCTURE4
RASTER_STRUCTURE3
RASTER_STRUCTURE2
RASTER_STRUCTURE1
REGISTER NAME
ADDRESS
1Ch
1Bh
1Ah
19h
18h
17h
16h
15h
14h
13h
12h
11h
10h
0Fh
0Eh
0Dh
0Ch
0Bh
0Ah
09h
08h
07h
06h
05h
04h
03h
02h
01h
00h
15
VDS-b3
13
22209 - 7
VDS-b4
14
VDS-b1
b11
b11
11
February 2007
VDS-b2
12
VDS-b0
b10
b10
b10
b10
10
2.6.1 Host Interface Map (Read only registers)
INT_PROG
b9
b9
b9
b9
9
STD_LOCK
b8
b8
b8
b8
8
b7
b7
b7
b7
7
b6
b6
b6
b6
6
b5
b5
b5
b5
5
b4
b4
b4
b4
4
b3
b3
b3
b3
3
b2
b2
b2
b2
2
b1
b1
b1
b1
1
19 of 46
b0
b0
b0
b0
0
GS9062 Data Sheet
IOPROC_DISABLE
EDH_FLAG
VIDEO_FORMAT_B
VIDEO_FORMAT_A
FF_LINE_END_F1
FF_LINE_START_F1
FF_LINE_END_F0
FF_LINE_START_F0
AP_LINE_END_F1
AP_LINE_START_F1
AP_LINE_END_F0
AP_LINE_START_F0
REGISTER NAME
LINE_352M_f2
LINE_352M_f1
ADDRESS
1Ch
1Bh
1Ah
19h
18h
17h
16h
15h
14h
13h
12h
11h
10h
0Fh
0Eh
0Dh
0Ch
0Bh
0Ah
09h
08h
07h
06h
05h
04h
03h
02h
01h
00h
VF4-b7
VF2-b7
15
ANC-IDA
VF4-b5
VF2-b5
13
22209 - 7
ANC-UES
VF4-b6
VF2-b6
14
ANC-EDA
VF4-b3
VF2-b3
11
February 2007
ANC-IDH
VF4-b4
VF2-b4
12
ANC-EDH
VF4-b2
VF2-b2
10
b10
b10
FF-UES
VF4-b1
VF2-b1
b9
b9
b9
b9
b9
b9
b9
b9
9
b9
b9
2.6.2 Host Interface Map (R/W configurable registers)
H_CONFIG
FF-IDA
VF4-b0
VF2-b0
b8
b8
b8
b8
b8
b8
b8
b8
8
b8
b8
FF-IDH
VF3-b7
VF1-b7
b7
b7
b7
b7
b7
b7
b7
b7
7
b7
b7
352M_INS
FF-EDA
VF3-b6
VF1-b6
b6
b6
b6
b6
b6
b6
b6
b6
6
b6
b6
ILLEGAL_
REMAP
FF-EDH
VF3-b5
VF1-b5
b5
b5
b5
b5
b5
b5
b5
b5
5
b5
b5
EDH_CRC_
INS
AP-UES
VF3-b4
VF1-b4
b4
b4
b4
b4
b4
b4
b4
b4
4
b4
b4
ANC_
CSUM_INS
AP-IDA
VF3-b3
VF1-b3
b3
b3
b3
b3
b3
b3
b3
b3
3
b3
b3
AP-IDH
VF3-b2
VF1-b2
b2
b2
b2
b2
b2
b2
b2
b2
2
b2
b2
AP-EDA
VF3-b1
VF1-b1
b1
b1
b1
b1
b1
b1
b1
b1
1
b1
b1
20 of 46
TRS_INS
AP-EDH
VF3-b0
VF1-b0
b0
b0
b0
b0
b0
b0
b0
b0
0
b0
b0
GS9062 Data Sheet
GS9062 Data Sheet
3. Detailed Description
3.1 Functional Overview
The GS9062 is a dual-standard serializer with an integrated cable driver. When
used in conjunction with the external GO1555/GO1525* Voltage Controlled
Oscillator, a transmit solution at 270Mb/s is realized.
The device has three different modes of operation which must be set by the
application layer through external device pins.
When SMPTE mode is enabled, the device will accept 10-bit multiplexed or 20-bit
demultiplexed SMPTE compliant data. The device’s additional processing features
are also enabled in this mode.
In DVB-ASI mode, the GS9062 will accept an 8-bit parallel DVB-ASI compliant
transport stream on its upper input bus. The serial output data stream will be
8b/10b encoded and stuffed.
The GS9062’s third mode allows for the serializing of data not conforming to
SMPTE or DVB-ASI streams.
The provided serial digital outputs feature a high impedance mode, output mute on
loss of parallel clock and adjustable signal swing.
In the digital signal processing core, several data processing functions are
implemented including SMPTE 352M and EDH data packet generation and
insertion, and automatic video standards detection. These features are all enabled
by default, but may be individually disabled via internal registers accessible
through the GSPI host interface.
Finally, the GS9062 contains a JTAG interface for boundary scan test
implementations.
*For new designs use GO1555
3.2 Parallel Data Inputs
Data inputs enter the device on the rising edge of PCLK as shown in Figure 3-1.
The input data format is defined by the setting of the external SMPTE_BYPASS
and DVB_ASI pins and may be presented in 10-bit or 20-bit format. The input data
bus width is controlled independently from the internal data bus width by the
20bit/10bit input pin.
22209 - 7
February 2007
21 of 46
GS9062 Data Sheet
PCLK
DIN[19:0]
DATA
Control signal
input
tIS
tIH
Figure 3-1: PCLK to Data Timing
3.2.1 Parallel Input in SMPTE Mode
When the device is operating in SMPTE mode, SMPTE Mode on page 23, data
may be presented to the input bus in either multiplexed or demultiplexed form
depending on the setting of the 20bit/10bit input pin.
In 20-bit mode, (20bit/10bit = HIGH), the input data format should be word aligned,
demultiplexed luma and chroma data. Luma words should be presented to
DIN[19:10] while chroma words should occupy DIN[9:0].
In 10-bit mode, (20bit/10bit = LOW), the input data format should be word aligned,
multiplexed luma and chroma data. The data should be presented to DIN[19:10].
DIN[9:0] will be high impedance in this mode.
3.2.2 Parallel Input in DVB-ASI Mode
When operating in DVB-ASI mode, DVB-ASI Mode on page 25, the GS9062
automatically configures the input port for 10-bit operation regardless of the setting
of the 20bit/10bit pin.
The device will accept 8-bit data words on DIN[17:10] such that DIN17 = HIN is the
most significant bit of the encoded transport stream data and DIN10 = AIN is the
least significant bit.
In addition, DIN19 and DIN18 will be configured as the DVB-ASI control signals
INSSYNCIN and KIN respectively. See DVB-ASI Mode on page 25 for a
description of these DVB-ASI specific input signals.
DIN[9:0] will be high impedance when the GS9062 is operating in DVB-ASI mode.
3.2.3 Parallel Input in Data-Through Mode
When operating in Data-Through mode, Data-Through Mode on page 26, the
GS9062 passes data presented to the parallel input bus to the serial output without
performing any encoding or scrambling.
The input data bus width accepted by the device in this mode is controlled by the
setting of the 20bit/10bit pin.
22209 - 7
February 2007
22 of 46
GS9062 Data Sheet
3.2.4 Parallel Input Clock (PCLK)
The frequency of the PCLK input signal required by the GS9062 is determined by
the input data format. Table 3-1 below lists the possible input signal formats and
their corresponding parallel clock rates. Note that DVB-ASI input will always be in
10-bit format, regardless of the setting of the 20bit/10bit pin.
Table 3-1: Parallel Data Input Format
Input Data Format
DOUT
[19:10]
DOUT
[9:0]
PCLK
LUMA
CHROMA
LUMA / CHROMA
Control Signals
20bit/10bit
SMPTE_BYPASS
DVB_ASI
13.5MHz
HIGH
HIGH
LOW
HIGH IMPEDANCE
27MHz
LOW
HIGH
LOW
DVB-ASI DATA
HIGH IMPEDANCE
27MHz
HIGH
LOW
HIGH
DVB-ASI DATA
HIGH IMPEDANCE
27MHz
LOW
LOW
HIGH
20bit DEMULTIPLEXED
DATA
DATA
13.5MHz
HIGH
LOW
LOW
10bit MULTIPLEXED
DATA
HIGH IMPEDANCE
27MHz
LOW
LOW
LOW
SMPTE MODE
20bit DEMULTIPLEXED
10bit MULTIPLEXED
DVB-ASI MODE
10bit DVB-ASI
DATA-THROUGH MODE
3.3 SMPTE Mode
The GS9062 is said to be in SMPTE mode when the SMPTE_BYPASS pin is set
HIGH and the DVB_ASI pin is set LOW.
In this mode, the parallel data will be scrambled according to SMPTE 259M, and
NRZ-to-NRZI encoded prior to serialization.
3.3.1 Internal Flywheel
The GS9062 has an internal flywheel which is used in the generation of internal /
external timing signals, and in automatic video standards detection. It is
operational in SMPTE mode only.
The flywheel consists of a number of counters and comparators operating at video
pixel and video line rates. These counters maintain information about the total line
length, active line length, total number of lines per field / frame and total active lines
per field / frame for the received video standard.
When DETECT_TRS is LOW, the flywheel will be locked to the externally supplied
H, V, and F timing signals.
22209 - 7
February 2007
23 of 46
GS9062 Data Sheet
When DETECT_TRS is HIGH, the flywheel will be locked to the embedded TRS
signals in the parallel input data. Both 8-bit and 10-bit TRS code words will be
identified by the device.
The flywheel 'learns' the video standard by timing the horizontal and vertical
reference information supplied a the H, V, and F input pins, or contained in the TRS
ID words of the received video data. Full synchronization of the flywheel to the
received video standard therefore requires one complete video frame.
Once synchronization has been achieved, the flywheel will continue to monitor the
received TRS timing or the supplied H, V, and F timing information to maintain
synchronization.
3.3.2 HVF Timing Signal Extraction
As discussed above, the GS9062's internal flywheel may be locked to externally
provided H, V, and F signals when DETECT_TRS is set LOW by the application
layer.
The H signal timing should also be configured via the H_CONFIG bit of the internal
IOPROC_DISABLE register as either active line based blanking or TRS based
blanking, Packet Generation and Insertion on page 28.
Active line based blanking is enabled when the H_CONFIG bit is set LOW. In this
mode, the H input should be HIGH for the entire horizontal blanking period,
including the EAV and SAV TRS words. This is the default H timing assumed by
the device.
When H_CONFIG is set HIGH, TRS based blanking is enabled. In this case, the H
input should be set HIGH for the entire horizontal blanking period as indicated by
the H bit in the associated TRS words.
The timing of these signals is shown in Figure 3-2.
PCLK
CHROMA DATA OUT
3FF
000
3FF
000
LUMA DATA OUT
000
XYZ
(eav)
000
XYZ
(SAV)
H
V
H SIGNAL TIMING:
H_CONFIG = LOW
F
H_CONFIG = HIGH
H:V:F TIMING – 20-BIT INPUT MODE
PCLK
MULTIPLEXED
Y/Cr/Cb DATA OUT
3FF
000
000
XYZ
(eav)
3FF
000
000
XYZ
(sav)
H
V
F
H:V:F TIMING – 10-BIT INPUT MODE
Figure 3-2: H, V, F Timing
22209 - 7
February 2007
24 of 46
GS9062 Data Sheet
3.4 DVB-ASI Mode
The GS9062 is said to be in DVB-ASI mode when the SMPTE_BYPASS pin is set
LOW and the DVB_ASI pin is set HIGH.
In this mode, all SMPTE processing functions are disabled, and the 8-bit transport
stream data will be 8b/10b encoded prior to serialization.
3.4.1 Control Signal Inputs
In DVB-ASI mode, the DIN19 and DIN18 pins will be configured as DVB-ASI
control signals INSSYNCIN and KIN respectively.
When INSSYNCIN is set HIGH, the device will insert K28.5 sync characters into
the data stream. This function is used to assist system implementations where the
GS9062 may be preceded by an external data FIFO. Parallel DVB-ASI data may
be clocked into the FIFO at some rate less than 27MHz. The INSSYNCIN input
may then be connected to the FIFO empty signal, thus providing a means of
padding up the data transmission rate to 27MHz. See Figure 3-3.
NOTE: 8b/10b encoding will take place after K28.5 sync character insertion.
KIN should be set HIGH whenever the parallel data input is to be interpreted as any
special character defined by the DVB-ASI standard (including the K28.5 sync
character). This pin should be set LOW when the input is to be interpreted as data.
NOTE: When operating in DVB-ASI mode, DIN[9:0] become high impedance.
AIN ~ HIN
SDO
TS
8
8
FIFO
GS9062
KIN
KIN
WRITE_CLK
<27MHz
READ CLK
=27MHz
SDO
CLK_IN
FE
INSSYNCIN
CLK_OUT
PCLK = 27MHz
Figure 3-3: DVB-ASI FIFO Implementation using the GS9062
22209 - 7
February 2007
25 of 46
GS9062 Data Sheet
3.5 Data-Through Mode
The GS9062 may be configured by the application layer to operate as a simple
parallel-to-serial converter. In this mode, the device presents data to the output
buffer without performing any scrambling or encoding.
Data-through mode is enabled only when both the SMPTE_BYPASS and
DVB_ASI pins are set LOW.
3.6 Additional Processing Functions
The GS9062 contains an additional data processing block which is available in
SMPTE mode only, SMPTE Mode on page 23.
3.6.1 Input Data Blank
The video input data may be 'blanked' by the GS9062. In this mode, all input video
data except TRS words are set to the appropriate blanking levels by the device.
Both the horizontal and vertical ancillary data spaces will also be set to blanking
levels.
This function is enabled by setting the BLANK pin LOW.
3.6.2 Automatic Video Standard Detection
The GS9062 can detect the input video standard by using the timing parameters
extracted from the received TRS ID words or supplied H, V, and F timing signals
Internal Flywheel on page 23. This information is presented to the host interface
via the VIDEO_STANDARD register (Table 3-2).
Total samples per line, active samples per line, total lines per field/frame and active
lines per field/frame are also calculated and presented to the host interface via the
RASTER_STRUCTURE registers (Table 3-3). These line and sample count
registers are updated once per frame at the end of line 12. This is in addition to the
information contained in the VIDEO_STANDARD register.
After device reset, the four RASTER_STRUCTURE registers default to zero.
Table 3-2: Host Interface Description for Video Standard Register
Register Name
Bit
Name
VIDEO_STANDARD
Address: 04h
15
Not Used
14–10
VD_STD[4:0]
9
Not Used
8
STD_LOCK
7–0
Description
R/W
Default
Video Data Standard (see Table 3-4)
R
0
Standard Lock: Set HIGH when flywheel has
achieved full synchronization.
R
0
Not Used
22209 - 7
February 2007
26 of 46
GS9062 Data Sheet
Table 3-3: Host Interface Description for Raster Structure Registers
Register Name
Bit
Name
Description
RASTER_STRUCTURE1
Address: 0Eh
15-12
RASTER_STRUCTURE2
Address: 0Fh
15-12
11-0
RASTER_STRUCTURE_2[11:0]
RASTER_STRUCTURE3
Address: 10h
15-11
Not Used
10-0
RASTER_STRUCTURE_3[10:0]
RASTER_STRUCTURE4
Address: 11h
15-11
Not Used
10-0
RASTER_STRUCTURE_4[10:0]
R/W
Default
Words Per Active Line
R
0
Words Per Total Line.
R
0
Total Lines Per Frame
R
0
Active Lines Per Field
R
0
Not Used
11-0
RASTER_STRUCTURE_1[11:0]
Not Used
3.6.2.1 Video Standard Indication
The video standard codes reported in the VD_STD[4:0] bits of the
VIDEO_STANDARD register represent the SMPTE standards as shown in
Table 3-4.
In addition to the 5-bit video standard code word, the VIDEO_STANDARD register
also contains an additional status bit. The STD_LOCK bit will be set HIGH
whenever the flywheel has achieved full synchronization.
The VD_STD[4:0] and STD_LOCK bits of the VIDEO_STANDARD register will
default to zero after device reset. The VD_STD[4:0] bits will also default to zero if
the SMPTE_BYPASS pin is asserted LOW or if the LOCKED output is LOW. The
STD_LOCK bit will retain its previous value if the PCLK is removed.
Table 3-4: Supported Video Standards
VD_STD[4:0]
SMPTE
Standard
16h
125M
Video Format
Length of
HANC
Length of
Active Video
Total
Samples
SMPTE352M
Lines
268
1440
1716
3, 276
268
1440
1716
3, 276
1440x487/60 (2:1)
(Or dual link progressive)
17h
125M
1440x507/60 (2:1)
19h
125M
525-line 487 generic
–
–
1716
3, 276
1Bh
125M
525-line 507 generic
–
–
1716
3, 276
18h
ITU-R BT.656
1440x576/50 (2:1)
280
1440
1728
9, 322
(Or dual link progressive)
1Ah
ITU-R BT.656
625-line generic (EM)
–
–
1728
9, 322
1Eh
Unknown SD
–
–
–
–
–
00h-15h,
Reserved
1Ch, 1Fh
22209 - 7
February 2007
27 of 46
GS9062 Data Sheet
3.6.3 Packet Generation and Insertion
In addition to input data blanking and automatic video standards detection, the
GS9062 may also calculate, assemble and insert into the data stream various
types of ancillary data packets and TRS ID words.
These features are only available when the device is set to operated in SMPTE
mode and the IOPROC_EN/DIS pin is set HIGH. Individual insertion features may
be enabled or disabled via the IOPROC_DISABLE register (Table 3-5).
All of the IOPROC_DISABLE register bits default to '0' after device reset, enabling
all of the processing features. To disable any individual error correction feature, the
host interface must set the corresponding bit HIGH in this register.
Table 3-5: Host Interface Description for Internal Processing Disable Register
Register Name
Bit
Name
IOPROC_DISABLE
Address: 00h
15-9
Not Used
Description
R/W
Default
Horizontal sync timing input configuration. Set LOW when
the H input timing is based on active line blanking (default).
Set HIGH when the H input timing is based on the H bit of
the TRS words. See Figure 3-2.
R/W
0
8
H_CONFIG
7
Not Used
6
352M_INS
SMPTE352M packet insertion. The IOPROC_EN/DIS pin
and SMPTE_BYPASS pin must also be set HIGH. Set HIGH
to disable.
R/W
0
5
ILLEGAL_REMAP
Illegal Code Remapping. Detection and correction of illegal
code words within the active picture area (AP). The
IOPROC_EN/DIS pin and SMPTE_BYPASS pin must also
be set HIGH. Set HIGH to disable.
R/W
0
4
EDH_CRC_INS
Error Detection & Handling (EDH) Cyclical Redundancy
Check (CRC) error correction. The IOPROC_EN/DIS pin
and SMPTE_BYPASS pin must also be set HIGH. Set HIGH
to disable.
R/W
0
3
ANC_CSUM_INS
Ancillary Data Checksum insertion. The IOPROC_EN/DIS
pin and SMPTE_BYPASS pin must also be set HIGH. Set
HIGH to disable.
R/W
0
Timing Reference Signal Insertion. Occurs only when
IOPROC_EN/DIS is HIGH and SMPTE_BYPASS is HIGH.
Set HIGH to disable.
R/W
0
2-1
Not Used
0
TRS_INS
22209 - 7
February 2007
28 of 46
GS9062 Data Sheet
3.6.3.1 SMPTE 352M Payload Identifier Insertion
The GS9062 can generate and insert SMPTE 352M payload identifier ancillary
data packets into the data stream, based on information programmed into the host
interface.
When this feature is enabled, the device will automatically generate the ancillary
data preambles, (DID, SDID, DBN, DC), and calculate the checksum. The SMPTE
352M packet will be inserted into the data stream according to the line number and
sample position rules defined in the standard. Where an alternate insertion line is
required, the host interface may program the LINE_352M registers (Table 3-6) with
the appropriate line numbers.
The insertion process will only take place if one or more of the four
VIDEO_FORMAT registers (Table 3-7) have been programmed with non-zero
values. In addition, the GS9062 requires the 352M_INS bit of the
IOPROC_DISABLE register be set LOW.
NOTE 1: For the purpose of determining the line and pixel position for insertion, the
GS9062 will differentiate between PsF and interlaced formats by interrogating bits
14 and 15 of the VIDEO_FORMAT_A register.
The packets will be inserted immediately after the EAV word.
NOTE 2: It is the responsibility of the user to ensure that there is sufficient space
in the horizontal blanking interval for the insertion of the SMPTE 352M packets.
If there are other ancillary data packets present, the SMPTE 352M packet will be
inserted in the first available location in the horizontal ancillary space. Ancillary
data must be adjacent to the EAV.
3.6.3.2 Illegal Code Remapping
If the ILLEGAL_REMAP bit of the IOPROC_DISABLE register is set LOW, the
GS9062 will remap all codes within the active picture between the values of 3FCh
and 3FFh to 3FBh. All codes within the active picture area between the values of
000h and 003h will be remapped to 004h.
In addition, 8-bit TRS and ancillary data preambles will be remapped to 10-bit
values if this feature is enabled.
22209 - 7
February 2007
29 of 46
GS9062 Data Sheet
Table 3-6: Host Interface Description for SMPTE 352M Packet Line Number Insertion Registers
Register Name
Bit
Name
Description
LINE_352M_f1
Address: 1Bh
15-11
Not Used
10-0
LINE_0_352M[10:0]
LINE_352M_f2
Address: 1Ch
15-11
Not Used
10-0
LINE_1_352M[10:0]
R/W
Default
Line number where SMPTE352M packet is
inserted in field 1. This line number overrides
the standard line number. If set to zero, the
standard line number is used.
R/W
0
Line number where SMPTE352M packet is
inserted in field 2. This line number overrides
the standard line number. If set to zero, the
standard line number is used.
R/W
0
R/W
Default
Table 3-7: Host Interface Description for SMPTE 352M Payload Identifier Registers
Register Name
Bit
Name
Description
VIDEO_FORMAT_B
Address: 0Bh
15-8
SMPTE352M
SMPTE 352M Byte 4 information must be
programmed in this register when 352M_INS =
LOW.
R/W
0
SMPTE 352M Byte 3 information must be
programmed in this register when 352M_INS =
LOW.
R/W
0
SMPTE 352M Byte 2 information must be
programmed in this register when 352M_INS =
LOW.
R/W
0
SMPTE 352M Byte 1 information must be
programmed in this register when 352M_INS =
LOW.
R/W
0
Byte 4
7-0
SMPTE352M
Byte 3
VIDEO_FORMAT_A
Address: 0Ah
15-8
SMPTE352M
Byte 2
7-0
SMPTE 352M
Byte 1
22209 - 7
February 2007
30 of 46
GS9062 Data Sheet
3.6.3.3 EDH Generation and Insertion
The GS9062 will generate and insert complete EDH packets into the data stream.
Packet generation and insertion will only take place if the EDH_CRC_INS bit of the
IOPROC_DISABLE register is set LOW.
The GS9062 will generate all of the required EDH packet data including all ancillary
data preambles, (DID, DBN, DC), reserved code words and checksum. Calculation
of both full field (FF) and active picture (AP) CRC's will be carried out by the device.
SMPTE RP165 specifies the calculation ranges and scope of EDH data for
standard 525 and 625 component digital interfaces. The GS9062 will utilize these
standard ranges by default.
If the received video format does not correspond to 525 or 625 digital component
video standards as determined by the flywheel pixel and line counters, then one of
two schemes for determining the EDH calculation ranges will be employed:
1. Ranges will be based on the line and pixel ranges programmed by the host
interface; or
2. In the absence of user-programmed calculation ranges, ranges will be
determined from the received TRS ID words or supplied H, V, and F timing
signals Internal Flywheel on page 23.
The registers available to the host interface for programming EDH calculation
ranges include active picture and full field line start and end positions for both
fields. Table 3-8 shows the relevant registers, which default to '0' after device reset.
If any or all of these register values are zero, then the EDH CRC calculation ranges
will be determined from the flywheel generated H signal. The first active and full
field pixel will always be the first pixel after the SAV TRS code word. The last active
and full field pixel will always be the last pixel before the start of the EAV TRS code
words.
EDH error flags (EDH, EDA, IDH, IDA and UES) for ancillary data, full field and
active picture will also be inserted. These flags must be programmed into the
EDH_FLAG registers of the device by the application layer (Table 3-9).
NOTE 1: It is the responsibility of the user to ensure that the EDH flag registers are
updated once per field.
The prepared EDH packet will be inserted at the appropriate line of the video
stream according to RP165. The start pixel position of the inserted packet will be
based on the SAV position of that line such that the last byte of the EDH packet
(the checksum) will be placed in the sample immediately preceding the start of the
SAV TRS word.
NOTE 2: It is also the responsibility of the user to ensure that there is sufficient
space in the horizontal blanking interval for the EDH packet to be inserted.
22209 - 7
February 2007
31 of 46
GS9062 Data Sheet
Table 3-8: Host Interface Description for EDH Calculation Range Registers
Register Name
Bit
AP_LINE_START_F0
Address: 12h
15-10
AP_LINE_END_F0
Address: 13h
15-10
AP_LINE_START_F1
Address: 14h
15-10
AP_LINE_END_F1
Address: 15h
15-10
FF_LINE_START_F0
Address: 16h
15-10
FF_LINE_END_F0
Address: 17h
15-10
FF_LINE_START_F1
Address: 18h
15-10
FF_LINE_END_F1
Address: 19h
15-10
9-0
9-0
9-0
9-0
9-0
9-0
9-0
9-0
Name
Description
R/W
Default
Field 0 Active Picture start line data used to
set EDH calculation range outside of RP 165
values.
R/W
0
Field 0 Active Picture end line data used to
set EDH calculation range outside of RP 165
values.
R/W
0
Field 1 Active Picture start line data used to
set EDH calculation range outside of RP 165
values.
R/W
0
Field 1 Active Picture end line data used to
set EDH calculation range outside of RP 165
values.
R/W
0
Field 0 Full Field start line data used to set
EDH calculation range outside of RP 165
values.
R/W
0
Field 0 Full Field end line data used to set
EDH calculation range outside of RP 165
values.
R/W
0
Field 1 Full Field start line data used to set
EDH calculation range outside of RP-165
values.
R/W
0
Field 1 Full Field end line data used to set
EDH calculation range outside of RP-165
values.
R/W
0
Not Used
AP_LINE_START_F0[9:0]
Not Used
AP_LINE_END_F0[9:0]
Not Used
AP_LINE_START_F1[9:0]
Not Used
AP_LINE_END_F1[9:0]
Not Used
FF_LINE_START_F0[9:0]
Not Used
FF_LINE_END_F0[9:0]
Not Used
FF_LINE_START_F1[9:0]
Not Used
FF_LINE_END_F1[9:0]
22209 - 7
February 2007
32 of 46
GS9062 Data Sheet
Table 3-9: Host Interface Description for EDH Flag Register
Register Name
Bit
Name
EDH_FLAG
Address: 02h
15
Not Used
14
ANC-UES
13
Description
R/W
Default
Ancillary Unknown Error Status flag will be generated and inserted
when IOPROC_EN/DIS and SMPTE_BYPASS pins are HIGH and
EDH_CRC_INS bit is LOW.
R/W
0
ANC-IDA
Ancillary Internal device error Detected Already flag will be
generated and inserted when IOPROC_EN/DIS and
SMPTE_BYPASS pins are HIGH and EDH_CRC_INS bit is LOW.
R/W
0
12
ANC-IDH
Ancillary Internal device error Detected Here flag will be generated
and inserted when IOPROC_EN/DIS and SMPTE_BYPASS pins
are HIGH and EDH_CRC_INS bit is LOW.
R/W
0
11
ANC-EDA
Ancillary Error Detected Already flag will be generated and
inserted when IOPROC_EN/DIS and SMPTE_BYPASS pins are
HIGH and EDH_CRC_INS bit is LOW.
R/W
0
10
ANC-EDH
Ancillary Error Detected Here flag will be generated and inserted
when IOPROC_EN/DIS and SMPTE_BYPASS pins are HIGH and
EDH_CRC_INS bit is LOW.
R/W
0
9
FF-UES
Full Field Unknown Error flag will be generated and inserted when
IOPROC_EN/DIS and SMPTE_BYPASS pins are HIGH and
EDH_CRC_INS bit is LOW.
R/W
0
8
FF-IDA
Full Field Internal device error Detected Already flag will be
generated and inserted when IOPROC_EN/DIS and
SMPTE_BYPASS pins are HIGH and EDH_CRC_INS bit is LOW.
R/W
0
7
FF-IDH
Full Field Internal device error Detected flag will be generated and
inserted when IOPROC_EN/DIS and SMPTE_BYPASS pins are
HIGH and EDH_CRC_INS bit is LOW.
R/W
0
6
FF-EDA
Full Field Error Detected Already flag will be generated and
inserted when IOPROC_EN/DIS and SMPTE_BYPASS pins are
HIGH and EDH_CRC_INS bit is LOW.
R/W
0
5
FF-EDH
Full Field Error Detected Here flag will be generated and inserted
when IOPROC_EN/DIS and SMPTE_BYPASS pins are HIGH and
EDH_CRC_INS bit is LOW.
R/W
0
4
AP-UES
Active Picture Unknown Error Status flag will be generated and
inserted when IOPROC_EN/DIS and SMPTE_BYPASS pins are
HIGH and EDH_CRC_INS bit is LOW.
R/W
0
3
AP-IDA
Active Picture Internal device error Detected Already flag will be
generated and inserted when IOPROC_EN/DIS and
SMPTE_BYPASS pins are HIGH and EDH_CRC_INS bit is LOW.
R/W
0
22209 - 7
February 2007
33 of 46
GS9062 Data Sheet
Table 3-9: Host Interface Description for EDH Flag Register (Continued)
Register Name
Bit
Name
Description
R/W
Default
2
AP-IDH
Active Picture Internal device error Detected Here flag will be
generated and inserted when IOPROC_EN/DIS and
SMPTE_BYPASS pins are HIGH and EDH_CRC_INS bit is LOW.
R/W
0
1
AP-EDA
Active Picture Error Detected Already flag will be generated and
inserted when IOPROC_EN/DIS and SMPTE_BYPASS pins are
HIGH and EDH_CRC_INS bit is LOW.
R/W
0
0
AP-EDH
Active Picture Error Detected Here flag will be generated and
inserted when IOPROC_EN/DIS and SMPTE_BYPASS pins are
HIGH and EDH_CRC_INS bit is LOW.
R/W
0
3.6.3.4 Ancillary Data Checksum Generation and Insertion
The GS9062 will calculate checksums for all detected ancillary data packets
presented to the device. These calculated checksum values are inserted into the
data stream prior to serialization.
Ancillary data checksum generation and insertion will only take place if the
ANC_CSUM_INS bit of the IOPROC_DISABLE register is set LOW.
3.6.3.5 TRS Generation and Insertion
The GS9062 can generate and insert 10-bit TRS code words into the data stream
as required. This feature is enabled by setting the TRS_INS bit of the
IOPROC_DISABLE register LOW.
TRS word generation will be performed in accordance with the timing parameters
generated by the flywheel which will be locked either to the received TRS ID words
or the supplied H, V, and F timing signals Internal Flywheel on page 23.
3.7 Parallel-To-Serial Conversion
The parallel data output of the internal data processing blocks is fed to the
parallel-to-serial converter. The function of this block is to generate a serial data
stream from the 10-bit or 20-bit parallel data words and pass the stream to the
integrated cable driver.
22209 - 7
February 2007
34 of 46
GS9062 Data Sheet
3.8 Serial Digital Data PLL
To obtain a clean clock signal for serialization and transmission, the input PCLK is
locked to an external reference signal via the GS9062's integrated phase-locked
loop. This PLL is also responsible for generating all internal clock signals required
by the device.
Internal division ratios for the locked PCLK are determined by the setting of the
20bit/10bit pin as shown in Table 3-10.
Table 3-10: Serial Digital Output Rates
20bit/10bit
Supplied PCLK Rate
Serial Digital
Output Rate
HIGH
13.5MHz
270Mb/s
LOW
27MHz
270Mb/s
3.8.1 External VCO
The GS9062 requires the GO1555/GO1525* external voltage controlled oscillator
as part of its internal PLL.
Power for the external VCO is generated entirely by the GS9062 from an integrated
voltage regulator. The internal regulator uses +3.3V supplied on the CP_VDD /
CP_GND pins to provide +2.5V on the VCO_VCC / VCO_GND pins.
The external VCO produces a reference signal for the PLL, input on the VCO pin
of the device. Both reference and control signals should be referenced to the
supplied VCO_GND as shown in the recommended application circuit of Typical
Application Circuit on page 42.
*For new designs use GO1555
3.8.2 Lock Detect Output
The lock detect block controls the serial digital output signal and indicates to the
application layer the lock status of the device via the LOCKED output pin.
LOCKED will be asserted HIGH if and only if the internal data PLL has locked the
PCLK signal to the external VCO reference signal and one of the following is true:
1. The device is set to operate in SMPTE mode and has detected SMPTE TRS
words in the serial stream; or
2. The device is set to operate in DVB-ASI mode and has detected K28.5 sync
characters in the serial stream; or
3. The device is set to operate in Data-Through mode.
22209 - 7
February 2007
35 of 46
GS9062 Data Sheet
3.8.3 Loop Bandwidth Adjustment
For new designs the GO1555 is recommended for use with the GS9062. The
recommended application ciruit can be seen in Section 4.1 Typical Application
Circuit.
Designs using the GO1525 VCO use different loop bandwidth components. The
application circuit is shown in Figure 3-4.
NOTE: When using the GS9062 with the GS4911B clock generator a narrower
loop bandwidth for the GS9062 serializer should be used. For more details please
refer to section 2.5 of the GS4911B Reference Design.
NC
2
1
O/P
GND
8
VCO_VCC
10n
1u
VCC
GND
VCTR
5
GND_VCO
GO1525
VCO_VCC
GND_VCO
10n
GND_VCO
7
GND
6
4
GND
3
GND_VCO
GND_VCO
10n
GND_VCO
2n2
0
GND_VCO
VCO_VCC
R2
D o n o t p o p u l a t e R2
100n
LOCK
GND_VCO
0
GND_A
10n
1u
1u
10n
0
CP_GND
LB_CONT
CP_CAP
LF
VCO_VCC
VCO_GND
VCO
VCO
LOCKED
80
79
78
77
76
75
74
73
72
+3.3V
GND_A
+1.8V_A
10n
1
2
3
4
CP_VDD
PD_GND
PD_VDD
GS9062
Figure 3-4: Typical Application Circuit using GO1525
3.9 Serial Digital Output
The GS9062 contains an integrated current mode differential serial digital cable
driver.
To enable this output, SDO_EN/DIS must be set HIGH by the application layer.
Setting the SDO_EN/DIS signal LOW will cause the SDO and SDO output pins to
become high impedance, resulting in reduced device power consumption.
With suitable external return loss matching circuitry, the GS9062's serial digital
outputs will provide a minimum output return loss of -15dB at 270Mb/s.
The integrated cable driver uses a separate power supply of +1.8V DC supplied via
the CD_VDD and CD_GND pins.
22209 - 7
February 2007
36 of 46
GS9062 Data Sheet
3.9.1 Output Swing
Nominally, the voltage swing of the serial digital output is 800mVp-p single-ended
into a 75Ω load. This is set externally by connecting the RSET pin to CD_VDD
through 281Ω .
The output swing may be decreased by increasing the value of the RSET resistor.
The relationship is approximated by the curve shown in Figure 3-5.
Alternatively, the serial digital output swing can drive 800mVp-p into a 50Ω load.
Since the output swing is reduced by a factor of approximately one third when the
smaller load is used, the RSET resistor must be 187Ω to obtain 800mVp-p.
1000
∆VSDO(mVp-p)
900
800
700
600
75Ω load
500
50Ω load
400
300
200 250 300 350 400 450 500 550 600 650 700
RSET(Ω)
Figure 3-5: Serial Digital Output Swing
3.9.2 Serial Digital Output Mute
The GS9062 will automatically mute the serial digital output when the LOCKED
output signal is LOW. In this case, the SDO and SDO signals are set to a constant
voltage level.
3.10 GSPI Host Interface
The GSPI, or Gennum Serial Peripheral Interface, is a 4-wire interface provided to
allow the host to enable additional features of the device and /or to provide
additional status information through configuration registers in the GS9062.
The GSPI comprises a serial data input signal SDIN, serial data output signal
SDOUT, an active low chip select CS, and a burst clock SCLK. The burst clock
must have a duty cycle between 40% and 60%.
Because these pins are shared with the JTAG interface port, an additional control
signal pin JTAG/HOST is provided. When JTAG/HOST is LOW, the GSPI interface
is enabled.
When operating in GSPI mode, the SCLK, SDIN, and CS signals are provided by
the host interface. The SDOUT pin is a high-impedance output allowing multiple
22209 - 7
February 2007
37 of 46
GS9062 Data Sheet
devices to be connected in parallel and selected via the CS input. The interface is
illustrated in the Figure 3-6 below.
All read or write access to the GS9062 is initiated and terminated by the host
processor. Each access always begins with a 16-bit command word on SDIN
indicating the address of the register of interest. This is followed by a 16-bit data
word on SDIN in write mode, or a 16-bit data word on SDOUT in read mode.
Application Host
GS9062
SCLK
SCLK
SDOUT
SDIN
CS
CS
SDOUT
SDIN
Figure 3-6: Gennum Serial Peripheral Interface (GSPI)
3.10.1 Command Word Description
The command word is transmitted MSB first and contains a read/write bit, nine
reserved bits and a 6-bit register address. Set R/W = '1' to read and R/W = '0' to
write from the GSPI.
Command words are clocked into the GS9062 on the rising edge of the serial clock
SCLK. The appropriate chip select signal, CS, must be asserted low a minimum of
1.5ns (t0 in Figure 3-9 and Figure 3-10) before the first clock edge to ensure proper
operation.
Each command word must be followed by only one data word to ensure proper
operation.
MSB
LSB
R/W
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Figure 3-7: Command Word
MSB
D15
LSB
D14
D13
D12
D11
D10
D9
D8
Figure 3-8: Data Word
22209 - 7
February 2007
38 of 46
GS9062 Data Sheet
3.10.2 Data Read and Write Timing
Read and write mode timing for the GSPI interface is shown in Figure 3-9 and
Figure 3-10 respectively. The maximum SCLK frequency allowed is 6.6MHz.
When writing to the registers via the GSPI, the MSB of the data word may be
presented to SDIN immediately following the falling edge of the LSB of the
command word. All SDIN data is sampled on the rising edge of SCLK.
When reading from the registers via the GSPI, the MSB of the data word will be
available on SDOUT 12ns (t5 in Figure 3-9) following the falling edge of the LSB of
the command word, and thus may be read by the host on the very next rising edge
of the clock. The remaining bits are clocked out by the GS9062 on the negative
edges of SCLK.
duty
cycle
t2
t0
t4
t5
period
SCLK
CS
t3
input data
setup time
RSV
RSV
t6
SDIN
R/W
RSV
RSV
RSV
RSV
RSV
RSV
RSV
A4
A5
A3
A2
A1
output data
hold time
A0
SDOUT
D15
D14
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D13
Figure 3-9: GSPI Read Mode Timing
t2
t0
duty
cycle
t4
period
SCLK
CS
SDIN
R/W
RSV
RSV
RSV
RSV
t3
input data
setup time
RSV
RSV
RSV
RSV
RSV
A5
A4
A3
A2
A1
A0
D15
D14
D13
Figure 3-10: GSPI Write Mode Timing
3.10.3 Configuration and Status Registers
Table 3-11 summarizes the GS9062's internal status and configuration registers.
All of these registers are available to the host via the GSPI and are all individually
addressable.
Where status registers contain less than the full 16 bits of information however, two
or more registers may be combined at a single logical address.
22209 - 7
February 2007
39 of 46
GS9062 Data Sheet
Table 3-11: GS9062 Internal Registers
Address
Register Name
See Section
00h
IOPROC_DISABLE
Section 3.6.3
02h
EDH_FLAG
Section 3.6.3.3
04h
VIDEO_STANDARD
Section 3.6.2
0Ah - 0Bh
VIDEO_FORMAT
Section 3.6.3.1
0Eh - 11h
RASTER_STRUCTURE
Section 3.6.2
12h - 19h
EDH_CALC_RANGES
Section 3.6.3.3
1Bh - 1Ch
LINE_352M
Section 3.6.3.1
3.11 JTAG
When the JTAG/HOST input pin of the GS9062 is set HIGH, the host interface port
will be configured for JTAG test operation. In this mode, pins 27 through 30
become TMS, TDO, TDI, and TCK. In addition, the RESET_TRST pin will operate
as the test reset pin.
Boundary scan testing using the JTAG interface will be enabled in this mode.
There are two methods in which JTAG can be used on the GS9062:
1. As a stand-alone JTAG interface to be used at in-circuit ATE (Automatic Test
Equipment) during PCB assembly; or
2. Under control of the host for applications such as system power on self tests.
When the JTAG tests are applied by ATE, care must be taken to disable any other
devices driving the digital I/O pins. If the tests are to be applied only at ATE, this
can be accomplished with tri-state buffers used in conjunction with the
JTAG/HOST input signal. This is shown in Figure 3-11.
Application HOST
GS9062
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
JTAG_HOST
In-circuit ATE probe
Figure 3-11: In-Circuit JTAG
22209 - 7
February 2007
40 of 46
GS9062 Data Sheet
Alternatively, if the test capabilities are to be used in the system, the host may still
control the JTAG/HOST input signal, but some means for tri-stating the host must
exist in order to use the interface at ATE. This is represented in Figure 3-12.
Application HOST
GS9062
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
JTAG_HOST
Tri-State
In-circuit ATE probe
Figure 3-12: System JTAG
Please contact your Gennum representative to obtain the BSDL model for the
GS9062.
3.12 Device Power Up
Because the GS9062 is designed to operate in a multi-volt environment, any power
up sequence is allowed. The charge pump, phase detector, core logic, serial digital
output buffers and digital I/O buffers should all be powered up within 1ms of one
another.
Device pins may also be driven prior to power up without causing damage.
To ensure that all internal registers are cleared upon power-up, the RESET_TRST
signal must be held LOW for a minimum of 1ms after the core power supply has
reached the minimum level specified in the DC Electrical Characteristics Table.
See Table 2-1. See Figure 3-13.
3.13 Device Reset
In order to initialize all internal operating conditions to their default states the
RESET_TRST signal must be held LOW for a minimum of treset = 1ms.
When held in reset, all device outputs will be driven to a high-impedance state.
+1.65V
+1.8V
CORE_VDD
treset
treset
Reset
Reset
RESET_TRST
Figure 3-13: Reset Pulse
22209 - 7
February 2007
41 of 46
GS9062 Data Sheet
4. Application Reference Design
4.1 Typical Application Circuit
20bit/10bitb
GND_VCO
2
1
O/P
3
NC
GND
VCTR
SDO_EN/DISb
DETECT_TRS
GND
8
DETECT_TRS
JTAG/HOSTb
VCO_VCC
JTAG/HOSTb
10n
1u
VCC
GND
IOPROC_EN/DISb
SDO_EN/DISb
GO1555
VCO_VCC
GND_VCO
SMPTE_BYPASSb
SMPTE_BYPASSb
10n
GND_VCO
DVB_ASI
7
6
DVB_ASI
GND_VCO
10n
GND_VCO
NOTE: For GO1525 loop bandwidth
component values see Section 3.8.3.
0
4 7n
33
+1.8V
GND_VCO
VCO_VCC
R2
10n
GND_D
D o n o t p o p u l a t e R2
100n
PCLK
75
10n
1u
PCLK
GND_A
DATA[19..0]
10n
1u
0
DATA19
DATA18
+3.3V
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
+3.3V
DETECT_TRS
LOCK
GND_VCO
0
20bit/10bitb
IOPROC_EN/DISb
SMPTE_BYPASSb
+1.8V_A
281 +/-1%
CP_VDD
PD_GND
PD_VDD
NC
RSV
NC
NC
NC
DVB_ASI
NC
NC
20bit/10bit
IOPROC_EN/DIS
NC
NC
NC
NC
SMPTE_BYPASS
RSET
CD_VDD
+1.8V_A
10n
GND_D
IO_GND
DIN17
DIN16
DIN15
DIN14
DIN13
DIN12
IO_VDD
DIN11
DIN10
DIN9
IO_GND
DIN8
DIN7
DIN6
DIN5
DIN4
DOUT3
DIN2
IO_VDD
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
DATA17
DATA16
DATA15
DATA14
DATA13
DATA12
+3.3V
DATA11
DATA10
DATA9
10n
DATA8
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
1u
GND_D
+3.3V
1u
C55
10n
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
2
10 n
GS9062
10n
1
GND_A
DVB_ASI
1u
CP_GND
LB_CONT
CP_CAP
LF
VCO_VCC
VCO_GND
VCO
VCO
LOCKED
NC
NC
PCLK
CORE_GND
DETECT_TRS
NC
NC
CORE_VDD
DIN19
DIN18
IO_VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
+1.8V_A
SDO_EN/DIS
CD_GND
SDO
SDO
RESET_TRST
JTAG/HOST
CS_TMS
SDOUT_TDO
SDIN_TDI
SCLK_TCK
NC
BLANK
CORE_GND
F
V
H
CORE_VDD
DIN0
DIN1
IO_GND
10n
GND_A
GND_D
DATA1
DATA0
10n
BNC
H
V
F
BLANKb
+1.8V_A
R, L, C form the output return
loss compensation network.
Values are subject to change.
JTAG/HOSTb
GND_A
SDO_EN/DISb
GND_VCO
GND
5
4
20bit/10bitb
IOPROC_EN/DISb
+1.8V
C
GND_A
4u7
L
R
75
10n
LOCK
BLANKb
75
LOCK
BLANKb
GND_D
GND_A
R
SCLK_TCK
SDIN_TDI
SDOUT_TDO
CSb_TMS
L
BNC
C
4u7
RESET_TRSTb
GND_A
22209 - 7
February 2007
42 of 46
GS9062 Data Sheet
5. References & Relevant Standards
SMPTE 125M
Component video signal 4:2:2 – bit parallel interface
SMPTE 291M
Ancillary Data Packet and Space Formatting
SMPTE 293M
720 x 483 active line at 59.94 Hz progressive scan production – digital
representation
SMPTE 352M
Video Payload Identification for Digital Television Interfaces
SMPTE RP165
Error Detection Checkwords and Status Flags for Use in Bit-Serial Digital
Interfaces for Television
SMPTE RP168
Definition of Vertical Interval Switching Point for Synchronous Video
Switching
22209 - 7
February 2007
43 of 46
GS9062 Data Sheet
6. Package & Ordering Information
6.1 Package Dimensions
Table X
CONTROL DIMENSIONS ARE IN MILLIMETERS.
Table Y
S Y MB OL
80L
MI L L I ME T E R
b
e
MI N
N OM
MA X
0.22
0.30
0.38
0.65 BSC
IN C H
MIN
N OM
MA X
0.009 0.012 0.01 5
0.026 B SC
D2
12.35
0.486
E2
12.35
0.486
TOLERANCES OF FORM AND POSITION
aaa
0.20
0.008
bbb
0.20
0.008
ccc
0.10
0.004
ddd
0.13
0.005
NOTES:
Diagram shown is representative only. Table X is fixed for all pin sizes, and
Table Y is specific to the 80-pin package.
1. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
ALLOWABLE PROTRUSION IS 0.25mm PER SIDE. D1 AND E1 ARE
MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD
MISMATCH.
2. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD
WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN
0.08mm. DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS
OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN
ADJACENT LEAD IS 0.07mm FOR 0.4mm AND 0.5mm PITCH PACKAGES.
22209 - 7
February 2007
44 of 46
GS9062 Data Sheet
6.2 Packaging Data
Parameter
Value
Package Type
14mm x 14mm 80-pin LQFP
Package Drawing Reference
JEDEC MS026
Moisture Sensitivity Level
3
Junction to Case Thermal Resistance, θj-c
11.6°C/W
Junction to Air Thermal Resistance, θj-a (at zero airflow)
39.9°C/W
Psi
0.6°C/W
Pb-free and RoHS compliant (GS9062-CFE3)
Yes
6.3 Ordering Information
Part Number
Pb-free and RoHS
Compliant
Package
Temperature Range
GS9062-CF
No
80-pin LQFP
0°C to 70°C
GS9062-CFE3
Yes
80-pin LQFP
0°C to 70°C
22209 - 7
February 2007
45 of 46
GS9062 Data Sheet
7. Revision History
Version
ECR
PCN
Date
Changes and/or Modifications
0
130132
–
July 2003
Upgrade to preliminary data sheet. Reformat detailed description and expand
information. AC/DC parameters updated. Reset Operation clarified. Edit pin
descriptions. Correct register addresses.
1
132415
–
October 2003
SYMBOLS for Input Data Set-Up and Hold times were corrected on the AC
ELECTRICAL CHARACTERISTICS Table. GSPI r/w Timing Diagram updated.
2
133886
–
May 2004
Converted GS9062 to new template format. Moved ESD to maximum absolute
ratings. Adjusted Input Data Setup Time in AC Electrical Characteristics. Added note
to host interface pins. Added Pb-free and Green availability and ordering
information. Added Pb-free reflow solder profile. Corrected minor typing errors.
3
136147
–
February 2005
Corrected pin 79 (LB_CONT) description. Added descriptive text to the Solder
Reflow Profile section. Added Packaging Data section. Updated SCLK on GSPI
timing figures to show burst clock. Updated to reflect RoHS compliance.
4
136662
–
May 2005
Updated document status to Data Sheet. Updated the status of the VD_STD[4:0]
and STD_LOCK bits following a device reset or the removal of the input PCLK.
Changed the GSPI Input Data Hold Time to a minimum instead of a maximum.
5
136982
–
May 2005
Restored missing overlines to pin names.
6
142405
41245
October 2006
Added built-in ClockCleanerTM feature to document title and functional block
diagram. Specified that serializer can reject >300ps pclk jitter in Description on
page 1.
7
143949
42774
February 2007
Recommended GO1555 VCO for new designs. Updated Section 4.1 Typical
Application Circuit. Added Section 3.8.3 Loop Bandwidth Adjustment.
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
DATA SHEET
The product is in production. Gennum reserves the right to make
changes at any time to improve reliability, function or design, in order to
provide the best product possible.
GENNUM CORPORATION
Mailing Address: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Shipping Address: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946
GENNUM JAPAN CORPORATION
Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan
Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505
GENNUM UK LIMITED
25 Long Garden Walk, Farnham, Surrey, England GU9 7HX
Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the
circuits or devices described herein. The sale of the circuit or device described herein does not imply any
patent license, and Gennum makes no representation that the circuit or device is free from patent infringement.
GENNUM and the G logo are registered trademarks of Gennum Corporation.
© Copyright 2002 Gennum Corporation. All rights reserved. Printed in Canada.
www.gennum.com
22209 - 7
February 2007
46 of 46
46