MC100LVEP111 2.5V / 3.3V 1:10 Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP111 is a low skew 1−to−10 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The PECL input signals can be either differential or single−ended (if the VBB output is used). HSTL inputs can be used when the LVEP111 is operating under PECL conditions. The LVEP111 specifically guarantees low output−to−output skew. Optimal design, layout, and processing minimize skew within a device and from device to device. To ensure tightest skew, both sides of differential outputs identically terminate into 50 W even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew. The MC100LVEP111, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the LVEP111 to be used for high performance clock distribution in +3.3 V or +2.5 V systems. Single−ended CLK input operation is limited to a VCC ≥ 3.0 V in PECL mode, or VEE v −3.0 V in NECL mode when using VBB (See Figure 10). Full operating range is available when using an external voltage reference (See Figure 9). Designers can take advantage of the LVEP111’s performance to distribute low skew clocks across the backplane or the board. Features • • • • • • • • http://onsemi.com MARKING DIAGRAMS* MC100 LVEP111 AWLYYWWG LQFP−32 FA SUFFIX CASE 873A Jitter Less than 1 ps RMS Maximum Frequency > 3 GHz Typical 1 1 1 32 QFN32 MN SUFFIX CASE 488AM A WL, L YY, Y WW, W G 85 ps Typical Device−to−Device Skew 20 ps Typical Output−to−Output Skew 32 MC100 LVEP111 ALYWG = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. VBB Output 430 ps Typical Propagation Delay ORDERING INFORMATION The 100 Series Contains Temperature Compensation PECL and HSTL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. • NECL Mode Operating Range: VCC = 0 V • • • • with VEE = −2.375 V to −3.8 V Open Input Default State LVDS Input Compatible Fully Compatible with MC100EP111 Pb−Free Packages are Available © Semiconductor Components Industries, LLC, 2008 December, 2008 − Rev. 17 1 Publication Order Number: MC100LVEP111/D MC100LVEP111 Q3 24 Q3 23 Q4 22 Q4 21 Q5 20 Q5 Q6 19 18 Table 1. PIN DESCRIPTION Q6 17 PIN FUNCTION CLK0*, CLK0** ECL/PECL/HSTL CLK Input VCC 25 16 VCC CLK1*, CLK1** ECL/PECL/HSTL CLK Input Q2 26 15 Q7 Q0:9, Q0:9 ECL/PECL Outputs Q2 27 14 Q7 CLK_SEL* ECL/PECL Active Clock Select Input Q1 28 13 Q8 VBB Reference Voltage Output VCC Positive Supply Q1 29 12 Q8 VEE Negative Supply Q0 30 11 Q9 EP The exposed pad (EP) on the package Q0 31 10 Q9 VCC 32 9 VCC MC100LVEP111 1 2 3 4 5 6 7 bottom must be attached to a heat−sinking conduit. The exposed pad may only be electrically connected to VEE. 8 CLK1 VBB CLK1 CLK0 CLK0 VCC CLK_SEL * Pins will default LOW when left open. ** Pins will default to 2/3VCC when left open. VEE Table 2. FUNCTION TABLE CLK_SEL Active Input L H CLK0, CLK0 CLK1, CLK1 Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. LQFP−32 Pinout (Top View) VCC VCC Q0 Q0 Q1 Q1 Q2 Q2 VCC 32 31 30 29 28 27 26 25 1 24 Q3 CLK_SEL 2 23 Q3 CLK0 3 22 Q4 CLK0 4 VBB 21 Q4 MC100LVEP111 5 20 Q5 CLK1 6 19 Q5 CLK1 7 18 Q6 8 17 Q6 VEE 9 10 11 12 13 14 15 16 VCC Q9 Q9 Q8 Q8 Q7 Q7 VCC Exposed Pad (EP) Figure 2. QFN−32 Pinout (Top View) http://onsemi.com 2 MC100LVEP111 Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor ESD Protection 37.5 kW Human Body Model Machine Model Charged Device Model Moisture Sensitivity (Note 1) LQFP QFN Flammability Rating Oxygen Index: 28 to 34 Transistor Count > 2 kV > 100 V > 2 kV Pb Pkgs Pb−Free Pkgs Level 2 Level 1 Level 2 Level 1 UL 94 V−0 @ 0.125 in 602 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, refer to Application Note AND8003/D. Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 CLK0 Q4 0 Q4 CLK0 Q5 CLK1 Q5 1 Q6 CLK1 VBB CLK_SEL VEE Q6 Q7 Q7 VCC Q8 Q8 Q9 Q9 Figure 3. Logic Diagram http://onsemi.com 3 MC100LVEP111 Table 4. MAXIMUM RATINGS Symbol Rating Unit VCC PECL Mode Power Supply Parameter VEE = 0 V 6 V VEE NECL Mode Power Supply VCC = 0 V −6 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm LQFP−32 LQFP−32 80 55 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board LQFP−32 12 to 17 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm QFN−32 QFN−32 31 27 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) 2S2P QFN−32 12 °C/W Tsol Wave Solder < 3 sec @ 248°C < 3 sec @ 260°C 265 265 °C Pb Pb−Free (QFN−32 Only) Condition 1 Condition 2 VI ≤ VCC VI ≥ VEE Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 4 MC100LVEP111 Table 5. PECL DC CHARACTERISTICS VCC = 2.5 V; VEE = 0 V (Note 2) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 60 90 120 60 90 120 60 90 120 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 3) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV VOL Output LOW Voltage (Note 3) 555 730 900 555 730 900 555 730 900 mV VIH Input HIGH Voltage (Single−Ended) (Note 4) 1335 1620 1335 1620 1275 1620 mV VIL Input LOW Voltage (Single−Ended) (Note 4) 555 875 555 875 555 875 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 5) 1.2 2.5 1.2 2.5 1.2 2.5 V IIH Input HIGH Current 150 mA IIL Input LOW Current 150 CLK CLK 0.5 −150 150 0.5 −150 0.5 −150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. VEE can vary + 0.125 V to −1.3 V. 3. All loading with 50 W to VEE. 4. Do not use VBB at VCC < 3.0 V. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 6. PECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0 V (Note 6) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 60 90 120 60 90 120 60 90 120 mA Output HIGH Voltage (Note 7) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV Output LOW Voltage (Note 7) 1355 1530 1700 1355 1530 1700 1355 1530 1700 mV VIH Input HIGH Voltage (Single−Ended) 2135 2420 2135 2420 2135 2420 mV VIL Input LOW Voltage (Single−Ended) 1355 1675 1355 1675 1355 1675 mV VBB Output Reference Voltage (Note 8) 1775 1975 1775 1975 1775 1975 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 9) 1.2 3.3 1.2 3.3 1.2 3.3 V IIH Input HIGH Current 150 mA IIL Input LOW Current IEE Power Supply Current VOH VOL 1875 150 CLK CLK 0.5 −150 1875 150 0.5 −150 0.5 −150 1875 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. Input and output parameters vary 1:1 with VCC. VEE can vary + 0.925 V to −0.5 V. 7. All loading with 50 W to VCC − 2.0 V. 8. Single ended input operation is limited VCC ≥ 3.0 V in PECL mode. 9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 5 MC100LVEP111 Table 7. NECL DC CHARACTERISTICS VCC = 0 V, VEE = −2.375 V to −3.8 V (Note 10) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 60 90 120 60 90 120 60 90 120 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 11) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV VOL Output LOW Voltage (Note 11) −1945 −1770 −1600 −1945 −1770 −1600 −1945 −1770 −1600 mV VIH Input HIGH Voltage (Single−Ended) −1165 −880 −1165 −880 −1165 −880 mV VIL Input LOW Voltage (Single−Ended) −1945 −1625 −1945 −1625 −1945 −1625 mV VBB Output Reference Voltage (Note 12) −1525 −1325 −1525 −1325 −1525 −1325 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 13) 0.0 V IIH Input HIGH Current 150 mA IIL Input LOW Current −1425 VEE + 1.2 0.0 −1425 VEE + 1.2 150 CLK CLK 0.5 −150 0.0 −1425 VEE + 1.2 150 0.5 −150 0.5 −150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Input and output parameters vary 1:1 with VCC. 11. All loading with 50 W to VCC − 2.0 V. 12. Single ended input operation is limited VEE ≤ −3.0V in NECL mode. 13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 8. HSTL DC CHARACTERISTICS VCC = 2.375 to 3.8 V, VEE = 0 V −40°C Symbol Characteristic Min VIH Input HIGH Voltage VIL Input LOW Voltage Vx Input Crossover Voltage 680 ICC Power Supply Current 70 Typ 25°C Max 1200 Min Typ 85°C Max 1200 Typ 680 120 70 100 900 680 120 70 Unit mV 400 900 Max 1200 400 100 Min 100 400 mV 900 mV 120 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. http://onsemi.com 6 MC100LVEP111 Table 9. AC CHARACTERISTICS VCC = 0 V; VEE = −2.375 to −3.8 V or VCC = 2.375 to 3.8 V; VEE = 0 V (Note 14) −40°C Characteristic Symbol Min fmaxPECL/HSTL Maximum Frequency (Figure 4) tPLH tPHL Propagation Delay (Differential Configuration) tskew Within−Device Skew (Note 15) Within−Device Skew @ 2.5 V (Note 15) Device−to−Device Skew (Note 16) tJITTER CLOCK Random Jitter (RMS) @ v0.5 GHz @ v1.0 GHz @ v1.5 GHz @ v2.0 GHz @ v2.5 GHz @ v3.0 GHz VPP Input Swing (Differential Interconnect Configuration) Measured Single−Ended tr/tf Output Rise/Fall Time (20%−80%) Typ 25°C Max Min 3 325 Typ 85°C Max Min 3 400 475 20 20 85 350 Typ Max 3 430 500 25 25 150 20 20 85 0.209 0.200 0.197 0.220 0.232 0.348 0.5 0.5 0.4 0.5 0.4 0.6 150 800 1200 105 200 255 375 Unit GHz 510 590 ps 25 25 150 25 20 85 35 25 150 ps 0.204 0.214 0.213 0.224 0.290 0.545 0.5 0.6 0.5 0.5 0.5 0.8 0.221 0.229 0.243 0.292 0.522 0.911 0.5 0.5 0.4 0.6 0.8 1.3 150 800 1200 150 800 1200 mV 125 200 275 150 230 320 ps ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 14. Measured with 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V. 15. Skew is measured between outputs under identical transitions and conditions on any one device. 16. Device−to−Device skew for identical transitions at identical VCC levels. 800 VOUTpp (mV) 700 600 500 400 300 200 100 0 0 1000 2000 3000 4000 FREQUENCY (MHz) Figure 4. Fmax Typical http://onsemi.com 7 5000 6000 MC100LVEP111 VCC VCC Z0 = 50 W VCC VCC Z0 = 50 W MC100LVEP111 CLKx 50 W LVPECL Driver LVDS Driver VTT 50 W 100 W Z0 = 50 W CLK MC100LVEP111 CLKx 50 W* CLK 50 W* Z0 = 50 W VT = VCC − 2.0 V VEE VEE GND Figure 5. LVPECL in Interface VCC Figure 6. LVDS in Interface VCC Z0 = 50 W GND VCC VCC Z0 = 50 W MC100LVEP111 CLKx 50 W 50 W HSTL Driver MC100LVEP111 CLKx CML Driver VDDQ VCC 50 W 50 W CLK CLK Z0 = 50 W VEE Z0 = 50 W VEE VEE Figure 7. HSTL in Interface VEE Figure 8. Standard 50 W Load CML in Interface http://onsemi.com 8 MC100LVEP111 VCC VCC Z0 = 50 W LVCMOS LVTTL Single−Ended Driver MC100LVEP111 CLKx VCC 1k CLK 1k VEE VEE Figure 9. Single−Ended Interface LVCMOS/LVTTL in Interface Using an External Voltage Reference VCC VCC Z0 = 50 W MC100LVEP111 CLKx LVCMOS LVTTL Single−Ended Driver CLK VEE VEE VBB VEE Figure 10. Single−Ended Interface LVCMOS/LVTTL in Interface Using VBB http://onsemi.com 9 MC100LVEP111 Zo = 50 W Q D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 11. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) Round Sprocket Holes Designations Quadrant A = Upper Left Quadrant B = Upper Right Quadrant C = Lower Left Quadrant D = Lower Right Quadrant A Quadrant B User Direction Quadrant C Quadrant D of Unreeling Figure 12. Tape and Reel Pin 1 Quadrant Orientation ORDERING INFORMATION Device Package Shipping† MC100LVEP111FA LQFP−32 250 Units / Tray MC100LVEP111FAG LQFP−32 (Pb−Free) 250 Units / Tray MC100LVEP111FAR2 LQFP−32 2000 / Tape & Reel (Pin 1 Orientation in Quadrant B, Figure 12) MC100LVEP111FARG LQFP−32 (Pb−Free) 2000 / Tape & Reel (Pin 1 Orientation in Quadrant B, Figure 12) M100LVEP111FATW LQFP−32 2000 / Tape & Reel (Pin 1 Orientation in Quadrant A, Figure 12) M100LVEP111FATWG LQFP−32 (Pb−Free) 2000 / Tape & Reel (Pin 1 Orientation in Quadrant A, Figure 12) MC100LVEP111MNG QFN−32 (Pb−Free) 74 Units / Rail MC100LVEP111MNRG QFN−32 (Pb−Free) 1000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 10 MC100LVEP111 Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 11 MC100LVEP111 PACKAGE DIMENSIONS A1 A 32 −T−, −U−, −Z− 32 LEAD LQFP CASE 873A−02 ISSUE C 4X 25 0.20 (0.008) AB T-U Z 1 AE −U− −T− B P V 17 8 BASE METAL DETAIL Y V1 AC T-U Z AE DETAIL Y ÉÉ ÉÉ ÉÉ −Z− 9 S1 4X 0.20 (0.008) AC T-U Z F S 8X G −AB− J R D DETAIL AD SECTION AE−AE C E −AC− H W K Q_ X DETAIL AD NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE −AB− IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS −T−, −U−, AND −Z− TO BE DETERMINED AT DATUM PLANE −AB−. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE −AC−. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE −AB−. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. http://onsemi.com 12 DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X 0.250 (0.010) 0.10 (0.004) AC GAUGE PLANE SEATING PLANE M_ M N 9 0.20 (0.008) B1 MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.450 0.750 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.018 0.030 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF MC100LVEP111 PACKAGE DIMENSIONS QFN32 5*5*1 0.5 P CASE 488AM−01 ISSUE O PIN ONE LOCATION 2X ÉÉ ÉÉ 0.15 C 2X A B D NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. E DIM A A1 A3 b D D2 E E2 e K L TOP VIEW 0.15 C (A3) 0.10 C A 32 X 0.08 C C L 32 X 9 D2 SEATING PLANE A1 SIDE VIEW MILLIMETERS MIN NOM MAX 0.800 0.900 1.000 0.000 0.025 0.050 0.200 REF 0.180 0.250 0.300 5.00 BSC 2.950 3.100 3.250 5.00 BSC 2.950 3.100 3.250 0.500 BSC 0.200 −−− −−− 0.300 0.400 0.500 SOLDERING FOOTPRINT* EXPOSED PAD 16 K 5.30 32 X 17 3.20 8 32 X E2 1 0.63 24 32 25 32 X b 0.10 C A B e 3.20 5.30 0.05 C BOTTOM VIEW 32 X 0.28 28 X 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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