Intersil ISL71090SEH25 Rh voltage regulators precision output Datasheet

DATASHEET
Radiation Hardened Ultra Low Noise, Precision Voltage
Reference
ISL71090SEH50
Features
The ISL71090SEH50 is an ultra low noise, high DC accuracy
precision voltage reference with a wide input voltage range
from 7V to 30V. The ISL71090SEH50 uses the Intersil
Advanced Bipolar technology to achieve 1.1µVP-P noise at
0.1Hz with an accuracy over-temperature of 0.15%.
• Reference output voltage . . . . . . . . . . . . . . . . . . 5.0V ±0.05%
The ISL71090SEH50 offers a 5.0V output voltage with
10ppm/°C temperature coefficient and also provides
excellent line and load regulation. The device is offered in an
8 Ld Flatpack package.
• Tempco (box method) . . . . . . . . . . . . . . 10ppm/°C maximum
The ISL71090SEH50 is ideal for high-end instrumentation,
data acquisition and applications requiring high DC precision
where low noise performance is critical.
Applications
• RH voltage regulators precision outputs
• Precision voltage sources for data acquisition system for
space applications
• Accuracy over temperature . . . . . . . . . . . . . . . . . . . . .±0.15%
• Output voltage noise . . . . . .1.1µVP-P typical (0.1Hz to 10Hz)
• Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . 930µA (typical)
• Output current capability . . . . . . . . . . . . . . . . . . . . . . . . 20mA
• Line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8ppm/V
• Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . .10ppm/mA
• Operating temperature range. . . . . . . . . . . .-55°C to +125°C
• Radiation environment
- High dose rate (50-300rad(Si)/s) . . . . . . . . . . . 100krad(Si)
- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . . 100krad(Si)*
- SET/SEL/SEB . . . . . . . . . . . . . . . . . . . . . . .86MeV•cm2/mg
• Strain and pressure gauge for space applications
*Product capability established by initial characterization. The
“EH” version is acceptance tested on a wafer-by-wafer basis to
50krad(Si) at low dose rate
Related Literature
• Electrically screened to SMD 5962-13211
• AN1847, “ISL71090SEH12EV1Z, ISL71090SEH25EV1Z,
ISL71090SEH50EV1Z, ISL71090SEH75EV1Z User Guide”
• AN1848, “Single Event Effects (SEE) Testing of the
ISL71090SEH Precision Voltage Reference”
• AN1849, “Total Dose Testing of the ISL71090SEH Precision
Voltage Reference”
ISL71090SEH50
2
VIN
0.1µF
3
1nF
4
DNC
DNC
VIN
DNC
COMP
VOUT
GND
TRIM
8
5.012
7
5.010
5.005V +0.1%
VREF
5.008
6
5
1µF
C
VOUT (V)
1
UNIT4
UNIT5
5.006
5.004
UNIT3
5.002
REFIN
VDD
VDD
VEE
VEE
BIPOFF
NOTE: SELECT C TO MINIMIZE
SETTLING TIME.
5.000
D12
D0
1.1k
GND
4.998
-55
5.005V -0.1%
-35
-15
5
25
45
65
85
105
125
TEMPERATURE (°C)
HS-565BRH
FIGURE 1. ISL71090SEH50 TYPICAL APPLICATION DIAGRAM
March 15, 2016
FN8588.3
UNIT1
UNIT2
DACOUT
1
FIGURE 2. VOUT vs TEMPERATURE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
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ISL71090SEH50
Ordering Information
ORDERING NUMBER
(Notes 1, 2)
PART NUMBER
VOUT OPTION
(V)
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
5962R1321103VXC
ISL71090SEHVF50
5.0
-55 to +125
8 Ld Flatpack
K8.A
ISL71090SEHF50/PROTO
ISL71090SEHF50/PROTO
5.0
-55 to +125
8 Ld Flatpack
K8.A
5962R1321103V9A
ISL71090SEHVX50
5.0
-55 to +125
Die
ISL71090SEHX50SAMPLE
ISL71090SEHX50SAMPLE
5.0
-55 to +125
Die
ISL71090SEH50EV1Z
Evaluation Board
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in this
“Ordering Information” table must be used when ordering.
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART
NUMBER
VOUT
(V)
TEMPCO
(ppm/°C)
OUTPUT VOLTAGE NOISE
(µVP-P)
LOAD REGULATION
(ppm/mA)
ISL71090SEH12
1.25
10
1
35
ISL71090SEH25
2.5
10
2
2.5
ISL71090SEH50
5.0
10
1.1
10
ISL71090SEH75
7.5
10
1
10
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ISL71090SEH50
Pin Configuration
ISL71090SEH50
(8 LD FLATPACK)
TOP VIEW
DNC
1
8
DNC
VIN
2
7
DNC
COMP
3
6
VOUT
GND
4
5
TRIM
NOTE: The ESD triangular mark is indicative of pin #1. It is a part of the device marking and is
placed on the lid in the quadrant where pin #1 is located.
Pin Descriptions
PIN NUMBER
PIN NAME
ESD CIRCUIT
DESCRIPTION
1, 7, 8
DNC
3
Do not connect. Internally terminated.
2
VIN
1
Input voltage connection
3
COMP
2
Compensation and noise reduction capacitor
4
GND
1
Ground connection. Also connected to the lid.
5
TRIM
2
Voltage reference trim input
6
VOUT
2
Voltage reference output
VDD
VDD
CAPACITIVELY
TRIGGERED CLAMP
VDD
PIN
DNC
GND
GND
ESD CIRCUIT 1
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ESD CIRCUIT 2
ESD CIRCUIT 3
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March 15, 2016
ISL71090SEH50
Functional Block Diagram
VIN
BIAS
REGULATOR
DNC
BAND
GAP
REFERENCE
DNC
3.7V
DNC
1.2V
Gm
VOUT
GND
COMP
TRIM
1.2V
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
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ISL71090SEH50
Absolute Maximum Ratings
Thermal Information
Maximum Voltage
VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +40V
VIN to GND at an LET = 86MeV•cm2/mg . . . . . . . . . . . . . . -0.5V to +36V
VOUT to GND (10s). . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VOUT + 0.5V
Voltage on any Pin to Ground . . . . . . . . . . . . . . . . . -0.5V to +VOUT + 0.5V
Voltage on DNC Pins . . . . . . . . . . . . No connections permitted to these pins
ESD Ratings
Human Body Model (Tested per MIL-PRF-883 3015.7). . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD22-C101D)). . . . . . . . . . . 750V
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
8 Ld Flatpack Package (Notes 3, 4). . . . . .
140
15
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature (TJMAX). . . . . . . . . . . . . . . . . . . . . .+150°C
Recommended Operating Conditions
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V to +30V
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
4. For JC, the “case temp” location is the center of the ceramic on the package underside.
5. Product capability established by initial characterization. The “EH” version is acceptance tested on a wafer-by-wafer basis to 50krad(Si) at low dose rate.
6. The output capacitance used for SEE testing is CIN = 0.1µF and COUT = 1µF.
Electrical Specifications for Flatpack VIN = 10V, IOUT = 0mA, CL = 0.1µF and CC = 1nF unless otherwise specified. Boldface
limits apply after radiation at +25°C and across the operating temperature range, -55°C to +125°C without radiation, unless otherwise specified.
PARAMETER
DESCRIPTION
VOUT
Output Voltage
VOA
VOUT Accuracy at TA = +25°C
MIN
(Note 7)
TYP
MAX
(Note 7)
5.005
UNIT
V
VOUT = 5.005V, (Note 10)
-0.05
+0.05
%
VOUT Accuracy at TA = -55°C to +125°C VOUT = 5.005V, (Note 10)
-0.15
+0.15
%
-0.3
+0.3
%
10
ppm/°C
VOUT Accuracy at TA = +25°C, Post
Radiation
TC VOUT
TEST CONDITIONS
VOUT = 5.005V, (Note 10)
Output Voltage Temperature
Coefficient (Note 8)
VIN
Input Voltage Range
IIN
Supply Current
VOUT /VIN
Line Regulation
VOUT/IOUT
Load Regulation
7.0
30
V
0.930
1.500
mA
VIN = 7.0V to 30V
8
20
ppm/V
Sourcing: 0mA ≤ IOUT ≤ 20mA
10
20
ppm/mA
Sinking: -10mA ≤ IOUT ≤ 0mA
21
40
ppm/mA
Dropout Voltage
(Note 9)
IOUT = 10mA
1.5
1.7
V
ISC+
Short-Circuit Current
TA = +25°C, VOUT tied to GND
53
mA
ISC-
Short-Circuit Current
TA = +25°C, VOUT tied to VIN
-63
mA
tR
Turn-On Settling Time
90% of final value, CL = 1.0µF,
CC = open
250
µs
Ripple Rejection
f = 120Hz
90
dB
eN
Output Voltage Noise
0.1Hz ≤ f ≤10Hz
1.1
µVP-P
VN
Broadband Voltage Noise
10Hz ≤ f ≤1kHz
2.2
µVRMS
Noise Density
f = 1kHz, VIN = 7.1V
68
nV/√Hz
Long Term Drift
TA = 125°C, 1000hrs
15
ppm
VD
PSRR
VOUT/t
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ISL71090SEH50
Electrical Specifications for Die VIN = 10V, IOUT = 0mA, CL = 0.1µF and CC = 1nF unless otherwise specified. Boldface limits apply
after radiation at 25°C and across the operating temperature range, -55°C to +125°C without radiation, unless otherwise specified. Specifications over
temperature are guaranteed but not production tested on die.
PARAMETER
DESCRIPTION
VOUT
Output Voltage
VOA
VOUT Accuracy at TA = +25°C
MIN
(Note 7)
TYP
MAX
(Note 7)
5.005
UNIT
V
VOUT = 5.005V (Note 11)
-0.05
+0.05
%
VOUT Accuracy at TA = -55°C to +125°C VOUT = 5.005V (Note 11)
-0.15
+0.15
%
-0.3
+0.3
%
10
ppm/°C
30
V
0.930
1.500
mA
VOUT Accuracy at TA = +25°C Post
Radiation
TC VOUT
TEST CONDITIONS
VOUT = 5.005V, (Note 11)
Output Voltage Temperature
Coefficient (Note 8)
VIN
Input Voltage Range
IIN
Supply Current
VOUT /VIN
Line Regulation
VIN = 7.0V to 30V
8
20
ppm/V
VOUT/IOUT
Load Regulation
Sourcing: 0mA ≤ IOUT ≤ 20mA
10
20
ppm/mA
Sinking: -10mA ≤ IOUT ≤ 0mA
21
40
ppm/mA
IOUT = 10mA
1.5
1.7
V
VD
Dropout Voltage (Note 9)
7.0
NOTES:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
8. Over the specified temperature range. Temperature coefficient is measured by the box method whereby the change in VOUT(max) - VOUT(min) is divided
by the temperature range; in this case, -55°C to +125°C = +180°C.
9. Dropout Voltage is the minimum VIN - VOUT differential voltage measured at the point where VOUT drops 1mV from VIN = nominal at TA = +25°C.
10. Post-reflow drift for the ISL71090SEH50 devices can be 100µV typical based on experimental results with devices on FR4 double sided boards. The
engineer must take this into account when considering the reference voltage after assembly.
11. The VOUT accuracy is based on die mount with Silver Glass die attach material such as “QMI 2569" or equivalent in a package with an Alumina
ceramic substrate.
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ISL71090SEH50
Typical Performance Curves
5.012
VOUT = 5.005V, TA = +25°C, COUT = 1µF, COMP = 1nF unless otherwise specified.
3.50
5.005V +0.1%
3.00
VOUT (V)
5.008
5.006
LINE REG (ppm/V)
5.010
VOUT(V) 0mA +25°C
VOUT(V) 0mA +125°C
VOUT(V) 0mA -55°C
5.004
5.002
5.005V -0.1%
LINE REG ppm/V M-55°C
2.00
1.50
1.00
0.50
5.000
4.998
LINE REG ppm/V +125°C
2.50
0
5
10
15
20
25
30
LINE REG ppm/V +25°C
0.00
0
35
5
10
15
20
25
35
30
VIN (V)
VIN (V)
FIGURE 5. LINE REGULATION OVER TEMPERATURE
FIGURE 4. VOUT ACCURACY OVER TEMPERATURE
5.012
5.005V -0.1%
5.005V +0.1%
VOUT (V) 0mA +25°C
VOUT (V) 20mA +25°C
VOUT (V) -10mA +25°C
VOUT (V) 0mA +125°C
VOUT (V) 20mA +125°C
VOUT (V) -10mA +125°C
VOUT (V) 0mA -55°C
VOUT (V) 20mA -55°C
VOUT (V) -10mA -55°C
5.010
VOUT (V)
5.008
5.006
5.004
5.002
5.000
4.998
0
5
10
20
15
25
30
35
VIN (V)
FIGURE 6. VOUT vs VIN AT 0mA, 20mA AND -10mA
5.012
25
5.005V +0.1%
VOUT (V)
5.008
20
VOUT(V) +125°C
LOAD REG (ppm/mA)
5.010
VOUT(V) +25°C
5.006
5.004
5.002
VOUT(V) 0mA -55°C
5.000
4.998
-10
0
5
10
15
20
25
IOUT (mA)
FIGURE 7. LOAD REGULATION OVER TEMPERATURE AT VIN = 7V (V)
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LOAD REG ppm/mA (VIN = 5V -55°C)
10
5
LOAD REG ppm/mA (VIN = 5V +25°C)
0
-5
-10
5.005V -0.1%
-5
15
-15
-10
LOAD REG ppm/mA (VIN = 5V +125°C)
-5
0
5
10
15
20
25
IOUT (mA)
FIGURE 8. LOAD REGULATION OVER TEMPERATURE AT VIN = 7V
(ppm/mA)
FN8588.3
March 15, 2016
ISL71090SEH50
Typical Performance Curves
VOUT = 5.005V, TA = +25°C, COUT = 1µF, COMP = 1nF unless otherwise specified.
1.6
+25°C VIN = 7V; VOUT = 5.005V;
IOUT = 0mA TO 1mA; SLEW RATE = 2mA/µs; COUT = 1µF
1.4
DROPOUT (V)
1.2 DROPOUT V AT +25°C
COMP = 1000pF
1.0
0.8
VOUT
DROPOUT V AT +125°C
0.6
0.4
DROPOUT V AT +150°C
0.2
0.0
5
0
10
15
20mV/DIV
25
20
IOUT (mA)
100µs/DIV
FIGURE 10. LOAD TRANSIENT (0mA TO 1mA)
FIGURE 9. DROPOUT VOLTAGE FOR 5.005V
5.012
10k
5.005V +0.1%
5.010
5.008
VOUT (V)
NOISE (nV/√Hz)
1k
100
UNIT4
UNIT5
5.006
5.004
UNIT3
5.002
10
UNIT1
UNIT2
f = 1kHz, En = 67.9nV/√Hz
5.000
1
0.1
1
10
100
1k
10k
4.998
-55
100k
5.005V -0.1%
-35
-15
5
25
45
65
85
105
125
TEMPERATURE (°C)
FREQUENCY (Hz)
FIGURE 12. 5.005V VOUT LIMITS PLOT
FIGURE 11. NOISE DENSITY vs FREQUENCY (VIN = 7.1V, IOUT = 0mA,
CIN = 0.1µF, COUT = 1µF, COMP = 1nF)
0
-20
PSRR (dB)
-40
-60
-80
-100
-120
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 13. PSRR (+25°C, VIN = 7V, VOUT = 5.005V, IOUT = 0mA, CIN = 0.1µF, COUT = 1.0µF, COMP = 1nF, VSIG = 300mVP-P)
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ISL71090SEH50
Device Operation
Bandgap Precision Reference
The ISL71090SEH50 uses a bandgap architecture and special
trimming circuitry to produce a temperature compensated,
precision voltage reference with high input voltage capability and
moderate output current drive.
Applications Information
Board Mounting Considerations
For applications requiring the highest accuracy, board mounting
location should be reviewed. The device uses a ceramic flatpack
package. Generally, mild stresses to the die when the Printed
Circuit (PC) board is heated and cooled, can slightly change the
shape. Because of these die stresses, placing the device in areas
subject to slight twisting can cause degradation of reference
voltage accuracy. It is normally best to place the device near the
edge of a board, or on the shortest side, because the axis of
bending is most limited in that location. Mounting the device in a
cutout also minimizes flex. Obviously, mounting the device on
flexprint or extremely thin PC material will likewise cause loss of
reference accuracy.
Board Assembly Considerations
Some PC board assembly precautions are necessary. Normal
output voltage shifts of typically 100µV can be expected with
Pb-free reflow profiles or wave solder on multilayer FR4 PC
boards. Precautions should be taken to avoid excessive heat or
extended exposure to high reflow or wave solder temperatures.
Output Voltage Adjustment
The output voltage can be adjusted above and below the
factory-calibrated value via the trim terminal. The trim terminal is
the negative feedback divider point of the output op amp. The
voltage at the trim pin is set at approximately 1.216V by the internal
bandgap and amplifier circuitry of the voltage reference. The
suggested method to adjust the output is to connect a 1MΩ external
resistor directly to the trim terminal and connect the other end to the
wiper of a potentiometer that has a 100kΩ resistance and whose
outer terminals connect to VOUT and ground. If a 1MΩ resistor is
connected to trim, the output adjust range will be ±6.3mV. The TRIM
pin should not have any capacitor tied to its output, also it is
important to minimize the capacitance on the trim terminal during
layout to preserve output amplifier stability. It is also best to connect
the series resistor directly to the trim terminal, to minimize that
capacitance and also to minimize noise injection. Small trim
adjustments will not disturb the factory-set temperature coefficient
of the reference, but trimming near the extreme values can.
Output Stage
The output stage of the device has a push pull configuration with
an high side PNP and a low-side NPN. This helps the device to act
as a source and sink. The device can source 20mA.
Use of COMP Capacitors
The reference can be compensated for the COUT capacitors used
by adding a capacitor from COMP pin to GND. See Table 2 for
recommended values of the COMP capacitor.
TABLE 2.
Noise Performance and Reduction
The output noise voltage over the 0.1Hz to 10Hz bandwidth is
typically 1.1µVP-P (VOUT = 5.0V). The noise measurement is made
with a 9.9Hz bandpass filter. Noise in the 10Hz to 1kHz
bandwidth is approximately 2.2µVRMS, with 1µF capacitance on
the output. This noise measurement is made with a bandpass
filter of 990Hz. Load capacitance up to 10µF (with COMP
capacitor from Table 2) can be added but will result in only
marginal improvements in output noise and transient response.
Turn-On Time
Normal turn-on time is typically 250µs, the circuit designer must
take this into account when looking at power-up delays or
sequencing.
COUT
(µF)
CCOMP
(nF)
0.1
1
1
1
10
10
SEE Testing
The SET result is based on the ISL71090SEH25. The
ISL71090SEH25 and ISL71090SEH50 share the same active
circuitry consisting of a precision bandgap ckt and a trimmable
amplifier to set the output reference with only a resistor change to
scale the output. The SET test was done under an ion beam having
an LET of 86MeV•cm2/mg. The device did not latch-up or burnout
to a VDD of 36V and at +125°C. Single Event transients were
observed and are summarized in the Table 3:
Temperature Coefficient
The limits stated for temperature coefficient (Tempco) are
governed by the method of measurement. The overwhelming
standard for specifying the temperature drift of a reference is to
measure the reference voltage at two temperatures, which
provide for the maximum voltage deviation and take the total
variation, (VHIGH - VLOW), this is then divided by the temperature
extremes of measurement (THIGH – TLOW). The result is divided by
the nominal reference voltage (at T = +25°C) and multiplied by
106 to yield ppm/°C. This is the “Box” method for specifying
temperature coefficient.
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TABLE 3.
VIN
(V)
IOUT
(mA)
COUT
(µF)
SET
(% VOUT)
4
5
1
-4.6
30
5
1
-4.4
30
5
10
-1.0
DNC Pins
These pins are for trimming purpose and for factory use only. Do
not connect these to the circuit in any way. It will adversely effect
the performance of the reference.
FN8588.3
March 15, 2016
ISL71090SEH50
Package Characteristics
TOP METALLIZATION
Type: AlCu (99.5%/0.5%)
Thickness: 30kÅ
Weight of Packaged Device
0. 31 Grams (typical)
BACKSIDE FINISH
Lid Characteristics
Silicon
Finish: Gold
Potential: Connected to lead #4 (GND)
Case Isolation to Any Lead: 20 x 109 Ω (minimum)
ASSEMBLY RELATED INFORMATION
SUBSTRATE POTENTIAL
Floating
Die Characteristics
ADDITIONAL INFORMATION
Die Dimensions
WORST CASE CURRENT DENSITY
1464µm x 1744µm (58 mils x 69 mils)
Thickness: 483µm ±25µm (19 mils ±1 mil)
<2 x 105 A/cm2
Interface Materials
PROCESS
Dielectrically Isolated Advanced Bipolar Technology- PR40 SOI
GLASSIVATION
Type: Nitrox
Thickness: 15kÅ
Metallization Mask Layout
DNC
DNC
DNC
VS
COMP
VOUT
SENSE
GND
POWR
VOUT
FORCE
GND
QUIET
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(see Note 12, Table 4)
TRIM
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ISL71090SEH50
TABLE 4. DIE LAYOUT X-Y COORDINATES
PAD NAME
PAD NUMBER
X
(µm)
Y
(µm)
BOND WIRES PER PAD
GND PWR
2
-104
0
1
GND QUIET
1
0
0
1
COMP
3
-108
589
1
VS
4
-125
1350
1
DNC
5
-108
1452
1
DNC
6
1089
1452
1
DNC
7
1089
1350
1
VOUT SENSE
8
1072
598
1
VOUT FORCE
9
1088
1
1
TRIM
10
985
-25
1
NOTES:
12. Origin of coordinates is the centroid of GND QUIET.
13. Bond wire size is 1.0 mil.
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FN8588.3
March 15, 2016
ISL71090SEH50
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
March 15, 2016
FN8588.3
-Updated Related Literature document titles to match titles on the actual documents.
-Corrected the Evaluation board part number in the Ordering Information table on page 2.
-Added Table 1 on page 2.
-On page 5:
Changed Electrical Specification for Flatpack note from: “Boldface limits apply over the operating
temperature range, -55°C to +125°C and radiation.” To: “Boldface limits apply after radiation at 25°C or
across the operating temperature range, -55°C to +125°C without radiation, unless otherwise specified.”
For parameter VOA (row 4) in Electrical Specifications for Flatpack table changed the description from: “VOUT
Accuracy, Post Rad”, to: “VOUT Accuracy at TA = +25°C, Post Radiation”.
For parameters VOA (rows 2, 3, 4) in Electrical Specifications for Flatpack table added “Note 10" to
Conditions column.
Removed reference to TB493 as this is not applicable to hermetic packages.
-On page 6:
Changed Electrical Specification for Die note from: “Boldface limits apply over the operating temperature
range, -55°C to +125°C and radiation.” To: “Boldface limits apply after radiation at 25°C or across the
operating temperature range, -55°C to +125°C without radiation, unless otherwise specified.
For parameter VOA (row 4) in Electrical Specifications for Die table changed the description from: “VOUT
Accuracy, Post Rad”, to: “VOUT Accuracy at TA = +25°C, Post Radiation”.
For parameters VOA for Post Rad (row 4) in Electrical Specifications for Die table added “Note 11” to
Conditions column.
-Updated POD K8.A to the latest revision changes are as follows:
Modified Note 2 by adding the words “...in addition to or instead of...”
December 2, 2013
FN8588.2
Electrical spec table on page 5 (Flatpack) and page 6 (Die): VOUT Accuracy Post Rad section, changed the value
for Min from -0.2 to -0.3 and Max from +0.2 to +0.3
October 9, 2013
FN8588.1
Initial Release.
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For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
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12
FN8588.3
March 15, 2016
ISL71090SEH50
Package Outline Drawing
K8.A
8 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
Rev 4, 12/14
0.015 (0.38)
0.008 (0.20)
PIN NO. 1
ID OPTIONAL
1
2
0.050 (1.27 BSC)
0.005 (0.13)
MIN
4
PIN NO. 1
ID AREA
0.022 (0.56)
0.015 (0.38)
0.110 (2.79)
0.087 (2.21)
0.265 (6.73)
0.245 (6.22)
TOP VIEW
0.036 (0.92)
0.026 (0.66)
0.009 (0.23)
0.004 (0.10)
6
0.265 (6.75)
0.245 (6.22)
-D-
-H-
-C-
0.180 (4.57)
0.170 (4.32)
SEATING AND
BASE PLANE
0.370 (9.40)
0.325 (8.26)
0.03 (0.76) MIN
SIDE VIEW
0.007 (0.18)
0.004 (0.10)
NOTES:
LEAD FINISH
0.009 (0.23)
BASE
METAL
0.004 (0.10)
0.019 (0.48)
0.015 (0.38)
0.0015 (0.04)
MAX
0.022 (0.56)
0.015 (0.38)
2. If a pin one identification mark is used in addition to or instead of a tab,
the limits of the tab dimension do not apply.
3. The maximum limits of lead dimensions (section A-A) shall be
measured at the centroid of the finished lead surfaces, when solder
dip or tin plate lead finish is applied.
4. Measure dimension at all four corners.
3
SECTION A-A
1. Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one
identification mark. Alternately, a tab may be used to identify pin one.
5. For bottom-brazed lead packages, no organic or polymeric materials
shall be molded to the bottom of the package to cover the leads.
6. Dimension shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension minimum shall
be reduced by 0.0015 inch (0.038mm) maximum when solder dip
lead finish is applied.
7. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
8. Controlling dimension: INCH.
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13
FN8588.3
March 15, 2016