iC-LFL1402 256x1 LINEAR IMAGE SENSOR Rev A5, Page 1/9 FEATURES APPLICATIONS • 256 active photo pixels of 56 µm at a gap and distortion free • Optical line sensors • CCD substitute • • • • • • • • • pitch of 63.5 µm (400 DPI) Integrating L-V conversion followed by a sample & hold circuit High sensitivity and uniformity over wavelength High clockrates of up to 5 MHz Only 256 clocks required for readout Shutter function enables flexible integration times Glitch-free analogue output Push-pull output amplifier 5 V single supply operation Function equivalent to TSL1402 (serial mode) PACKAGES OBGA™ LFL1C BLOCK DIAGRAM VCC VDD TP CONTROL AND SHIFT REGISTER Sample and Hold Control CLK NS D NS Q C SI Bit 1 NRCI Q C D NQ NQ Bit 2 C Q D NQ NR Bit 3 RPIXp1:256d SNH C Q C D NQ NR Q D NQ NR Bit 255 Bit 256 SNH256 ACTIVE PIXELS DIS Pixel 1 Pixel 2 Pixel 256 PIXEI PIXOI RSET ONE VHE REF LFL1402 PIXEL MULTIPLEXER BIAS AGND Copyright © 2004, 2017 iC-Haus AO VHO OUTPUT AMPLIFIER GND http://www.ichaus.com iC-LFL1402 256x1 LINEAR IMAGE SENSOR Rev A5, Page 2/9 DESCRIPTION iC-LFL1402 is an integrating light-to-voltage converter with a single line of 256 pixels pitched at 63.5 µm (center-to-center distance). Due to the monolithical integration there is no pixel-gap or pitch distortion whatsoever. Each pixel consists of a 56.4 µm x 200 µm photodiode, an integration capacitor and a sample and hold circuit. The integrated control logic makes operation very simple, with only a start and clock signal necessary. A third control input enables the integration period to be prematurely terminated at any time (electronic shutter). When the start signal is given the hold mode is activated for all pixels simultaneously with the next rising clock edge; starting with pixel 1 the hold voltages are switched in sequence to the push-pull output amplifier. The second clock pulse deletes all integration capacitors and the integration period starts again in the background during the output phase. A run is complete after 256 clock pulses. iC-LFL1402 is suitable for high clock rates of up to 5 MHz. PACKAGING INFORMATION OBGA™ LFL1C PIN CONFIGURATION OBGA™ LFL1C PIN FUNCTIONS No. Name Function 1 2 3 4 5 6 7 8 SI CLK AO VCC RSET AGND GND DIS Start Integration Input Clock Input Analogue Output +5 V Supply Voltage Connect to GND for internal bias Analogue Ground Digital Ground Disable Integration Input CHIP-LAYOUT iC-LFL1402 Chip size: 16.6 mm x 1.7 mm DIS Pitch 63.5 um PIXEL 1 SI AGND GND CLK Active Area 56.4 um x 200 um TP RSET PIXEL 256 AO VDD VCC iC-LFL1402 256x1 LINEAR IMAGE SENSOR Rev A5, Page 3/9 ABSOLUTE MAXIMUM RATINGS Beyond these values damage may occur; device operation is not guaranteed. Item No. Symbol Parameter Conditions Unit Min. Max. G001 VDD Digital Supply Voltage -0.3 6 V G002 VCC Analogue Supply Voltage -0.3 6 V G003 V() Voltage at SI, CLK, DIS, RSET, TP, AO -0.3 VCC + 0.3 V G004 I() Current in RSET, TP, AO -10 10 mA G005 Vd() ESD Susceptibility at all pins 2 kV G006 Tj Operating Junction Temperature -40 125 °C G007 Ts Storage Temperature Range HBM, 100 pF/1.5 kΩ see package specification OBGA™ LFL1C THERMAL DATA Operating Conditions: VCC = VDD = 5 V ±10% Item No. T01 Symbol Parameter Conditions Unit Min. Ta Operating Ambient Temperature Range see package specification OBGA™ LFL1C All voltages are referenced to ground unless otherwise stated. All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative. Typ. Max. iC-LFL1402 256x1 LINEAR IMAGE SENSOR Rev A5, Page 4/9 ELECTRICAL CHARACTERISTICS Operating Conditions: VCC = VDD = 5 V ±10%, RSET = GND, Tj = -25...110 °C unless otherwise noted Item No. Symbol Parameter Conditions Unit Min. Typ. Max. Total Device 001 VDD Digital Supply Voltage Range 4.5 5.5 002 003 VCC Analogue Supply Voltage Range 4.5 5.5 I(VDD) Supply Current in VDD 004 I(VCC) Supply Current in VCC 005 Vc()hi Clamp Voltage hi at SI, CLK, DIS, Vc()hi = V() − V(VCC); I() = 1 mA TP, RSET 0.3 1.8 V 006 Vc()lo Clamp Voltage lo at SI, CLK, DIS, Vc()hi = V() − V(AGND); I() = -1 mA TP, RSET -1.5 0.3 V 007 Vc()hi Clamp Voltage hi at AO Vc()hi = V(AO) − V(VCC); I(AO) = 1 mA 0.3 1.5 V 008 Vc()lo Clamp Voltage lo at AO, VCC, VDD, GND Vc()lo = V() − V(AGND); I() = -1 mA -1.5 -0.3 V f(CLK) = 1 MHz f(CLK) = 5 MHz 0.39 1.85 V V mA mA 11.5 mA Photodiode Array 201 A() Radiant Sensitive Area 200 µm x 56.40 µm per Pixel 202 S(λ)max Spectral Sensitivity λ = 680 nm (see Fig. 1) 203 λar Spectral Application Range S(λar ) = 0.25 x S(λ)max (see Fig. 1) mm2 0.01128 0.5 400 A/W 980 nm 0.5 V Analogue Output AO 301 Vs()lo Saturation Voltage lo I() = 1 mA 302 Vs()hi Saturation Voltage hi Vs()hi = VCC - V(), I() = -1 mA 303 K Sensitivity λ = 680 nm, package OBGA™ LFL1C 304 V0() Offset Voltage integration time 1 ms, no illumination 800 mV 305 ∆V0() Offset Voltage Deviation during integration mode ∆V0() = V(AO)t1 − V(AO)t2, ∆t = t2 − t1 = 1 ms -250 50 mV 306 ∆V() Signal Deviation during hold mode ∆V() = V(AO)t1 − V(AO)t2, ∆t = t2 − t1 = 1 ms -150 150 mV 307 tp(CLK-AO) Settling Time 200 ns 4.4 V 1 2.88 400 Cl(AO) = 10 pF, CLK lo → hi until V(AO) = 0.98 x V(VCC) V V/pWs Power-On-Reset 801 VCCon Power-On Release by VCC 802 VCCoff Power-Down Reset by VCC 803 VCChys Hysteresis 1 VCChys = VCCon − VCCoff 0.4 V 1 2 V 100 µA 3.5 V V Bias Current Adjust RSET 901 Ibias() Permissible External Bias Current 902 Vref Reference Voltage 20 I(RSET) = Ibias 2.5 3 Input Interface SI, CLK, DIS B01 Vt()hi Threshold Voltage hi 1.4 1.8 B02 Vt()lo Threshold Voltage lo 0.9 1.2 V B03 Vt()hys Hysteresis 300 800 mV B04 I() Pull-Down Current B05 fclk Permissible Clock Frequency Vt()hys = Vt()hi − Vt()lo 10 30 50 µA 5 MHz iC-LFL1402 256x1 LINEAR IMAGE SENSOR Rev A5, Page 5/9 OPTICAL CHARACTERISTICS: Diagrams 100 % 90 80 70 60 50 40 30 20 10 400 600 800 1000 nm Figure 1: Relative spectral sensitivity OPERATING REQUIREMENTS: Logic Operating Conditions: VCC = VDD = 5 V ±10%, Tj = -25...110 °C input levels lo = 0...0.45 V, hi = 2.4 V...VCC, see Fig. 2 for reference levels Item No. Symbol Parameter Conditions Fig. Unit Min. Max. I001 tset Setup Time: SI stable before CLK lo → hi 3 50 ns I002 thold Hold Time: SI stable after CLK lo → hi 3 50 ns thold CLK V Input/Output 2.4V 2.0V SI 0.8V 0.45V t 1 0 Figure 2: Reference levels tset Figure 3: Timing diagram iC-LFL1402 256x1 LINEAR IMAGE SENSOR Rev A5, Page 6/9 DESCRIPTION OF FUNCTIONS Normal operation Following an internal power-on reset the integration and hold capacitors are discharged and the sample and hold circuit is set to sample mode. A high signal at SI and a rising edge at CLK triggers a readout cycle and with it a new integration cycle. In this process the hold capacitors of pixels 1 to 255 are switched to hold mode immediately (SNH = 1), with 254 255 256 1 2 3 Pix254 Pix255 Pix256 Pix1 Pix2 Pix3 pixel 256 (SNH256 = 1) following suit one clock pulse later. This special procedure allows all pixels to be read out with just 256 clock pulses. The integration capacitors are discharged by a one clock long reset signal (NRCI = 0) which occurs between the 2nd and 3rd falling edge of the readout clock pulse (cf. Figure 4). After the 255 pixels have been read out these are again set to sample mode (SNH = 0), likewise for pixel 256 one clock pulse later (SNH256 = 0). ... 4 255 256 Pix255 Pix256 1 2 CLK SI V(AO) ... Pix1 SNH SNH256 NRCI Integration Time Pixel 1−255 Integration Time Pixel 256 Figure 4: Readout cycle and integration sequence If prior to the 256th clock pulse a high signal occurs at SI the present readout is halted and immediately reinitiated with pixel 1. In this instance the hold ca254 255 256 1 2 3 Pix255 Pix256 Pix1 Pix2 Pix3 4 pacitors retain their old value i.e. hold mode prevails (SNH/SNH256 = 0). 1 5 2 3 4 ... 256 1 2 CLK SI V(AO) Pix254 Pix4 Pix5 Pix1 Pix2 Pix3 Pix4 ... Pix256 Pix1 SNH SNH256 NRCI Figure 5: Restarting a readout cycle With more than 256 clock pulses until the next SI signal, pixel 1 is output without entering hold mode; the out- put voltage tracks the voltage of the pixel 1 integration capacitor. iC-LFL1402 256x1 LINEAR IMAGE SENSOR Rev A5, Page 7/9 254 255 256 Pix254 Pix255 Pix256 1 2 3 Pix1 Pix2 Pix3 4 ... 255 256 257 258 259 CLK SI V(AO) Pix255 ... Pix256 Pix1 SNH SNH256 NRCI Integration Time Figure 6: Clock pulse continued without giving a new integration start signal current integration capacitor voltages are maintained. If this pin is open or switched to GND the pixel photocurrents are summed up by the integration capacitors until the next successive SI signal follows. Operation with the shutter function Integration can be stopped at any time via pin DIS, i.e. the photodiodes are disconnected from their corresponding integration capacitor when DIS is high and the 1 2 3 4 5 6 ... 255 256 1 CLK SI SNH NRCI DIS PIX SAMPLE−C Integration Disabled Integration Enabled Integration Disabled Figure 7: Defining the integration time via shutter input DIS External bias current setting In order to reduce the power consumption of the device an external reference current can be supplied to pin RSET which reduces the maximum readout frequency, however. To this end a resistor must be connected from VCC to RSET. If this pin is not used, it should be connected to GND. iC-LFL1402 256x1 LINEAR IMAGE SENSOR Rev A5, Page 8/9 REVISION HISTORY Rel. Rel. Date∗ A5 2017-08-11 ELECTRICAL CHARACTERISTICS Chapter OPERATING REQUIREMENTS Modification Page Operating conditions: Tj = -25...110 °C 4 Operating conditions: Tj = -25...110 °C 5 iC-Haus expressly reserves the right to change its products and/or specifications. An Infoletter gives details as to any amendments and additions made to the relevant current specifications on our internet website www.ichaus.com/infoletter and is automatically generated and shall be sent to registered users by email. Copying – even as an excerpt – is only permitted with iC-Haus’ approval in writing and precise reference to source. The data specified is intended solely for the purpose of product description and shall represent the usual quality of the product. In case the specifications contain obvious mistakes e.g. in writing or calculation, iC-Haus reserves the right to correct the specification and no liability arises insofar that the specification was from a third party view obviously not reliable. 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Safety-Critical Applications include, without limitation, life support devices and systems. iC-Haus products are not designed nor intended for use in military or aerospace applications or environments or in automotive applications unless specifically designated for such use by iC-Haus. iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product. Software and its documentation is provided by iC-Haus GmbH or contributors "AS IS" and is subject to the ZVEI General Conditions for the Supply of Products and Services with iC-Haus amendments and the ZVEI Software clause with iC-Haus amendments (www.ichaus.com/EULA). ∗ Release Date format: YYYY-MM-DD iC-LFL1402 256x1 LINEAR IMAGE SENSOR Rev A5, Page 9/9 ORDERING INFORMATION Type Package Order Designation iC-LFL iC-LFL OBGA™ LFL1C - iC-LFL OBGA LFL1C iC-LFL Chip Please send your purchase orders to our order handling team: Fax: +49 (0) 61 35 - 92 92 - 692 E-Mail: [email protected] For technical support, information about prices and terms of delivery please contact: iC-Haus GmbH Am Kuemmerling 18 D-55294 Bodenheim GERMANY Tel.: +49 (0) 61 35 - 92 92 - 0 Fax: +49 (0) 61 35 - 92 92 - 192 Web: http://www.ichaus.com E-Mail: [email protected] Appointed local distributors: http://www.ichaus.com/sales_partners