PD - 96030
IRF9540NSPbF
IRF9540NLPbF
HEXFET® Power MOSFET
l
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Advanced Process Technology
Ultra Low On-Resistance
150°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
Some Parameters are Different from
IRF9540NS/L
P-Channel
Lead-Free
D
RDS(on) = 117mΩ
G
Description
Features of this design are a 150°C junction
operating temperature, fast switching speed and
improved repetitive avalanche rating . These features combine to make this design an extremely
efficient and reliable device for use in a wide
variety of other applications.
VDSS = -100V
ID = -23A
S
D
D
G
D
S
G
D2Pak
IRF9540NSPbF
Absolute Maximum Ratings
D
S
TO-262
IRF9540NLPbF
G
D
S
Gate
Drain
Source
Max.
Units
ID @ TC = 25°C
Continuous Drain Current, VGS @ -10V
Parameter
-23
A
ID @ TC = 100°C
Continuous Drain Current, VGS @ -10V
-14
IDM
Pulsed Drain Current
-92
PD @TA = 25°C
Maximum Power Dissipation
3.1
PD @TC = 25°C
Maximum Power Dissipation
110
VGS
Linear Derating Factor
Gate-to-Source Voltage
0.9
± 20
W/°C
V
EAS
Single Pulse Avalanche Energy
84
mJ
IAR
Avalanche Current
-14
A
c
c
d
c
e
EAR
Repetitive Avalanche Energy
dv/dt
TJ
Peak Diode Recovery dv/dt
Operating Junction and
TSTG
Storage Temperature Range
W
11
mJ
-13
-55 to + 150
V/ns
°C
300 (1.6mm from case )
Soldering Temperature, for 10 seconds
Thermal Resistance
Parameter
RθJC
Junction-to-Case
RθJA
Junction-to-Ambient (PCB Mount, steady state)
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g
Typ.
Max.
Units
–––
1.1
°C/W
–––
40
1
09/30/05
IRF9540NS/LPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
V
Conditions
V(BR)DSS
Drain-to-Source Breakdown Voltage
-100
–––
–––
VGS = 0V, ID = -250µA
∆ΒVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
–––
-0.11
–––
V/°C Reference to 25°C, ID = -1mA
RDS(on)
Static Drain-to-Source On-Resistance
–––
–––
117
mΩ
VGS(th)
Gate Threshold Voltage
-2.0
–––
-4.0
V
VDS = VGS, ID = -250µA
gfs
Forward Transconductance
5.6
–––
–––
S
VDS = -50V, ID = -14A
IDSS
Drain-to-Source Leakage Current
µA
VDS = -100V, VGS = 0V
nA
VGS = -20V
VGS = -10V, ID = -14A
f
–––
–––
-50
–––
–––
-250
Gate-to-Source Forward Leakage
–––
–––
100
Gate-to-Source Reverse Leakage
–––
–––
-100
Qg
Total Gate Charge
–––
73
110
Qgs
Gate-to-Source Charge
–––
13
20
Qgd
Gate-to-Drain ("Miller") Charge
–––
38
57
td(on)
Turn-On Delay Time
–––
13
–––
tr
Rise Time
–––
64
–––
ID = -14A
td(off)
Turn-Off Delay Time
–––
40
–––
RG = 5.1Ω
tf
Fall Time
–––
45
–––
LD
Internal Drain Inductance
–––
4.5
–––
LS
Internal Source Inductance
–––
7.5
–––
Ciss
Input Capacitance
–––
1450
–––
Coss
Output Capacitance
–––
430
–––
VDS = -25V
Crss
Reverse Transfer Capacitance
–––
230
–––
ƒ = 1.0MHz, See Fig. 5
IGSS
VDS = -80V, VGS = 0V, TJ = 125°C
VGS = 20V
nC
ID = -14A
VDS = -80V
VGS = -10V
ns
VDD = -50V
VGS = -10V
nH
f
f
Between lead,
6mm (0.25in.)
from package
pF
and center of die contact
VGS = 0V
Source-Drain Ratings and Characteristics
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
-23
ISM
(Body Diode)
Pulsed Source Current
–––
–––
-92
c
A
(Body Diode)
VSD
Diode Forward Voltage
–––
–––
-1.6
V
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
–––
–––
140
890
210
1340
ns
nC
ton
Forward Turn-On Time
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11)
Starting TJ = 25°C, L = 0.88mH
RG = 25Ω, IAS = -14A. (See Figure 12)
ISD ≤ -14A, di/dt ≤ -620A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 150°C.
2
Conditions
MOSFET symbol
showing the
integral reverse
p-n junction diode.
TJ = 25°C, IS = -14A, VGS = 0V
f
TJ = 25°C, IF = -14A, VDD = -25V
di/dt = -100A/µs
f
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Pulse width ≤ 300µs; duty cycle ≤ 2%.
When mounted on 1" square PCB (FR-4or G-10
Material). For recommended footprint and soldering
techniques refer to application note #AN-994.
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IRF9540NS/LPbF
1000
1000
100
BOTTOM
VGS
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
-4.5V
TOP
-ID, Drain-to-Source Current (A)
-ID, Drain-to-Source Current (A)
TOP
10
1
-4.5V
100
BOTTOM
VGS
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
-4.5V
10
-4.5V
1
≤60µs PULSE WIDTH
≤60µs PULSE WIDTH
Tj = 25°C
Tj = 150°C
0.1
0.1
0.1
1
10
100
0.1
-VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
10
100
Fig 2. Typical Output Characteristics
100
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
TJ = 25°C
-ID, Drain-to-Source Current (A)
1
-VDS, Drain-to-Source Voltage (V)
TJ = 150°C
10
1
VDS = -50V
≤60µs PULSE WIDTH
0.1
ID = -14A
VGS = -10V
1.5
1.0
0.5
2
4
6
8
10
12
-VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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14
-60 -40 -20 0
20 40 60 80 100 120 140 160
TJ , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
vs. Temperature
3
IRF9540NS/LPbF
10000
20
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
-VGS, Gate-to-Source Voltage (V)
ID= -14A
C, Capacitance(pF)
Coss = Cds + Cgd
Ciss
1000
Coss
Crss
100
VDS = -80V
VDS = -50V
VDS = -20V
16
12
8
4
0
1
10
100
0
20
-VDS , Drain-to-Source Voltage (V)
1000
-ID, Drain-to-Source Current (A)
-ISD , Reverse Drain Current (A)
TJ = 150°C
10
TJ = 25°C
VGS = 0V
0.8
1.0
1.2
1.4
1.6
1.8
-VSD , Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
100
120
OPERATION IN THIS AREA
LIMITED BY R DS (on)
100
10
100µsec
1msec
10msec
1
Tc = 25°C
Tj = 150°C
Single Pulse
0.1
0.1
0.6
80
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
100
0.4
60
QG, Total Gate Charge (nC)
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
1
40
2.0
1
10
100
1000
-VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF9540NS/LPbF
RD
VDS
VGS
24
D.U.T.
RG
-
+
-ID, Drain Current (A)
20
VDD
-10V
16
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
12
Fig 10a. Switching Time Test Circuit
8
td(on)
tr
t d(off)
tf
VGS
10%
4
0
25
50
75
100
125
150
90%
VDS
TC , Case Temperature (°C)
Fig 10b. Switching Time Waveforms
Fig 9. Maximum Drain Current vs.
Case Temperature
Thermal Response ( Z thJC )
10
1
D = 0.50
0.20
0.10
0.1
τJ
0.05
0.02
0.01
0.01
R1
R1
τJ
τ1
R2
R2
Ri (°C/W)
R3
R3
τC
τ2
τ1
τ2
Ci= τi/Ri
Ci
i/Ri
τ3
τ3
τi (sec)
0.1737838 0.0000610
0.4335992 0.0019590
0.4921007 0.0260060
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF9540NS/LPbF
L
VDS
D.U.T
RG
-20V
IAS
tp
VDD
A
DRIVER
0.01Ω
15V
Fig 12a. Unclamped Inductive Test Circuit
I AS
EAS , Single Pulse Avalanche Energy (mJ)
350
ID
-6.7A
-9.6A
BOTTOM -14A
TOP
300
250
200
150
100
50
0
25
50
75
100
125
150
Starting TJ , Junction Temperature (°C)
Fig 13. Maximum Avalanche Energy
vs. Drain Current
tp
V(BR)DSS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
QG
-10V
QGS
.2µF
.3µF
QGD
D.U.T.
+VDS
VGS
VG
-3mA
Charge
Fig 14a. Basic Gate Charge Waveform
6
50KΩ
12V
IG
ID
Current Sampling Resistors
Fig 14b. Gate Charge Test Circuit
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IRF9540NS/LPbF
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T*
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
RG
• dv/dt controlled by RG
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VGS
*
+
-
VDD
Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
[VGS=10V ] ***
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
[VDD]
Forward Drop
Inductor Curent
Ripple ≤ 5%
[ ISD]
*** VGS = 5.0V for Logic Level and 3V Drive Devices
Fig 15. For P-Channel HEXFETS
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7
IRF9540NS/LPbF
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information
T HIS IS AN IRF530S WIT H
LOT CODE 8024
AS S EMBLED ON WW 02, 2000
IN THE AS S EMBLY LINE "L"
INTERNAT IONAL
RECTIFIER
LOGO
AS S EMBLY
LOT CODE
PART NUMBER
F530S
DAT E CODE
YEAR 0 = 2000
WEEK 02
LINE L
OR
INT ERNATIONAL
RECT IFIER
LOGO
AS S EMBLY
LOT CODE
8
PART NUMBER
F530S
DATE CODE
P = DES IGNAT ES LEAD - FREE
PRODUCT (OPT IONAL)
YEAR 0 = 2000
WEEK 02
A = AS S EMBLY S IT E CODE
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IRF9540NS/LPbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
EXAMPLE: THIS IS AN IRL3103L
LOT CODE 1789
AS S EMBLED ON WW 19, 1997
IN T HE AS S EMBLY LINE "C"
Note: "P" in assembly line
pos ition indicates "Lead-Free"
INTERNATIONAL
RECT IFIER
LOGO
AS S EMBLY
LOT CODE
PART NUMBER
DATE CODE
YEAR 7 = 1997
WEEK 19
LINE C
OR
INT ERNATIONAL
RECT IF IER
LOGO
AS S EMBLY
LOT CODE
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PART NUMBER
DATE CODE
P = DES IGNATES LEAD-FREE
PRODUCT (OPTIONAL)
YEAR 7 = 1997
WEEK 19
A = AS S EMBLY S ITE CODE
9
IRF9540NS/LPbF
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
11.60 (.457)
11.40 (.449)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
10.90 (.429)
10.70 (.421)
1.75 (.069)
1.25 (.049)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
3
30.40 (1.197)
MAX.
4
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 09/05
10
www.irf.com
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/