Precision, Dual-Channel, JFET Input, Rail-to-Rail Instrumentation Amplifier AD8224 Data Sheet APPLICATIONS OUT1 OUT2 –VS FUNCTIONAL BLOCK DIAGRAM 16 15 14 13 AD8224 1 12 –IN2 RG1 2 11 RG2 RG1 3 10 RG2 9 +IN2 4 6 7 8 06286-001 +VS 5 –VS +IN1 REF2 –IN1 REF1 Two channels in a small 4 mm × 4 mm LFCSP Custom LFCSP package with hidden paddle Permits routing and vias underneath package Allows full bias current performance Low input currents 10 pA maximum input bias current (B grade) 0.6 pA maximum input offset current (B grade) High CMRR 100 dB CMRR (minimum), G = 10 (B grade) 90 dB CMRR (minimum) to 10 kHz, G = 10 (B grade) Excellent ac specifications and low power 1.5 MHz bandwidth (G = 1) 14 nV/√Hz input noise (1 kHz) Slew rate: 2 V/µs 750 µA quiescent current per amplifier Versatility Rail-to-rail output Input voltage range to below negative supply rail 4 kV ESD protection 4.5 V to 36 V single supply ±2.25 V to ±18 V dual supply Gain set with single resistor (G = 1 to 1000) +VS FEATURES Figure 1. Table 1. In Amps and Difference Amplifiers by Category High Perform AD82201 AD8221 AD8222 1 Low Cost AD85531 AD6231 High Voltage AD628 AD629 Mil Grade AD620 AD621 AD524 AD526 AD624 Low Power AD6271 Digital Gain AD82311 AD8250 AD8251 AD85551 AD85561 AD85571 Rail-to-rail output. Medical instrumentation Precision data acquisition Transducer interfaces Differential drives for high resolution input ADCs Remote sensors GENERAL DESCRIPTION The AD8224 is the first single-supply, JFET input instrumentation amplifier available in the space-saving 16-lead, 4 mm × 4 mm LFCSP. It requires the same board area as a typical single instrumentation amplifier yet doubles the channel density and offers a lower cost per channel without compromising performance. Designed to meet the needs of high performance, portable instrumentation, the AD8224 has a minimum common-mode rejection ratio (CMRR) of 86 dB at dc and a minimum CMRR of 80 dB at 10 kHz for G = 1. Maximum input bias current is 10 pA and typically remains below 300 pA over the entire industrial temperature range. Despite the JFET inputs, the AD8224 typically has a noise corner of only 10 Hz. With the proliferation of mixed-signal processing, the number of power supplies required in each system has grown. Designed Rev. D to alleviate this problem, the AD8224 can operate on a ±18 V dual supply, as well as on a single +5 V supply. The device’s railto-rail output stage maximizes dynamic range on the low voltage supplies common in portable applications. Its ability to run on a single 5 V supply eliminates the need for higher voltage, dual supplies. The AD8224 draws 750 µA of quiescent current per amplifier, making it ideal for battery powered devices. In addition, the AD8224 can be configured as a single-channel, differential output, instrumentation amplifier. Differential outputs provide high noise immunity, which can be useful when the output signal must travel through a noisy environment, such as with remote sensors. The configuration can also be used to drive differential input ADCs. For a single-channel version, use the AD8220. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2007–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD8224* Product Page Quick Links Last Content Update: 11/01/2016 Comparable Parts Reference Materials View a parametric search of comparable parts • AD8224 Evaluation Board Technical Articles • Auto-Zero Amplifiers • Biopotential Electrode Sensors in ECG/EEG/EMG Systems • High-performance Adder Uses Instrumentation Amplifiers Documentation Design Resources Application Notes • AN-1401: Instrumentation Amplifier Common-Mode Range: The Diamond Plot Data Sheet • AD8224: Precision, Dual-Channel, JFET Input, Rail-to-Rail Instrumentation Amplifier Data Sheet Technical Books • A Designer's Guide to Instrumentation Amplifiers, 3rd Edition, 2006 • • • • Evaluation Kits Tools and Simulations • AD8224 SPICE Macro-Model AD8224 Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints Discussions View all AD8224 EngineerZone Discussions Sample and Buy Visit the product page to see pricing options Technical Support Submit a technical question or find your regional support number * This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. 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AD8224 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Layout .......................................................................................... 22 Applications ....................................................................................... 1 Solder Wash................................................................................. 23 Functional Block Diagram .............................................................. 1 Input Bias Current Return Path ............................................... 23 General Description ......................................................................... 1 Input Protection ......................................................................... 23 Revision History ............................................................................... 2 RF Interference ........................................................................... 24 Specifications..................................................................................... 3 Common-Mode Input Voltage Range ..................................... 24 Absolute Maximum Ratings ............................................................ 9 Applications Information .............................................................. 25 Thermal Resistance ...................................................................... 9 Driving an ADC ......................................................................... 25 ESD Caution .................................................................................. 9 Differential Output .................................................................... 25 Pin Configurations and Function Descriptions ......................... 10 Driving a Differential Input ADC ............................................ 26 Typical Performance Characteristics ........................................... 12 Driving Cabling .......................................................................... 26 Theory of Operation ...................................................................... 21 Outline Dimensions ....................................................................... 27 Gain Selection ............................................................................. 21 Ordering Guide .......................................................................... 28 Reference Terminal .................................................................... 22 REVISION HISTORY 4/16—Rev. C to Rev. D Changed CP-16-13 to CP-16-26 .................................. Throughout Changes to Figure 3 ........................................................................ 10 Added Figure 4 and Table 12; Renumbered Sequentially ......... 11 Updated Outline Dimensions ....................................................... 27 Changes to Ordering Guide .......................................................... 28 12/13—Rev. B to Rev. C Changes to Input Current Parameter and Power Supply Parameter, Table 2............................................................................. 3 Changes to Table 3 and Table 4 ....................................................... 5 Changes to Input Current Parameter and Power Supply Parameter, Table 5............................................................................. 6 Changes to Table 9 ............................................................................ 9 Changes to Figure 53 ...................................................................... 19 Change to Theory of Operation Section ..................................... 20 Change to Exposed Paddle Package Section ............................... 21 Change to Input Protection Section ............................................. 22 Updated Outline Dimensions (Dimensions Not Changed, Minimums and Maximums Added) ............................................ 26 5/10—Rev. A to Rev. B Changes to Features Section............................................................ 1 Added Table 10 ................................................................................. 9 Changes to Figure 3 and Table 11 ................................................. 10 Added Hidden Paddle Package Section and Exposed Paddle Package Section and Figure 58 ..................................................... 21 Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 27 4/07—Rev. 0 to Rev. A Changes to Features, General Description, and Figure 1 .............1 Changes to Table 2.............................................................................3 Changes to Table 3 and Table 4........................................................5 Changes to Table 5.............................................................................6 Changes to Table 6 and Table 7........................................................8 Changes to Figure 2 ...........................................................................9 Changes to Figure 3 ........................................................................ 10 Inserted Figure 4, Figure 5, and Figure 6; Renumbered Sequentially ..................................................................................... 11 Changes to Figure 7 ........................................................................ 11 Changes to Figure 20 and Figure 21 ............................................ 13 Changes to Figure 28...................................................................... 15 Changes to Theory of Operation and Figure 55 ........................ 20 Changes to Ordering Guide .......................................................... 26 1/07—Revision 0: Initial Version Rev. D | Page 2 of 28 Data Sheet AD8224 SPECIFICATIONS VS+ = +15 V, VS− = −15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 2 kΩ1, unless otherwise noted. Table 2 displays the specifications for an individual instrumentation amplifier configured for a single-ended output or dual instrumentation amplifiers configured for differential outputs as shown in Figure 64. Table 2. Individual Amplifier in Single-Ended Configuration or Dual Amplifiers in Differential Output Configuration2, VS = ±15 V Parameter COMMON-MODE REJECTION RATIO (CMRR) CMRR DC to 60 Hz with 1 kΩ Source Imbalance G=1 G = 10 G = 100 G = 1000 CMRR at 10 kHz G=1 G = 10 G = 100 G = 1000 NOISE Voltage Noise, 1 kHz Input Voltage Noise, eni Output Voltage Noise, eno RTI, 0.1 Hz to 10 Hz G=1 Test Conditions/ Comments Min VOLTAGE OFFSET Input Offset, VOSI Average TC Output Offset, VOSO Average TC Offset RTI vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current Over Temperature3 Input Offset Current Over Temperature3 REFERENCE INPUT RIN IIN Voltage Range Gain to Output Min B Grade Typ Max Unit VCM = ±10 V 78 94 94 94 86 100 100 100 dB dB dB dB 74 84 84 84 80 90 90 90 dB dB dB dB VCM = ±10 V RTI noise = √(eni2 + (eno/G)2) VIN+, VIN− = 0 V VIN+, VIN− = 0 V G = 1000 Current Noise A Grade Typ Max f = 1 kHz 14 90 14 90 17 100 nV/√Hz nV/√Hz 5 5 0.8 0.8 µV p-p 1 1 fA/√Hz µV p-p RTI VOS = (VOSI) + (VOSO/G) 300 10 1200 10 T = −40°C to +85°C T = −40°C to +85°C VS = ±5 V to ±15 V 86 96 96 96 175 5 800 5 86 100 100 100 dB dB dB dB 25 T = −40°C to +85°C 10 300 300 2 T = −40°C to +85°C 0.6 5 5 40 VIN+, VIN− = 0 V −VS 1± 0.0001 Rev. D | Page 3 of 28 40 70 +VS µV µV/°C µV µV/°C 70 +VS −VS 1± 0.0001 pA pA pA pA kΩ µA V V/V AD8224 Parameter GAIN Gain Range Gain Error G=1 G = 10 G = 100 G = 1000 Gain Nonlinearity G=1 G = 10 G = 100 G = 1000 G=1 G = 10 G = 100 G=1000 Gain vs. Temperature G=1 G > 10 INPUT Impedance (Pin to Ground)4 Input Operating Voltage Range5 Over Temperature OUTPUT Output Swing Over Temperature Output Swing Over Temperature Short-Circuit Current POWER SUPPLY Operating Range Quiescent Current (Per Amplifier) Over Temperature TEMPERATURE RANGE For Specified Performance Operational7 Data Sheet Test Conditions/ Comments G = 1 + (49.4 kΩ/RG) Min A Grade Typ Max 1 1000 Min B Grade Typ Max 1 Unit 1000 V/V 0.04 0.2 0.2 0.2 % % % % VOUT = ±10 V 0.06 0.3 0.3 0.3 VOUT = −10 V to +10 V RL = 10 kΩ RL = 10 kΩ RL = 10 kΩ RL = 10 kΩ RL = 2 kΩ RL = 2 kΩ RL = 2 kΩ RL = 2 kΩ 8 5 15 100 15 12 35 180 15 10 25 150 20 20 50 250 8 5 15 100 15 12 35 180 15 10 25 150 20 20 50 250 ppm ppm ppm ppm ppm ppm ppm ppm 3 10 −50 2 5 −50 ppm/°C ppm/°C 104||5 104||5 VS = ±2.25 V to ±18 V for dual supplies T = −40°C to +85°C −VS − 0.1 +VS − 2 −VS − 0.1 +VS − 2 GΩ||pF V −VS − 0.1 +VS − 2.1 −VS − 0.1 +VS − 2.1 V RL = 2 kΩ T = −40°C to +85°C RL = 10 kΩ T = −40°C to +85°C −14.25 −14.3 −14.7 −14.6 +14.25 +14.1 +14.7 +14.6 −14.25 −14.3 −14.7 −14.6 +14.25 +14.1 +14.7 +14.6 V V V V mA ±18 800 900 V µA µA +85 +125 °C °C 15 ±2.256 750 850 T = −40°C to +85°C −40 −40 1 15 ±18 800 900 ±2.256 +85 +125 −40 −40 750 850 When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ. Refers to the differential configuration shown in Figure 64. Refer to Figure 15 and Figure 16 for the relationship between input current and temperature. 4 Differential and common-mode input impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2. 5 The AD8224 can operate up to a diode drop below the negative supply; however, the bias current increases sharply. The input voltage range reflects the maximum allowable voltage where the input bias current is within the specification. 6 At this supply voltage, ensure that the input common-mode voltage is within the input voltage range specification. 7 The AD8224 is characterized from −40°C to +125°C. See the Typical Performance Characteristics section for expected operation in this temperature range. 2 3 Rev. D | Page 4 of 28 Data Sheet AD8224 VS+ = +15 V, VS− = −15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 2 kΩ1, unless otherwise noted. Table 3 displays the specifications for the dynamic performance of each individual instrumentation amplifier. Table 3. Dynamic Performance of Each Individual Amplifier—Single-Ended Output Configuration, VS = ±15 V Parameter DYNAMIC RESPONSE Small Signal Bandwidth −3 dB G=1 G = 10 G = 100 G =1000 Settling Time 0.01% G=1 G = 10 G = 100 G =1000 Settling Time 0.001% G=1 G = 10 G = 100 G =1000 Slew Rate G = 1 to 100 1 Test Conditions/ Comments Min A Grade Typ Max Min B Grade Typ Max Unit 1500 800 120 14 1500 800 120 14 kHz kHz kHz kHz 5 4.3 8.1 58 5 4.3 8.1 58 µs µs µs µs 6 4.6 9.6 74 6 4.6 9.6 74 µs µs µs µs ΔVO = ±10 V step ΔVO = ±10 V step 2 2 V/µs When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ. VS+ = +15 V, VS− = −15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 2 kΩ1, unless otherwise noted. Table 4 displays the specifications for the dynamic performance of both amplifiers when used in the differential output configuration shown in Figure 64. Table 4. Dynamic Performance of Both Amplifiers—Differential Output Configuration2, VS = ±15 V Parameter DYNAMIC RESPONSE Small Signal Bandwidth −3 dB G=1 G = 10 G = 100 G =1000 Settling Time 0.01% G=1 G = 10 G = 100 G =1000 Settling Time 0.001% G=1 G = 10 G = 100 G =1000 Slew Rate G = 1 to 100 Test Conditions/ Comments Min A Grade Typ Max Min B Grade Typ Max Unit 1500 800 120 14 1500 800 120 14 kHz kHz kHz kHz 5 4.3 8.1 58 5 4.3 8.1 58 µs µs µs µs 6 4.6 9.6 74 6 4.6 9.6 74 µs µs µs µs ΔVO = ±10 V step ΔVO = ±10 V step 2 1 2 When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ. 2 Refers to the differential configuration shown in Figure 64. Rev. D | Page 5 of 28 V/µs AD8224 Data Sheet VS + = 5 V, VS− = 0 V, VREF = 2.5 V, TA = 25°C, G = 1, RL = 2 kΩ1, unless otherwise noted. Table 5 displays the specifications for an individual instrumentation amplifier configured for a single-ended output or dual instrumentation amplifiers configured for differential outputs as shown in Figure 64. Table 5. Individual Amplifier in Single-Ended Configuration or Dual Amplifiers in Differential Output Configuration2, VS =+5 V Parameter COMMON-MODE REJECTION RATIO (CMRR) CMRR DC to 60 Hz with 1 kΩ Source Imbalance G=1 G = 10 G = 100 G = 1000 CMRR at 10 kHz G=1 G = 10 G = 100 G = 1000 NOISE Voltage Noise, 1 kHz Input Voltage Noise, eni Output Voltage Noise, eno RTI, 0.1 Hz to 10 Hz G=1 G = 1000 Current Noise VOLTAGE OFFSET Input Offset, VOSI Average TC Output Offset, VOSO Average TC Offset RTI vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current Over Temperature3 Input Offset Current Over Temperature3 REFERENCE INPUT RIN IIN Voltage Range Gain to Output Test Conditions/ Comments Min A Grade Typ Max Min B Grade Typ Max Unit VCM = 0 to 2.5 V 78 94 94 94 86 100 100 100 dB dB dB dB 74 84 84 84 80 90 90 90 dB dB dB dB RTI noise = √(eni2 + (eno/G)2) VS = ±2.5 V VIN+, VIN− = 0 V, VREF = 0 V VIN+, VIN− = 0 V, VREF = 0 V f = 1 kHz RTI VOS = (VOSI) + (VOSO/G) 14 90 14 90 5 0.8 1 5 0.8 1 300 10 1200 10 T = −40°C to +85°C T = −40°C to +85°C 86 96 96 96 250 5 800 5 T = −40°C to +85°C 5 10 300 2 0.6 5 40 VIN+, VIN− = 0 V 40 70 +VS −VS 1± 0.0001 µV µV/°C µV µV/°C dB dB dB dB 25 300 nV/√Hz nV/√Hz µV p-p µV p-p fA/√Hz 86 100 100 100 T = −40°C to +85°C Rev. D | Page 6 of 28 17 100 70 +VS −VS 1± 0.0001 pA pA pA pA kΩ µA V V/V Data Sheet Parameter GAIN Gain Range Gain Error G=1 G = 10 G = 100 G = 1000 Nonlinearity G=1 G = 10 G = 100 G = 1000 G=1 G = 10 G = 100 G = 1000 Gain vs. Temperature G=1 G > 10 INPUT Impedance (Pin to Ground)4 Input Voltage Range5 Over Temperature OUTPUT Output Swing Over Temperature Output Swing Over Temperature Short-Circuit Current POWER SUPPLY Operating Range Quiescent Current (Per Amplifier) Over Temperature TEMPERATURE RANGE For Specified Performance Operational6 AD8224 Test Conditions/ Comments G = 1 + (49.4 kΩ/RG) Min A Grade Typ Max 1 VOUT = 0.3 V to 2.9 V VOUT = 0.3 V to 3.8 V VOUT = 0.3 V to 3.8 V VOUT = 0.3 V to 3.8 V VOUT = 0.3 V to 2.9 V for G = 1 VOUT = 0.3 V to 3.8 V for G > 1 RL = 10 kΩ RL = 10 kΩ RL = 10 kΩ RL = 10 kΩ RL = 2 kΩ RL = 2 kΩ RL = 2 kΩ RL = 2 kΩ 1000 Min B Grade Typ Max 1 0.06 0.3 0.3 0.3 Unit 1000 V/V 0.04 0.2 0.2 0.2 % % % % 35 35 50 90 35 35 50 175 50 50 75 115 50 50 75 200 35 35 50 90 35 35 50 175 50 50 75 115 50 50 75 200 ppm ppm ppm ppm ppm ppm ppm ppm 3 10 −50 2 5 −50 ppm/°C ppm/°C GΩ||pF V V 104||6 104||6 T = −40°C to +85°C −0.1 −0.1 +VS − 2 +VS − 2.1 −0.1 −0.1 +VS − 2 +VS − 2.1 RL = 2 kΩ T = −40°C to +85°C RL = 10 kΩ T = −40°C to +85°C 0.25 0.3 0.15 0.2 4.75 4.70 4.85 4.80 0.25 0.3 0.15 0.2 4.75 4.70 4.85 4.80 V V V V mA 36 800 900 V µA µA +85 +125 °C °C 15 4.5 750 850 T = −40°C to +85°C −40 −40 1 15 36 800 900 4.5 +85 +125 −40 −40 750 850 When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ. Refers to the differential configuration shown in Figure 64. 3 Refer to Figure 15 and Figure 16 for the relationship between input current and temperature. 4 Differential and common-mode impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2. 5 The AD8224 can operate up to a diode drop below the negative supply, but the bias current increases sharply. The input voltage range reflects the maximum allowable voltage where the input bias current is within the specification. 6 The AD8224 is characterized from −40°C to +125°C. See the Typical Performance Characteristics section for expected operation in that temperature range. 2 Rev. D | Page 7 of 28 AD8224 Data Sheet VS + = 5 V, VS− = 0 V, VREF = 2.5 V, TA = 25°C, G = 1, RL = 2 kΩ1, unless otherwise noted. Table 6 displays the specifications for the dynamic performance of each individual instrumentation amplifier. Table 6. Dynamic Performance of Each Individual Amplifier—Single-Ended Output Configuration, VS = +5 V Parameter DYNAMIC RESPONSE Small Signal Bandwidth −3 dB G=1 G = 10 G = 100 G =1000 Settling Time 0.01% G=1 G = 10 G = 100 G =1000 Settling Time 0.001% G=1 G = 10 G = 100 G =1000 Slew Rate G = 1 to 100 1 Test Conditions/ Comments Min A Grade Typ Max B Grade Typ Min Max Unit 1500 800 120 14 1500 800 120 14 kHz kHz kHz kHz ΔVO = 3 V step ΔVO = 4 V step ΔVO = 4 V step ΔVO = 4 V step 2.5 2.5 7.5 60 2.5 2.5 7.5 60 µs µs µs µs ΔVO = 3 V step ΔVO = 4 V step ΔVO = 4 V step ΔVO = 4 V step 3.5 3.5 8.5 75 3.5 3.5 8.5 75 µs µs µs µs 2 2 V/µs When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ. VS + = 5 V, VS− = 0 V, VREF = 2.5 V, TA = 25°C, G = 1, RL = 2 kΩ1 unless otherwise noted. Table 7 displays the specifications for the dynamic performance of both amplifiers when used in the differential output configuration shown in Figure 64. Table 7. Dynamic Performance of Both Amplifiers—Differential Output Configuration2, VS = +5 V Parameter DYNAMIC RESPONSE Small Signal Bandwidth −3 dB G=1 G = 10 G = 100 G =1000 Settling Time 0.01% G=1 G = 10 G = 100 G =1000 Settling Time 0.001% G=1 G = 10 G = 100 G =1000 Slew Rate G = 1 to 100 Test Conditions/Comments Min A Grade Typ Max Min B Grade Typ Max Unit 1500 800 120 14 1500 800 120 14 kHz kHz kHz kHz ΔVO = 3 V step ΔVO = 4 V step ΔVO = 4 V step ΔVO = 4 V step 2.5 2.5 7.5 60 2.5 2.5 7.5 60 µs µs µs µs ΔVO = 3 V step ΔVO = 4 V step ΔVO = 4 V step 3.5 3.5 8.5 3.5 3.5 8.5 µs µs µs ΔVO = 4 V step 75 75 µs 2 1 2 When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ. 2 Refers to the differential configuration shown in Figure 64. Rev. D | Page 8 of 28 V/µs Data Sheet AD8224 ABSOLUTE MAXIMUM RATINGS Maximum Power Dissipation Rating ±18 V See Figure 2 Indefinite1 ±VS ±VS −65°C to +130°C −40°C to +125°C 300°C 130°C 130°C 4 kV 1 kV 0.4 kV The maximum safe power dissipation for the AD8224 is limited by the associated rise in junction temperature (TJ) on the die. At approximately 130°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the amplifiers. Exceeding a temperature of 130°C for an extended period can result in a loss of functionality. Figure 2 shows the maximum safe power dissipation in the package vs. the ambient temperature for the LFCSP on a 4-layer JEDEC standard board. 4.0 1 Assumes the load is referenced to midsupply. 2 Temperature for specified performance is −40°C to +85°C. For performance to 125°C, see the Typical Performance Characteristics section. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. 3.5 3.0 θJA = 48°C/W WHEN THERMAL PAD IS SOLDERED TO BOARD 2.5 2.0 1.5 1.0 0.5 θJA = 86°C/W WHEN THERMAL PAD IS NOT SOLDERED TO BOARD 0 –60 –40 –20 0 20 40 60 80 100 120 140 AMBIENT TEMPERATURE (°C) THERMAL RESISTANCE Figure 2. Maximum Power Dissipation vs. Ambient Temperature Table 9. Exposed Pad Package CP-16-26: LFCSP, EPAD Soldered to Board CP-16-26: LFCSP, EPAD Not Soldered to Board θJA 48 86 Unit °C/W °C/W ESD CAUTION Table 10. Hidden Paddle Package CP-16-19: LFCSP θJA 86 Unit °C/W The θJA values in Table 9 and Table 10 assume a 4-layer JEDEC standard board. If the thermal pad is soldered to the board, it is also assumed it is connected to a plane. θJC at the exposed pad is 4.4°C/W. Rev. D | Page 9 of 28 06286-002 Parameter Supply Voltage Power Dissipation Output Short-Circuit Current Input Voltage (Common Mode) Differential Input Voltage Storage Temperature Range Operating Temperature Range2 Lead Temperature (Soldering, 10 sec) Junction Temperature Package Glass Transition Temperature ESD (Human Body Model) ESD (Charge Device Model) ESD (Machine Model) MAXIMUM POWER DISSIPATION (W) Table 8. AD8224 Data Sheet 16 +VS 15 OUT1 14 OUT2 13 –VS PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 12 –IN2 11 RG2 10 RG2 9 +IN2 –VS 8 TOP VIEW +VS 5 +IN1 4 AD8224 REF1 6 REF2 7 RG1 2 RG1 3 06286-003 PIN 1 INDICATOR –IN1 1 Figure 3. 16-Lead LFCSP Pin Configuration with Hidden Paddle Table 11. Pin Function Descriptions Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic −IN1 RG1 RG1 +IN1 +VS REF1 REF2 −VS +IN2 RG2 RG2 −IN2 −VS OUT2 OUT1 +VS Description Negative Input Instrumentation Amplifier (In-Amp) 1 Gain Resistor In-Amp 1 Gain Resistor In-Amp 1 Positive Input In-Amp 1 Positive Supply Reference Adjust In-Amp 1 Reference Adjust In-Amp 2 Negative Supply Positive Input In-Amp 2 Gain Resistor In-Amp 2 Gain Resistor In-Amp 2 Negative Input In-Amp 2 Negative Supply Output In-Amp 2 Output In-Amp 1 Positive Supply Rev. D | Page 10 of 28 13 –VS –IN1 1 12 –IN2 RG1 2 AD8224 11 RG2 RG1 3 TOP VIEW (Not to Scale) 10 RG2 9 +IN2 –VS 8 REF2 7 +VS 5 REF1 6 +IN1 4 NOTES 1. THE EXPOSED THERMAL PAD IS CONNECTED INTERNALLY TO +VS. THE PAD CAN EITHER BE LEFT UNCONNECTED OR CONNECTED TO THE POSITIVE SUPPLY RAIL. 06286-104 14 OUT2 16 +VS AD8224 15 OUT1 Data Sheet Figure 4. 16-Lead LFCSP Pin Configuration with Exposed Pad Table 12. Pin Function Descriptions Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic −IN1 RG1 RG1 +IN1 +VS REF1 REF2 −VS +IN2 RG2 RG2 −IN2 −VS OUT2 OUT1 +VS EPAD Description Negative Input In-Amp 1. Gain Resistor In-Amp 1. Gain Resistor In-Amp 1. Positive Input In-Amp 1. Positive Supply. Reference Adjust In-Amp 1. Reference Adjust In-Amp 2. Negative Supply. Positive Input In-Amp 2. Gain Resistor In-Amp 2. Gain Resistor In-Amp 2. Negative Input In-Amp 2. Negative Supply. Output In-Amp 2. Output In-Amp 1. Positive Supply. Exposed Pad. The exposed thermal pad is connected internally to +VS. The pad can either be left unconnected or connected to the positive supply rail. Rev. D | Page 11 of 28 AD8224 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 25°C, VS = ±15 V, RL =10 kΩ, unless otherwise noted. 1000 400 VOLTAGE NOISE RTI (nV/ Hz) NUMBER OF UNITS 350 300 250 200 150 100 GAIN = 100 BANDWIDTH ROLL-OFF 100 GAIN = 1 GAIN = 10 GAIN = 100/GAIN = 1000 10 GAIN = 1000 BANDWIDTH ROLL-OFF 0 –20 0 20 40 CMRR (µV/V) 1 06286-070 –40 1 10 100 1k 100k 10k FREQUENCY (Hz) 06286-009 50 Figure 8. Voltage Spectral Density vs. Frequency Figure 5. Typical Distribution of CMRR (G = 1) XX 400 300 250 XXX (X) NUMBER OF UNITS 350 200 150 100 50 0 100 200 VOSI (µV) 1s/DIV XX XX XX 06286-010 –100 06286-071 –200 XX 06286-011 5µV/DIV 0 XXX (X) Figure 6. Typical Distribution of Input Offset Voltage Figure 9. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1) XX XXX (X) 300 200 100 0 –1200 1µV/DIV –900 –600 –300 0 300 600 900 VOSO (µV) 1200 06286-072 NUMBER OF UNITS 400 1s/DIV XX XX XXX (X) Figure 10. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000) Figure 7. Typical Distribution of Output Offset Voltage Rev. D | Page 12 of 28 Data Sheet AD8224 0.3 4.5 INPUT BIAS CURRENT (pA) 3.5 3.0 2.5 2.0 1.5 1.0 INPUT OFFSET CURRENT ±5 7 5 –15.1V 3 0.1 INPUT BIAS CURRENT ±15 –0.1 INPUT BIAS CURRENT ±5 –0.3 –5.1V 1 INPUT OFFSET CURRENT (pA) 4.0 DELTA VOSI (µV) INPUT OFFSET CURRENT ±15 9 0.5 10 TIME (s) 100 1000 –1 –16 –12 –8 –4 0 4 8 –0.5 16 12 06286-068 1 06286-012 0 0.1 COMMON-MODE VOLTAGE (V) Figure 14. Input Bias Current and Input Offset Current vs. Common-Mode Voltage Figure 11. Change in Input Offset Voltage vs. Warmup Time 150 GAIN = 1000 GAIN = 10 90 GAIN = 1 70 50 IBIAS 100p 10p IOS 1p 0.1p 30 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) –50 06286-013 10 1n –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 06286-016 PSRR (dB) BANDWIDTH LIMITED GAIN = 100 110 10n INPUT BIAS CURRENT (A) 130 Figure 15. Input Bias Current and Offset Current vs. Temperature, VS = ±15 V, VREF = 0 V Figure 12. Positive PSRR vs. Frequency, RTI 150 10n 130 1n 90 CURRENT (A) GAIN = 1000 GAIN = 1 70 IBIAS 100p 10p GAIN = 10 IOS 1p 50 GAIN = 100 10 1 10 100 1k 10k 100k FREQUENCY (Hz) 1M –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) Figure 16. Input Bias Current and Offset Current vs. Temperature, VS = 5 V, VREF = 2.5 V Figure 13. Negative PSRR vs. Frequency, RTI Rev. D | Page 13 of 28 06286-017 0.1p 30 06286-014 PSRR (dB) 110 AD8224 Data Sheet 70 160 60 140 GAIN = 1000 BANDWIDTH LIMITED GAIN = 100 40 GAIN = 100 30 GAIN = 10 GAIN (dB) CMRR (dB) 120 100 GAIN = 1000 50 GAIN = 1 20 GAIN = 10 10 0 80 GAIN = 1 –10 60 –20 40 –40 100 100 1000 10000 100000 FREQUENCY (Hz) 1k 10k 100k 06286-021 10 06286-018 –30 10M 1M FREQUENCY (Hz) Figure 20. Gain vs. Frequency Figure 17. CMRR vs. Frequency 160 GAIN = 100 GAIN = 10 XXX CMRR (dB) 120 100 GAIN = 1 BANDWIDTH LIMITED 80 NONLINEARITY (10ppm/DIV) 140 GAIN = 1000 RLOAD = 2kΩ RLOAD = 10kΩ 06286-022 60 1 10 100 1000 10000 100000 FREQUENCY (Hz) 06286-019 VS = ±15V 40 –10 –8 –6 –4 –2 0 2 4 6 8 10 OUTPUT VOLTAGE (V) Figure 21. Gain Nonlinearity, G = 1 Figure 18. CMRR vs. Frequency, 1 kΩ Source Imbalance 7 XXX 4 3 2 RLOAD = 2kΩ RLOAD = 10kΩ 0 –50 06286-023 1 VS = ±15V –30 –10 10 30 50 70 90 110 TEMPERATURE (°C) 130 06286-020 CMRR (µV/V) 5 NONLINEARITY (10ppm/DIV) 6 Figure 19. Change in CMRR vs. Temperature, G = 1 –10 –8 –6 –4 –2 0 2 4 OUTPUT VOLTAGE (V) Figure 22. Gain Nonlinearity, G = 10 Rev. D | Page 14 of 28 6 8 10 Data Sheet AD8224 RLOAD = 10kΩ VS = ±15V –10 –8 –6 –4 –2 0 2 4 6 8 2 +4.9V, +1.7V +0.1V, +1.7V +5V SINGLE SUPPLY, VREF = +2.5V 1 +4.9V, +0.5V +0.1V, +0.5V 0 –0.3V –1 –1 10 +3V 3 0 1 2 3 4 5 6 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 06286-027 INPUT COMMON-MODE VOLTAGE (V) RLOAD = 2kΩ 06286-024 XXX NONLINEARITY (20ppm/DIV) 4 Figure 26. Input Common-Mode Voltage Range vs. Output Voltage, G = 1, VS = 5 V, VREF = 2.5 V Figure 23. Gain Nonlinearity, G = 100 VS = ±15V –10 –8 –6 –4 –2 0 2 4 6 8 +13V 12 6 +3V –14.9V, +5.4V 0 –4.9V, –4.1V –5.3V –14.8V, –9V +14.9V, –9V –12 –15.3V –12 –8 –4 0 8 4 12 16 Figure 27. Input Common-Mode Voltage Range vs. Output Voltage, G = 100, VREF = 0 V 4 18 +13V INPUT COMMON-MODE VOLTAGE (V) INPUT COMMON-MODE VOLTAGE (V) +4.9V, –4.1V –6 OUTPUT VOLTAGE (V) Figure 24. Gain Nonlinearity, G = 1000 ±15V SUPPLIES 6 –14.8V, +5.5V 0 +4.9V, +0.5V –4.9V, +0.4V OUTPUT VOLTAGE (V) 12 +14.9V, +5.4V ±5V SUPPLIES –18 –16 10 ±15V SUPPLIES 06286-028 06286-025 RLOAD = 10kΩ INPUT COMMON-MODE VOLTAGE (V) RLOAD = 2kΩ NONLINEARITY (100ppm/DIV) XXX 18 +14.9V, +5.5V +3V +4.95V, +0.6V –4.8V, +0.6V ±5V SUPPLIES –4.8V, –3.3V +4.95V, –3.3V –6 –14.8V, –8.3V +14.9V, –8.3V –5.3V –12 +3V 3 2 +4.9V, +1.7V +0.1V, +1.7V +5V SINGLE SUPPLY, VREF = +2.5V 1 0 +0.1V, –0.5V +4.9V, –0.5V –0.3V –12 –8 –4 0 4 8 12 16 OUTPUT VOLTAGE (V) Figure 25. Input Common-Mode Voltage Range vs. Output Voltage, G = 1, VREF = 0 V –1 –1 06286-026 –18 –16 0 1 2 3 4 5 6 OUTPUT VOLTAGE (V) Figure 28. Input Common-Mode Voltage Range vs. Output Voltage, G = 100, VS = 5 V, VREF = 2.5 V Rev. D | Page 15 of 28 06286-029 –15.3V AD8224 Data Sheet 15 –1 +125°C –2 +25°C +85°C NOTES 1. THE AD8224 CAN OPERATE UP TO A VBE BELOW THE NEGATIVE SUPPLY, BUT THE BIAS CURRENT WILL INCREASE SHARPLY. +1 –40°C +25°C +85°C +125°C 6 8 10 12 14 16 18 SUPPLY VOLTAGE (V) +125°C 0 +125°C –5 +85°C +25°C –40°C –1 –40°C +85°C +25°C –3 +85°C OUTPUT VOLTAGE SWING (V) –40°C –2 +125°C –4 +4 +3 +2 +125°C +85°C +25°C +25°C 4 +125°C 3 2 +125°C 1 +25°C –40°C +1 +85°C 4 6 8 10 12 14 16 18 0 100 06286-031 2 10k 1k RLOAD (Ω) 06286-034 –40°C DUAL SUPPLY VOLTAGE (±V) Figure 33. Output Voltage Swing vs. Load Resistance, VS = 5 V, VREF = 2.5 V Figure 30. Output Voltage Swing vs. Dual Supply Voltage, RLOAD = 2 kΩ, G = 10, VREF = 0 V VS+ VS+ –0.2 +0.4 +125°C +85°C +25°C +25°C OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES +85°C –0.4 –40°C –1 +125°C –40°C –40°C +85°C +125°C –2 +25°C –3 –4 +4 +3 +2 +0.2 +1 VS– VS– +125°C +85°C +25°C 4 6 8 10 12 14 16 DUAL SUPPLY VOLTAGE (±V) Figure 31. Output Voltage Swing vs. Dual Supply Voltage, RLOAD = 10 kΩ, G = 10, VREF = 0 V 18 0 2 4 6 8 IOUT (mA) 10 12 14 16 06286-035 –40°C 2 06286-032 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES 10k 5 VS+ VS– 1k RLOAD (Ω) Figure 32. Output Voltage Swing vs. Load Resistance, VS = ±15 V, VREF = 0 V Figure 29. Input Voltage Limit vs. Supply Voltage, G = 1, VREF =0 V OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES +85°C 5 –15 100 06286-030 –1 4 +25°C –10 VS– 2 –40°C 10 OUTPUT VOLTAGE SWING (V) INPUT VOLTAGE LIMIT (V) –40°C 06286-033 VS+ Figure 34. Output Voltage Swing vs. Output Current, VS = ±15 V, VREF = 0 V Rev. D | Page 16 of 28 Data Sheet AD8224 35 +25°C +85°C +125°C –2 +2 +85°C +25°C +125°C +1 2 4 6 8 10 12 14 16 IOUT (mA) GAIN = 1 20 15 10 0 100 06286-036 0 25 GAIN = 10, 100, 1000 5 –40°C VS– 30 Figure 35. Output Voltage Swing vs. Output Current, VS = 5 V, VREF = 2.5 V 1k 10k 100k 10M 1M FREQUENCY (Hz) 06286-039 –1 OUTPUT VOLTAGE SWING (V p-p) OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES VS+ Figure 38. Output Voltage Swing vs. Large Signal Frequency Response XX XX 47pF NO LOAD 100pF XXX (X) XXX (X) 5V/DIV 0.002%/DIV XX XXX (X) XX XX XX XXX (X) Figure 36. Small Signal Pulse Response for Various Capacitive Loads, VS = ±15 V, VREF = 0 V 06286-040 20µs/DIV 5µs/DIV 06286-037 20mV/DIV XX XX 5µs TO 0.01% 6µs TO 0.001% Figure 39. Large Signal Pulse Response and Settle Time, G = 1, RLOAD = 10 kΩ, VS = ±15 V, VREF = 0 V XX XX 47pF 100pF NO LOAD XXX (X) XXX (X) 5V/DIV 0.002%/DIV XX XXX (X) Figure 37. Small Signal Pulse Response for Various Capacitive Loads, VS = 5 V, VREF = 2.5 V Rev. D | Page 17 of 28 XX XX XX XXX (X) Figure 40. Large Signal Pulse Response and Settle Time, G = 10, RLOAD = 10 kΩ, VS = ±15 V, VREF = 0 V 06286-041 20µs/DIV 5µs/DIV 06286-038 20mV/DIV XX XX 4.3μs TO 0.01% 4.6μs TO 0.001% AD8224 Data Sheet XX XXX XXX (X) 5V/DIV 0.002%/DIV 8.1μs TO 0.01% 9.6μs TO 0.001% 20mV/DIV 4µs/DIV XXX 06286-045 XX XXX (X) 06286-042 20µs/DIV XX XX Figure 44. Small Signal Pulse Response, G = 10, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = ±15 V, VREF = 0 V Figure 41. Large Signal Pulse Response and Settle Time, G = 100, RLOAD = 10 kΩ, VS = ±15 V, VREF = 0 V XX XXX XXX (X) 5V/DIV 0.002%/DIV 58μs TO 0.01% 74μs TO 0.001% 20mV/DIV 4µs/DIV XXX Figure 42. Large Signal Pulse Response and Settle Time, G = 1000, RLOAD = 10 kΩ, VS = ±15 V, VREF = 0 V 06286-046 XX XXX (X) 06286-043 200µs/DIV XX XX XXX XXX Figure 45. Small Signal Pulse Response, G = 100, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = ±15 V, VREF = 0 V 06286-044 4µs/DIV XXX Figure 43. Small Signal Pulse Response, G = 1, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = ±15 V, VREF = 0 V 40µs/DIV XXX Figure 46. Small Signal Pulse Response, G = 1000, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = ±15 V, VREF = 0 V Rev. D | Page 18 of 28 06286-047 20mV/DIV 20mV/DIV AD8224 XXX XXX Data Sheet 20mV/DIV 40µs/DIV XXX Figure 47. Small Signal Pulse Response, G = 1, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = 5 V, VREF = 2.5 V 06286-051 4µs/DIV XXX 06286-048 20mV/DIV Figure 50. Small Signal Pulse Response, G = 1000, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = 5 V, VREF = 2.5 V 4µs/DIV XXX SETTLED TO 0.001% SETTLED TO 0.01% 5 0 06286-049 20mV/DIV 10 0 5 10 20 15 OUTPUT VOLTAGE STEP SIZE (V) 06286-052 XXX SETTLING TIME (µs) 15 Figure 51. Settling Time vs. Output Voltage Step Size, (G = 1) ±15 V, VREF = 0 V Figure 48. Small Signal Pulse Response, G = 10, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = 5 V, VREF = 2.5 V 4µs/DIV XXX Figure 49. Small Signal Pulse Response, G = 100, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = 5 V, VREF = 2.5 V 10 SETTLED TO 0.01% 1 06286-050 20mV/DIV SETTLED TO 0.001% 1 10 100 1000 GAIN (V/V) Figure 52. Settling Time vs. Gain for a 10 V Step, VS = ±15 V, VREF = 0 V Rev. D | Page 19 of 28 06286-053 XXX SETTLING TIME (µs) 100 AD8224 180 Data Sheet SOURCE VOUT = 20V p-p 160 VDIFF_OUT VCM_OUT 80 THERMAL CROSSTALK VARIES WITH LOAD 140 120 70 GAIN = 1 100 LIMITED BY MEASUREMENT SYSTEM 60 50 40 30 80 20 60 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) 40 20 0 GAIN = 1000 GAIN = 100 GAIN = 10 GAIN = 1 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 06286-055 –20 –40 1 10 100 1k 10k 100k FREQUENCY (Hz) Figure 55. Differential Output Configuration: Common-Mode Output (CMROUT) vs. Frequency Figure 53. Channel Separation vs. Frequency, RLOAD = 2 kΩ, Source Channel at G = 1 60 0 Figure 54. Differential Output Configuration: Gain vs. Frequency Rev. D | Page 20 of 28 1M 06286-056 10 06286-069 40 GAIN (dB) CMROUT = 20 log 90 CMROUT (dB) CHANNEL SEPARATION (dB) 100 SOURCE V OUT SMALLER TO AVOID SLEW RATE LIMIT GAIN = 1000 Data Sheet AD8224 THEORY OF OPERATION +VS +VS +VS NODE A R1 24.7kΩ RG +VS NODE B –VS 20kΩ R2 24.7kΩ –VS NODE F +VS 20kΩ OUTPUT 20kΩ +VS +VS NODE C J1 Q1 +IN –VS A3 VPINCH NODE E NODE D C1 C2 A1 A2 Q2 –IN J2 VPINCH +VS –VS REF 20kΩ –VS –VS I VB 06286-057 I –VS Figure 56. Simplified Schematic The AD8224 is a JFET input, monolithic instrumentation amplifier based on the classic three op amp topology (see Figure 56). Input Transistor J1 and Input Transistor J2 are biased at a fixed current so that any input signal forces the output voltages of A1 and A2 to change accordingly. The input signal creates a current through RG that flows in R1 and R2 such that the outputs of A1 and A2 provide the correct, gained signal. Topologically, J1, A1, and R1 and J2, A2, and R2 can be viewed as precision current feedback amplifiers. The common-mode voltage and amplified differential signal from A1 and A2 are applied to a difference amplifier that rejects the common-mode voltage but amplifies the differential signal. The difference amplifier employs 20 kΩ laser trimmed resistors that result in an in-amp with a gain error of less than 0.04%. New trim techniques were developed to ensure that the CMRR exceeds 86 dB (G = 1). Using JFET transistors, the AD8224 offers an extremely high input impedance, extremely low bias currents of 10 pA maximum, low offset current of 0.6 pA maximum, and no input bias current noise. In addition, input offset is less than 175 μV and drift is less than 5 μV/°C. Ease of use and robustness were considered. A common problem for instrumentation amplifiers is that at high gains, when the input is overdriven, an excessive milliampere input bias current can result, and the output can undergo phase reversal. Overdriving the input at high gains refers to when the input signal is within the supply voltages but the amplifier cannot output the gained signal. For example, at a gain of 100, driving the amplifier with 10 V on ±15 V constitutes overdriving the inputs because the amplifier cannot output 100 V. The AD8224 has none of these problems; its input bias current is limited to less than 10 μA, and the output does not phase reverse under overdrive fault conditions. The AD8224 has extremely low load induced nonlinearity. All amplifiers that comprise the AD8224 have rail-to-rail output capability for enhanced dynamic range. The input of the AD8224 can amplify signals with wide common-mode voltages even slightly lower than the negative supply rail. The AD8224 operates over a wide supply voltage range. It can operate from either a single +4.5 V to +36 V supply or a dual ±2.25 V to ±18 V. The transfer function of the AD8224 is G 1 49.4 kΩ RG Users can easily and accurately set the gain using a single, standard resistor. Because the input amplifiers employ a current feedback architecture, the AD8224 gain bandwidth product increases with gain, resulting in a system that does not experience as much bandwidth loss as voltage feedback architectures at higher gains. GAIN SELECTION Placing a resistor across the RG terminals sets the gain of the AD8224. This is calculated by referring to Table 13 or by using the following gain equation Rev. D | Page 21 of 28 RG 49.4 kΩ G 1 AD8224 Data Sheet LAYOUT Table 13. Gains Achieved Using 1% Resistors The AD8224 is a high precision device. To ensure optimum performance at the PCB level, care must be taken in the design of the board layout. The AD8224 pinout is arranged in a logical manner to aid in this task. Calculated Gain 1.990 4.984 9.998 19.93 50.40 100.0 199.4 495.0 991.0 Package Considerations The AD8224 is available in two version s of the 16-lead, 4 mm × 4 mm LFCSP package: with or without an exposed pad. Blindly copying the footprint from another 4 mm × 4 mm LFCSP part is not recommended because it may not have the same thermal pad size and leads. Refer to the Outline Dimensions section to verify that the PCB symbol has the correct dimensions. The AD8224 defaults to G = 1 when no gain resistor is used. The tolerance and gain drift of the RG resistor should be added to the AD8224 specifications to determine the total gain accuracy of the system. When the gain resistor is not used, gain error and gain drift are kept to a minimum. Hidden Paddle Package REFERENCE TERMINAL The output voltage of the AD8224 is developed with respect to the potential on the reference terminal. This is useful when the output signal needs to be offset to a precise midsupply level. For example, a voltage source can be tied to the REF1 pin or the REF2 pin to level-shift the output so that the AD8224 can drive a single-supply ADC. Pin REFx is protected with ESD diodes and should not exceed either +VS or −VS by more than 0.5 V. For best performance, source impedance to the REF terminal should be kept below 1 Ω. As shown in Figure 56, the reference terminal, REF, is at one end of a 20 kΩ resistor. Additional impedance at the REF terminal adds to this 20 kΩ resistor and results in amplification of the signal connected to the positive input. The amplification from the additional RREF can be computed by The AD8224 is available in an LFCSP package with a hidden paddle. It is the preferred package for the AD8224. Unlike chip scale packages where the pad limits routing capability, this package allows routes and vias directly underneath the chip, so that the full space savings of the small LFCSP can be realized. Although the package has no metal in the center of the part, the manufacturing process does leave a very small section of exposed metal at each of the package corners, shown in Figure 58 as well as Figure 69 in the Outline Dimensions section. This metal is connected to +VS through the part. Because of a possibility of a short, vias should not be placed underneath these exposed metal tabs. HIDDEN PADDLE BOTTOM VIEW 2 20 kΩ RREF NOTES 1. EXPOSED LEAD FRAME TABS AT THE FOUR CORNERS OF THE PACKAGE ARE INTERNALLY CONNECTED TO +VS. REFER TO THE OUTLINE DIMENSIONS PAGE, FOR FURTHER INFORMATION ON PACKAGE AVAILABILITY. 40 kΩ RREF Figure 58. Hidden Paddle Package: Bottom View Only the positive signal path is amplified; the negative path is unaffected. This uneven amplification degrades the CMRR of the amplifier. INCORRECT EXPOSED LEAD FRAME TABS CORRECT AD8224 Exposed Pad Package CORRECT AD8224 VREF AD8224 VREF + + AD8224 – – Figure 57. Driving the Reference Pin 06286-058 VREF OP2177 06286-101 1% Standard Table Value of RG (Ω) 49.9 k 12.4 k 5.49 k 2.61 k 1.00 k 499 249 100 49.9 The AD8224 4 mm × 4 mm LFCSP is also available with an exposed thermal pad package version. This pad is connected internally to +VS. The pad can either be left unconnected or connected to the positive supply rail. Space between the leads and thermal pad should be kept as wide as possible for the best bias current performance. To maintain the AD8224 ultralow bias current performance, the thermal pad area can be reduced to extend the gap between the leads and the pad. The exposed pad package also has exposed lead frame tabs at the corners of the package, similar to those of the hidden paddle package, which are internally connected to +VS. Do not place vias underneath these metal tabs. Rev. D | Page 22 of 28 Data Sheet AD8224 To preserve maximum pin compatibility with other dual instrumentation amplifiers, such as the AD8222, leave the pad unconnected. This can be done by not soldering the paddle at all or by soldering the part to a landing that is a not connected to any other net. For high vibration applications, a landing is recommended. Because the AD8224 dissipates little power, heat dissipation is rarely an issue. If improved heat dissipation is desired (for example, when driving heavy loads), connect the exposed pad to the positive supply rail. For the best heat dissipation performance, the positive supply rail should be a plane in the board. See the Thermal Resistance section for more information. 0.1µF 16 Errors introduced at the reference terminal feed directly to the output. Take care to tie the REFx pins to the appropriate local ground. Power Supplies A stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect performance. The AD8224 has two positive supply pins (Pin 5 and Pin 16) and two negative supply pins (Pin 8 and Pin 13). While the part functions with only one pin from each supply pair connected, both pins should be connected for specified performance and optimum reliability. The AD8224 should be decoupled with 0.1 µF bypass capacitors, one for each supply. Place the positive supply decoupling capacitor near Pin 16, and the negative supply decoupling capacitor near Pin 8. Each supply should also be decoupled with a 10 µF tantalum capacitor. The tantalum capacitor can be placed further away from the AD8224 and can generally be shared by other precision integrated circuits. Figure 59 shows an example layout. 13 1 12 2 11 3 10 4 9 RG The AD8224 has a higher CMRR over frequency than typical in-amps, which gives it greater immunity to disturbances, such as line noise and its associated harmonics. A well-implemented layout is required to maintain this high performance. Input source impedances should be matched closely. Source resistance should be placed close to the inputs so that it interacts with as little parasitic capacitance as possible. Reference 14 RG Common-Mode Rejection over Frequency 5 6 7 8 0.1µF 06286-059 Parasitics at the RGx pins can also affect CMRR over frequency. The PCB should be laid out so that the parasitic capacitances at each pin match. Traces from the gain setting resistor to the RGx pins should be kept short to minimize parasitic inductance. 15 AD8224 Figure 59. Example Layout SOLDER WASH The solder process can leave flux and other contaminants on the board. When these contaminants are between the AD8224 leads and thermal pad, they can create leakage paths that are larger than the AD8224 bias currents. A thorough washing process removes these contaminants and restores the device’s excellent bias current performance. INPUT BIAS CURRENT RETURN PATH The input bias current of the AD8224 must have a return path to common. When the source, such as a transformer, cannot provide a return current path, one should be created, as shown in Figure 60. INPUT PROTECTION All terminals of the AD8224 are protected against ESD. ESD protection is guaranteed to 4 kV (human body model). In addition, the input structure allows for dc overload conditions a diode drop above the positive supply and a diode drop below the negative supply. Voltages beyond a diode drop of the supplies cause the ESD diodes to conduct and enable current to flow through the diode. Therefore, an external resistor should be used in series with each of the inputs to limit current for voltages beyond the supplies. In either scenario, the AD8224 safely handles a continuous 6 mA current at room temperature. Rev. D | Page 23 of 28 AD8224 Data Sheet The relationship between external, matched series resistors and the internal gate capacitance is expressed as For applications where the AD8224 encounters extreme overload voltages, as in cardiac defibrillators, external series resistors and low leakage diode clamps, such as BAV199Ls, FJH1100s, or SP720s, should be used. INCORRECT FilterFreqDIFF CORRECT +VS FilterFreqCM +VS AD8224 REF –VS 1 2RCG To eliminate high frequency common-mode signals while using smaller source resistors, a low-pass RC network can be placed at the input of the instrumentation amplifier (see Figure 62). The filter limits the input signal bandwidth according to the following relationship: AD8224 REF –VS TRANSFORMER FilterFreqDIFF TRANSFORMER +VS +VS C FilterFreqCM C C R 1 fHIGH-PASS = 2πRC AD8224 AD8224 C REF REF R –VS 06286-060 –VS CAPACITIVELY COUPLED CAPACITIVELY COUPLED Figure 60. Creating an IBIAS Path 1 2RCG 1 2R(2 CD CC CG ) 1 2R(CC CG ) Mismatched CC capacitors result in mismatched low-pass filters. The imbalance causes the AD8224 to treat what would have been a common-mode signal as a differential signal. To reduce the effect of mismatched external CC capacitors, select a value of CD greater than 10 times CC. This sets the differential filter frequency lower than the common-mode frequency. +15V RF INTERFERENCE 0.1µF CC +IN 4.02kΩ CD R REF –IN CC + VOUT AD8224 10nF 4.02kΩ 10µF + 1nF R +15V 0.1µF 10µF 1nF 0.1µF 10µF + –15V 06286-062 RF rectification is often a problem in applications where there are large RF signals. The problem appears as a small dc offset voltage. The AD8224 by its nature has a 5 pF gate capacitance (CG) at its inputs. Matched series resistors form a natural low-pass filter that reduces rectification at high frequency (see Figure 61). Figure 62. RFI Suppression +IN COMMON-MODE INPUT VOLTAGE RANGE CG AD8224 –VS R –IN VOUT CG –VS 0.1µF REF 10µF + –15V 06286-061 R The 3-op amp architecture of the AD8224 applies gain and then removes the common-mode voltage. Therefore, internal nodes in the AD8224 experience a combination of both the gained signal and the common-mode signal. This combined signal can be limited by the voltage supplies even when the individual input and output signals are not. Figure 25 through Figure 28 show the allowable common-mode input voltage ranges for various output voltages, supply voltages, and gains. Figure 61. RFI Filtering Without External Capacitors Rev. D | Page 24 of 28 Data Sheet AD8224 APPLICATIONS INFORMATION DRIVING AN ADC +IN An instrumentation amplifier is often used in front of an ADC to provide CMRR and additional conditioning such as a voltage level shift and gain (see Figure 63). In this example, a 2.7 nF capacitor and a 500 Ω resistor create an antialiasing filter for the AD7685. The 2.7 nF capacitor also serves to store and deliver the necessary charge to the switched capacitor input of the ADC. The 500 Ω series resistor reduces the burden of the 2.7 nF load from the amplifier. However, large source impedance in front of the ADC can degrade the total harmonic distortion (THD). 4.7µF 500Ω AD8224 AD7685 REF 2.7nF –IN 06286-063 +2.5V Figure 63. Driving an ADC in a Low Frequency Application The differential configuration of the AD8224 has the same excellent dc precision specifications as the single-ended output configuration and is recommended for applications in the frequency range of dc to 1 MHz. The circuit configuration, outlined in Table 4 and Table 7, refers to the configuration shown in Figure 64 only. The circuit includes an RC filter that maintains the stability of the loop. VDIFF_OUT = V+OUT − V−OUT = (V+IN − V−IN) × G A common application sets the common-mode output voltage to the midscale of a differential ADC. In this case, the ADC reference voltage is sent to the +IN2 terminal, and ground is connected to the REF2 terminal. This produces a commonmode output voltage of half the ADC reference voltage. Another differential output topology is shown in Figure 65. Instead of a second in-amp, ½ of a dual OP2177 op amp creates the inverted output. Because the OP2177 comes in an MSOP, this configuration allows the creation of a dual-channel, precision differential output in-amp with little board area. Errors from the op amp are common to both outputs and are, thus, common mode. Errors from mismatched resistors also create a common-mode dc offset. Because these errors are common mode, they are likely to be rejected by the next device in the signal chain. where: +IN AD8224 49.4 kΩ +OUT –IN RG REF 4.99kΩ 4.99kΩ VREF + – OP2177 –OUT Figure 65. Differential Output Using Op Amp Rev. D | Page 25 of 28 06286-065 G =1+ 06286-064 –OUT Figure 64. Differential Circuit Schematic 2-Channel Differential Output Using a Dual Op Amp DIFFERENTIAL OUTPUT The transfer function for the differential output is REF2 +IN2 and REF2 have different properties that allow the reference voltage to be easily set for a wide variety of applications. +IN2 has high impedance but cannot swing to the positive supply rail. REF2 must be driven with a low impedance but can go 300 mV beyond the supply rails. +IN 1.07kΩ +IN2 VCM_OUT = (V+OUT + V−OUT)/2 = (V+IN2 + VREF2)/2 ADR435 ±50mV 33pF The output common-mode voltage is set by the average of +IN2 and REF2. The transfer function is 0.1µF +5V AD8224 + 10µF +OUT 20kΩ – Setting the Common-Mode Voltage +5V + –IN + AD8224 – For applications where THD performance is critical, the series resistor needs to be small. At worst, a small series resistor can load the AD8224, potentially causing the output to overshoot or ring. In such cases, a buffer amplifier, such as the AD8615 should be used after the AD8224 to drive the ADC. RG AD8224 Data Sheet +12V 10µF + 0.1µF +5V 1kΩ +IN 100pF NPO 5% 0.1µF +OUT 1000pF AD8224 –IN +IN2 100pF NPO 5% –OUT REF2 IN– 2.7nF 2.7nF + AD7688 GND REF 10µF X5R +12V +5V REF 10µF VDD IN+ 806Ω (DIFF OUT) 1kΩ 806Ω 0.1µF 0.1µF VIN –12V +5V REF VOUT 0.1µF ADR435 06286-066 GND Figure 66. Driving a Differential ADC The AD8224 can be configured in differential output mode to drive a differential ADC. Figure 66 illustrates several of the concepts. First Antialiasing Filter The 1 kΩ resistor, 1000 pF capacitor, and 100 pF capacitors in front of the in-amp form a 76 kHz filter. This is the first of two antialiasing filters in the circuit and helps to reduce the noise of the system. The 100 pF capacitors protect against commonmode RFI signals. Note that they are 5% COG/NPO types. These capacitors match well over time and temperature, which keeps the CMRR of the system high over frequency. Second Antialiasing Filter An 806 Ω resistor and a 2.7 nF capacitor are located between each AD8224 output and ADC input. These components create a 73 kHz low-pass filter for another stage of antialiasing protection. These four elements also isolate the ADC from loading the AD8224. The 806 Ω resistor shields the AD8224 from the switched capacitor input of the ADC, which looks like a timevarying load. The 2.7 nF capacitor provides a charge to the switched capacitor front end of the ADC. If the application requires a lower frequency antialiasing filter, increase the value of the capacitor rather than the resistor. However, other converters have less robust inputs and may need the added protection. Reference The ADR435 supplies a reference voltage to both the ADC and the AD8224. Because REF2 on the AD8224 is grounded, the common-mode output voltage is precisely half the reference voltage, exactly where it needs to be for the ADC. DRIVING CABLING All cables have a certain capacitance per unit length, which varies widely with cable type. The capacitive load from the cable may cause peaking in the AD8224 output response. To reduce peaking, use a resistor between the AD8224 and the cable. Because cable capacitance and desired output response vary widely, this resistor is best determined empirically. A good starting point is 50 Ω. The AD8224 operates at a low enough frequency that transmission line effects are rarely an issue; therefore, the resistor need not match the characteristic impedance of the cable. The 806 Ω resistors can also protect an ADC from overvoltages. Because the AD8224 runs on wider supply voltages than a typical ADC, there is a possibility of overdriving the ADC. This is not an issue with a PulSAR® converter, such as the AD7688. Its input can handle a 130 mA overdrive, which is much higher than the short-circuit limit of the AD8224. AD8224 (DIFF OUT) AD8224 (SINGLE OUT) 06286-067 DRIVING A DIFFERENTIAL INPUT ADC Figure 67. Driving a Cable Rev. D | Page 26 of 28 Data Sheet AD8224 OUTLINE DIMENSIONS 4.10 4.00 SQ 3.90 0.65 BSC PIN 1 INDICATOR 16 13 1 12 EXPOSED PAD 2.60 2.50 SQ 2.40 9 0.50 0.40 0.30 TOP VIEW 0.80 0.75 0.70 4 5 8 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 042709-A PIN 1 INDICATOR 0.35 0.30 0.25 COMPLIANT TO JEDEC STANDARDS MO-220-WGGC. Figure 68. 16-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.75 mm Package Height (CP-16-26) Dimensions are shown in millimeters 4.10 4.00 SQ 3.90 0.60 MAX 1.95 REF 0.60 MAX 13 16 12 PIN 1 INDICATOR 3.75 BSC SQ 1 0.65 BSC 9 TOP VIEW SEATING PLANE 12° MAX 4 8 5 BOTTOM VIEW 0.80 MAX 0.65 TYP 0.35 0.30 0.25 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-263-VBBC Figure 69. 16-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.85 mm Package Height, with Hidden Paddle (CP-16-19) Dimensions shown in millimeters Rev. D | Page 27 of 28 04-06-2012-A 1.00 0.85 0.80 0.75 0.60 0.50 AD8224 Data Sheet ORDERING GUIDE Model1 AD8224ACPZ-R7 AD8224ACPZ-RL AD8224ACPZ-WP AD8224BCPZ-R7 AD8224BCPZ-RL AD8224BCPZ-WP AD8224HACPZ-R7 AD8224HACPZ-RL AD8224HACPZ-WP AD8224HBCPZ-R7 AD8224HBCPZ-RL AD8224HBCPZ-WP AD8224-EVALZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 16-Lead Lead Frame Chip Scale Package [LFCSP] 16-Lead Lead Frame Chip Scale Package [LFCSP] 16-Lead Lead Frame Chip Scale Package [LFCSP] 16-Lead Lead Frame Chip Scale Package [LFCSP] 16-Lead Lead Frame Chip Scale Package [LFCSP] 16-Lead Lead Frame Chip Scale Package [LFCSP] 16-Lead Lead Frame Chip Scale Package [LFCSP] 16-Lead Lead Frame Chip Scale Package [LFCSP] 16-Lead Lead Frame Chip Scale Package [LFCSP] 16-Lead Lead Frame Chip Scale Package [LFCSP] 16-Lead Lead Frame Chip Scale Package [LFCSP] 16-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board Z = RoHS Compliant Part. ©2007–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06286-0-4/16(D) Rev. D | Page 28 of 28 Package Option CP-16-26 CP-16-26 CP-16-26 CP-16-26 CP-16-26 CP-16-26 CP-16-19 CP-16-19 CP-16-19 CP-16-19 CP-16-19 CP-16-19