Zarlink MAC5104FB Radiation hard 4096 x 1 bit static ram Datasheet

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APRIL
1995
MA5104
DS3580-3.2
MA5104
RADIATION HARD 4096 x 1 BIT STATIC RAM
The MA5104 4k Static RAM is configured as 4096 x 1 bits and
manufactured using CMOS-SOS high performance, radiation hard,
3µm technology.
The device has separate input and output terminals controlled by
Chip Select and Write Enable. The design uses a 6 transistor cell and
has full static operation with no clock or timing strobe required.
Address input buffers are deselected when Chip Select is in the HIGH
state.
Operation Mode
CS
WE
I/O
Power
Read
L
H
D OUT
ISB1
Write
L
L
D IN
Standby
H
X
High Z
FEATURES
■ 3µm CMOS-SOS Technology
■ Latch-up Free
■ Fast Access Time 90ns Typical
■ Total Dose 106 Rad(Si)
■ Transient Upset >1010 Rad(Si)/sec
■ SEU <10-10 Errors/bitday
■ Single 5V Supply
Figure 1: Truth Table
■ Three State Output
■ Low Standby Current 10µA Typical
ISB2
■ -55°C to +125°C Operation
■ All Inputs and Outputs Fully TTL or CMOS
Compatible
■ Fully Static Operation
Figure 2: Block Diagram
1
MA5104
CHARACTERISTICS AND RATINGS
Symbol
Parameter
Min.
Max.
Units
Supply Voltage
-0.5
7
V
VI
Input Voltage
-0.3
VDD+0.3
V
TA
Operating Temperature
-55
125
°C
TS
Storage Temperature
-65
150
°C
VCC
Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and
functlonal operation of the device at these condltions,
or at any other condition above those indicated in the
operations section of this specification, is not Implied
Exposure to absolute maxlmum rating conditions for
extended perlods may affect device reliability.
Figure 3: Absolute Maximum Ratings
Notes for Tables 4 and 5:
1. Characteristics apply to pre radiation at TA = -55°C to +125°C with VDD = 5V ±10% and to post 100k Rad(Si) total dose
radiation at TA = 25°C with VDD = 5V ±10% (characteristics at higher radiation levels available on request).
2. Worst case at TA = +125°C, guaranteed but not tested at TA = -55°C.
GROUP A SUBGROUPS 1, 2, 3.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VDD
Supply voltage
-
4.5
5.0
5.5
V
VlH
Input High Voltage
-
VDD/2
-
VDD
V
VlL
Input Low Voltage
-
VSS
-
0.8
V
VOH
Output High Voltage
IOH1 = -1mA
2.4
-
-
V
VOL
Output Low Voltage
IOL = 2mA
-
-
0.4
V
ILI
Input Leakage Current (note 2)
All inputs except CS
-
-
±10
µA
ILO
Output Leakage Current (note 2)
Output disabled, VOUT = VSS or VDD
-
-
±20
µA
IPUI
Input Pull-Up Current
VIN = VSS on CS input only
-
-
-100
µA
IPDI
Input Leakage Current
VIN = VSS on CS input only
-
-
5
µA
IDD
Power Supply Current
fRC = 1MHz, CS = 50% mark:space
-
12
16
mA
ISB1
Selected Supply Current
CS = VSS
-
25
35
mA
ISB2
Standby Supply Current
Chip disabled
-
50
3000
µA
Figure 4: Electrical Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VDR
VCC for Data Retention
CS = VDR
2.0
-
-
V
IDDR
Data Retention Current
CS = VDR, VDR = 2.0V
-
30
2000
µA
Figure 5: Data Retention Characteristics
2
MA5104
AC CHARACTERISTICS
Conditions of Test for Tables 5 and 6:
1. Input pulse = VSS to 3.0V.
2. Times measurement reference level = 1.5V.
3. Transition is measured at ±500mV from steady state.
4. This parameter is sampled and not 100% tested.
Notes for Tables 6 and 7:
Characteristics apply to pre-radiation at TA = -55°C to +125°C with VDD = 5V±10% and to post 100k Rad(Si) total dose radiation
at TA = 25°C with VDD = 5V ±10%. GROUP A SUBGROUPS 9, 10, 11.
Symbol
Parameter
Min
Max
Units
TAVAVR
Read Cycle Time
135
-
ns
TAVQV
Address Access Time
-
135
ns
TELQV
Chip Select to Output Valid
-
135
ns
TELQX (4)
Chip Select to Output Active
10
-
ns
TELQZ (4)
Chip Select to Output Tri State
10
50
ns
Output Hold from Address Change
10
-
ns
Parameter
Min
Max
Units
TAVAVW
Write Cycle Tlme
135
-
ns
TAVWL
Address Set Up Time
10
-
ns
TWLWH
Write Pulse Width
50
-
ns
TWHAV
Write Recovery Time
5
-
ns
TDVWH
Data Set Up Time
35
-
ns
TNHDX
Data Hold Time
5
-
ns
Write Enable to Output Tri State
10
50
ns
TELWL
Chip Selection to Write Low
25
-
ns
TELWH
Chip Selection to End of Write
85
-
ns
TAVWH
Address Valid to End of Write
80
-
ns
Output Active from End to Write
5
-
ns
TAXQX
Figure 6: Read Cycle AC Electrical Characteristics
Symbol
TWLQZ (4)
TWHQX (4)
Figure 7: Write Cycle AC Electrical Characteristics
Symbol
CIN
COUT
Parameter
Conditions
Min.
Typ.
Max.
Units
Input Capacitance
Vl = 0V
-
6
10
pF
Output Capacitance
VO = 0V
-
8
12
pF
Note: TA = 25°C and f = 1MHz. Data obtained by characterisation or analysis; not routinely measured.
Figure 8: Capacitance
3
MA5104
Symbol
FT
Parameter
Conditions
Basic Functionality
VDD = 4.5V - 5.5V, FREQ = 1MHz
VIL = VSS, VIH = VDD, VOL ≤ 1.5V, VOH ≥ 1.5V
TEMP = -55°C to +125°C, GPS PATTERN SET
GROUP A SUBGROUPS 7, 8A, 8B
Figure 9: Functionality
Subgroup
Definition
1
Static characteristics specified in Tables 4 and 5 at +25°C
2
Static characteristics specified in Tables 4 and 5 at +125°C
3
Static characteristics specified in Tables 4 and 5 at -55°C
7
Functional characteristics specified in Table 9 at +25°C
8A
Functional characteristics specified in Table 9 at +125°C
8B
Functional characteristics specified in Table 9 at -55°C
9
Switching characteristics specified in Tables 6 and 7 at +25°C
10
Switching characteristics specified in Tables 6 and 7 at +125°C
11
Switching characteristics specified in Tables 6 and 7 at -55°C
Figure 10: Definition of Subgroups
4
MA5104
TIMING DIAGRAMS
TAVAVR
ADDRESS
TAVQV
TAXQX
TELQV
CS
TELQX
DATA OUT
TEHQZ
HIGH
IMPEDANCE
DATA VALID
1. WE is high for Read Cycle.
2. Address Vaild prior to or coincident with CS transition low.
Figure 11a: Read Cycle 1
TAVAVR
ADDRESS
TAVQV
DATA OUT
TAXQX
DATA VALID
1. WE is high for Read Cycle.
2. Device is continually selected. CS low.
Figure 11b: Read Cycle 2
5
MA5104
TAVAVW
ADDRESS
TAVWH
TWHAV (3)
TWLWH (2)
TAVWL
(4)
WE
TAXQX
TWLQZ
TELWL
TWLQH
(5)
(7)
DATA OUT
HIGH
IMPEDANCE
TDVWH
DATA IN
TWHDX
DATA VALID
TELWH
CS
1. WE must be high during all address transitions.
2. A write occurs during the overlap (TWLWH) of a low CS, a high CE and a low WE.
3. TWHAV is measured from either CS or WE going high or CE going low, whichever is the earlier, to the end
of the write cycle.
4. If the CS low transition occurs simultaneously with, or after, the WE low transition, the output remains in
the high impedance state.
5. DATA OUT is the write data of the current cycle, if selected.
6. DATA OUT is the read data of the next address,if selected.
7. TELWL must be met to prevent memory corruption.
Figure 12: Write Cycle
6
(6)
MA5104
OUTLINES AND PIN ASSIGNMENTS
D
9
1
10
18
W
ME
Seating Plane
A1
A
C
H
e1
e
Ref
b
Z
Millimetres
15°
Inches
Min.
Nom.
Max.
Min.
Nom.
Max.
A
-
-
5.715
-
-
0.225
A1
0.38
-
1.53
0.015
-
b
0.35
-
0.59
0.014
c
0.20
-
0.36
0.008
A0
1
18 Vdd
0.060
A1
2
17 A6
-
0.023
A2
3
16 A7
-
0.014
A3
4
15 A8
Top
View
D
-
-
23.11
-
-
0.910
A4
5
e
-
2.54 Typ.
-
-
0.100 Typ.
-
A5
6
13 A10
e1
-
8.13 Typ.
-
-
0.300 Typ.
-
Dout
7
12 A11
H
4.44
-
5.38
0.175
-
0.212
Me
-
-
8.28
-
-
0.326
WE
8
11 Din
Vss
9
10 CS
Z
-
-
1.27
-
-
0.050
W
-
-
1.53
-
-
0.060
14 A9
XG406
Figure 13: 18-Lead Ceramic DIL (Solder Seal) - Package Style C
7
MA5104
M
b
D
Z
e
L
A
c
ME
A1
Inches
Ref
Pin 1
Min.
Nom.
Max.
A
-
-
0.105
A1
0.026
-
-
b
0.015
-
0.019
c
0.003
-
0.006
D
0.590
-
0.610
e
-
0.050
-
L
0.265
-
0.305
0.405
M
0.395
-
Me
0.30
-
-
Z
0.005
-
0.045
XG537
Vdd 24
1 NC
A6 23
2 A0
A7 22
3 A1
A8 21
4 A2
NC 20
5 A3
NC 19
A9 18
Bottom
View
A10 17
7 A5
8 Dout
A11 16
9 NC
Din 15
10 WE
NC 14
11 Vss
CS 13
12 NC
Figure 14: 24-Lead Ceramic Flatpack (Solder Seal) - Package Style F
8
6 A4
MA5104
Func t ion
A0
A1
A2
A3
A4
A5
DOUT
WEB
VSS
CSB
DIN
A11
A10
A9
A8
A7
A6
VDD
P a c k a ge O pt ion
F
C
2
3
4
5
6
7
8
10
11
13
15
16
17
18
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
V ia
S t a t ic 1
Burnin
S t a t ic 2
Dy na mic
R
R
R
R
R
R
R
R
Direct
R
R
R
R
R
R
R
R
Direct
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
0V
5V
5V
5V
5V
5V
5V
5V
5V
5V
0V
5V
5V
5V
5V
5V
5V
5V
5V
5V
F0
F1
F2
F3
F4
F5
LOAD
F12
0V
0V
F13
F11
F10
F9
F8
F7
F6
5V
Ra dia t ion
5V
5V
5V
5V
5V
5V
5V
5V
0V
5V
5V
5V
5V
5V
5V
5V
5V
5V
1. F0=150KHz, F1=F0/2, F2=F0/4, F3=F0/8 etc.
2. Burnin R=1k
3. Radiation R=10k
Figure 15: Burnin and Radiation Configuration
9
MA5104
RADIATION TOLERANCE
Total Dose Radiation Testing
For product procured to guaranteed total dose radiation
levels, each wafer lot will be approved when all sample
devices from each lot pass the total dose radiation test.
The sample devices will be subjected to the total dose
radiation level (Cobalt-60 Source), defined by the ordering
code, and must continue to meet the electrical parameters
specified in the data sheet. Electrical tests, pre and post
irradiation, will be read and recorded.
GEC Plessey Semiconductors can provide radiation
testing compliant with MIL-STD-883 test method 1019,
Ionizing Radiation (Total Dose).
Total Dose (Function to specification)*
1x105 Rad(Si)
Transient Upset (Stored data loss)
5x1010 Rad(Si)/sec
Transient Upset (Survivability)
>1x1012 Rad(Si)/sec
Neutron Hardness (Function to specification)
>1x1015 n/cm2
Single Event Upset**
3.4x10-9 Errors/bit day
Latch Up
Not possible
* Other total dose radiation levels available on request
** Worst case galactic cosmic ray upset - interplanetary/high altitude orbit
Figure 16: Radiation Hardness Parameters
SINGLE EVENT UPSET CHARACTERISTICS
UPSET BIT
CROSS-SECTION
(cm2/bit)
Ion LET (MeV.cm2/mg)
Figure 17: Typical Per-Bit Upset Cross-Section vs Ion LET
10
MA5104
ORDERING INFORMATION
Unique Circuit Designator
Radiation Tolerance
S
L
C
R
MAx5104xxxxx
Radiation Hard Processing
30 kRads (Si) Guaranteed
50 kRads (Si) Guaranteed
100 kRads (Si) Guaranteed
QA/QCI Process
(See Section 9 Part 4)
Test Process
(See Section 9 Part 3)
Package Type
C
F
Ceramic DIL (Solder Seal)
Flatpack (Solder Seal)
Assembly Process
(See Section 9 Part 2)
Reliability Level
L
C
D
E
B
S
Rel 0
Rel 1
Rel 2
Rel 3/4/5/STACK
Class B
Class S
For details of reliability, QA/QC, test and assembly
options, see ‘Manufacturing Capability and Quality
Assurance Standards’ Section 9.
HEADQUARTERS OPERATIONS
CUSTOMER SERVICE CENTRES
GEC PLESSEY SEMICONDUCTORS
Cheney Manor, Swindon,
Wiltshire, SN2 2QW, United Kingdom.
Tel: (01793) 518000
Fax: (01793) 518411
• FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax: (1) 64 46 06 07
• GERMANY Munich Tel: (089) 3609 06-0 Fax: (089) 3609 06-55
• ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993
• JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510
• NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 7023
• SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872
• SWEDEN Stockholm Tel: 46 8 702 97 70 Fax: 46 8 640 47 36
• TAIWAN, ROC Taipei Tel: 886 2 5461260 Fax: 886 2 7190260
• UK, EIRE, DENMARK, FINLAND & NORWAY Swindon, UK
GEC PLESSEY SEMICONDUCTORS
P.O. Box 660017,
1500 Green Hills Road, Scotts Valley,
California 95067-0017,
United States of America.
Tel: (408) 438 2900
Fax: (408) 438 5576
Tel: (01793) 518527/518566 Fax: (01793) 518582
These are supported by Agents and Distributors in major countries world-wide.
© GEC Plessey Semiconductors 1995 Publication No. DS3580-3.2 April 1995
TECHNICAL DOCUMENTATION - NOT FOR RESALE. PRINTED IN UNITED KINGDOM.
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to
be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or
service. The Company reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide
only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of
any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose
failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
11
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