IDT61298SA CMOS STATIC RAM 256K (64K x 4-BIT) Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • 64K x 4 high-speed static RAM • Fast Output Enable (OE) pin available for added system flexibility • High speed (equal access and cycle times) — Commercial: 12/15 ns (max.) • JEDEC standard pinout • 300 mil 28-pin SOJ • Produced with advanced CMOS technology • Bidirectional data inputs and outputs • Inputs/Outputs TTL-compatible • Three-state outputs • Military product compliant to MIL-STD-883, Class B The lDT61298SA is a 262,144-bit high-speed static RAM organized as 64K x 4. It is fabricated using IDT’s highperformance, high-reliability CMOS technology. This state-ofthe-art technology, combined with innovative circuit design techniques, provides a cost-effective approach for memory intensive applications. The IDT61298SA features two memory control functions: Chip Select (CS) and Output Enable (OE). These two functions greatly enhance the IDT61298SA's overall flexibility in high-speed memory applications. Access times as fast as 12ns are available. The IDT61298SA offers a reduced power standby mode, ISB1, which enables the designer to considerably reduce device power requirements. This capability significantly decreases system power and cooling levels, while greatly enhancing system reliability. All inputs and outputs are TTL-compatible and the device operates from a single 5 volt supply. Fully static asynchronous FUNCTIONAL BLOCK DIAGRAM A0 VCC GND D E C O D E R 262,144-BIT MEMORY ARRAY A15 I/O0 I/O1 I/O2 I/O CONTROL INPUT DATA CONTROL I/O3 CS WE OE 2971 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGES MAY 1996 1996 Integrated Device Technology, Inc. DSC-2971/6 7.1 1 IDT61298SA CMOS STATIC RAM 256K (64K x 4-BIT) COMMERCIAL TEMPERATURE RANGE TRUTH TABLE(1,2) DESCRIPTION (Continued) circuitry, along with matching access and cycle times, favor the simplified system design approach. The IDT61298SA is packaged in a 300 mil, 28-pin SOJ, providing improved board-level packing densities. CS OE WE I/O L L H DATAOUT Read Data Function L X L DATAIN Write Data L H H High-Z Outputs Disabled X X High-Z Deselected - Standby (ISB) X X High-Z Deselected - Standby (ISB1) H (3) VHC NOTES: 1. H = VIH, L = VIL, x = Don't care. 2. VLC = 0.2V, VHC = VCC -0.2V. 3. Other inputs ≥VHC or ≤VLC. ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol NC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 CS OE GND 1 28 2 27 3 26 4 25 24 5 6 23 22 7 8 2971 tbl 01 SO28-5 9 10 21 20 12 19 18 17 13 16 14 15 11 VCC A15 A14 A13 A12 A11 A10 NC NC I/O3 I/O2 I/O1 I/O0 Rating Com’l. Unit VTERM Terminal Voltage with Respect to GND –0.5 to +7.0 V TA Operating Temperature 0 to +70 °C TBIAS Temperature Under Bias –55 to +125 °C TSTG Storage Temperature –55 to +125 °C PT Power Dissipation 1.0 W IOUT DC Output Current 50 mA (2) WE 2971 drw 02 NOTES: 2971 tbl 02 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 0.5V. SOJ TOP VIEW PIN DESCRIPTIONS Name A0–A14 I/O0–I/O7 CS WE OE GND VCC Description CAPACITANCE Addresses Data Input/Output Chip Select (TA = +25°C, f = 1.0MHz, SOJ Package) Symbol Write Enable Output Enable Ground Power Parameter(1) CIN Input Capacitance CI/O I/O Capacitance Conditions Max. Unit VIN = 3dV 5 pF VOUT = 3dV 7 pF NOTE: 2971 tbl 03 1. This parameter is determined by device characterization, but is not production tested. 2971 tbl 04 7.1 2 IDT61298SA CMOS STATIC RAM 256K (64K x 4-BIT) COMMERCIAL TEMPERATURE RANGE RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE RECOMMENDED DC OPERATING CONDITIONS Grade Temperature GND Vcc Commercial 0°C to +70°C 0V 5V ± 10% Symbol 2971 tbl 05 Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V GND Supply Voltage 0 0 0 V VIH Input High Voltage — VCC + 0.5V V — 0.8 V VIL 2.2 Input Low Voltage –0.5 (1) NOTE: 2971 tbl 06 1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle. DC ELECTRICAL CHARACTERISTICS(1) (VCC = 5V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V) 61298SA12 Symbol ICC ISB ISB1 Parameter Dynamic Operating Current CS = VIL, Outputs Open VCC = Max., f = fMAX(2) 61298SA15 Com’l. Mil. Com’l. Mil. Unit 160 — 140 — mA 50 — 45 — mA 20 — 20 — mA Standby Power Supply Current (TTL Level) CS ≥ VIH, VCC = Max., Outputs Open, f = fMAX(2) Full Standby Power Supply Current (CMOS Level) CS ≥ VHC, VCC = Max., f = 0(2), VLC ≥ VIN ≥ VHC NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing. 2971 tbl 07 AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V AC Test Load See Figures 1 and 2 2971 tbl 08 5V 5V 480Ω 480Ω DATA OUT DATA OUT 255Ω 255Ω 30pF* 5pF* 2971 drw 04 2971 drw 03 Figure 1. AC Test Load Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, tWHZ) *Includes scope and jig capacitances 7.1 3 IDT61298SA CMOS STATIC RAM 256K (64K x 4-BIT) COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS VCC = 5.0V ± 10% IDT61298SA Symbol |ILI| Input Leakage Current |ILO| Min. Typ. VCC = Max., VIN = GND to VCC — — 5 VCC = Max., CS = VIH, VOUT = GND to VCC — — 5 Parameter Output Leakage Current Test Condition Max. Unit µA µA VOL Output Low Voltage IOL = 8mA, VCC = Min. IOL = 10mA, VCC = Min. — — — — 0.4 0.5 VOH Output High Voltage IOH = –4mA, VCC = Min. 2.4 — — V V 2971 tbl 09 AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%) Symbol Parameter 61298SA12 61298SA15 Min. Min. Max. Max. Unit Read Cycle tRC Read Cycle Time 12 — 15 — ns tAA Address Access Time — 12 — 15 ns tACS Chip Select Access Time — 12 — 15 ns tCLZ(1) Chip Select to Output in Low-Z 4 — 4 — ns tCHZ Chip Deselect to Output in High-Z — 6 — 7 ns tOE Output Enable to Output Valid — 6 — 7 ns tOLZ(1) Output Enable to Output in Low-Z 0 — 0 — ns tOHZ Output Disable to Output in High-Z — 6 — 6 ns tOH Output Hold from Address Change 3 — 3 — ns (1) (1) tPU (1) tPD(1) Chip Select to Power-Up Time 0 — 0 — ns Chip Deselect to Power-Down Time — 12 — 15 ns 12 — 15 — ns Write Cycle tWC Write Cycle Time tCW Chip Select to End-of-Write 9 — 10 — ns tAW Address Valid to End-of-Write 9 — 10 — ns tAS Address Set-up Time 0 — 0 — ns tWP Write Pulse Width 9 — 10 — ns tWR Write Recovery Time 0 — 0 — ns tDW Data Valid to End-of-Write 6 — 7 — ns tDH Data Hold Time 0 — 0 — ns Write Enable to Output in High-Z — 6 — 6 ns Output Active from End-of-Write 4 — 4 — ns tWHZ (1) tOW(1) NOTES: 1. This parameter is guaranteed with AC test load (Figure 2) by device characterization, but is not production tested. 7.1 2971 tbl 10 4 IDT61298SA CMOS STATIC RAM 256K (64K x 4-BIT) COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF READ CYCLE NO. 1(1) t RC ADDRESS t AA t OH OE t OLZ t OE (5) t OHZ (5) CS t ACS t CLZ t CHZ (5) DATAOUT (5) DATA VALID 2971 drw 05 TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4) t RC ADDRESS t AA t OH t OH DATA VALID DATAOUT 2971 drw 06 TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4) CS t ACS t CHZ t CLZ (5) DATAOUT (5) DATA VALID t PU t PD VCC I CC SUPPLY CURRENT I SB 2971 drw 07 NOTES: 1. WE is HIGH for Read cycle. 2. Device is continuously selected, CS is LOW. 3. Address valid prior to or coincident with CS transition LOW. 4. OE is LOW. 5. Transition is measured ±200mV from steady state. 7.1 5 IDT61298SA CMOS STATIC RAM 256K (64K x 4-BIT) COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1,2,3,5) tWC ADDRESS tAW CS tAS tWP (3) tWR WE tWHZ DATAOUT (6) tOW (6) (4) (4) tDW tDH DATA VALID DATAIN 2971 drw 08 TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1,2,5) tWC ADDRESS tAW CS tAS tWR tCW WE tDW DATAIN tDH DATA VALID 2971 drw 09 NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap of a LOW CS and a LOW WE. 3. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the spectified tWP. 4. During this period, I/O pins are in the output state so that the input signals must not be applied. 5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 6. Transition is measured ±200mV from steady state. 7.1 6 IDT61298SA CMOS STATIC RAM 256K (64K x 4-BIT) COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT 61298 SA XX XX X Device Type Power Speed Package Process/ Temperature Range Blank Commercial (0°C to +70°C) Y 300-mil SOJ (SO28-5) 12 15 Commercial Only Commercial Only Speed in nanoseconds 2971 drw 10 7.1 7