NCP5383 2 Phase Buck Controller with Integrated Gate Drivers and AVP The NCP5383 is a two phase buck controller used in low voltage, high current power supplies. Dual-edge pulse-width modulation (PWM) combined with inductor current sensing and adaptive voltage positioning (AVP) reduces system cost by providing the fastest initial response to transient loads thereby requiring less bulk and ceramic output capacitors to satisfy transient load-line requirements. A high performance operational error amplifier is provided, which allows for easy compensation of the system. Protection features include overcurrent protection, undervoltage lockout (UVLO), thermal shutdown and power good monitor. http://onsemi.com MARKING DIAGRAM 1 5383 ALYWG G 24 PIN QFN, 4x4 MN SUFFIX CASE 485L Features 5383 A L Y W G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package (Note: Microdot may be in either location) PIN CONNECTIONS PG BST1 TG1 SWN1 PGND1 BG1 •Dual-edge PWM for Fastest Initial Response to Transient Loading •High Performance Operational Error Amplifier •1% Internal Reference Voltage Accuracy •Phase-to-Phase Current Balancing •“Lossless” Differential Inductor Current Sensing •Differential Current Sense Amplifiers for Each Phase •Adaptive Voltage Positioning (AVP) •Frequency Range: 100 kHz – 400 kHz Set by the Resistor •Power Good Output with Internal Delays •Programmable Soft Start Time •Integrated Gate Drivers •This is a Pb-Free Device VCCP BG2 PGND2 SWN2 TG2 BST2 ROSC ILIM VCC AGND SS COMP Applications VFB VDRP CS1 CSN CS2 EN •Pentium IV Processors •Graphics Cards •Low Voltage, High Current Power Supplies (Top View) ORDERING INFORMATION Device NCP5383MNR2G Package Shipping† QFN-24 4000 / Tape & Reel (Pb-Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2007 December, 2007 - Rev. 3 1 Publication Order Number: NCP5383/D NCP5383 FAULT 2 SS SS Vcore 23 OVP (125% of VFB) UVP (75% of VFB) FB 22 PG 7 + 21 Gate Driver I 18 0.8 V AGND 4 19 6 8 VDRP CSN CS2 + 20 9 13 + - + - EN VCC VCCP BG1 PGND1 BST2 10 14 11 + - + 1 Gate Driver II OSCILLATOR + - 2 16 Fault Logic 12 3 9V TG2 SWN2 VCCP 17 ILIM SWN1 0.8 V 15 ROSC TG1 Droop Amplifier COMP CS1 BST1 + + - UVLO Figure 1. Simplified Block Diagram http://onsemi.com 2 24 BG2 PGND2 PG NCP5383 VCC NCP5383 VCC 3 12 V VCCP 1 ROSC VCCP 18 2 ILIM BST1 23 24 PG TG1 22 5 SS SWN1 21 BG1 19 PGND1 20 Vcore 5V VCCP VCC 7 VFB 6 COMP 8 VDRP 9 CS1 10 11 BST2 13 TG2 14 SWN2 15 BG2 17 PGND2 16 EN 12 CSN CS2 AGND 4 Figure 2. Typical Application Schematic http://onsemi.com 3 Vcore NCP5383 PIN DESCRIPTIONS Pin No. Symbol Description 1 ROSC A resistance from this pin to ground programs the oscillator frequency according to fSW = 1 / (ROSC w 100pF). Also, this pin supplies a trimmed output voltage of 2.00 V so it may be used to form a voltage divider at the ILIM pin to set the over current shutdown threshold as shown in the Applications Schematics. 2 ILIM Over current shutdown threshold. To program the shutdown threshold, connect this pin to the ROSC pin via a resistor divider as shown in the Applications Schematics. To disable the over current feature connect this pin directly to the ROSC pin. To guarantee correct operation, this pin should only be connected to the voltage generated by the ROSC pin – do not connect this pin to any externally generated voltages. 3 VCC Power for the internal control circuits. 4 AGND 5 SS 6 COMP 7 VFB Voltage feedback pin and error amplifier inverting input. Connect a resistor from this pin to VCORE. The value of this resistor and the amount of current from the droop resistor (RDRP) will set the amount of output voltage droop (AVP) during load. 8 VDRP Current signal output for Adaptive Voltage Positioning (AVP). The offset of this pin above the no-load set-point is proportional to the output current. Connect a resistor from this pin to VFB to set the amount of AVP current into the feedback resistor (RFB) that will result in output voltage droop. Leave this pin open for no AVP. 9 CSx Non-inverting input to current sense amplifier #x, x = 1, 2 10 CSxN 12 EN 18 VCCP 19, 17 BG 20, 16 PGND Ground reference for the bottom gate drivers 21, 15 SWN Switch node pin. This is the reference for the floating top gate driver. Connect this pin to the source of the top MOSFET. : Phase #x, x = 1, 2 22, 14 TG Top gate MOSFET driver pin. Connect this pin to the gate of the top N-channel MOSFET. : : Phase #x, x = 1,2 23, 13 BST Supply rail for the floating top gate driver. To form a boost circuit, use an external diode to bring the desired input voltage to this pin (cathode connected to BST pin). Connect a capacitor (CBST) between this pin and the PHASE pin. Typical values for CBST range from 0.1 mF to 1 mF. Ensure that CBST is placed near the IC.: Phase #x, x = 1, 2. 24 PG PowerGood output. Open drain type output with internal delays. The output is latched low if Vfb is 125% of VFB or 75% of VFB. Power supply return for the analog circuits that control output voltage. A capacitor from this pin to ground programs the soft-start time. Output of the error amplifier and input to the inverting pin of the PWM comparators. Inverting input to current sense amplifier #x, x = 1 (Tie to VCORE) When this pin is pulled High the controller is enabled. When it is pulled Low the controller will be disabled. Either an open-collector output (with a pull-up resistor) or a logic gate (CMOS or totem-pole output) may be used to drive this pin. A Low to High transition on this pin will induce soft start. If the Enable function is not required, this pin should be tied directly to VCCP. Power for the gate drivers Bottom gate MOSFET driver pin. Connect this pin to the gate of the bottom N-channel MOSFET.: Phase #x, x=1, 2 http://onsemi.com 4 NCP5383 ABSOLUTE MAXIMUM RATINGS Rating Value Unit Operating Ambient Temperature Range 0 to 70 °C Operating Junction Temperature Range 0 to 125 °C -55 to 150 °C Lead Temperature Soldering, Reflow (60 second maximum above 183°C): 230 °C Thermal Resistance, Junction-to-Ambient (RqJA) on a thermally conductive PCB in free air 56 °C/W ESD Susceptibility (Human Body Model) 2.0 kV Storage Temperature Range JEDEC Moisture Sensitivity Level 1 MSL Maximum Voltage VCC with respect to AGND 13.2 V Maximum Voltage VCCP and all other pins with respect to ground 5.5 V Maximum Voltage VBST and all other pins with respect to ground 18.7 V Maximum Voltage VBST and all other pins with respect to SWN 5.5 V Maximum Voltage SWN and all other pins with respect to ground 3.0 V Minimum Voltage SWN and all other pins with respect to ground -2.0 V Minimum Voltage all pins with respect to ground -0.3 V Maximum Current into pins: COMP, VDRP 3.0 mA Maximum Current out of pins: COMP, VDRP, ROSC, SS 3.0 mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 5 NCP5383 ELECTRICAL CHARACTERISTICS (Unless otherwise stated: 0°C < TA < 70°C; 0°C < TJ < 125°C; 4.5 V < VCC < 13.2 V; Fsw = 400 KHz) Parameter Test Conditions Min Typ Max Units Input Bias Current -200 -50 -10 nA Input Offset Voltage -1.0 1.0 mV 808 mV Error Amplifier Inverting Input Voltage 1.0 KW between VFB and COMP Pins 792 Open Loop DC Gain CL = 100 pF to GND, RL = 10 KW to GND 78 dB Open Loop Unity Gain Bandwidth CL = 100 pF to GND, RL = 10 KW to GND 15 MHz Open Loop Phase Margin CL = 100 pF to GND, RL = 10 KW to GND 65 deg Slew Rate DVin = 100 mV, G = -1 V/V, DVout = 1.0 V – 2.0 V, CL = 10 pF to GND, Load = ±125 mA to GND 5.0 V/ms Maximum Output Voltage ISOURCE = 2.0 mA 3.3 V Minimum Output Voltage ISINK = 2.0 mA 0.9 Output Source Current (Note 1) Vout = 3.0 V 2.0 mA Output Sink Current (Note 1) Vout = 1.0 V 2.0 mA 3.0 800 1.05 V Boost Current Supply Voltage Input Voltage VCCP Operating Voltage VCCP 4.5 12 18 V 4.5 5.0 5.5 V 5.7 6.0 6.3 VDRP Adaptive Voltage Positioning Amplifier Current Sense Input to VDRP Gain Current Sense Input to VDRP Output Unity Gain Bandwidth V/V CL = 330 pF to GND, RL = 10 KW to GND 7.2 MHz Current Sense Input to VDRP Output Slew Rate DVin = 100 mV, G = 6 V/V, DVout = 1.3 V – 1.9 V, CL = 330 pF to GND, Load = ±400 mA to GND 3.7 V/ms Current Summing Amp Output Offset Voltage CSx – CSNx = 0, CSx = 1 V 10 mV Maximum VDRP Output Voltage CSx – CSNx = 0.12 V, Isource = 1 mA Minimum VDRP Output Voltage CSx – CSNx = -0.12 V, Isink = 1 mA Output Source Current (Note 1) Vout = 1.2 V 9.0 mA Output Sink Current (Note 1) Vout = 1.0 V 2.0 mA 1.2 V 0.5 V Current Sense Amplifiers Input Bias Current CSx = CSxN = 1.4 V -200 -50 -1.0 nA Common Mode Input Voltage Range -0.3 3.3 V Differential Mode Input Voltage Range -120 120 mV 3.0 mV 6.3 V/V Input Offset Voltage CSx = CSxN = 1.00 V -3.0 Current Sense Input to PWM Gain 0 mV < (CSx- CSxN) < 25 mV TA = 25°C 5.7 1. Guaranteed by design, not tested in production. http://onsemi.com 6 6.0 NCP5383 ELECTRICAL CHARACTERISTICS (Unless otherwise stated: 0°C < TA < 70°C; 0°C < TJ < 125°C; 4.5 V < VCC < 13.2 V; Fsw = 400 KHz) Parameter Test Conditions Min Typ Max Units 400 KHz Oscillator Switching Frequency Range 100 Switching Frequency Accuracy ROSC = 100 KW 90 100 110 KHz Switching Frequency Accuracy ROSC = 49.9 KW 180 200 220 KHz Switching Frequency Accuracy ROSC = 24.9 KW 360 400 440 KHz 1.92 2.00 2.08 V 30 40 ns ROSC Output Voltage Modulators (PWM Comparators) Minimum Pulse Width (Note 1) Fs = 400 KHz Propagation Delay 20 ns Magnitude of the PWM Ramp 1.0 V 0% Duty Cycle COMP voltage when the PWM outputs remain LO 1.3 V 100% Duty Cycle COMP voltage when the PWM outputs remain HI 2.3 V PWM Comparator Offset Mismatch Phase Angle Error -15 PWM Linear Duty Cycle 40 Mv 15 deg 90 % Gate Drivers Upper Gate Source Vbst - Vswn = 5 V, VTG – VSWN = 4 V 1.8 W Upper Gate Sink Vbst - Vswn = 5 V, VTG – VSWN = 1 V 1.8 W Lower Gate Source VCCP = 5 V, Vgs = 4 V 1.8 W Lower Gate Sink VCCP = 5 V, Vgs = 1 V 0.9 W Upper gate transition times Cload = 3 nF 16 ns Cload = 3 nF 16 ns Cload = 3 nF 16 ns Cload = 3 nF 7.0 ns SWN falling to BG rising delay Cload = 3 nF 18 ns BG falling to TG rising delay Cload = 3 nF 40 ns 5.0 mA Lower gate transition times Soft-Start Soft-Start Pin Source Current Soft-Start Pin Discharge Voltage Fault = 1 50 Soft-Start Pin Discharge Time From EN = 0 to VSS pin < max discharge voltage, CSS = 0.01mF mV ms 5.0 Enable Input Enable High Input Leakage Current EN = 3.0 V Upper Threshold VUPPER Total Hysteresis VUPPER – VLOWER 10 mA 0.80 0.85 0.90 V 50 100 150 mV 160 C Thermal Shutdown Thermal Trip Point TSD 1. Guaranteed by design, not tested in production. http://onsemi.com 7 NCP5383 ELECTRICAL CHARACTERISTICS (Unless otherwise stated: 0°C < TA < 70°C; 0°C < TJ < 125°C; 4.5 V < VCC < 13.2 V; Fsw = 400 KHz) Parameter Test Conditions Min Typ Max Units 5.7 6.0 6.3 V/V 0.1 1.0 mA Current Limit Current Sense Amp to ILIM Gain 20mV<(Csx-CSxN)<60mV TA = 25°C ILIM Pin Input Bias Current Vilim = 2.0 V ILIM Pin Working Voltage Range 0.3 2.0 V ILIM Input Offset Voltage -50 50 mV 9.5 8.5 V Undervoltage Protection UVLO Start Threshold UVLO Stop Threshold VCC = 12 V 8.2 7.2 UVLO Hysteresis UVLO 9.0 8.0 1.0 VCCP = 5 V 3.7 Hysteresis 4.0 V 4.3 0.5 V V Power Good Output Saturation Voltage IPG = 10 mA, VCC = 12 Vdc 0.4 V Rise Time External pull-up of 1 KW to 1.25V, CTOT = 45pF, DVO = 10% to 90% 150 ns Output Voltage at Power-up External PG pull-up resistor of 2 KW to 5 V tR_VCC ≤ 3 x tR_5V, 1.0 V 0.1 mA 100 ms ≤ tR_VCC ≤ 20 ms High – Output Leakage Current PG = 5.5 V via 1 K Upper Threshold Voltage 125 % of VFB Lower Threshold Voltage 75 % of VFB Rising Delay VCORE increasing Falling Delay VCORE decreasing 0.3 1.40 5 http://onsemi.com 8 2 ms ms NCP5383 TYPICAL CHARACTERISTICS ROSC = 24.9 k VCC = 5.0 V 405 fSW, FREQUENCY (kHz) VCCP, UVLO THRESHOLD VOLTAGE (V) 408 402 399 396 393 25 50 75 100 4.5 VCC Increasing Voltage 4.0 VCC Decreasing Voltage 3.5 3.0 125 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 3. Oscillator Frequency vs. Temperature Figure 4. UVLO Threshold Voltage vs. Temperature 125 10.8 5.2 10.7 ICC, CURRENT (mA) 5.1 5.0 4.9 10.6 10.5 10.4 10.3 FSW = 400 kHz 4.8 10.2 0 25 50 75 100 125 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 5. Soft-Start Sourcing Current vs. Temperature Figure 6. ICC Current vs. Temperature 10 16.8 9.5 16.5 ICCP, CURRENT (mA) VCC UVLO THRESHOLD VOLTAGE (V) SOFT-START SOURCING CURRENT (mA) 390 0 5.0 VCC Increasing Voltage 9.0 8.5 VCC Decreasing Voltage 8.0 125 16.2 15.9 15.6 7.5 15.3 7.0 15.0 FSW = 400 kHz 0 25 50 75 100 125 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 7. VCC UVLO Threshold Voltage vs. Temperature Figure 8. ICCP Current vs. Temperature http://onsemi.com 9 125 NCP5383 1.980 1.0 1.975 0.9 ROSC VOLTAGE (V) Enable Increasing Voltage 0.8 Enable Decreasing Voltage 0.7 0.6 1.970 1.965 1.960 1.955 1.950 0.5 0 25 50 75 100 125 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 9. Enable Threshold Voltage vs. Temperature Figure 10. ROSC Voltage vs. Temperature 804 Vref, REFERENCE VOLTAGE (mV) EN, ENABLE THRESHOLD VOLTAGE (V) TYPICAL CHARACTERISTICS 802 800 798 796 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) Figure 11. Reference Voltage vs. Temperature http://onsemi.com 10 125 NCP5383 Figure 12. 20 A Sustaining Load Figure 13. UVLO Start VCCP Figure 14. UVLO Stop Figure 15. Power-up Waveforms VCCP Figure 16. Soft Start Sequence Figure 17. Power-down Waveforms http://onsemi.com 11 NCP5383 APPLICATIONS INFORMATION PROTECTION FEATURES General Undervoltage Lockout The NCP5383 dual edge modulated multiphase PWM controller is specifically designed with the necessary features for a high current power system. The IC consists of the following blocks: High Performance Voltage Error Amplifier, Precision Oscillator and Triangle Wave Generators, and PWM Comparators. Protection features include Undervoltage Lockout, Soft-Start, Overcurrent Protection, Thermal Shutdown and Power Good Monitor. An undervoltage lockout (UVLO) senses the VCC input. During powerup, the input voltage to the controller is monitored, and the PWM outputs and the soft-start circuit are disabled until the input voltage exceeds the threshold voltage of the UVLO comparator. The UVLO comparator incorporates hysteresis to avoid chattering, since VCC is likely to decrease as soon as the converter initiates soft-start. There is a separate undervoltage lockout (UVLO) for the drivers that sense the VCCP inputs. High Performance Voltage Error Amplifier Overcurrent Shutdown The error amplifier is designed to provide high slew rate and bandwidth. A capacitor from COMP to VFB is required for stable unity gain test configurations. A programmable overcurrent function is incorporated within the IC. A comparator and latch makeup this function. The inverting input of the comparator is connected to the ILIM pin. The voltage at this pin sets the maximum output current the converter can produce. The ROSC pin provides a convenient and accurate reference voltage from which a resistor divider can create the overcurrent setpoint voltage. Although not actually disabled, tying the ILIM pin directly to the ROSC pin sets the limit above useful levels – effectively disabling overcurrent shutdown. The comparator non inverting input is the summed current information from the current sense amplifiers. The overcurrent latch is set when the current information exceeds the voltage at the ILIM pin. The outputs are immediately, and the soft-start is pulled low. The outputs will remain disabled until the VCC voltage is removed and re-applied, or the ENABLE input is brought low and then high. Oscillator and Triangle Wave Generator A programmable precision oscillator is provided. The oscillator 's frequency is programmed by the resistance connected from the ROSC pin to ground. The user will usually form this resistance from two resistors in order to create a voltage divider that uses the ROSC output voltage as the reference for creating the current limit setpoint voltage. The oscillator frequency range is 100 kHz/phase to 400 kHz/phase. The oscillator generates 2 triangle waveforms (symmetrical rising and falling slopes) between 1.3 V and 2.3 V. The triangle waves have a phase delay between them such that for 2 phase operation the PWM outputs are separated by 180 degrees. PWM Comparators with Hysteresis Two PWM comparators receive the error amplifier output signal at their non inverting input. Each comparator receives one of the triangle waves offset by 1.3 V at it's inverting input. During steady state operation, the duty cycle will center on the valley of the triangle waveform, with steady state duty cycle calculated by Vout/Vin. During a transient event, both high and low comparator output transitions shift phase to the points where the error amplifier output intersects the down and up ramp of the triangle wave. Power Good Monitor NCP5383 has a power good monitor set at 125% of Vfb or 75% of Vfb for upper and lower thresholds respectively. It is an open drain type output. Soft-Start The NCP5383 incorporates an externally programmable soft-start. The soft-start circuit works by controlling the ramp-up of the Vref voltage during powerup. The initial soft-start pin voltage is 0 V. The soft-start sequence ends when VSS = 0.8 V. The soft-start pin is pulled to 0 V if there is an overcurrent shutdown, if VCC is below the UVLO threshold, or if VCCP is below the UVLO threshold. Programming the Current Limit and Oscillator Frequency The OSC pin provides a 2.0 V reference voltage which is divided down with a resistor divider and fed into the current limit pin ILIM. Calculate the total series resistance to set the frequency and then calculate the individual values for current limit divider. The series resistors RLIM1 and RLIM2 sink current to ground. This current is internally mirrored into a capacitor to create an oscillator. The period is proportional to the resistance and frequency is inversely proportional to the resistance. http://onsemi.com 12 NCP5383 120 Calculate the current limit voltage: The current limit function is based on the total sensed current of two phases multiplied by a gain of 5.94. DCR sensed inductor current is function of the winding temperature. The best approach is to set the maximum current limit based on the expected average maximum temperature of the inductor windings. ROSC (KW) 100 80 60 DCRTmax + DCR25C· (1 ) 0.00393·C-1(TTmax-25·C)) 40 (eq. 1) 20 0 100 200 300 400 FREQUENCY (KHz) Figure 18. ROSC vs. Phase Frequency ǒ VILIMIT ^ 5.94· IMIN_OCP·DCRTmax ) ǓǓ * 0.02 ǒ DCR50C·Vout · Vin-Vout * (N-1)· Vout L L 2·Vin·Fs (eq. 2) Solve for the individual resistors: V ·ROSC RLIM2 + ILIMIT 2·V RLIM1 + ROSC-RLIM2 (eq. 3) Final Equation for the Current Limit Threshold ILIMIT(Tinductor) ^ 2·V·RLIM2 Ǔ ǒRLIM1)RLIM2 ) 0.02 5.94·(DCR25C·(1 ) 0.00393·C-1(TInductor-25·C))) * ǒ Ǔ Vout · Vin-Vout * 1· Vout 2·Vin·Fs L L (eq. 4) Selecting the closest available values of 16.9KW for RLIM1 and 15.8 KW yield a nominal operating frequency of 305 Khz and an approximate current limit of 180A at 100C. The total sensed current can be observed at the VDRP pin added to a positive, no-load offset of approximately 0.8V. Inductor Selection: When using the inductor current sensing it is recommended that the inductor does not saturate by more than 10% at the maximum load. The inductor also must not go into hard saturation before current limit trips. Small DCR values can be used, however current sharing accuracy and droop accuracy decrease as DCR decreases. Figure 19. The demoboard inductor measured 950 nH and 0.75 mW at room temp. The actual value used for Rsense matches the equation for Rsense at approximately 50C. Because the inductor value is a function of load and inductor temperature final selection of R is best done experimentally on the bench by monitoring the Vdroop pin and performing a step load test on the actual solution. It is desirable to keep the Rsense resistor value below 1.0 k whenever possible by increasing the capacitor values in the inductor compensation network. The bias current flowing out of the current sense pins is approximately 100 nA. This current flows through the current sense resistor and creates an offset at the capacitor which will appear as a load current at the Vdroop pin. A 1.0 k resistor will keep this offset at the droop pin below 2.5 mV. Inductor Current Sense Compensation The NCP5383 uses the inductor current sensing method. This method uses an RC filter to cancel out the inductance of the inductor and recover the voltage that is the result of the current flowing through the inductor's DCR. This is done by matching the RC time constant of the current sense filter to the L/DCR time constant. The first cut approach is to use a 0.47 mF capacitor for C and then solve for R. Rsense(T) + (eq. 5) L 0.47·mF·DCR25C·(1 ) 0.00393·C-1·(T-25·C)) http://onsemi.com 13 NCP5383 Simple Average PSPICE Model A simple state average model shown in Figure 20 can be used to determine a stable solution and provide insight into the control system. Figure 20. Thermal Shutdown Droop Injection The VDRP signal is generated by summing the sensed output currents for each phase and applying a gain of approximately six. VDRP is externally summed into the feedback network by the resistor RDRP. This induces an offset which is proportional to the output current thereby forcing the controlled resistive output impedance. RRDP determines the target output impedance by the basic equation: Vout + Zout + RFB·DCR·5.94 Iout RDRP The NCP5383 also provides Thermal Shutdown (TSD) for added protection. The TSD circuit monitors the die temperature and turns off the top and bottom gate drivers if an over temperature condition is detected. The internal soft-start capacitor is also discharged. This is a latched state and requires a power cycle to reset. (eq. 6) RDRP + RFB·DCR·5.94 Zout http://onsemi.com 14 NCP5383 PACKAGE DIMENSIONS 24 PIN QFN, 4x4 CASE 485L-01 ISSUE O D A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. B PIN 1 IDENTIFICATION E 2X 0.15 C DIM A A1 A2 A3 b D D2 E E2 e L 0.15 C 2X A2 0.10 C A 0.08 C A3 A1 SEATING PLANE REF C MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.60 0.80 0.20 REF 0.23 0.28 4.00 BSC 2.70 2.90 4.00 BSC 2.70 2.90 0.50 BSC 0.35 0.45 D2 e L 7 12 6 13 E2 24X b 1 0.10 C A B 18 24 19 e 0.05 C ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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