STMicroelectronics M95160FMN6TG/S 16-kbit serial spi bus eeprom with high-speed clock Datasheet

M95160 M95160-W
M95160-R M95160-F
16-Kbit serial SPI bus EEPROM
with high-speed clock
Datasheet − production data
Features
■
Compatible with the Serial Peripheral Interface
(SPI) bus
■
Memory array
– 16 Kb (2 Kbytes) of EEPROM
– Page size: 32 bytes
SO8 (MN)
150 mil width
■
Write
– Byte Write within 5 ms
– Page Write within 5 ms
■
Write Protect: quarter, half or whole memory
array
■
High-speed clock: 10 MHz
■
Single supply voltage:
– 4.5 V to 5.5 V for M95160
– 2.5 V to 5.5 V for M95160-W
– 1.8 V to 5.5 V for M95160-R
– 1.7 V to 5.5 V for M95160-F
■
Operating temperature range: from -40°C up to
+85°C
■
Enhanced ESD protection
■
More than 1 million Write cycles
■
More than 40-year data retention
■
Packages
– RoHS compliant and halogen-free
(ECOPACK®)
January 2013
This is information on a product in full production.
TSSOP8 (DW)
169 mil width
UFDFPN8 (MC)
2 x 3 mm (MLP)
WLCSP (CS)
(preliminary data)
Doc ID 022580 Rev 3
1/46
www.st.com
1
Contents
M95160 M95160-W M95160-R M95160-F
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
3.1
Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6
Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.7
VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.8
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
5
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.1
6
5.1.2
Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.3
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.4
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2
Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3
Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.5
Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.1
2/46
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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Contents
6.3.2
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.3
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.4
SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.5
Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.6
Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1
Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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List of tables
M95160 M95160-W M95160-R M95160-F
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
4/46
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Operating conditions (M95160, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Operating conditions (M95160-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Operating conditions (M95160-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Operating conditions (M95160-F, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DC characteristics (M95160, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DC characteristics (M95160-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DC characteristics (M95160-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DC characteristics (M95160-F, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
AC characteristics (M95160-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
AC characteristics (M95160-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
AC characteristics (M95160-F, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
AC characteristics (M95160, device grade 6)
End of life products: these values apply only to M95160-MN6TP/S devices . . . . . . . . . . . 36
AC characteristics (M95160-W, device grade 6)
End of life products: these values apply only to M95160-WMN6TP/S
and M95160-WDW6TP/S devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data . . . . . . . . . . . 40
TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 41
UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
WLCSP-R – 1.350 x 1.365 mm 0.4 mm pitch 8 bumps, package mechanical
data (preliminary data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WLCSP connections (top view, marking side, with balls on the underside) . . . . . . . . . . . . . 7
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 40
TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 41
UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no lead, package outline. . . . . . . 42
WLCSP-R – 1.350 x 1.365 mm 0.4 mm pitch 8 bumps, package outline . . . . . . . . . . . . . . 43
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Description
1
M95160 M95160-W M95160-R M95160-F
Description
The M95160 devices are Electrically Erasable PROgrammable Memories (EEPROMs)
organized as 2048 x 8 bits, accessed through the SPI bus.
The M95160 can operate with a supply voltage from 4.5 V to 5.5 V, the M95160-W can
operate with a supply voltage from 2.5 V to 5.5 V, the M95160-R can operate with a supply
voltage from 1.8 V to 5.5 V, and the M95160-F can operate with a supply voltage from 1.7 V
to 5.5 V, over an ambient temperature range of -40 °C / +85 °C.
Figure 1.
Logic diagram
VCC
D
Q
C
S
M95xxx
W
HOLD
VSS
AI01789C
The SPI bus signals are C, D and Q, as shown in Figure 1 and Table 1. The device is
selected when Chip Select (S) is driven low. Communications with the device can be
interrupted when the HOLD is driven low.
Table 1.
Signal names
Signal name
6/46
Function
Direction
C
Serial Clock
Input
D
Serial Data Input
Input
Q
Serial Data Output
Output
S
Chip Select
Input
W
Write Protect
Input
HOLD
Hold
Input
VCC
Supply voltage
VSS
Ground
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M95160 M95160-W M95160-R M95160-F
Figure 2.
Description
8-pin package connections (top view)
M95xxx
S
Q
W
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
C
D
AI01790D
1. See Section 10: Package mechanical data section for package dimensions, and how to identify pin 1.
Figure 3.
WLCSP connections (top view, marking side, with balls on the underside)
Q
VSS
D
S
HOLD
W
VCC
C
Orientation reference
ai15166
Caution:
As EEPROM cells lose their charge (and so their binary value) when exposed to ultra violet
(UV) light, EEPROM dice delivered in wafer form or in WLCSP package by
STMicroelectronics must never be exposed to UV light.
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Memory organization
2
M95160 M95160-W M95160-R M95160-F
Memory organization
The memory is organized as shown in the following figure.
Figure 4.
Block diagram
HOLD
W
High voltage
generator
Control logic
S
C
D
I/O shift register
Q
Address register
and counter
Data
register
Size of the
read-only
EEPROM
area
Y decoder
Status
Register
1 page
X decoder
AI01272d
8/46
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M95160 M95160-W M95160-R M95160-F
3
Signal description
Signal description
During all operations, VCC must be held stable and within the specified valid range:
VCC(min) to VCC(max).
All of the input and output signals must be held high or low (according to voltages of VIH,
VOH, VIL or VOL, as specified in Section 9: DC and AC parameters). These signals are
described next.
3.1
Serial Data Output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
3.2
Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).
3.3
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) change from the falling edge of Serial Clock (C).
3.4
Chip Select (S)
When this input signal is high, the device is deselected and Serial Data Output (Q) is at high
impedance. The device is in the Standby Power mode, unless an internal Write cycle is in
progress. Driving Chip Select (S) low selects the device, placing it in the Active Power mode.
After power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
3.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven low.
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Signal description
3.6
M95160 M95160-W M95160-R M95160-F
Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is
protected against Write instructions (as specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either high or low, and must be stable during all Write instructions.
3.7
VCC supply voltage
VCC is the supply voltage.
3.8
VSS ground
VSS is the reference for all signals, including the VCC supply voltage.
10/46
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M95160 M95160-W M95160-R M95160-F
4
Connecting to the SPI bus
Connecting to the SPI bus
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
Figure 5.
Bus master and memory devices on the SPI bus
VSS
VCC
R
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
VCC
C Q D
SPI Bus Master
SPI Memory
Device
R
CS3
VCC
C Q D
VSS
C Q D
VCC
VSS
SPI Memory
Device
R
VSS
SPI Memory
Device
R
CS2 CS1
S
W
HOLD
S
W
HOLD
S
W
HOLD
AI12836b
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
Figure 5 shows an example of three memory devices connected to an SPI bus master. Only
one memory device is selected at a time, so only one memory device drives the Serial Data
Output (Q) line at a time. The other memory devices are high impedance.
The pull-up resistor R (represented in Figure 5) ensures that a device is not selected if the
Bus Master leaves the S line in the high impedance state.
In applications where the Bus Master may leave all SPI bus lines in high impedance at the
same time (for example, if the Bus Master is reset during the transmission of an instruction),
the clock line (C) must be connected to an external pull-down resistor so that, if all
inputs/outputs become high impedance, the C line is pulled low (while the S line is pulled
high): this ensures that S and C do not become high at the same time, and so, that the
tSHCH requirement is met. The typical value of R is 100 kΩ..
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Connecting to the SPI bus
4.1
M95160 M95160-W M95160-R M95160-F
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the following two modes:
●
CPOL=0, CPHA=0
●
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 6, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
●
C remains at 0 for (CPOL=0, CPHA=0)
●
C remains at 1 for (CPOL=1, CPHA=1)
Figure 6.
SPI modes supported
CPOL CPHA
0
0
C
1
1
C
D
MSB
Q
MSB
AI01438B
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Operating features
5
Operating features
5.1
Supply voltage (VCC)
5.1.1
Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions
in Section 9: DC and AC parameters). This voltage must remain stable and valid until the
end of the transmission of the instruction and, for a Write instruction, until the completion of
the internal write cycle (tW). In order to secure a stable DC supply voltage, it is
recommended to decouple the VCC line with a suitable capacitor (usually of the order of
10 nF to 100 nF) close to the VCC/VSS device pins.
5.1.2
Device reset
In order to prevent erroneous instruction decoding and inadvertent Write operations during
power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not
respond to any instruction until VCC reaches the POR threshold voltage. This threshold is
lower than the minimum VCC operating voltage (see Operating conditions in Section 9: DC
and AC parameters).
At power-up, when VCC passes over the POR threshold, the device is reset and is in the
following state:
●
in Standby Power mode,
●
deselected,
●
Status Register values:
–
The Write Enable Latch (WEL) bit is reset to 0.
–
The Write In Progress (WIP) bit is reset to 0.
–
The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).
It is important to note that the device must not be accessed until VCC reaches a valid and
stable level within the specified [VCC(min), VCC(max)] range, as defined under Operating
conditions in Section 9: DC and AC parameters.
5.1.3
Power-up conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this
time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage. It is
therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see
Figure 5).
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edgesensitive as well as level-sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been high, prior to going low to start the first operation.
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
defined under Operating conditions in Section 9: DC and AC parameters, and the rise time
must not vary faster than 1 V/µs.
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Operating features
5.1.4
M95160 M95160-W M95160-R M95160-F
Power-down
During power-down (continuous decrease of the VCC supply voltage below the minimum
VCC operating voltage defined under Operating conditions in Section 9: DC and AC
parameters), the device must be:
5.2
●
deselected (Chip Select S should be allowed to follow the voltage applied on VCC),
●
in Standby Power mode (there should not be any internal write cycle in progress).
Active Power and Standby Power modes
When Chip Select (S) is low, the device is selected, and in the Active Power mode. The
device consumes ICC.
When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in
progress, the device then goes into the Standby Power mode, and the device consumption
drops to ICC1, as specified in DC characteristics (see Section 9: DC and AC parameters).
5.3
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
To enter the Hold condition, the device must be selected, with Chip Select (S) low.
During the Hold condition, the Serial Data Output (Q) is high impedance, and the Serial
Data Input (D) and the Serial Clock (C) are Don’t Care.
Normally, the device is kept selected for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition has the effect of resetting the state of
the device, and this mechanism can be used if required to reset any processes that had
been in progress.(a)(b)
Figure 7.
Hold condition activation
c
HOLD
Hold
condition
Hold
condition
ai02029E
The Hold condition starts when the Hold (HOLD) signal is driven low when Serial Clock (C)
is already low (as shown in Figure 7).
a. This resets the internal logic, except the WEL and WIP bits of the Status Register.
b. In the specific case where the device has shifted in a Write command (Inst + Address + data bytes, each data
byte being exactly 8 bits), deselecting the device also triggers the Write cycle of this decoded command.
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Operating features
The Hold condition ends when the Hold (HOLD) signal is driven high when Serial Clock (C)
is already low.
Figure 7 also shows what happens if the rising and falling edges are not timed to coincide
with Serial Clock (C) being low.
5.4
Status Register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a
detailed description of the Status Register bits.
5.5
Data protection and protocol control
The device features the following data protection mechanisms:
●
Before accepting the execution of the Write and Write Status Register instructions, the
device checks whether the number of clock pulses comprised in the instructions is a
multiple of eight.
●
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit.
●
The Block Protect (BP1, BP0) bits in the Status Register are used to configure part of
the memory as read-only.
●
The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits in the
Status Register.
For any instruction to be accepted, and executed, Chip Select (S) must be driven high after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points should be noted in the previous sentence:
●
The “last bit of the instruction” can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
●
The “next rising edge of Serial Clock (C)” might (or might not) be the next bus
transaction for some other device on the SPI bus.
Table 2.
Write-protected block size
Status Register bits
Protected block
Protected array addresses
0
none
none
0
1
Upper quarter
0600h - 07FFh
1
0
Upper half
0400h - 07FFh
1
1
Whole memory
0000h - 07FFh
BP1
BP0
0
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Instructions
6
M95160 M95160-W M95160-R M95160-F
Instructions
Each instruction starts with a single-byte code, as summarized in Table 3.
If an invalid instruction is sent (one not contained in Table 3), the device automatically
deselects itself.
Table 3.
Instruction set
Instruction
Description
WREN
Write Enable
0000 0110
WRDI
Write Disable
0000 0100
RDSR
Read Status Register
0000 0101
WRSR
Write Status Register
0000 0001
READ
Read from Memory Array
0000 0011
WRITE
Write to Memory Array
0000 0010
Table 4.
Address range bits
A10-A0(1)
Address significant bits
1. Upper MSBs are Don’t Care.
16/46
Instruction format
Doc ID 022580 Rev 3
M95160 M95160-W M95160-R M95160-F
6.1
Instructions
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for the device to be deselected, by Chip Select (S) being driven
high.
Figure 8.
Write Enable (WREN) sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI02281E
6.2
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 9, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
●
Power-up
●
WRDI instruction execution
●
WRSR instruction completion
●
WRITE instruction completion.
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Instructions
M95160 M95160-W M95160-R M95160-F
Figure 9.
Write Disable (WRDI) sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI03750D
6.3
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction is used to read the Status Register. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in Figure 10.
Figure 10. Read Status Register (RDSR) sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
D
Status Register Out
Status Register Out
High Impedance
Q
7
6
5
4
3
MSB
2
1
0
7
6
5
4
3
2
1
0
7
MSB
AI02031E
The status and control bits of the Status Register are as follows:
6.3.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0, no such
cycle is in progress.
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6.3.2
Instructions
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1, the internal Write Enable Latch is set. When set to 0, the internal Write
Enable Latch is reset, and no Write or Write Status Register instruction is accepted.
The WEL bit is returned to its reset state by the following events:
6.3.3
●
Power-up
●
Write Disable (WRDI) instruction completion
●
Write Status Register (WRSR) instruction completion
●
Write (WRITE) instruction completion
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non volatile. They define the size of the area to be
software-protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set
to 1, the relevant memory area (as defined in Table 2) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
6.3.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal enable the device to be put in the Hardware Protected mode (when the Status
Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this
mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits
and the Write Status Register (WRSR) instruction is no longer accepted for execution.
Table 5.
Status Register format
b7
SRWD
b0
0
0
0
BP1
BP0
WEL
WIP
Status Register Write Protect
Block Protect bits
Write Enable Latch bit
Write In Progress bit
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Instructions
6.4
M95160 M95160-W M95160-R M95160-F
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction is used to write new values to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must have been
previously executed.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low,
followed by the instruction code, the data byte on Serial Data input (D) and Chip Select (S)
driven high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that
latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C).
Otherwise, the Write Status Register (WRSR) instruction is not executed.
The instruction sequence is shown in Figure 11.
Figure 11. Write Status Register (WRSR) sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
Status
Register In
7
D
High Impedance
6
5
4
3
2
1
0
MSB
Q
AI02282D
Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the selftimed Write cycle that takes tW to complete (as specified in AC tables under Section 9: DC
and AC parameters).
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed
Write cycle tW, and 0 when the Write cycle is complete. The WEL bit (Write Enable Latch) is
also reset at the end of the Write cycle tW.
The Write Status Register (WRSR) instruction enables the user to change the values of the
BP1, BP0 and SRWD bits:
●
The Block Protect (BP1, BP0) bits define the size of the area that is to be treated as
read-only, as defined in Table 2.
●
The SRWD (Status Register Write Disable) bit, in accordance with the signal read on
the Write Protect pin (W), enables the user to set or reset the Write protection mode of
the Status Register itself, as defined in Table 6. When in Write-protected mode, the
Write Status Register (WRSR) instruction is not executed.
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the
WRSR instruction, including the tW Write cycle.
The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1, b0 bits in
the Status Register. Bits b6, b5, b4 are always read as 0.
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Table 6.
Protection modes
W
SRWD
signal
bit
1
0
0
0
1
0
Instructions
1
1
Mode
Write protection of the
Status Register
Memory content
Protected area(1)
Unprotected area(1)
Status Register is
writable (if the WREN
Software- instruction has set the
protected WEL bit).
(SPM)
The values in the BP1
and BP0 bits can be
changed.
Write-protected
Ready to accept
Write instructions
Status Register is
Hardware writeHardwareprotected.
protected
The values in the BP1
(HPM)
and BP0 bits cannot be
changed.
Write-protected
Ready to accept
Write instructions
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register. See Table 2.
The protection features of the device are summarized in Table 6.
When the Status Register Write Disable (SRWD) bit in the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register (provided that the WEL bit has
previously been set by a WREN instruction), regardless of the logic level applied on the
Write Protect (W) input pin.
When the Status Register Write Disable (SRWD) bit in the Status Register is set to 1, two
cases should be considered, depending on the state of the Write Protect (W) input pin:
●
If Write Protect (W) is driven high, it is possible to write to the Status Register (provided
that the WEL bit has previously been set by a WREN instruction).
●
If Write Protect (W) is driven low, it is not possible to write to the Status Register even if
the WEL bit has previously been set by a WREN instruction. (Attempts to write to the
Status Register are rejected, and are not accepted for execution). As a consequence,
all the data bytes in the memory area, which are Software-protected (SPM) by the
Block Protect (BP1, BP0) bits in the Status Register, are also hardware-protected
against data modification.
Regardless of the order of the two events, the Hardware-protected mode (HPM) can be
entered by:
●
either setting the SRWD bit after driving the Write Protect (W) input pin low,
●
or driving the Write Protect (W) input pin low after setting the SRWD bit.
Once the Hardware-protected mode (HPM) has been entered, the only way of exiting it is to
pull high the Write Protect (W) input pin.
If the Write Protect (W) input pin is permanently tied high, the Hardware-protected mode
(HPM) can never be activated, and only the Software-protected mode (SPM), using the
Block Protect (BP1, BP0) bits in the Status Register, can be used.
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Instructions
6.5
M95160 M95160-W M95160-R M95160-F
Read from Memory Array (READ)
As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
Input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data Output (Q).
Figure 12. Read from Memory Array (READ) sequence
S
0
1
2
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
15 14 13
D
3
2
1
0
MSB
Data Out 1
High Impedance
7
Q
6
5
4
3
2
Data Out 2
1
0
7
MSB
AI01793D
1. Depending on the memory size, as shown in Table 4, the most significant address bits are Don’t Care.
If Chip Select (S) continues to be driven low, the internal address register is incremented
automatically, and the byte of data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
6.6
Write to Memory Array (WRITE)
As shown in Figure 13, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted
in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input
data. The self-timed Write cycle, triggered by the Chip Select (S) rising edge, continues for a
period tW (as specified in AC characteristics in Section 9: DC and AC parameters), at the
end of which the Write in Progress (WIP) bit is reset to 0.
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Instructions
Figure 13. Byte Write (WRITE) sequence
S
0
1
2
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
15 14 13
D
3
2
Data Byte
1
0
7
6
5
4
3
2
1
0
High Impedance
Q
AI01795D
1. Depending on the memory size, as shown in Table 4, the most significant address bits are Don’t Care.
In the case of Figure 13, Chip Select (S) is driven high after the eighth bit of the data byte
has been latched in, indicating that the instruction is being used to write a single byte.
However, if Chip Select (S) continues to be driven low, as shown in Figure 14, the next byte
of input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If more bytes are sent than will fit up to the end of the page, a
condition known as “roll-over” occurs. In case of roll-over, the bytes exceeding the page size
are overwritten from location 0 of the same page.
The instruction is not accepted, and is not executed, under the following conditions:
Note:
●
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before),
●
if a Write cycle is already in progress,
●
if the device has not been deselected, by driving high Chip Select (S), at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in),
●
if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
The self-timed write cycle tW is internally executed as a sequence of two consecutive
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.
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Instructions
M95160 M95160-W M95160-R M95160-F
Figure 14. Page Write (WRITE) sequence
S
0
1
2
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
15 14 13
D
3
2
Data Byte 1
1
0
7
6
5
4
3
2
0
1
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Data Byte 2
D
7
6
5
4
3
2
Data Byte 3
1
0
7
6
5
4
3
2
Data Byte N
1
0
6
5
4
3
2
1
0
AI01796D
1. Depending on the memory size, as shown in Table 4, the most significant address bits are Don’t Care.
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Power-up and delivery state
7
Power-up and delivery state
7.1
Power-up state
After power-up, the device is in the following state:
●
Standby power mode,
●
deselected (after power-up, a falling edge is required on Chip Select (S) before any
instructions can be started),
●
not in the Hold condition,
●
the Write Enable Latch (WEL) is reset to 0,
●
Write In Progress (WIP) is reset to 0.
The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous
power-down (they are non-volatile bits).
7.2
Initial delivery state
The device is delivered with the memory array bits and identification page bits set to all 1s
(each byte = FFh). The Status Register Write Disable (SRWD) and Block Protect (BP1 and
BP0) bits are initialized to 0.
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Maximum rating
8
M95160 M95160-W M95160-R M95160-F
Maximum rating
Stressing the device outside the ratings listed in Table 7 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 7.
Absolute maximum ratings
Symbol
TSTG
TLEAD
Parameter
Min.
Max.
Unit
Ambient operating temperature
–40
130
°C
Storage temperature
–65
150
°C
Lead temperature during soldering
See
note (1)
°C
VO
Output voltage
–0.50
VCC+0.6
V
VI
Input voltage
–0.50
6.5
V
VCC
Supply voltage
–0.50
6.5
V
IOL
DC output current (Q = 0)
5
mA
IOH
DC output current (Q = 1)
5
mA
4000
V
VESD
Electrostatic discharge voltage (human body
model)(2)
1. Compliant with JEDEC Std J-STD-020 (for small body, Sn-Pb or Pb assembly), with the ST ECOPACK®
7191395 specification, and with the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
2. Positive and negative pulses applied on different combinations of pin connections, according to AECQ100-002 (compliant with JEDEC Std JESD22-A114, C1=100 pF, R1=1500 Ω, R2=500 Ω).
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9
DC and AC parameters
DC and AC parameters
This section summarizes the operating conditions and the DC/AC characteristics of the
device.
Table 8.
Operating conditions (M95160, device grade 6)
Symbol
VCC
TA
Table 9.
Parameter
Min.
Max.
Unit
Supply voltage
4.5
5.5
V
Ambient operating temperature
–40
85
°C
Min.
Max.
Unit
Supply voltage
2.5
5.5
V
Ambient operating temperature
–40
85
°C
Min.
Max.
Unit
Supply voltage
1.8
5.5
V
Ambient operating temperature
–40
85
°C
Min.
Max.
Unit
Supply voltage
1.7
5.5
V
Ambient operating temperature
–40
85
°C
Max.
Unit
Operating conditions (M95160-W, device grade 6)
Symbol
VCC
TA
Table 10.
Parameter
Operating conditions (M95160-R, device grade 6)
Symbol
VCC
TA
Table 11.
Parameter
Operating conditions (M95160-F, device grade 6)
Symbol
VCC
TA
Table 12.
Parameter
AC measurement conditions
Symbol
CL
Parameter
Load capacitance
Min.
30
Input rise and fall times
pF
50
ns
Input pulse voltages
0.2 VCC to 0.8 VCC
V
Input and output timing reference voltages
0.3 VCC to 0.7 VCC
V
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DC and AC parameters
M95160 M95160-W M95160-R M95160-F
Figure 15. AC measurement I/O waveform
)NPUT VOLTAGE LEVELS
6##
)NPUT AND OUTPUT
TIMING REFERENCE LEVELS
6##
6##
6##
!)#
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Table 13.
Capacitance
Symbol
COUT
CIN
DC and AC parameters
Test conditions(1)
Parameter
Max.
Unit
VOUT = 0 V
8
pF
Input capacitance (D)
VIN = 0 V
8
pF
Input capacitance (other pins)
VIN = 0 V
6
pF
Output capacitance (Q)
Min.
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 5 MHz.
Table 14.
Memory cell data retention
Parameter
Test conditions
Min.
Unit
Data retention(1)
TA = 55 °C
40
Year
Cycling
TA = 25 °C
1 million
Cycle
1. The data retention behavior is checked in production. The 40-year limit is defined from characterization and
qualification results.
Table 15.
Symbol
DC characteristics (M95160, device grade 6)
Test conditions in addition to
those defined in Table 8 and
Table 12
Parameter
Min.
Max.
Unit
ILI
Input leakage current
VIN = VSS or VCC
±2
µA
ILO
Output leakage current
S = VCC, VOUT = VSS or VCC
±2
µA
ICC
Supply current (Read)
C = 0.1 VCC/0.9 VCC at 10 MHz,
VCC = 5 V, Q = open
5
mA
ICC1
Supply current
(Standby)
S = VCC, VCC = 5 V,
VIN = VSS or VCC
2
µA
VIL
Input low voltage
–0.45
0.3 VCC
V
VIH
Input high voltage
0.7 VCC
VCC+1
V
VOL(1)
Output low voltage
IOL = 2 mA, VCC = 5 V
0.4
V
Output high voltage
IOH = –2 mA, VCC = 5 V
VOH
(1)
VRES(2)
Internal reset threshold
voltage
0.8 VCC
2.5
V
3.5
V
1. For all 5 V range devices, the device meets the output requirements for both TTL and CMOS standards.
2. Characterized only, not tested in production.
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DC and AC parameters
Table 16.
Symbol
M95160 M95160-W M95160-R M95160-F
DC characteristics (M95160-W, device grade 6)
Parameter
Test conditions in addition to those
defined in Table 9 and Table 12
Max.
Unit
ILI
Input leakage
current
VIN = VSS or VCC
±2
µA
ILO
Output leakage
current
S = VCC, VOUT = VSS or VCC
±2
µA
ICC
Supply current
(Read)
C = 0.1 VCC/0.9 VCC at 5 MHz,
VCC = 2.5 V, Q = open
2
C = 0.1 VCC/0.9 VCC at 10 MHz,
VCC = 2.5 V, Q = open
5
S = VCC, 2.5 V <VCC < 5.5 V
VIN = VSS or VCC
2
µA
mA
ICC1
Supply current
(Standby Power
mode)
VIL
Input low voltage
–0.45
0.3 VCC
V
VIH
Input high voltage
0.7 VCC
VCC+1
V
VOL
Output low voltage
0.4
V
VOH
Output high voltage IOH = –0.4 mA, VCC = 2.5 V
VRES(1)
IOL = 1.5 mA, VCC = 2.5 V
Internal reset
threshold voltage
0.8 VCC
1.0
1. Characterized only, not tested in production.
30/46
Min.
Doc ID 022580 Rev 3
V
1.65
V
M95160 M95160-W M95160-R M95160-F
Table 17.
Symbol
DC and AC parameters
DC characteristics (M95160-R, device grade 6)
Parameter
Test conditions in addition to those
defined in Table 10 and Table 12(1)
Min.
Max.
Unit
ILI
Input leakage
current
VIN = VSS or VCC
±2
µA
ILO
Output leakage
current
S = VCC, voltage applied on Q = VSS or VCC
±2
µA
ICCR
ICC1
Supply current
(Read)
Supply current
(Standby)
VIL
Input low voltage
VIH
Input high voltage
VOL
VOH
VRES(2)
Output low voltage
Output high voltage
VCC = 1.8 V, C = 0.1 VCC or 0.9 VCC
fC = 5 MHz, Q = open
2
VCC = 2.5 V, C = 0.1 VCC or 0.9 VCC,
fC = 5 MHz, Q = open
3
VCC = 5.0 V, S = VCC, VIN = VSS or VCC
2
VCC = 2.5 V, S = VCC, VIN = VSS or VCC
1
VCC = 1.8 V, S = VCC, VIN = VSS or VCC
1
mA
2.5 V < VCC < 5.5 V
–0.45
0.3 VCC
1.8 V < VCC < 2.5 V
–0.45
0.25 VCC
2.5 V < VCC < 5.5 V
0.7 VCC
VCC+1
1.8 V < VCC < 2.5 V
0.75 VCC
VCC+1
VCC = 2.5 V, IOL = 1.5 mA,
or VCC = 5.5 V, IOL = 2 mA
0.2 VCC
VCC = 1.8 V, IOL = 0.15 mA
0.3
VCC = 2.5 V, IOH = –0.4 mA,
or VCC = 5.5 V, IOH = –2 mA,
or VCC = 1.8 V, IOH = –0.1 mA
Internal reset
threshold voltage
µA
V
V
V
0.8 VCC
1.0
V
1.65
V
1. If the application uses the M95160-R device with 2.5 V < VCC < 5.5 V and -40 °C < TA < +85 °C, please refer to Table 16:
DC characteristics (M95160-W, device grade 6), rather than to the above table.
2. Characterized only, not tested in production.
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DC and AC parameters
Table 18.
Symbol
M95160 M95160-W M95160-R M95160-F
DC characteristics (M95160-F, device grade 6)
Parameter
Test conditions in addition to those
defined in Table 11 and Table 12(1)
Min.
Max.
Unit
ILI
Input leakage current
VIN = VSS or VCC
±2
µA
ILO
Output leakage current
S = VCC, voltage applied on Q = VSS or VCC
±2
µA
VCC = 2.5 V, C = 0.1 VCC or 0.9 VCC,
fC = 5 MHz, Q = open
3
mA
VCC = 1.7 V, C = 0.1 VCC or 0.9VCC
fC = 3.5 MHz, Q = open
2
mA
VCC = 5.0 V, S = VCC, VIN = VSS or VCC
2
µA
Supply current (Standby) VCC = 2.5 V, S = VCC, VIN = VSS or VCC
1
µA
VCC = 1.7 V, S = VCC, VIN = VSS or VCC
1
µA
ICCR
ICC1
VIL
VIH
VOL
VOH
VRES(2)
Supply current (Read)
Input low voltage
Input high voltage
Output low voltage
Output high voltage
2.5 V < VCC < 5.5 V
–0.45
0.3 VCC
V
1.8 < VCC < 2.5 V
–0.45
0.25 VCC
V
1.7 V < VCC < 1.8 V
–0.45
0.2 VCC
V
2.5 V < VCC < 5.5 V
0.7 VCC
VCC+1
V
1.7 V < VCC < 2.5 V
0.75 VCC
VCC+1
V
VCC = 2.5 V, IOL = 1.5 mA,
or VCC = 5.5 V, IOL = 2 mA
0.2 VCC
V
VCC = 1.7 V, IOL = 0.15 mA
0.2
V
VCC = 2.5 V, IOH = –0.4 mA,
or VCC = 5.5 V, IOH = –2 mA,
or VCC = 1.7 V, IOH = –0.1 mA
Internal reset threshold
voltage
0.8 VCC
1.0
V
1.65
V
1. If the application uses the M95160-F device with 2.5 V < VCC < 5.5 V and -40 °C < TA < +85 °C, please refer to Table 16:
DC characteristics (M95160-W, device grade 6), rather than to the above table.
2. Characterized only, not tested in production.
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Doc ID 022580 Rev 3
M95160 M95160-W M95160-R M95160-F
Table 19.
DC and AC parameters
AC characteristics (M95160-W, device grade 6)
Test conditions specified in Table 9 and Table 12
Symbol
Alt.
fC
fSCK
Clock frequency
tSLCH
tCSS1
S active setup time
30
ns
tSHCH
tCSS2
S not active setup time
30
ns
tSHSL
tCS
S deselect time
40
ns
tCHSH
tCSH
S active hold time
30
ns
S not active hold time
30
ns
tCHSL
Parameter
Min.
Max.
Unit
D.C.
10
MHz
tCH(1)
tCLH
Clock high time
40
ns
tCL(1)
40
ns
tCLL
Clock low time
tCLCH
(2)
tRC
Clock rise time
2
µs
tCHCL
(2)
tFC
Clock fall time
2
µs
tDVCH
tDSU
Data in setup time
10
ns
tCHDX
tDH
Data in hold time
10
ns
tHHCH
Clock low hold time after HOLD not active
30
ns
tHLCH
Clock low hold time after HOLD active
30
ns
tCLHL
Clock low set-up time before HOLD active
0
ns
tCLHH
Clock low set-up time before HOLD not
active
0
ns
tSHQZ(2)
tDIS
tCLQV
tV
tCLQX
tHO
Output hold time
tQLQH(2)
tRO
Output rise time
40
ns
tQHQL(2)
tFO
Output fall time
40
ns
tHHQV
tLZ
HOLD high to output valid
40
ns
tHLQZ(2)
tHZ
HOLD low to output high-Z
40
ns
tW
tWC
Write time
5
ms
Output disable time
40
ns
Clock low to output valid
40
ns
0
ns
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Characterized only, not tested in production.
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DC and AC parameters
Table 20.
M95160 M95160-W M95160-R M95160-F
AC characteristics (M95160-R, device grade 6)
Test conditions specified in Table 10 and Table 12
Symbol
fC
Alt.
Parameter
fSCK Clock frequency
Min.
Max.
Unit
D.C.
5
MHz
tSLCH
tCSS1 S active setup time
60
ns
tSHCH
tCSS2 S not active setup time
60
ns
90
ns
60
ns
60
ns
tCLH Clock high time
80
ns
tCLL Clock low time
80
ns
tSHSL
tCS
tCHSH
tCSH S active hold time
S not active hold time
tCHSL
tCH(1)
tCL
(1)
S deselect time
tCLCH
(2)
tRC
Clock rise time
2
µs
tCHCL
(2)
tFC
Clock fall time
2
µs
tDVCH
tDSU Data in setup time
20
ns
tCHDX
tDH
Data in hold time
20
ns
tHHCH
Clock low hold time after HOLD not active
60
ns
tHLCH
Clock low hold time after HOLD active
60
ns
tCLHL
Clock low set-up time before HOLD active
0
ns
tCLHH
Clock low set-up time before HOLD not active
0
ns
tSHQZ
(2)
tDIS
Output disable time
80
ns
Clock low to output valid
80
ns
tCLQV
tV
tCLQX
tHO
Output hold time
tQLQH(2)
tRO
Output rise time
80
ns
tQHQL(2)
tFO
Output fall time
80
ns
tHHQV
tLZ
HOLD high to output valid
80
ns
tHLQZ(2)
tHZ
HOLD low to output high-Z
80
ns
tW
tWC
Write time
5
ms
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Characterized only, not tested in production.
34/46
Doc ID 022580 Rev 3
0
ns
M95160 M95160-W M95160-R M95160-F
Table 21.
DC and AC parameters
AC characteristics (M95160-F, device grade 6)
Test conditions specified in Table 11 and Table 12
Symbol
fC
Alt.
Parameter
fSCK Clock frequency
Min.
Max.
Unit
D.C.
3.5
MHz
tSLCH
tCSS1 S active setup time
85
ns
tSHCH
tCSS2 S not active setup time
85
ns
120
ns
85
ns
85
ns
tCLH Clock high time
110
ns
tCLL Clock low time
110
ns
tSHSL
tCS
tCHSH
tCSH S active hold time
S not active hold time
tCHSL
tCH(1)
tCL
(1)
S deselect time
tCLCH
(2)
tRC
Clock rise time
2
µs
tCHCL
(2)
tFC
Clock fall time
2
µs
tDVCH
tDSU Data in setup time
30
ns
tCHDX
tDH
Data in hold time
30
ns
tHHCH
Clock low hold time after HOLD not active
85
ns
tHLCH
Clock low hold time after HOLD active
85
ns
tCLHL
Clock low set-up time before HOLD active
0
0
tCLHH
Clock low set-up time before HOLD not active
0
0
tSHQZ
(2)
tDIS
Output disable time
120
ns
Clock low to output valid
120
ns
tCLQV
tV
tCLQX
tHO
Output hold time
tQLQH(2)
tRO
Output rise time
100
ns
tQHQL(2)
tFO
Output fall time
100
ns
tHHQV
tLZ
HOLD high to output valid
110
ns
tHLQZ(2)
tHZ
HOLD low to output high-Z
110
ns
tW
tWC
Write time
5
ms
0
ns
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Characterized only, not tested in production.
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DC and AC parameters
M95160 M95160-W M95160-R M95160-F
The values in the following table must not be considered for any new design.
Table 22.
AC characteristics (M95160, device grade 6)
End of life products: these values apply only to M95160-MN6TP/S devices
Test conditions specified in Table 8 and Table 12
Symbol
Alt.
fC
fSCK
Clock frequency
tSLCH
tCSS1
S active setup time
15
ns
tSHCH
tCSS2
S not active setup time
15
ns
tSHSL
tCS
S deselect time
40
ns
tCHSH
tCSH
S active hold time
25
ns
S not active hold time
15
ns
tCHSL
Parameter
Max.
Unit
D.C.
10
MHz
tCH
(1)
tCLH
Clock high time
40
ns
tCL
(1)
tCLL
Clock low time
40
ns
tCLCH(2)
tRC
Clock rise time
1
µs
(2)
tFC
Clock fall time
1
µs
tCHCL
tDVCH
tDSU
Data in setup time
15
ns
tCHDX
tDH
Data in hold time
15
ns
tHHCH
Clock low hold time after HOLD not active
15
ns
tHLCH
Clock low hold time after HOLD active
20
ns
tCLHL
Clock low set-up time before HOLD active
0
ns
tCLHH
Clock low set-up time before HOLD not active
0
ns
tSHQZ(2)
tDIS
tCLQV
tV
tCLQX
tHO
Output hold time
tQLQH(2)
tRO
Output rise time
20
ns
tQHQL(2)
tFO
Output fall time
20
ns
tHHQV
tLZ
HOLD high to output valid
25
ns
tHLQZ(2)
tHZ
HOLD low to output high-Z
35
ns
tW
tWC
Write Time
5
ms
Output disable time
25
ns
Clock low to output valid
35
ns
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Characterized only, not tested in production.
36/46
Min.
Doc ID 022580 Rev 3
0
ns
M95160 M95160-W M95160-R M95160-F
DC and AC parameters
The values in the following table must not be considered for any new design.
Table 23.
AC characteristics (M95160-W, device grade 6)
End of life products: these values apply only to M95160-WMN6TP/S
and M95160-WDW6TP/S devices)
Test conditions specified in Table 9 and Table 12
Symbol
Alt.
fC
fSCK
Clock frequency
tSLCH
tCSS1
S active setup time
90
ns
tSHCH
tCSS2
S not active setup time
90
ns
tSHSL
tCS
S deselect time
100
ns
tCHSH
tCSH
S active hold time
90
ns
S not active hold time
90
ns
tCHSL
Parameter
Min.
Max.
Unit
D.C.
5
MHz
tCH(1)
tCLH
Clock high time
90
ns
tCL(1)
tCLL
Clock low time
90
ns
tCLCH(2)
tRC
Clock rise time
1
µs
(2)
tFC
Clock fall time
1
µs
tCHCL
tDVCH
tDSU
Data in setup time
20
ns
tCHDX
tDH
Data in hold time
30
ns
tHHCH
Clock low hold time after HOLD not active
70
ns
tHLCH
Clock low hold time after HOLD active
40
ns
tCLHL
Clock low set-up time before HOLD active
0
ns
tCLHH
Clock low set-up time before HOLD not active
0
ns
tSHQZ(2)
tDIS
tCLQV
tV
tCLQX
Output disable time
100
ns
Clock low to output valid
60
ns
tHO
Output hold time
(2)
tRO
Output rise time
50
ns
tQHQL(2)
tFO
Output fall time
50
ns
tHHQV
tLZ
HOLD high to output valid
50
ns
tHZ
HOLD low to output high-Z
100
ns
tWC
Write time
5
ms
tQLQH
tHLQZ
tW
(2)
0
ns
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Characterized only, not tested in production.
Doc ID 022580 Rev 3
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DC and AC parameters
M95160 M95160-W M95160-R M95160-F
Figure 16. Serial input timing
tSHSL
S
tCHSL
tCH
tSLCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCL
tCLCH
tCHDX
D
Q
LSB IN
MSB IN
High impedance
AI01447d
Figure 17. Hold timing
S
tHLCH
tCLHL
tHHCH
C
tCLHH
tHLQZ
tHHQV
Q
HOLD
AI01448c
38/46
Doc ID 022580 Rev 3
M95160 M95160-W M95160-R M95160-F
DC and AC parameters
Figure 18. Serial output timing
S
tCH
tSHSL
C
tCLQV
tCLCH
tCHCL
tCL
tSHQZ
tCLQX
Q
tQLQH
tQHQL
ADDR
D LSB IN
AI01449f
Doc ID 022580 Rev 3
39/46
Package mechanical data
10
M95160 M95160-W M95160-R M95160-F
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 19. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
GAUGE PLANE
D
k
8
E1
E
1
A1
L
L1
SO-A
1. Drawing is not to scale.
Table 24.
SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data
inches(1)
millimeters
Symbol
Typ
Min
A
Max
Typ
1.750
Max
0.0689
A1
0.100
A2
1.250
b
0.280
0.480
0.0110
0.0189
c
0.170
0.230
0.0067
0.0091
ccc
0.250
0.0039
0.0098
0.0492
0.100
0.0039
D
4.900
4.800
5.000
0.1929
0.1890
0.1969
E
6.000
5.800
6.200
0.2362
0.2283
0.2441
E1
3.900
3.800
4.000
0.1535
0.1496
0.1575
e
1.270
-
-
0.0500
-
-
h
0.250
0.500
0.0098
0.0197
k
0°
8°
0°
8°
L
0.400
1.270
0.0157
0.0500
L1
1.040
0.0409
1. Values in inches are converted from mm and rounded to four decimal digits.
40/46
Min
Doc ID 022580 Rev 3
M95160 M95160-W M95160-R M95160-F
Package mechanical data
Figure 20. TSSOP8 – 8-lead thin shrink small outline, package outline
D
8
5
c
E1
1
E
4
α
A1
A
L
A2
L1
CP
b
e
TSSOP8AM
1. Drawing is not to scale.
Table 25.
TSSOP8 – 8-lead thin shrink small outline, package mechanical data
inches(1)
millimeters
Symbol
Typ
Min
A
Max
Min
1.200
A1
0.050
0.150
0.800
1.050
b
0.190
c
0.090
A2
Typ
1.000
CP
Max
0.0472
0.0020
0.0059
0.0315
0.0413
0.300
0.0075
0.0118
0.200
0.0035
0.0079
0.0394
0.100
0.0039
D
3.000
2.900
3.100
0.1181
0.1142
0.1220
e
0.650
-
-
0.0256
-
-
E
6.400
6.200
6.600
0.2520
0.2441
0.2598
E1
4.400
4.300
4.500
0.1732
0.1693
0.1772
L
0.600
0.450
0.750
0.0236
0.0177
0.0295
L1
1.000
0°
8°
0.0394
α
0°
N
8
8°
8
1. Values in inches are converted from mm and rounded to four decimal digits.
Doc ID 022580 Rev 3
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Package mechanical data
M95160 M95160-W M95160-R M95160-F
Figure 21. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no lead, package
outline
E
$
,
,
0IN %
B
%
+
,
!
$
EEE
!
:7?-%E6
1. Drawing is not to scale.
2. The central pad (area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be
connected to any other voltage or signal line on the PCB, for example during the soldering process.
Table 26.
UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data
inches(1)
millimeters
Symbol
Typ
Min
Max
Typ
Min
Max
A
0.550
0.450
0.600
0.0217
0.0177
0.0236
A1
0.020
0.000
0.050
0.0008
0.0000
0.0020
b
0.250
0.200
0.300
0.0098
0.0079
0.0118
D
2.000
1.900
2.100
0.0787
0.0748
0.0827
1.200
1.600
0.0472
0.0630
2.900
3.100
0.1142
0.1220
1.200
1.600
0.0472
0.0630
D2 (rev MC)
E
3.000
E2 (rev MC)
e
0.500
0.1181
0.0197
K (rev MC)
0.300
L
0.300
L1
0.0118
0.500
0.0118
0.150
0.0197
0.0059
L3
0.300
0.0118
eee(2)
0.080
0.0031
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.
42/46
Doc ID 022580 Rev 3
M95160 M95160-W M95160-R M95160-F
Package mechanical data
Figure 22. WLCSP-R – 1.350 x 1.365 mm 0.4 mm pitch 8 bumps, package outline
e1
G
e
D
C
e
Detail A
e1
B
E
Orientation
reference
A
Orientation
reference
aaa
Wafer back side
3
(×4)
A
2
F
1
Bump side
A2
Side view
Bump
A1
eee Z
Z
b
Seating plane
(see note 1)
Detail A
Rotated 90˚
1C_ME
1. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
2. Drawing is not to scale.
3. Preliminary data.
Table 27.
WLCSP-R – 1.350 x 1.365 mm 0.4 mm pitch 8 bumps, package mechanical
data (preliminary data)
inches(1)
millimeters
Symbol
Typ
Min
Max
Typ
Min
Max
A
0.545
0.490
0.600
0.0193
0.0215
0.0236
A1
0.190
0.0075
A2
0.355
0.014
b(2)
0.270
0.0094
0.0118
D
0.240
0.300
0.0106
1.350
1.475
0.0531
0.0581
E
1.365
1.490
0.0537
0.0587
e
0.400
0.0157
e1
0.800
0.0315
F
0.282
0.0111
G
0.275
0.0108
N (total number of
terminals)
8
8
aaa
0.110
0.0043
eee
0.060
0.0024
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
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Part numbering
11
M95160 M95160-W M95160-R M95160-F
Part numbering
Table 28.
Ordering information scheme
Example:
Device type
M95 = SPI serial access EEPROM
M95160
W MN 6
T
P /S
Device function
160 = 16 Kbit (2048 x 8)
Operating voltage
blank = VCC = 4.5 to 5.5 V
W = VCC = 2.5 to 5.5 V
R = VCC = 1.8 to 5.5 V
F = VCC = 1.7 to 5.5 V
Package(1)
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
MC = UFDFPN8 (MLP8)
CS = WLCSP
Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
Option
blank = Standard packing
T = Tape and reel packing
Plating technology
G or P = RoHS compliant and halogen-free
(ECOPACK®)
Process(2)
/G or /S= Manufacturing technology code
1. All packages are ECOPACK2® (RoHS compliant and halogen-free).
2. The process letters apply to WLCSP devices only. The process letters appear on the device package
(marking) and on the shipment box. Please contact your nearest ST Sales Office for further information.
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12
Revision history
Revision history
Table 29.
Document revision history
Date
Revision
Changes
22-Mar-2012
1
Initial release.
17-Dec-2012
2
Updated:
– All information about package UFDFPN8
– Introduction of Description
– Section 7.2: Initial delivery state
08-Jan-2013
3
Updated plating technology in Section 11: Part numbering.
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M95160 M95160-W M95160-R M95160-F
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