AVAGO HDLO-3416 Four character 6.9 mm (0.27 inch) smart 5 x 7 alphanumeric display Datasheet

HDLx-3416 Series
Four Character 6.9 mm (0.27 inch)
Smart 5 x 7 Alphanumeric Displays
Data Sheet
Description
Features
These are 5 x 7 dot matrix displays with four 0.27” tall characters, driven by an on-board CMOS IC. The IC stores and
decodes7bitASCIIdataanddisplaysitwithaneasytoread5x7
font. Multi-plexing circuitry and drivers are included in the IC
to allow the display to interface simply with bus-based
microprocessor systems.
 Smart alphanumeric display
Built-in RAM, ASCII decoder, and LED drive circuitry
The address and data inputs of the display can be directly
connected to the microprocessor address and data buses.
 Categorized for luminous intensity
– Yellow and Green categories for color
– Use of like categories yields a uniform display
These displays are related to the HDLX-2416 family, and
thus share the same enhancements over the HPDL-2416
segmented displays. These features include support
for the full 128 character US ASCII character set, 8 level
dimming control, external hardware dimming capability,
and digit blanking.
 Software controlled dimming and blanking
 128 ASCII character set
 End-stackable
 Wide operating temperature range -40°C to +85°C
 Wave solderable
 Wide viewing angle (50° typical)
An extended function disable exists for those designers
who desire compatibility with competitive displays.
This function disables the dimming and digit blanking
controls.
Devices:
High Efficiency Red
Orange
Yellow
Green
HDLO-3416
HDLA-3416
HDLY-3416
HDLG-3416
ESD WARNING: Standard CMOS handling precautions should be observed to avoid static discharge.
Package Dimensions
32.77
(1.290)
0.38
(0.015)
8.26
(0.325)
0.25 TYP.
(0.010)
10.03
(0.395)
6.86
(0.270)
20.07
(0.790)
PIN 1 IDENTIFIER
15.24
(0.600)
10.16
(0.400)
4.45
(0.175)
2.41 TYP.
(0.095)
8.64
(0.340)
4.06
(0.160)
0.51 TYP.
(0.020)
2.54 TYP.
(0.100)
Notes:
1. Unless otherwise specified, the tolerance on all dimensions is ± 0.254 mm (0.010).
2. All dimensions are in millimeters (inches).
PIN NO.
1
2
3
4
5
6
7
8
9
10
11
Absolute Maximum Ratings
Supply Voltage, VDD to Ground[1]
-0.5 V to 7.0 V
Input Voltage, Any Pin to Ground
-0.5 V to VDD + 0.5 V
Free Air Operating Temperature Range, TA
-40°C to +85°C
Storage Temperature, TS
-40°C to +85°C
CMOS IC Junction Temperature, TJ (IC)
+150°C
Relative Humidity (non-condensing) at 65°C
85%
Soldering Temperature [1.59 mm (0.063 in.) Below Body]
Solder Dipping
Wave Soldering
260°C for 5 secs
250°C for 3 secs
ESD Protection, R = 1.5 k, C = 100 pF
VZ = 1 kV (each pin)
Note:
1. Maximum Voltage is with no LEDs illuminated.
2
FUNCTION
NO CONNECT
NO CONNECT
CE1
CE2
CLR
VDD
A0
A1
WR
CU
CUE
PIN NO.
12
13
14
15
16
17
18
19
20
21
22
FUNCTION
GROUND
NO CONNECT
BL
NO CONNECT
D0
D1
D2
D3
D4
D5
D6
Character Set
D0
D1
D2
D3
D6 D5 D4 HEX
ASCII
CODE
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
0
0
0
0
0
NOTES: 1 = HIGH LEVEL
0 = LOW LEVEL
3
1
0
0
0
1
0
1
0
0
2
1
1
0
0
3
0
0
1
0
4
1
0
1
0
5
0
1
1
0
6
1
1
1
0
7
0
0
0
1
8
1
0
0
1
9
0
1
0
1
A
1
1
0
1
B
0
0
1
1
C
1
0
1
1
D
0
1
1
1
E
1
1
1
1
F
Recommended Operating Conditions
Parameter
Symbol
Min.
Typ.
Max.
Units
Supply Voltage
VDD
4.5
5.0
5.5
V
Electrical/Optical Characteristics over Operating Temperature Range
4.5 < VDD < 5.5 V (unless otherwise specified)
All Devices
25°C[1]
Parameter
Symbol
IDD Blank
IDD (blnk)
Input Current
II
Input Voltage High
Min.
Typ.
Max.
Units
Test Conditions
4.0
mA
All Digits Blanked
-40
10
A
VIN = 0 V to VDD
VDD = 5.0 V
VIH
2.0
VDD
V
Input Voltage Low
VIL
GND
0.8
V
IDD 4 Digits 20 Dots/
Character[2,3]
IDD (#)
110
130
160
mA
“#” ON in All Four
Locations
IDD Cursor All Dots
ON @ 50%
IDD (CU)
92
110
135
mA
Cursor ON in All
Four Locations
1.0
Notes:
1. VDD = 5.0 V
2. Average IDD measured at full brightness. Peak IDD = 28/15 x Average IDD (#).
3. IDD (#) max. = 130 mA, 150°C IC junction temperature and VDD = 5.5 V.
4
Max.
Optical Characteristics at 25°C[1]
VDD = 5.0 V at Full Brightness
High Efficiency Red HDLO-3416
Parameter
Symbol
Min.
Typ.
Units
Test Conditions
Average Luminous Intensity
per Digit, Character Average
IV
1.2
3.5
mcd
“*” Illuminated in All Four Digits.
19 Dots ON per Digit.
Peak Wavelength
PEAK
635
nm
Dominant Wavelength[2]
D
626
nm
Orange HDLA-3416
Parameter
Symbol
Min.
Typ.
Units
Test Conditions
Average Luminous Intensity
per Digit, Character Average
IV
1.2
3.5
mcd
“*” Illuminated in All Four Digits
19 Dots ON per Digit.
Peak Wavelength
PEAK
600
nm
Dominant Wavelength[2]
D
602
nm
Yellow HDLY-3416
Parameter
Symbol
Min.
Typ.
Units
Test Conditions
Average Luminous Intensity
per Digit, Character Average
IV
1.2
3.7
mcd
“*” Illuminated in All Four Digits
19 Dots ON per Digit.
Peak Wavelength
PEAK
583
nm
Dominant Wavelength[2]
D
585
nm
Green HDLG-3416
Parameter
Symbol
Min.
Typ.
Units
Test Conditions
Average Luminous Intensity
per Digit, Character Average
IV
1.2
5.6
mcd
“*” Illuminated in All Four Digits
19 Dots ON per Digit.
Peak Wavelength
PEAK
568
nm
Dominant Wavelength[2]
D
574
nm
Notes:
1. Refers to the initial case temperature of the device immediately prior to the light measurement.
2. Dominant wavelength, D, is derived from the CIE chromaticity diagram, and represents the single wavelength which defines the color of the
device.
5
AC Timing Characteristics over Operating Temperature Range at VDD = 4.5 V
Parameter
Symbol
Min
Units
Address Setup
tAS
10
ns
Address Hold
tAH
40
ns
Data Setup
tDS
50
ns
Data Hold
tDH
40
ns
Chip Enable Setup
tCES
0
ns
Chip Enable Hold
tCEH
0
ns
Write Time
tW
75
ns
Clear
tCLR
10
s
Clear Disable
tCLRD
1
s
Timing Diagram
Enlarged Character Font
tCES
tCEH
2.0 V
0.8 V
A0 – A1, CU
tAS
6.9 (0.27)
TYP.
2.0 V
0.8 V
tW
2.0 V
0.8 V
D0 – D6
tDS
tCLR
6
1.09 (0.043)
TYP.
tAH
WR
CLR
4.4 (0.175)
TYP.
2.0 V
0.8 V
CE1
CE2
tCLRD
2.0 V
0.8 V
tDH
0.25 (0.010)
TYP.
1.05 (0.041)
TYP.
Notes:
1. Unless otherwise specified, the tolerance on
all dimensions is ± 0.254 mm (0.010").
2. Dimensions are in millimeters (inches).
Electrical Description
Pin Function
Description
Chip Enable (CE1 and
CE2, Pins 3 and 4)
CE1 and CE2 must be a logic 0 to write to the display.
Clear (CLR, Pin 5)
When CLR is a logic 0 the ASCII RAM is reset to
20hex (space) and the Control Register/Attribute
RAM is reset to 00hex.
Cursor Enable
(CUE Pin 11)
CUE determines whether the IC displays the ASCII or
the Cursor memory. (1 = Cursor, 0 = ASCII.)
Cursor Select
(CU, Pin 10)
CU determines whether data is stored in the ASCII
RAM or the Attribute RAM/Control Register.
(1 = ASCII, 0 = Attribute RAM/ Control Register.)
Write (WR, Pin 9)
WR must be a logic 0 to store data in the display.
Address Inputs
(A1 and A0, Pins
7 and 8)
A0-A1 selects a specific location in the display
memory. Address 00 accesses the far right display
location. Address 11 accesses the far left location.
Data Inputs (D0-D6,
Pins 16 – 22)
D0-D6 are used to specify the input data for
the display.
VDD (Pin 6)
VDD is the positive power supply input.
GND (Pin 12)
GND is the display ground.
Blanking Input
(BL, Pin 14)
BL is used to flash the display, blank the
display or to dim the display.
Display Internal Block Diagram
Figure 1 shows the HDLX-3416 display internal block
diagram. The CMOS IC consists of a 4 x 7 Character RAM, a
2 x 4 Attribute RAM, a 5 bit Control Register, a 128 character
ASCII decoder and the refresh circuitry necessary to synchronize the decoding and driving of four 5 x 7 dot matrix
displays.
Four 7 bit ASCII words are stored in the Character RAM.
The IC reads the ASCII data and decodes it via the 128
character ASCII decoder. The ASCII decoder includes the
64 character set of the HPDL-2416, 32 lower case ASCII
symbols, and 32 foreign language symbols.
A 5 bit word is stored in the Control Register. Three fields
within the Control Register provide an 8 level brightness
control, master blank, and extended functions disable.
7
For each display digit location, two bits are stored in the
Attribute RAM. One bit is used to enable a cursor character
at each digit location. A second bit is used to individually
disable the blanking features at each digit location.
The display is blanked and dimmed through an internal
blanking input on the row drivers. Logic within the IC
allows the user to dim the display either through the BL
input or through the brightness control in the control
register. Similarly the display can be blanked through the
BL input, the Master Blank in the Control Register, or the
Digit Blank Disable in the Attribute RAM.
CHARACTER RAM
A0 – A1
CE1
CE2
WR
CU
D0 – D6
2 WRITE
ADDRESS
7 DATA IN
DATA
OUT
CHARACTER/CURSOR
MULTIPLEXER
ASCII DECODER
7
CHARACTER
SELECT
5
COLUMN
DATA
0
CHARACTER/
CURSOR
MULTIPLEXER
WRITE
(4 x 7)
2 READ
ADDRESS
CLR
3 ROW
SELECT
CURSOR
CHARACTER
5 1
SELECT
CLR
ATTRIBUTE RAM
D0
DIGIT CURSOR
D1
DIGIT BLANK
DISABLE
A0 – A1
CUE
DCn
WRITE ADDRESS
(2 x 4)
WRITE
2 READ ADDRESS
CLR
CLR
BL
CONTROL REGISTER
MASTER
BLANK
D2
ROW
DRIVERS
ROW
SELECT
BLANK
MB
EFD
DBDn
D3 – D5
3 BRIGHTNESS
LEVELS
D6
CE1
CE2
WR
CU
EFD
EFD
EXTENDED
FUNCTIONS
DISPLAY
1x5
WRITE
3
CLR
CLR
3
DIGITAL
DUTY
CONTROL
4 (LSBs)
OSC
+ 32
2 (MSBs)
Figure 1. Internal block diagram.
8
+7
COLUMN
DRIVERS
DISPLAY
Display Clear
Cursor
Data stored in the Character RAM, Control Register, and
Attribute RAM will be cleared if the clear (CLR) is held
low for a minimum of 10 μs. Note that the display will be
cleared regardless of the state of the chip enables (CE1,
CE2). After the display is cleared, the ASCII code for a space
(20hex) is loaded into all character RAM locations and
00hex is loaded into all Attribute RAM/Control Register
memory locations.
When cursor enable (CUE) is a logic 1, a cursor will be
displayed in all digit locations where a logic 1 has been
stored in the Digit Cursor memory in the Attribute RAM.
The cursor consists of all 35 dots ON at half brightness. A
flashing cursor can be displayed by pulsing CUE. When
CUE is a logic 0, the ASCII data stored in the Character RAM
will be displayed regardless of the Digit Cursor bits.
Blanking
Data Entry
Blanking of the display is controlled through the BL input,
the Control Register, and Attribute RAM. The user can
achieve a variety of functions by using these controls
in different combinations, such as full hardware display
blank, software blank, blanking of individual characters,
and synchronized flashing of individual characters or
entire display (by strobing the blank input). All of these
blanking modes affect only the output drivers, maintaining the contents and write capability of the internal RAMs
and Control Register, so that normal loading of RAMs and
Control Register can take place even with the display
blanked.
Figure 2 shows a truth table for the HDLX-3416 display.
Setting the chip enables (CE1, CE2) to logic 0 and the cursor
select (CU) to logic 1 will enable ASCII data loading. When
cursor select (CU) is set to logic 0, data will be loaded into
the Control Register and Attribute RAM. Address inputs
A0-A1 are used to select the digit location in the display.
Data inputs D0-D6 are used to load information into the
display. Data will be latched into the display on the rising
edge of the WR signal. D0-D6, A0-A1, CE1, CE2, and CU
must be held stable during the write cycle to ensure that
correct data is stored into the display. Data can be loaded
into the display in any order. Note that when A0 and A1 are
logic 0, data is stored in the right most display location.
CUE
BL
CLR
0
1
1
Display ASCII
1
1
1
Display Stored Cursor
X
X
0
Reset RAMs
X
0
1
Blank Display but do not reset
RAMs and Control Register
X
X
1
CE1
X
0
CE2
X
0
WR
X
CU
X
X
1
0
1
X
X
1
0
0
X
X
1
X
X
X
1
0 = Logic 0; 1 = Logic 1; X = Do Not Care
9
X
D6
X
D5
X
D4
X
0
0
Extended
Functions
Disable
Intensity
Control
0
0
1
0=
Enable
D1-D5
0
1=
Disable
D1-D5
000 = 100%
001 = 60%
010 = 40%
011 = 27%
100 = 17%
101 = 10%
110 = 7%
111 = 3%
0
X
Figure 2. Display truth table.
X
A0
0
0
X
A1
1
D3
X
D2
X
Master
Blank
D1
X
Digit
Cursor
0
Write to Attribute RAM
and Control Register
0=
Digit
Display
Blank
ON
Disable 1
Digit
Cursor
1
DBDn = 0, Allows Digit n to be
blanked
1=
Digit
Display
Blank
Blanked Disable 2
Digit
Cursor
2
Digit
Blank
Disable 3
Digit
Cursor
3
D0
Always
Enabled
1
1
1
0
0
Digit 0 ASCII Data (Right Most Character)
1
0
1
Digit 1 ASCII Data
1
1
0
Digit 2 ASCII Data
1
1
1
Digit 3 ASCII Data (Left Most Character)
X
X
X
X
X
X
X
Function
Digit
Blank
Disable 0
0
X
D0
DBDn = 1 Prevents Digit n from
being blanked.
DCn = 0 Removes cursor from
Digit n
DCn = 1 Stores cursor at
Digit n
Write to Character RAM
X
X
X
No Change
Figure 3 shows how the Extended Function Disable (bit D6
of the Control Register), Master Blank (bit D2 of the Control
Register), Digit Blank Disable (bit D1 of the Attribute RAM),
and BL input can be used to blank the display.
Dimming
Dimming of the display is controlled through either the
BL input or the Control Register. A pulse width modulated
signal can be applied to the BL input to dim the display.
A three bit word in the Control Register generates an
internal pulse width modulated signal to dim the display.
The internal dimming feature is enabled only if the
Extended Function Disable is a logic 0.
When the Extended Function Disable is a logic 1, the
display can be blanked only with the BL input. When
the Extended Function Disable is a logic 0, the display
can be blanked through the BL input, the Master
Blank, and the Digit Blank Disable. The entire display
will be blanked if either the BL input is logic 0 or the
Master Blank is logic 1, providing all Digit Blank Disable
bits are logic 0. Those digits with Digit Blank
Disable bits a logic 1 will ignore both blank signals
and remain ON. The Digit Blank Disable bits allow individual characters to be blanked or flashed in synchronization
with the BL input.
Bits 3–5 in the Control Register provide internal brightness
control. These bits are inter-preted as a three bit binary
code, with code (000) corresponding to the maximum
brightness and code (111) to the minimum brightness. In
addition to varying the display brightness, bits 3–5 also
vary the average value of IDD . IDD can be specified at any
brightness level as shown in Table 1.
EFD
MB
DBDn
BL
0
0
0
0
– Display Blanked by BL
0
0
X
1
– Display ON
0
X
1
0
– Display Blanked by BL.
Individual Characters “ON”
based on “1” being stored in DBDn
0
1
0
X
– Display Blanked by MB
0
1
1
1
– Display Blanked by MB.
Individual characters “ON”
based on “1” being stored in DBDn
1
X
X
0
– Display Blanked by BL
1
X
X
1
– Display ON
Figure 3. Display blanking truth table.
Table 1. Current Requirements at Different Brightness Levels
Symbol
D5
D4
D3
Brightness
25°C Typ.
25°C Max.
Max. over Temp.
Units
IDD(#)
0
0
0
100%
110
130
160
mA
0
0
1
60%
66
79
98
mA
0
1
0
40%
45
53
66
mA
0
1
1
27%
30
37
46
mA
1
0
0
17%
20
24
31
mA
1
0
1
10%
12
15
20
mA
1
1
0
7%
9
11
15
mA
1
1
1
3%
4
6
9
mA
10
+ VDD
1k
8
4
7
3
1k
1N914
555
BL
(PIN 18)
10 kHz
OUTPUT
6
250 k
LOG
2
1
400 pF
Figure 4. Intensity modulation control using an astable multivibrator
(reprinted with permission from Electronics magazine, Sept. 19, 1974, V
NU Business pub. Inc.).
Figure 4 shows a circuit designed to dim the display from
98% to 2% by pulse width modulating the BL input. A logarithmic or a linear potentiometer may be used to adjust
the display intensity. However, a logarithmic potentiometer matches the response of the human eye and
therefore provides better resolution at low intensities.
The circuit frequency should be designed to operate at 10
kHz or higher. Lower frequencies may cause the display
to flicker.
Extended Function Disable
Extended Function Disable (bit D6 of the Control Register)
disables the extended blanking and dimming functions in
the HDLX-3416. If the Extended Function Disable is a logic
1, the internal brightness control, Master Blank, and Digit
Blank Disable bits are ignored. However, the BL input and
Cursor control are still active.
Mechanical and Electrical Considerations
The HDLX-3416 is a 22 pin DIP package that can be stacked
horizontally and vertically to create arrays of any size. The
display is designed to operate continuously from -40°C to
+85°C for all possible input conditions.
The HDLX-3416 is assembled by die attaching and wire
bonding 140 LEDs and a CMOS IC to a high temperature
printed circuit board. A polycarbonate lens is placed over
the PC board creating an air gap environment for the
LED wire bonds. Backfill epoxy environmentally seals the
display package. This package construction makes the
display highly tolerant to temperature cycling and allows
wave soldering.
11
The inputs to the CMOS IC are protected against static
discharge and input current latchup. However, for best
results standard CMOS handling precautions should be
used. Prior to use, the HDLX-3416 should be stored in
anti-static tubes or conductive material. During assembly
a grounded conductive work area should be used, and
assembly personnel should wear conductive wrist straps.
Lab coats made of synthetic material should be avoided
since they are prone to static charge build-up.
Input current latchup is caused when the CMOS inputs are
subjected either to a voltage below ground (Vin < ground)
or to a voltage higher than VDD (Vin > VDD) and when a
high current is forced into the input. To prevent input
current latchup and ESD damage, unused inputs should
be connected either to ground or to VDD . Voltages
should not be applied to the inputs until VDD has been
applied to the display.Transient input voltages should
be eliminated.
Soldering and Post Solder Cleaning Instructions for the
HDLX-3416
The HDLX-3416 may be hand soldered or wave soldered
with SN63 solder. When hand soldering it is recommended that an electronically temperature controlled and
securely grounded soldering iron be used. For best results,
the iron tip temperature should be set at 315°C (600°F).
For wave soldering, a rosin-based RMA flux can be used.
The solder wave temperature should be set at 245°C ± 5°C
(473°F ± 9°F), and dwell in the wave should be set between
1½ to 3 seconds for optimum soldering. The preheat temperature should not exceed 110°C (230°F) as measured on
the solder side of the PC board.
For further information on soldering and post solder
cleaning, see Application Note 1027, Soldering LED
Components.
Contrast Enhancement
The objective of contrast enhancement is to provide good
readability in the end user’s ambient lighting conditions.
The concept is to employ both luminance and chrominance contrast techniques. These enhance readability by
having the OFF-dots blend into the display background
and the ON-dots vividly stand out against the same background. For additional information on contrast enhancement, see Application Note 1015.
Color Bin Limits
Intensity Bin Limits
Color Range (nm)
Intensity Range (mcd)
Bin
Min.
Max.
Color
Bin
Min.
Max.
A
1.20
1.77
Green
1
576.0
580.0
B
1.45
2.47
2
573.0
577.0
C
2.02
3.46
3
570.0
574.0
D
2.83
4.85
4
567.0
571.5
E
3.97
6.79
3
581.5
585.0
F
5.55
9.50
4
584.0
587.5
G
7.78
13.30
5
586.5
590.0
6
589.0
592.5
Note:
Test conditions as specified in Optical Characteristic table.
For product information and a complete list of distributors, please go to our web site:
Yellow
Note:
Test conditions as specified in Optical Characteristic table.
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. Obsoletes 5989-3189EN
AV02-3642EN - June 20, 2012
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