MCP8025/6
3-Phase Brushless DC (BLDC) Motor Gate Driver
with Power Module, Sleep Mode, and LIN Transceiver
Features
Applications
• AEC-Q100 Grade 0 Qualified
• Quiescent Current:
- Sleep Mode: 5 µA Typical
- Standby Mode: < 200 µA
• LIN Transceiver Interface (MCP8025):
- Compliant with LIN Bus Specifications 1.3,
2.2, and SAE J2602
- Supports baud rates up to 20K baud
- Internal pull-up resistor and diode
- Protected against ground shorts
- Protected against loss of ground
- Automatic thermal shutdown
- LIN Bus dominant timeout
• Three Half-Bridge Drivers Configured to Drive
External High-Side NMOS and Low-Side NMOS
MOSFETs:
- Independent input control for high-side
NMOS and low-side NMOS MOSFETs
- Peak output current: 0.5A @ 12V
- Shoot-through protection
- Overcurrent and short-circuit protection
• Adjustable Output Buck Regulator (750 mW)
• Fixed Output Linear Regulators:
- 5V @ 30 mA
- 12V @ 30 mA
• Operational Amplifiers:
- one in MCP8025
- three in MCP8026
• Overcurrent Comparator with DAC Reference
• Phase Comparator with Multiplexer (MCP8025)
• Neutral Simulator (MCP8025)
• Level Translators (MCP8026)
• Input Voltage Range: 6V to 40V
• Operational Voltage Range:
- 6V to 19V (MCP8025)
- 6V to 28V (MCP8026)
• Buck Regulator Undervoltage Lockout: 4.0V
• Undervoltage Lockout (UVLO): 5.5V (except Buck)
• Overvoltage Lockout (OVLO)
- 20V (MCP8025)
- 32V (MCP8026)
• Transient (100 ms) Voltage Tolerance: 48V
• Extended Temperature Range (TA): -40 to +150°C
• Thermal Shutdown
• Automotive Fuel, Water, Ventilation Motors
• Home Appliances
• Permanent Magnet Synchronous Motor (PMSM)
Control
• Hobby Aircraft, Boats, Vehicles
2016 Microchip Technology Inc.
Description
The MCP8025/6 devices are 3-phase brushless DC
(BLDC) power modules containing three integrated
half-bridge drivers capable of driving three external
NMOS/NMOS transistor pairs. The three half-bridge
drivers are capable of delivering a peak output current
of 0.5A at 12V for driving high-side and low-side NMOS
MOSFET transistors. The drivers have shoot-through,
overcurrent and short-circuit protection. A Sleep mode
has been added to achieve a typical “key-off” quiescent
current of 5 µA.
The MCP8025 device integrates a comparator, a buck
voltage regulator, two LDO regulators, power
monitoring comparators, an overtemperature sensor, a
LIN transceiver, a zero-crossing detector, a neutral
simulator and an operational amplifier for motor current
monitoring. The phase comparator and multiplexer
allow for hardware commutation detection. The neutral
simulator allows commutation detection without a
neutral tap in the motor. The buck converter is capable
of delivering 750 mW of power for powering a
companion microcontroller. The buck regulator may be
disabled if not used. The on-board 5V and 12V
low-dropout voltage regulators are capable of
delivering 30 mA of current.
The MCP8026 replaces the LIN transceiver, neutral
simulator and zero-crossing detector in MCP8025 with
two level shifters and two additional op amps.
The MCP8025/6 operation is specified over a
temperature range of -40°C to +150°C.
Package options include 40-lead 5x5 QFN and 48-lead
7x7 TQFP with Exposed Pad (EP).
DS20005339B-page 1
MCP8025/6
Package Types – MCP8025
PWM2L
PWM3H
PWM3L
DE2
CAP1
CAP2
+5V
FB
VDD
LX
40
39
38
37
36
35
34
33
32
31
5 mm x 5 mm QFN-40
PWM2H
1
30
+12V
PWM1L
2
29
VBA
PWM1H
3
28
VBB
CE
4
27
VBC
EP
(41)
18
19
20
LSB
LSC
HSC
LSA
21
17
10
PGND
HSB
MUX2
16
HSA
22
15
23
9
I_SENSE1-
8
MUX1
I_SENSE1+
FAULTn/TXE
14
PHC
13
24
I_OUT1
7
ILIMIT_OUT
PHB
TX
12
PHA
25
11
26
6
ZC_OUT
5
RX
COMP_REF
LIN_BUS
PWM2H
PWM2L
PWM3H
PWM3L
DE2
CAP1
CAP2
+5V
FB
VDD
VDD
LX
47
46
45
44
43
42
41
40
39
38
37
+
48
7 mm x 7 mm TQFP-48
PWM1L
1
36
PGND
PWM1H
2
35
PGND
CE
3
34
+12V
NC
4
33
VBA
32
VBB
31
VBC
NC
5
LIN_BUS
6
PGND
7
30
PHA
RX
8
29
PHB
TX
9
28
PHC
FAULTn/TXE
10
27
HSA
MUX1
11
26
HSB
MUX2
12
25
HSC
13
14
15
16
17
18
19
20
21
22
23
24
ZC_OUT
COMP_REF
ILIMIT_OUT
I_OUT1
I_SENSE1-
I_SENSE1+
PGND
PGND
LSA
LSB
LSC
PGND
EP
(49)
* Includes Exposed Thermal Pad (EP), see Table 3-1.
DS20005339B-page 2
2016 Microchip Technology Inc.
MCP8025/6
Package Types – MCP8026
PWM2L
PWM3H
PWM3L
DE2
CAP1
CAP2
+5V
FB
VDD
LX
40
39
38
37
36
35
34
33
32
31
5 mm x 5 mm QFN-40
PWM2H
1
30
+12V
PWM1L
2
29
VBA
PWM1H
3
28
VBB
CE
4
27
VBC
HV_IN1
5
26
PHA
LV_OUT1
6
25
PHB
IOUT3
7
24
PHC
ISENSE3-
8
23
HSA
ISENSE3+
9
22
HSB
IOUT2
10
21
HSC
EP
13
14
15
16
17
18
19
20
I_OUT1
I_SENSE1-
I_SENSE1+
PGND
LSA
LSB
LSC
12
ILIMIT_OUT
11
ISENSE2-
ISENSE2+
(41)
PWM2H
PWM2L
PWM3H
PWM3L
DE2
CAP1
CAP2
+5V
FB
VDD
VDD
LX
47
46
45
44
43
42
41
40
39
38
37
+
48
7 mm x 7 mm TQFP-48
PWM1L
1
36
PGND
PWM1H
2
35
PGND
CE
3
34
+12V
LV_OUT2
4
33
VBA
HV_IN2
5
32
VBB
HV_IN1
6
31
VBC
PGND
7
30
PHA
LV_OUT1
8
29
PHB
EP
(49)
18
19
20
21
22
23
24
PGND
PGND
LSA
LSB
LSC
PGND
HSC
I_SENSE1+
25
17
12
16
IOUT2
I_OUT1
HSB
I_SENSE1-
26
15
11
ILIMIT_OUT
HSA
ISENSE3+
14
PHC
27
13
28
ISENSE2-
9
10
ISENSE2+
IOUT3
ISENSE3-
* Includes Exposed Thermal Pad (EP), see Table 3-2.
2016 Microchip Technology Inc.
DS20005339B-page 3
MCP8025/6
Functional Block Diagram – MCP8025
COMMUNICATION PORT
BIAS GENERATOR
VDD
LIN_BUS
VDD
+12V
LDO
I/O
CAP1
LIN
XCVR
CE
FAULTn/TXE
RX
TX
CHARGE PUMP
CAP2
I
+5V
LDO
I/O
O
I
BUCK SMPS
LX
FB
SUPERVISOR
DE2
MOTOR CONTROL UNIT
SIM Select
COMP_REF
+
ZC_OUT
-
O
MUX1
MUX2
I
I
I
MUX I
I
NEUTRAL_SIM
PHASE DETECT
VBA
VBB
VBC
VDD
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
O
HSA
O
HSB
O
HSC
I
I
GATE
I CONTROL I
I
I
LOGIC
I
I
PHA
PHB
PHC
+12V
I
DRIVER
FAULT
O
O
LSA
O
LSB
O
LSC
PGND
ILIMIT_REF
+
ILIMIT_OUT
I_OUT1
DS20005339B-page 4
+
I_SENSE1+
-
I_SENSE1-
2016 Microchip Technology Inc.
MCP8025/6
Functional Block Diagram – MCP8026
COMMUNICATION PORT
BIAS GENERATOR
VDD
HV_IN1
LV_OUT1
HV_IN2
LV_OUT2
I
O
I
CE
I
LDO
+12V
CAP1
O
CHARGE PUMP
LEVEL
TRANSLATOR
LDO
CAP2
+5V
BUCK SMPS
LX
FB
SUPERVISOR
DE2
MOTOR CONTROL UNIT
VBA
VBB
VBC
VDD
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
O
HSA
O
HSB
O
HSC
I
I
GATE
I CONTROL I
I
I
LOGIC
I
I
I
PHA
PHB
PHC
DRIVER
FAULT
O
+12V
O
LSA
O
LSB
O
LSC
PGND
ILIMIT_REF
+
ILIMIT_OUT
I_OUT1
I_OUT2
I_OUT3
2016 Microchip Technology Inc.
+
I_SENSE1+
-
I_SENSE1-
+
I_SENSE2+
-
I_SENSE2-
+
I_SENSE3+
-
I_SENSE3-
DS20005339B-page 5
COMMUNICATION PORT
BIAS GENERATOR
VDD
VDD
LIN_BUS
MCP8025/6
DS20005339B-page 6
Typical Application Circuit – MCP8025
I/O
LDO
+12V
CAP1
LIN
XCVR
CE
FAULTn/TXE
RX
TX
CHARGE PUMP
I
I/O
O
I
LDO
CAP2
+5V
BUCK SMPS
LX
FB
SUPERVISOR
DE2
100 nF
Ceramic
VADJ
MOTOR CONTROL UNIT
SIM Select
+
ZC_OUT
-
O
I MUX
I
MUX1
MUX2
COMP_REF
I
I
I
NEUTRAL_SIM
+12V
PHASE DETECT
VBA
VBB
VBC
VDD
HSA
O
HSB
O
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
I
I
GATE
I CONTROL I
I
I
LOGIC
I
I
I
PHA
PHB
PHC
B
+12V
LSA
O
2016 Microchip Technology Inc.
DRIVER
FAULT
LSB
O
O
LSC
O
PGND
ILIMIT_REF
+
ILIMIT_OUT
+
I_OUT1
A
HSC
O
-
I_SENSE1+
I_SENSE1-
C
+
_
E
2016 Microchip Technology Inc.
Typical Application Circuit – MCP8026
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DS20005339B-page 7
)?3%.3%
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MCP8025/6
)?/54
MCP8025/6
1.0
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification
is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
Input Voltage, VDD .............................(GND – 0.3V) to +46.0V
Input Voltage, < 100 ms Transient ...............................+48.0V
Internal Power Dissipation ...........................Internally-Limited
Operating Ambient Temperature Range .......-40°C to +150°C
Operating Junction Temperature (Note 1) ....-40°C to +160°C
Transient Junction Temperature (Note 2) ................... +170°C
Storage Temperature (Note 1) ......................-55°C to +150°C
Digital I/O .......................................................... -0.3V to 5.5V
LV Analog I/O .................................................... -0.3V to 5.5V
VBx ...................................................(GND – 0.3V) to +46.0V
PHx, HSx ..........................................(GND – 5.5V) to +46.0V
ESD and Latch-Up Protection:
VDD, LIN_BUS/HV_IN1 8 kV HBM and 750V CDM
All other pins ..................... 2 kV HBM and 750V CDM
Latch-up protection – all pins .............................. > 100 mA
Note 1: The maximum allowable power dissipation
is a function of ambient temperature, the
maximum allowable junction temperature
and the thermal resistance from junction to
air (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation may
cause the device operating junction temperature to exceed the maximum 160°C
rating. Sustained junction temperatures
above 150°C can impact the device reliability and ROM data retention.
2: Transient junction temperatures should not
exceed one second in duration. Sustained
junction temperatures above 170°C may
impact the device reliability.
AC/DC CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, TJ = -40°C to +150°C, typical values are for +25°C, VDD = 13V.
Parameters
Symbol
Min.
Typ.
Max.
Units
Conditions
VDD
6.0
—
19.0
V
6.0
—
28.0
Operating (MCP8026)
6.0
—
40.0
Shutdown
POWER SUPPLY INPUT
Input Operating Voltage
Transient Maximum Voltage
Input Current (MCP8025)
Input Current (MCP8026)
4.0
—
32.0
VDDmax
—
—
48.0
V
IDD
—
—
—
µA
—
5
15
IDD
Buck Operating Range
< 100 ms
VDD > 13V
Sleep mode
—
175
—
Standby, CE = 0V, TJ = -45°C
—
175
—
Standby, CE = 0V, TJ = +25°C
—
195
300
Standby, CE = 0V, TJ = +150°C
—
940
—
Active, CE > VDIG_HI_TH
—
1150
—
Active, VDD = 6V, TJ = +25°C
—
—
—
—
5
15
µA
VDD > 13V
Sleep mode
—
120
—
Standby, CE = 0V, TJ = -45°C
—
120
—
Standby, CE = 0V, TJ = +25°C
—
144
300
Standby, CE = 0V, TJ = +150°C
—
950
—
Active, CE > VDIG_HI_TH
—
1090
—
Active, VDD = 6V, TJ = +25°C
Digital Input/Output
DIGITALI/O
0
—
5.5
V
Digital Open-Drain Drive
Strength
DIGITALIOL
—
1
—
mA
Note 1:
2:
Operating (MCP8025)
VDS < 50 mV
1000 hour cumulative maximum for ROM data retention (typical).
Limits are by design, not production tested.
DS20005339B-page 8
2016 Microchip Technology Inc.
MCP8025/6
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, TJ = -40°C to +150°C, typical values are for +25°C, VDD = 13V.
Parameters
Symbol
Min.
Typ.
Max.
Units
Digital Input Rising Threshold
VDIG_HI_TH
1.26
—
—
V
Digital Input Falling Threshold
VDIG_LO_TH
—
—
0.54
V
VDIG_HYS
—
500
—
mV
IDIG
—
30
100
µA
—
0.2
—
ANALOGVIN
0
—
5.5
V
Excludes LIN and high-voltage
pins
ANALOGVOUT
0
—
VOUT5
V
Excludes LIN and high-voltage
pins
ICP
20
—
—
mA
VDD = 9.0V
Charge Pump Start
CPSTART
11.0
11.5
—
V
VDD falling
Charge Pump Stop
CPSTOP
—
12.0
12.5
V
VDD rising
Charge Pump Frequency
(50% charging/
50% discharging)
CPFSW
—
76.80
—
kHz
VDD = 9.0V
—
0
—
CPRDSON
—
14
—
RDSON sum of high side and
low side
VOUT12
—
12
—
V
VDD 7.5V, CPUMP = 100 nF
IOUT = 20 mA
—
9
—
|TOLVOUT12|
—
—
4.0
%
IOUT
30
—
—
mA
Average current
Average current
Digital Input Hysteresis
Digital Input Current
Analog Low-Voltage Input
Analog Low-Voltage Output
Conditions
VDIG = 3.0V
VDIG = 0V
BIAS GENERATOR
+12V Regulated Charge Pump
Charge Pump Current
Charge Pump Switch
Resistance
Output Voltage
Output Voltage Tolerance
Output Current
VDD = 13V (stopped)
VDD = 5.1V, CPUMP = 260 nF
IOUT = 15 mA
IOUT = 1 mA
ILIMIT
40
50
—
mA
TCVOUT12
—
50
—
ppm/°C
Line Regulation
|VOUT/
(VOUT x VDD)
|
—
0.1
0.5
%/V
Load Regulation
|VOUT/VOUT|
—
0.2
0.5
%
IOUT = 0.1 mA to 15 mA
PSRR
—
60
—
dB
f = 1 kHz
IOUT = 10 mA
VOUT5
—
5
—
V
VDD = VOUT5 + 1V
IOUT = 1 mA
|TOLVOUT5|
—
—
4.0
%
Output Current
IOUT
30
—
—
mA
Average current
Output Current Limit
ILIMIT
40
50
—
mA
Average current
|TCVOUT5|
—
50
—
ppm/°C
Output Current Limit
Output Voltage Temperature
Coefficient
Power Supply Rejection Ratio
13V < VDD < 19V
IOUT = 20 mA
+5V Linear Regulator
Output Voltage
Output Voltage Tolerance
Output Voltage Temperature
Coefficient
Note 1:
2:
1000 hour cumulative maximum for ROM data retention (typical).
Limits are by design, not production tested.
2016 Microchip Technology Inc.
DS20005339B-page 9
MCP8025/6
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, TJ = -40°C to +150°C, typical values are for +25°C, VDD = 13V.
Parameters
Symbol
Min.
Typ.
Max.
Units
Line Regulation
|VOUT/
(VOUT x VDD)
|
—
0.1
0.5
%/V
Load Regulation
|VOUT/VOUT|
—
0.2
0.5
%
Dropout Voltage
VDD – VOUT5
—
180
350
mV
IOUT = 20 mA
measurement taken when
output voltage drops 2% from
no-load value
PSRR
—
60
—
dB
f = 1 kHz
IOUT = 10 mA
VFB
1.19
1.25
1.31
V
TOLVFB
—
—
5.0
%
Feedback Voltage Line
Regulation
VFB/VFB)/
VDD|
—
0.1
0.5
%/V
Feedback Voltage Load
Regulation
VFB/VFB|
—
0.1
0.5
%
IOUT = 5 mA to 150 mA
Feedback Input Bias Current
IFB
-100
—
+100
nA
Sink/Source
Feedback Voltage
To Shutdown Buck Regulator
VBUCK_DIS
2.5
—
5.5
V
VDD > 6V
fSW
—
461
—
kHz
Power Supply Rejection Ratio
Conditions
6V < VDD < 19V
IOUT = 20 mA
IOUT = 0.1 mA to 15 mA
Buck Regulator
Feedback Voltage
Feedback Voltage Tolerance
Switching Frequency
IFB = 1 µA
VDD = 6V to 28V
Duty Cycle Range
DCMAX
3
—
96
%
PMOS Switch On Resistance
RDSON
—
0.6
—
PMOS Switch Current Limit
IP(MAX)
—
2.5
—
A
IGND
—
1.5
2.5
mA
Switching
IQ
—
150
200
µA
IOUT = 0 mA
Ground Current –
PWM Mode
Quiescent Current –
PFM Mode
TJ = 25°C
Output Voltage Adjust Range
VOUT
2.0
—
5.0
V
Output Current
IOUT
150
—
—
mA
250
—
—
—
750
—
mW
Buck Input Undervoltage Lock- UVLOBK_STRT
out – Start-Up
—
4.3
4.5
V
VDD rising
Buck Input Undervoltage Lock- UVLOBK_STOP
out – Shutdown
3.8
4.0
—
V
VDD falling
Buck Input Undervoltage
Lockout Hysteresis
UVLOBK_HYS
—
0.3
—
V
5V LDO Undervoltage Fault
Inactive
UVLO5VLDO_INACT
—
4.5
—
V
VOUT5 rising
5V LDO Undervoltage Fault
Active
UVLO5VLDO_ACT
—
4.0
—
V
VOUT5 falling
Output Power
POUT
5V, VDD – VOUT > 0.5V
3V, VDD – VOUT > 0.5V
P = IOUT x VOUT
2.5A peak current
Voltage Supervisor
Note 1:
2:
1000 hour cumulative maximum for ROM data retention (typical).
Limits are by design, not production tested.
DS20005339B-page 10
2016 Microchip Technology Inc.
MCP8025/6
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, TJ = -40°C to +150°C, typical values are for +25°C, VDD = 13V.
Parameters
Symbol
Min.
Typ.
Max.
Units
UVLO5VLDO_HYS
—
0.5
—
V
Input Undervoltage Lockout –
Start-Up
UVLOSTRT
—
6.0
6.25
V
VDD rising
Input Undervoltage Lockout –
Shutdown
UVLOSTOP
5.1
5.5
—
V
VDD falling
Input Undervoltage Lockout
Hysteresis
UVLOHYS
0.20
0.45
0.70
V
Input Overvoltage Lockout –
Driver Disabled (MCP8025)
DOVLOSTOP
—
20.0
20.5
V
VDD rising
Input Overvoltage Lockout –
Driver Enabled (MCP8025)
DOVLOSTRT
18.75
19.5
—
V
VDD falling
Input Overvoltage Lockout
Hysteresis (MCP8025)
DOVLOHYS
0.15
0.5
0.75
V
Input Overvoltage Lockout
– All Functions Disabled
AOVLOSTOP
—
32.0
33.0
V
VDD rising
Input Overvoltage Lockout
– All Functions Enabled
AOVLOSTRT
29.0
30.0
—
V
VDD falling
Input Overvoltage Lockout
Hysteresis
AOVLOHYS
1.0
2.0
3.0
V
Thermal Warning Temperature
TWARN
—
72
—
%TSD
Thermal Warning Hysteresis
TWARN
—
15
—
°C
Falling temperature
TSD
160
170
—
°C
Rising temperature
TSD
—
25
—
°C
Falling temperature
PWMH/L Input Pull Down
RPULLDN
—
47
—
k
Output Driver Source Current
ISOURCE
0.3
—
—
A
VDD = 12V, HS[A:C], LS[A:C]
ISINK
0.3
—
—
A
VDD = 12V, HS[A:C], LS[A:C]
Output Driver Source
Resistance
RDSON
—
17
—
IOUT = 10 mA, VDD = 12V
HS[A:C], LS[A:C]
Output Driver Sink
Resistance
RDSON
—
17
—
IOUT = 10 mA, VDD = 12V
HS[A:C], LS[A:C]
Output Driver Blanking
tBLANK
500
—
4000
ns
Configurable
Output Driver UVLO Threshold
DUVLO
7.2
8.0
—
V
Config Register 0 bit 3 = 0
Output Driver UVLO Minimum
Duration
tDUVLO
tBLANK
+ 700
—
tBLANK
+ 1400
ns
Fault latched after tDUVLO
Output Driver HS Drive
Voltage
VHS
8.0
12
13.5
V
With respect to the phase pin
-5.5
—
—
Output Driver LS Drive Voltage
VLS
8.0
12
13.5
V
With respect to ground
VBOOTSTRAP
—
—
—
V
—
—
44
Continuous
—
—
48
< 100 ms
5V LDO Undervoltage Fault
Hysteresis
Conditions
Temperature Supervisor
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
Rising temperature (115°C)
MOTOR CONTROL UNIT
Output Drivers
Output Driver Sink Current
Output Driver Bootstrap
Voltage
Note 1:
2:
With respect to ground
With respect to ground
1000 hour cumulative maximum for ROM data retention (typical).
Limits are by design, not production tested.
2016 Microchip Technology Inc.
DS20005339B-page 11
MCP8025/6
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, TJ = -40°C to +150°C, typical values are for +25°C, VDD = 13V.
Parameters
Output Driver Phase Pin
Voltage
Output Driver Short-Circuit
Protection Threshold
Symbol
Min.
Typ.
Max.
Units
VPHASE
—
—
—
V
DSC_THR
High Side (VDD – VPHx)
Low Side (VPHx – PGND)
Output Driver Short-Circuit
Detected Propagation Delay
TSC_DLY
Conditions
With respect to ground
-5.5
—
44
Continuous
-5.5
—
48
< 100 ms
—
—
—
—
0.250
—
V
00 (Default)
Set In Register CFG0
—
0.500
—
01
—
0.750
—
10
—
1.000
—
—
—
—
—
430
—
Detection after blanking
—
10
—
Detection during blanking,
value is delay after blanking
11
ns
CLOAD = 1000 pF, VDD = 12V
Output Driver OVLO Turn-Off
Delay
TOVLO_DLY
3
5
—
µs
Detection synchronized with
internal clock (Note 2)
Power-Up or Sleep to Standby
tPOWER
—
—
—
ms
CE High-Low-High
Transition < 100 µs (Fault
Clearing)
—
10
—
Standby to Motor Operational
Fault to Driver Output Turn-Off
tMOTOR
TFAULT_OFF
MCP8025
—
5
—
—
5
—
µs
CE High-Low-High
Transition < 0.9 ms (Fault
Clearing)
—
—
5
ms
Standby state to Operational
state (MCP8025) (Note 2)
—
—
10
ms
Standby state to Operational
state (MCP8026) (Note 2)
—
—
—
µs
CLOAD = 1000 pF, VDD = 12V
Time after fault occurs
MCP8026
—
1
—
UVLO, OCP faults
—
10
—
All other faults
CE Low to Driver Output
Turn-Off
TDEL_OFF
—
100
250
ns
CLOAD = 1000 pF, VDD = 12V
Time after CE = Low (Note 2)
CE Low to Standby State
tSTANDBY
—
1
—
ms
Time after CE = Low
SLEEP bit = 0
tSLEEP
—
1
—
ms
Time after CE = Low
SLEEP bit = 1
tFAULT_CLR
1
—
900
µs
CE High-Low-High Transition
Time (Note 2)
CE Low to Sleep State
CE Fault Clearing Pulse
Note 1:
2:
1000 hour cumulative maximum for ROM data retention (typical).
Limits are by design, not production tested.
DS20005339B-page 12
2016 Microchip Technology Inc.
MCP8025/6
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, TJ = -40°C to +150°C, typical values are for +25°C, VDD = 13V.
Parameters
Symbol
Min.
Typ.
Max.
Units
VOS
-3.0
—
+3.0
mV
VOS/TA
—
±2.0
—
µV/°C
Conditions
Current Sense Amplifier
Input Offset Voltage
Input Offset Temperature Drift
Input Bias Current
VCM = 0V
TA = -40°C to +150°C
VCM = 0V
IB
-1
—
+1
µA
Common Mode Input Range
VCMR
-0.3
—
3.5
V
Common Mode Rejection Ratio
CMRR
—
80
—
dB
Freq = 1 kHz
IOUT = 10 µA
VOL, VOH
0.05
—
4.5
V
IOUT = 200 µA
SR
—
±7
—
V/µs
GBWP
—
10.0
—
MHz
Maximum Output Voltage
Swing
Slew Rate
Gain Bandwidth Product
Symmetrical
Current Comparator Hysteresis
CCHYS
—
10
—
mV
Current Comparator Common
Mode Input Range
VCC_CMR
1.0
—
4.5
V
—
8
—
bits
VOL, VOH
0.991
—
4.503
V
IOUT = 1 mA
VDAC
—
—
—
V
CFG1 Code x
13.77 mV/bit + 0.991V
—
0.991
—
Current Limit DAC
Resolution
Output Voltage Range
Output Voltage
Code 00H
—
1.872
—
Code 40H
—
4.503
—
Code FFH
Input to Output Delay
TDELAY
—
50
—
Integral Nonlinearity
INL
-0.5
—
+0.5
%FSR %Full Scale Range (Note 2)
µs
Differential Nonlinearity
DNL
-50
—
+50
%LSB
ILIMIT_OUT Sink Current
(Open-Drain)
ILOUT
—
1
—
mA
ZCVOL,
ZCVOH
0.05
—
5.0
V
Reference Input Impedance
ZCZREF
—
83
—
k
Input to Output Delay
ZCDELAY
—
—
500
ns
Voltage Divider RC Time
Constant
ZCTRC
—
100
—
ns
ZC Output Pull-Up Range
ZCRPULLUP
3.3
10
—
k
ZCIOL
—
1
—
mA
%LSB (Note 2)
VILIMIT_OUT 50 mV
ZC Back EMF Sampler Comparator (MCP8025)
Maximum Output Voltage
Swing
ZC Output Sink Current
(Open-Drain)
Note 1:
2:
IOUT = 1 mA
VIN_STEP = 500 mV (Note 2)
VOUT 50 mV
1000 hour cumulative maximum for ROM data retention (typical).
Limits are by design, not production tested.
2016 Microchip Technology Inc.
DS20005339B-page 13
MCP8025/6
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, TJ = -40°C to +150°C, typical values are for +25°C, VDD = 13V.
Parameters
Symbol
Min.
Typ.
Max.
Units
Conditions
Back EMF Sampler Phase Multiplexer (MCP8025)
MUX[1:2] Input Pull Down
RPULLDN
—
47
—
k
tTRAN
—
150
250
ns
MUXDELAY
—
210
—
ns
CPHASE
—
1.5
—
pF
MUX input to ground
RPUTXD
—
48
—
k
Pull up to 5V
LIN Bus High-Level Input
Voltage
VHI
0.6 x
VDD
—
—
V
Recessive state
LIN Bus Low-Level Input
Voltage
VLO
—
—
0.4 x
VDD
V
Dominant state
LIN Bus Input Hysteresis
VHYS
—
—
0.175 x
VDD
V
VHI – VLO
IOL
7.3
—
—
mA
16.5
—
—
30.6
—
—
5
—
180
µA
50
—
200
mA
—
—
0.2 x
VDD
V
-1
—
—
mA
Driver OFF
VBUS = 0V
VDD = 12V
—
12
20
µA
Driver OFF
VBUS VDD
7V < VBUS < 19V
7V < VDD < 19V
-1
—
1
mA
GND = VDD = 12V
0V < VBUS < 19V
IBUS_NO_BAT
—
—
10
µA
VDD = 0V
0V < VBUS < 19V
Receiver Center Voltage
VBUS_CNT
0.475
x VDD
0.5 x
VDD
0.525 x
VDD
V
VBUS _CNT = (VHI – VLO)/2
LIN Bus Slave Pull-Up
Resistance
RPULLUP
20
30
47
k
tDOM_TOUT
—
25
—
ms
TRX_PD
—
3.0
6.0
µs
Transition Time
Delay from MUX Select to ZC
Out
Phase Filter Capacitors
(Note 2)
COMMUNICATION PORTS
Standard LIN (MCP8025)
Microcontroller Interface
TX Input Pull-Up Resistor
Bus Interface
LIN Bus Low-Level Output
Current
LIN Bus Input Pull-Up Current
IPU
LIN Bus Short-Circuit Current
Limit
ISC
LIN Bus Low-Level Output
Voltage
LIN Bus Input Leakage Current
(at receiver during dominant
bus level)
VOL
IBUS_PAS_REC
LIN Bus Input Leakage Current
(disconnected from ground)
IBUS_NO_GND
LIN Bus Input Leakage Current
(disconnected from VDD)
LIN Dominant State Timeout
Propagation Delay
Note 1:
2:
VO = 0.2 x VDD, VDD = 18V
VO = 0.251 x VDD, VDD = 18V
IBUS_PAS_DOM
LIN Bus Input Leakage Current
(at receiver during recessive
bus level)
VO = 0.2 x VDD, VDD = 8V
Propagation delay of receiver
1000 hour cumulative maximum for ROM data retention (typical).
Limits are by design, not production tested.
DS20005339B-page 14
2016 Microchip Technology Inc.
MCP8025/6
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, TJ = -40°C to +150°C, typical values are for +25°C, VDD = 13V.
Parameters
Symmetry
Symbol
Min.
Typ.
Max.
Units
TRX_SYM
-2
—
+2
µs
0
—
VDD
V
Conditions
Symmetry of receiver
propagation delay rising edge
w.r.t.falling edge
Voltage Level Translators (MCP8026)
High-Voltage Input Range
VIN
Low-Voltage Output Range
VOUT
0
—
5.0V
V
Input Pull-Up Resistor
RPU
—
30
—
k
High-Level Input Voltage
VIH
0.60
—
—
VDD
VDD = 15V
Low-Level Input Voltage
VIL
—
—
0.40
VDD
VDD = 15V
Input Hysteresis
VHYS
—
—
0.30
VDD
TLV_OUT
—
3.0
6.0
µs
(Note 2)
FMAX
—
—
20
kHz
(Note 2)
IOL
—
1
—
mA
VOUT 50 mV
BAUD
—
9600
—
bps
Power-Up Delay
PU_DELAY
—
1
—
ms
Time from rising VDD 6V
to DE2 active
DE2 Sink Current
DE2iSINK
1
—
—
mA
VDE2 50 mV (Note 2)
DE2 Message Response Time
DE2RSP
0
—
—
µs
Time from last received Stop
bit to Response Start bit
(Note 2)
DE2 Host Wait Time
DE2WAIT
3.125
—
—
ms
Minimum time for host
to wait for response. Three
packets based on 9600 baud
(Note 2)
DE2RCVTOUT
—
5
—
ms
Time between message bytes
Propagation Delay
Maximum Communication Frequency
Low-Voltage Output Sink
Current (Open-Drain)
DE2 Communications
Baud Rate
DE2 Message Receive Timeout
INTERNAL ROM (READ-ONLY MEMORY) DATA RETENTION
Cell High Temperature
Operating Life
Cell Operating Life
Note 1:
2:
HTOL
—
1000
—
Hours
TJ = 150°C (Note 1)
—
10
—
Years
TJ = 85°C
1000 hour cumulative maximum for ROM data retention (typical).
Limits are by design, not production tested.
2016 Microchip Technology Inc.
DS20005339B-page 15
MCP8025/6
TEMPERATURE SPECIFICATIONS
Parameters
Sym.
Min.
Specified Temperature Range
TA
Operating Temperature Range
Typ.
Max.
Units
-40
+150
°C
TA
-40
+150
°C
TJ
-40
+160
°C
TA
-55
+150
°C
Conditions
Temperature Ranges (Note 1)
Storage Temperature Range
(Note 2)
Package Thermal Resistances
Thermal Resistance, 5 mm x 5 mm
40LD-QFN
Thermal Resistance, 7 mm x 7 mm
48LD-TQFP with Exposed Pad
Note 1:
2:
JA
—
37
—
JC
—
6.9
—
°C/W 4-Layer JC51-5 standard board
Natural convection
JA
—
30
—
°C/W
JC
—
15
—
The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable
junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the
maximum allowable power dissipation will cause the device operating junction temperature to exceed the
maximum 160°C rating. Sustained junction temperatures above 160°C can impact the device reliability.
1000 hour cumulative maximum for ROM data retention (typical).
ESD, SUSCEPTIBILITY, SURGE AND LATCH-UP TESTING
Parameter
Input voltage surges
ESD according to IBEE LIN EMC
– Pins LIN_BUS, VDD (HMM)
ESD HBM with 1.5 k/100 pF
Standard and Test Condition
28V for 1 minute,
45V for 0.5 seconds
Test specification 1.0 following IEC 61000-4.2 ± 8 kV
CEI/IEC 60749-26: 2006
AEC-Q100-002-Ref E
JEDEC JS-001-2012
ESD HBM with 1.5 k/100 pF
CEI/IEC 60749-26: 2006
– Pins LIN_BUS, VDD, HV_IN1 against PGND AEC-Q100-002-Ref E
JEDEC JS-001-2012
ESD CDM (Charged Device Model,
ESD-STM5.3.1-1999
field-induced method – replaces
machine-model method)
Latch-Up Susceptibility
AEC Q100-004, 150°C
DS20005339B-page 16
Value
ISO 16750-2
± 2 kV
± 8 kV
± 750V all pins
> 100 mA
2016 Microchip Technology Inc.
MCP8025/6
2.0
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Note: Unless otherwise indicated, TA = +25°C; Junction Temperature (TJ) is approximated by soaking the device under
test to an ambient temperature equal to the desired junction temperature. The test time is small enough such that the
rise in junction temperature over the ambient temperature is not significant.
0.010
VOUT = 5V
0.006
0.004
Volts (V)
0.002
0.000
-0.002
VOUT = 12V
-0.004
-0.006
-0.008
-0.010
-45
-20
5
FIGURE 2-1:
Temperature.
30
55
80
Temperature (°C)
105
130
HSA
VBA
20
15
10
5
0
155
0
5
10
15
FIGURE 2-4:
Duty Cycle.
LDO Line Regulation vs.
0.35
20 25 30
Time (µs)
35
40
45
Bootstrap Voltage @ 92%
145
12V LDO
140
0.20
Current (mA)
0.25
VOUT = 12V
0.15
0.10
135
130
5V LDO
125
120
115
110
0.05
105
0.00
100
-45
-20
5
FIGURE 2-2:
Temperature.
30
55
80
Temperature (°C)
105
130
155
LDO Load Regulation vs.
7
10
13
FIGURE 2-5:
vs. Input Voltage.
16
19
22
Voltage (V)
25
28
140
VIN (V)
120
100
CIN = COUT = 10 µF
IOUT = 20 mA
12
DE2
VIN = 15V
VIN = 14V
15
ILIMIT_OUT
80
60
9
40
VOUT (AC)
6
20
0
3
-20
0
1
2
3
FIGURE 2-3:
Message Delay.
4
5
6
Time (µs)
7
8
9
ILIMIT_OUT Low to DE2
2016 Microchip Technology Inc.
10
31
LDO Short-Circuit Current
18
0
50
150
VOUT = 5V
0.30
Load Regulation (%)
VDD = 6V
25
20
15
10
5
0
VOUT (mV)
Line Regulation (%/V)
0.008
-40
0
20
FIGURE 2-6:
Rising VDD.
40
60
Time (µs)
80
100
5V LDO Dynamic Linestep –
DS20005339B-page 17
MCP8025/6
Note: Unless otherwise indicated, TA = +25°C; Junction Temperature (TJ) is approximated by soaking the device under
test to an ambient temperature equal to the desired junction temperature. The test time is small enough such that the
rise in junction temperature over the ambient temperature is not significant.
15
CIN = COUT = 10 µF
IOUT = 20 mA
80
100
60
80
60
9
40
VOUT (AC)
6
20
0
0
20
40
60
Time (µs)
FIGURE 2-7:
Falling VDD.
80
-80
-40
-100
9
60
VOUT (AC)
40
20
6
0
0
20
40
60
Time (µs)
FIGURE 2-8:
– Rising VDD.
80
40
1 mA
20
0
20 mA
-20
-40
-60
-80
-40
-100
100
0.0
12V LDO Dynamic Linestep
0.5
FIGURE 2-11:
Loadstep.
1.0
1.5
Time (ms)
2.0
2.5
12V LDO Dynamic
14.0
80
VIN = 15V
Charge Pump
Switch Point
13.0
15
2.5
VIN = 14V
VOUT = 12V
CIN = COUT = 10 µF
IOUT = 1 mA to 20 mA Pulse
60
-20
16
2.0
5V LDO Dynamic Loadstep.
80
0
3
1.0
1.5
Time (ms)
100
VOUT AC (mV)
80
0.5
FIGURE 2-10:
100
CIN = COUT = 10 µF
IOUT = 20 mA
20 mA
0.0
120
15
12
0
-20
-60
140
VIN = 15V
1 mA
20
-20
5V LDO Dynamic Linestep –
VIN = 14V
40
100
18
VIN = 14V
VOUT = 5V
CIN = COUT = 10 µF
IOUT = 1 mA to 20 mA Pulse
-40
0
3
VIN (V)
100
120
VOUT (mV)
VIN (V)
12
140
VOUT AC (mV)
VIN = 14V
VIN = 15V
VOUT (mV)
18
60
VIN = 14V
VOUT (AC)
13
20
12
CIN = COUT = 10 µF
IOUT = 20 mA
11
10
0
20
FIGURE 2-9:
– Falling VDD.
DS20005339B-page 18
40
60
Time (µs)
80
VOUT (V)
VIN (V)
40
VOUT (mV)
12.0
14
11.0
10.0
0
9.0
-20
8.0
-40
7.0
100
12V LDO Dynamic Linestep
VOUT = 12V
CIN = COUT = 10 µF
IOUT = 20 mA
6
10
14
18
VIN (V)
22
26
30
FIGURE 2-12:
12V LDO Output Voltage vs.
Rising Input Voltage.
2016 Microchip Technology Inc.
MCP8025/6
Note: Unless otherwise indicated, TA = +25°C; Junction Temperature (TJ) is approximated by soaking the device under
test to an ambient temperature equal to the desired junction temperature. The test time is small enough such that the
rise in junction temperature over the ambient temperature is not significant.
24
1000
22
CE High
20
800
600
16
400
14
CE Low
200
Low-Side
12
10
0
-45
-20
5
30
55
80
Temperature (°C)
105
130
-45
155
FIGURE 2-13:
Quiescent Current vs.
Temperature (MCP8025).
-20
5
30
55
80
Temperature(°C)
FIGURE 2-16:
Temperature.
105
130
155
130
155
Driver RDSON vs.
5.0
Typical Baud Rate Deviation (%)
1200
CE High
1000
Quiescent Current (µA)
High-Side
18
RDSON (Ω)
Quiescent Current (µA)
1200
800
600
400
CE Low
200
4.0
MAX
3.0
2.0
1.0
AVERAGE
0.0
-1.0
MIN
-2.0
-3.0
-4.0
-5.0
0
-45
-20
5
30
55
80 105
Temperature (°C)
130
155
-45
-20
FIGURE 2-17:
Deviation.
FIGURE 2-14:
Quiescent Current vs.
Temperature (MCP8026).
5
30
55
80
Temperature (&
105
Typical Baud Rate
PWMxH
Dead Time
PWMxL
Dead Time
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Time (µs)
FIGURE 2-15:
Injection.
500 ns PWM Dead Time
2016 Microchip Technology Inc.
DS20005339B-page 19
MCP8025/6
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Tables 3-1 and 3-2.
TABLE 3-1:
MCP8025 – PIN FUNCTION TABLE
QFN
TQFP
Symbol
I/O
2
1
PWM1L
I
Description
3
2
PWM1H
I
Digital input, phase A high-side control, 47 k pull down
4
3
CE
I
Digital input, device enable, 47 k pull down
—
4
NC
—
No connection
—
5
NC
—
No connection
LIN Bus physical layer
Digital input, phase A low-side control, 47 k pull down
5
6
LIN_BUS
I/O
—
7
PGND
Power
6
8
RX
O
LIN Bus receive data, open-drain
7
9
TX
I
LIN Bus transmit data
8
10
FAULTn/TXE
I/O
9
11
MUX1
I
10
12
MUX2
I
Digital input Back EMF sampler phase multiplexer control, 47 k pull down
11
13
ZC_OUT
O
Back EMF sampler comparator output, open-drain
12
14
COMP_REF
I
Back EMF sampler comparator reference
13
15
ILIMIT_OUT
O
Current limit comparator, MOSFET driver fault output, open-drain
14
16
I_OUT1
O
Motor current sense amplifier output
15
17
ISENSE1-
I
Motor current sense amplifier inverting input
16
18
ISENSE1+
I
17
19,20
PGND
Power
18
21
LSA
O
Phase A low-side N-channel MOSFET driver, active high
19
22
LSB
O
Phase B low-side N-channel MOSFET driver, active high
20
23
LSC
O
—
24
PGND
Power
21
25
HSC
O
Phase C high-side N-channel MOSFET driver, active high
22
26
HSB
O
Phase B high-side N-channel MOSFET driver, active high
Phase A high-side N-channel MOSFET driver, active high
Power 0V reference
LIN transceiver fault and transmit enable
Digital input Back EMF sampler phase multiplexer control, 47 k pull down
Motor current sense amplifier non-inverting input
Power 0V reference
Phase C low-side N-channel MOSFET driver, active high
Power 0V reference
23
27
HSA
O
24
28
PHC
I/O
Phase C high-side MOSFET driver reference, Back EMF sense input
25
29
PHB
I/O
Phase B high-side MOSFET driver reference, Back EMF sense input
26
30
PHA
I/O
Phase A high-side MOSFET driver reference, Back EMF sense input
27
31
VBC
Power
Phase C high-side MOSFET driver bias
28
32
VBB
Power
Phase B high-side MOSFET driver bias
29
33
VBA
Power
Phase A high-side MOSFET driver bias
30
34
+12V
Power
Analog circuitry and low-side gate drive bias
—
35, 36
PGND
Power
Power 0V reference
31
37
LX
Power
Buck regulator switch node, external inductor connection
32
38, 39
VDD
Power
33
40
FB
I
34
41
+5V
Power
Internal circuitry bias
35
42
CAP2
Power
Charge pump flying capacitor input
36
43
CAP1
Power
37
44
DE2
O
Voltage and temperature supervisor output, open-drain
Digital input, phase C low-side control, 47 k pull down
Input Supply
Buck regulator feedback node
Charge pump flying capacitor input
38
45
PWM3L
I
39
46
PWM3H
I
Digital input, phase C high-side control, 47 k pull down
40
47
PWM2L
I
Digital input, phase B low-side control, 47 k pull down
1
48
PWM2H
I
Digital input, phase B high-side control, 47 k pull down
EP
EP
PGND
Power
DS20005339B-page 20
Exposed Pad. Connect to Power 0V reference.
2016 Microchip Technology Inc.
MCP8025/6
TABLE 3-2:
MCP8026 – PIN FUNCTION TABLE
QFN
TQFP
Symbol
I/O
Description
2
1
PWM1L
I
Digital input, phase A low-side control, 47 k pull down
3
2
PWM1H
I
Digital input, phase A high-side control, 47 k pull down
4
3
CE
I
Digital input, device enable, 47 k pull down
—
4
LV_OUT2
O
Level Translator 2 logic level translated output, open-drain
—
5
HV_IN2
I
Level Translator 2 high-voltage input, 30 k configurable pull up
5
6
HV_IN1
I
Level Translator 1 high-voltage input, 30 k configurable pull up
—
7
PGND
Power
6
8
LV_OUT1
O
Level Translator 1 logic level translated output, open-drain
7
9
I_OUT3
O
Motor phase current sense amplifier 3 output
8
10
ISENSE3-
I
Motor phase current sense amplifier 3 inverting input
9
11
ISENSE3+
I
Motor phase current sense amplifier 3 non-inverting input
10
12
I_OUT2
O
Motor phase current sense amplifier 2 output
Power 0V reference
11
13
ISENSE2-
I
Motor phase current sense amplifier 2 inverting input
12
14
ISENSE2+
I
Motor phase current sense amplifier 2 non-inverting input
13
15
ILIMIT_OUT
O
Current limit comparator, MOSFET driver fault output, open-drain
14
16
I_OUT1
O
Motor current sense amplifier 1 output
15
17
ISENSE1-
I
Motor current sense amplifier 1 inverting input
16
18
ISENSE1+
I
Motor current sense amplifier 1 non-inverting input
17
19,20
PGND
Power
18
21
LSA
O
Power 0V reference
Phase A low-side N-Channel MOSFET driver, active high
19
22
LSB
O
Phase B low-side N-Channel MOSFET driver, active high
20
23
LSC
O
Phase C low-side N-Channel MOSFET driver, active high
—
24
PGND
Power
21
25
HSC
O
Phase C high-side N-Channel MOSFET driver, active high
22
26
HSB
O
Phase B high-side N-Channel MOSFET driver, active high
23
27
HSA
O
Phase A high-side N-Channel MOSFET driver, active high
24
28
PHC
I/O
Phase C high-side MOSFET driver reference, Back EMF sense input
25
29
PHB
I/O
Phase B high-side MOSFET driver reference, Back EMF sense input
26
30
PHA
I/O
27
31
VBC
Power
Phase C high-side MOSFET driver bias
28
32
VBB
Power
Phase B high-side MOSFET driver bias
Power 0V reference
Phase A high-side MOSFET driver reference, Back EMF sense input
29
33
VBA
Power
Phase A high-side MOSFET driver bias
30
34
+12V
Power
Analog circuitry and low-side gate drive bias
—
35,36
PGND
Power
Power 0V reference
31
37
LX
Power
Buck regulator switch node, external inductor connection
32
38, 39
VDD
Power
Input supply
33
40
FB
I
34
41
+5V
Power
Internal circuitry bias
35
42
CAP2
Power
Charge pump flying capacitor input
36
43
CAP1
Power
Charge pump flying capacitor input
37
44
DE2
O
Voltage and temperature supervisor output, open-drain
38
45
PWM3L
I
Digital input, phase C low-side control, 47 k pull down
39
46
PWM3H
I
Digital input, phase C high-side control, 47 k pull down
40
47
PWM2L
I
Digital input, phase B low-side control, 47 k pull down
1
48
PWM2H
I
EP
EP
PGND
Power
2016 Microchip Technology Inc.
Buck regulator feedback node
Digital input, phase B high-side control, 47 k pull down
Exposed Pad. Connect to Power 0V reference.
DS20005339B-page 21
MCP8025/6
3.1
Low-Side PWM Inputs
(PWM1L, PWM2L, PWM3L)
3.5
Level Translators (HV_IN1,
HV_IN2, LV_OUT1, LV_OUT2)
Digital PWM inputs for low-side driver control. Each
input has a 47 k pull down to ground. The PWM
signals may contain dead-time timing or the system
may use configuration register 2 (CFG2) to set the
dead time.
Unidirectional digital level translators. These pins
translate digital input signal on the HV_INx pin to a
low-level digital output signal on the LV_OUTx pin. The
HV_INx pins have internal 30 k pull ups to VDD that
are controlled by bit PU30K in the CFG0 configuration
register. The PU30K bit is only sampled during CE = 0.
3.2
The HV_IN1 pin has higher ESD protection than the
HV_IN2 pin. The higher ESD protection makes the
HV_IN1 pin better suited for connection to external
switches.
High-Side PWM Inputs
(PWM1H, PWM2H, PWM3H)
Digital PWM inputs for high-side driver control. Each
input has a 47 k pull down to ground. The PWM
signals may contain dead-time timing or the system
may use the configuration register 2 (CFG2) to set the
dead time.
3.3
No Connect (NC)
Reserved. Do not connect.
3.4
Chip Enable Input (CE)
Chip Enable input is used to enable/disable the output
driver and on-board functions. When CE is high, all
device functions are enabled. When CE is low, the
device operates in Standby or Sleep mode. When
Standby mode is active, the current amplifiers and the
12V LDO are disabled. The buck regulator, the DE2
pin, the voltage and temperature sensor functions are
not affected. The 5V LDO is disabled on the MCP8026.
The H-bridge driver outputs are all set to a low state
within 100 ns of CE = 0. The device transitions to
Standby or Sleep mode 1 ms after CE = 0.
The CE pin may be used to clear any hardware faults.
When a fault occurs, the CE input may be used to clear
the fault by setting the pin low and then high again. The
fault is cleared by the rising edge of the CE signal if the
hardware fault is no longer active.
The CE pin is used to enable Sleep mode when the
SLEEP bit in the CFG0 configuration register is set
to ‘1’. CE must be low for a minimum of 1 ms before the
transition to Standby or Sleep mode occurs. This allows
time for CE to be toggled to clear any faults without
going into Sleep mode.
The CE pin is used to awaken the device from the
Sleep mode state. To awaken the device from a Sleep
mode state, the CE pin must be set low for a minimum
of 250 μs. The device will then wake up with the next
rising edge of the CE pin.
The CE pin has an internal 47 k pull down.
LV_OUT1 and LV_OUT2 are open-drain outputs. An
external pull-up resistor to the low-voltage logic supply
is required.
The HV_IN1 pin may be used to awaken the device
from the Sleep mode state. The MCP8026 will awaken
on the rising edge of the pin after detecting a low state
lasting > 250 µs on the pin.
3.6
LIN Transceiver Bus (LIN_BUS)
The bidirectional LIN_BUS interface pin connects to
the LIN Bus network. The LIN_BUS driver is controlled
by the TX pin. The driver is an open-drain output. The
MCP8025 device contains a LIN Bus 30 k pull-up
resistor that may be enabled or disabled by setting the
PU30K bit in the CFG0 configuration register. The pull
up may only be changed while in Standby mode.
During normal operation, the 30 k pull up is always
enabled. In Sleep mode, the 30 k pull up is always
disabled.
The LIN bus may be used to awaken the device from
the Sleep mode state. When a LIN wake-up event is
detected on the LIN_BUS pin, the device will wake up.
The MCP8025 will awaken on the rising edge of the
bus after detecting a dominant state lasting > 150 µs
on the bus. The LIN Bus master must provide the
dominant state for > 250 µs to meet the LIN 2.2A
specifications.
3.7
Power Ground (PGND),
Exposed Pad (EP)
Device ground. The PCB ground traces should be short
and wide and should form a STAR pattern to the power
source. The Exposed Pad (EP) must be soldered to the
PCB. The PCB area below the EP should be a copper
pour with thermal vias to help transfer heat away from
the device.
3.8
LIN Transceiver Received Data
Output (RX)
The RX output pin follows the state of the LIN_BUS pin.
The data received from the LIN bus is output on the RX
pin for connection to a host MCU.
The RX pin is an open-drain output.
DS20005339B-page 22
2016 Microchip Technology Inc.
MCP8025/6
3.9
LIN Transceiver Transmit Data
Input (TX)
3.14
Current Limit and Driver Fault
Output (ILIMIT_OUT)
The TX input pin is used to send data to the LIN Bus.
The LIN_BUS pin is low (dominant) when TXD is low
and high (recessive) when TXD is high. Data to be
transmitted from a host MCU is sent to the LIN bus via
the TX pin.
Dual-purpose output pin. The open-drain output goes
low when the current sensed by current sense
amplifier 1 exceeds the value set by the internal current
reference DAC. The DAC has an offset of 0.991V
(typical) which represents the zero current flow.
3.10
The open-drain output will also go low while a fault is
active. Table 4-1 shows the faults that cause the
ILIMIT_OUT pin to go low.
LIN Transceiver Fault/
Transmit Enable (FAULTn/TXE)
Fault Detect output and Transmitter Enable input
bidirectional pin. The FAULTn/TXE pin will be driven
low whenever a LIN fault occurs. There is a
47 k resistor between the internal fault signal and the
FAULTn/TXE pin to allow the pin to be externally driven
high after a fault has occurred. The FAULTn/TXE pin
must be pulsed high to start a transmit. If there is no
fault present when the pin is pulsed, the FAULTn/TXE
pin will latch and be driven high by an internal 47 k
impedance. The FAULTn/TXE pin may then be
monitored for faults.
No external pull up is needed. The microcontroller pin
controlling the FAULTn/TXE pin must be able to switch
between output and input modes.
3.11
Zero-Crossing Multiplexer Inputs
(MUX1, MUX2)
The MUX1 and MUX2 multiplexer inputs select the
desired phase winding to be used as the zero-crossing
Back EMF phase reference. The output of the
multiplexer connects to one input of the zero-crossing
comparator. The other zero-crossing comparator input
connects to the neutral voltage. The MUX1 and MUX2
inputs must be driven by the host processor
synchronously with the motor commutation.
3.12
Zero-Crossing Detector Output
(ZC_OUT)
The ILIMIT_OUT pin is able to sink 1 mA of current
while maintaining less than a 50 mV drop across the
output.
3.15
Operational Amplifier Outputs
(I_OUT1, I_OUT2, I_OUT3)
Current sense amplifier outputs. May be used with
feedback resistors to set the current sense gain. The
amplifiers are disabled when CE = 0.
3.16
Operational Amplifier Inputs
(ISENSE1 +/-, ISENSE2 +/-,
ISENSE3 +/-)
Current sense amplifier inverting and non-inverting
inputs. Used in conjunction with the I_OUTn pin to set
the current sense gain. The amplifiers are disabled
when CE = 0.
3.17
Low-Side N-Channel MOSFET
Driver Outputs (LSA, LSB, LSC)
Low-side N-channel MOSFET drive signal. Connect to
the gate of the external MOSFETs. A low-impedance
resistor may be used between these pins and the
MOSFET gates to limit current and slew rate.
3.18
High-Side N-Channel MOSFET
Driver Outputs (HSA, HSB, HSC)
The ZC_OUT output pin is the output of the
zero-crossing comparator. When the phase voltage
selected by the multiplexer inputs crosses the neutral
voltage, the zero-crossing detector will change the
output state.
High-side N-channel MOSFET drive signal. Connect to
the gate of the external MOSFETs. A low-impedance
resistor may be used between these pins and the
MOSFET gates to limit current and slew rate.
The ZC_OUT output is an open-drain output.
3.19
3.13
Phase signals from motor. These signals provide
high-side N-channel MOSFET driver reference and
Back EMF sense input. The phase signals are also
used with the bootstrap capacitors to provide high-side
gate drive via the VBx inputs.
Neutral Voltage Reference Input
(COMP_REF)
The COMP_REF input pin is used to connect to the
neutral point of a motor if the neutral point is available.
The COMP_REF input may be selected via a
configuration register as the neutral voltage reference
used by the zero-crossing comparator.
2016 Microchip Technology Inc.
Driver Phase Inputs
(PHA, PHB, PHC)
DS20005339B-page 23
MCP8025/6
3.20
Driver Bootstrap Inputs
(VBA, VBB, VBC)
High-side MOSFET driver bias. Connect these pins
between the bootstrap charge pump diode cathode and
the bootstrap charge pump capacitor. The 12V LDO
output is used to provide 12V at the diode anodes. The
phase signals are connected to the other side of the
bootstrap charge pump capacitors. The bootstrap
capacitors charge to 12V when the phase signals are
pulled low by the low-side drivers. When the low-side
drivers turn off and the high-side drivers turn on, the
phase signal is pulled to VDD, causing the bootstrap
voltage to rise to VDD + 12V.
3.21
12V LDO (+12V)
+12-volt Low Dropout (LDO) voltage regulator output.
The +12V LDO may be used to power external devices
such as Hall-effect sensors or amplifiers. The LDO
requires an output capacitor for stability. The positive
side of the output capacitor should be physically
located as close to the +12V pin as is practical. For
most applications, 4.7 µF of capacitance will ensure
stable operation of the LDO circuit. The +12V LDO is
supplied by the internal charge pump when the charge
pump is active. When the charge pump is inactive, the
+12V LDO is supplied by VDD.
The type of capacitor used can be ceramic, tantalum or
aluminum electrolytic. The low ESR characteristics of
the ceramic will yield better noise and PSRR
performance at high frequency.
3.22
Buck Regulator Switch Output
(LX)
Buck regulator switch node external inductor
connection. Connect this pin to the external inductor
chosen for the buck regulator.
3.23
Power Supply Input (VDD)
Connect VDD to the main supply voltage. This voltage
should be the same as the motor voltage. The driver
overcurrent and overvoltage shutdown features are
relative to the VDD pin. When the VDD voltage is
separate from the motor voltage, the overcurrent and
overvoltage protection features may not be available.
The VDD voltage must not exceed the maximum
operating limits of the device. Connect a bulk capacitor
close to this pin for good loadstep performance and
transient protection.
3.24
Buck Regulator Feedback Input
(FB)
Buck regulator feedback node that is compared to an
internal 1.25V reference voltage. Connect this pin to a
resistor divider that sets the buck regulator output
voltage. Connecting this pin to a separate +2.5V to
+5.5V supply will disable the buck regulator. The FB pin
should not be connected to the +5V LDO to disable the
buck because the +5V LDO starts after the buck in the
internal state machine. The lack of voltage at the FB pin
would cause a buck UVLO fault.
3.25
5V LDO (+5V)
+5-volt Low Dropout (LDO) voltage regulator output.
The +5V LDO may be used to power external devices,
such as Hall-effect sensors or amplifiers. The +5V LDO
is disabled on the MCP8026 when CE = 0. The internal
state machine starts the buck regulator before the +5V
LDO, so the +5V LDO should not be connected to the
buck FB pin to disable the buck regulator. A buck UVLO
fault will occur if the +5V LDO is used to disable the
buck regulator. The LDO requires an output capacitor
for stability. The positive side of the output capacitor
should be physically located as close to the +5V pin as
is practical. For most applications, 4.7 µF of
capacitance will ensure stable operation of the LDO
circuit.
The type of capacitor used can be ceramic, tantalum or
aluminum electrolytic. The low ESR characteristics of
the ceramic will yield better noise and PSRR
performance at high frequency.
3.26
Charge Pump Flying Capacitor
(CAP1, CAP2)
Charge pump flying capacitor connections. Connect
the charge pump capacitor across these two pins. The
charge pump flying capacitor supplies the power for the
12V LDO when the charge pump is active.
3.27
Communications Port (DE2)
Open-drain
communication
node.
The
DE2
communication is a half-duplex, 9600 baud, 8-bit, no
parity communication link. The open-drain DE2 pin
must be pulled high by an external pull-up resistor. The
pin has a minimum drive capability of 1 mA resulting in
a VDE2 of 50 mV when driven low.
The type of capacitor used can be ceramic, tantalum or
aluminum electrolytic. The low ESR characteristics of
the ceramic will yield better noise and PSRR
performance at high frequency.
DS20005339B-page 24
2016 Microchip Technology Inc.
MCP8025/6
4.0
DETAILED DESCRIPTION
4.1
State Diagrams
4.1.1
MCP8025 STATE DIAGRAM
Power-on Reset
All states
Brown-out
LIN wake-up event or
CE wake-up event
Start-up
Sleep
Supply > 6V
Supply < 30V
Temp < 145°C
Digital
configuration
CE = 0
Supply < 30V
Temp < 145°C
ACK
FB>1.1V
BK_OFF
V5>4.5V
and CE=1
V12
enabled
BK_ACK
V12>10.8V
Supply < 5.5V
All states
CE = 1 and time<1ms
CE = 0 and
Supply > 6.0V
V5
enabled
(standby)
ACTIVE
CE = 0 and time>=1 ms and EnableSleep=0
All states
CE = 0 and time>=1 ms and EnableSleep=1
Buck
enabled
Supply > 32V
Temp>170°C
FB<1.0V
CE = 0
CE timeout
Driver over current or
Driver UVLO or
Supply >20V
MTC_FAULT
FIGURE 4-1:
MCP8025 State Diagram.
2016 Microchip Technology Inc.
DS20005339B-page 25
MCP8025/6
4.1.2
MCP8026 STATE DIAGRAM
Power-on Reset
All states
Brown-out
HV_IN1 wake-up event
or CE wake-up event
Start-up
Sleep
Supply > 6V
Supply < 30V
Temp < 145°C
Digital
configuration
CE = 0
Supply < 30V
Temp < 145°C
ACK
HV_IN
ready
(standby)
CE = 0 and
Supply > 6.0V
CE=1
V5
enabled
BK_OFF
V5>4.5V
BK_ACK
V12>10.8V
Supply < 5.5V
All states
CE = 1 and time<1ms
V12
enabled
ACTIVE
FB<1.0V
CE = 0
CE = 0 and time>=1 ms and EnableSleep=0
FB>1.1V
All states
CE = 0 and time>=1 ms and EnableSleep=1
Buck
enabled
Supply > 32V
Temp>170°C
CE timeout
Driver over current or
Driver UVLO
MTC_FAULT
FIGURE 4-2:
DS20005339B-page 26
MCP8026 State Diagram.
2016 Microchip Technology Inc.
MCP8025/6
4.2
Bias Generator
The internal bias generator controls three voltage rails.
Two fixed-output low-dropout linear regulators, an
adjustable buck switch-mode power converter and an
unregulated charge pump are controlled through the
bias generator. In addition, the bias generator performs
supervisory functions.
4.2.1
+12V LOW-DROPOUT LINEAR
REGULATOR (LDO)
The +12V rail is used for bias of the 3-phase power
MOSFET bridge.
The regulator is capable of supplying 30 mA of external
load current. The regulator has a minimum overcurrent
limit of 40 mA.
When operating at a supply voltage (VDD) that is in the
range of +12V to +12.7V, the +12V charge pump will be
off and the +12V source will be the VDD supply voltage.
The +12V output may be lower than +12V while
operating in the VDD range of +12V to +12.7V due to
the dropout voltage of the regulator.
The low-dropout regulators require an output capacitor
connected from VOUT to GND to stabilize the internal
control loop. A minimum of 4.7 µF ceramic output
capacitance is required for the 12V LDO.
4.2.3
BUCK SWITCH MODE POWER
SUPPLY (SMPS)
The SMPS is a high-efficiency, fixed-frequency,
step-down DC-DC converter. The SMPS provides all
the active functions for local DC-DC conversion with
fast transient response and accurate regulation.
During normal operation of the buck power stage, Q1 is
repeatedly switched on and off with the ON and
OFF times governed by the control circuit. This
switching action causes a train of pulses at the LX node
which are filtered by the L/C output filter to produce a
DC output voltage, VO. Figure 4-3 depicts the
functional block diagram of the SMPS.
CURRENT_REF
VIN
+
-
Q1
OUTPUT
CONTROL
LOGIC
VDD-12V
LX
The +12V LDO is disabled when the Chip Enable (CE)
pin is not active.
Table 4-1 shows the faults that will also disable the
+12V LDO.
4.2.2
+5V LOW-DROPOUT LINEAR
REGULATOR (LDO)
+
+
-
BANDGAP
REFERENCE
FB
The +5V LDO is used for bias of an external
microcontroller, the internal current sense amplifier and
the gate control logic.
The +5V LDO is capable of supplying 30 mA of external
load current. The regulator has a minimum overcurrent
limit of 40 mA.
If additional external current is
required, the buck switch-mode power converter
should be utilized.
A minimum of 4.7 µF ceramic output capacitance is
required for the +5V LDO.
The +5V LDO is disabled when the system is in Sleep
mode. The +5V LDO is enabled in the MCP8025 and
disabled in the MCP8026 when in Standby mode.
Table 4-1 shows the faults that will also disable the +5V
LDO.
2016 Microchip Technology Inc.
FIGURE 4-3:
Diagram.
SMPS Functional Block
The SMPS is designed to operate in Discontinuous
Conduction Mode (DCM) with Voltage mode control
and current-limit protection. The SMPS is capable of
supplying 750 mW of power to an external load at a
fixed switching frequency of 460 kHz with an input
voltage of 6V. The output of the SMPS is power-limited.
For a programmed output voltage of 3V, the SMPS will
be capable of supplying 250 mA to an external load. An
external diode is required between the LX pin and
ground. The diode will be required to handle the
inductor current when the switch is off. The diode is
external to the device to reduce substrate currents and
power dissipation caused by the switcher. The external
diode carries the current during the switch-off time,
eliminating the current path back through the device.
DS20005339B-page 27
MCP8025/6
The SMPS enters Pulse Frequency Modulation (PFM)
mode at light loads, improving efficiency at the expense
of higher output voltage ripple. The PFM circuitry
provides a means to disable the SMPS as well. If the
SMPS is not utilized in the application, connecting the
feedback pin (FB) to an external supply (2.5V to 5.5V)
will force the SMPS to a shutdown state.
desirable, the user should add a voltage suppression
device to the VDD input in order to prevent VDD from
rising above AOVLOSTOP.
The Voltage Supervisor is also designed to shut down
the buck regulator when VDD falls below
UVLOBK_STOP.
The maximum inductor value for operation in
Discontinuous Conduction mode can be determined by
using Equation 4-1.
The device will set the BUVLOF bit in the STAT0
register and send a STATUS_0 message to the host
when the buck input voltage drops below
UVLOBK_STOP.
EQUATION 4-1:
Table 4-1 shows the faults that will disable the buck
regulator.
LMAX SIMPLIFIED
VO
VO 1 – -------- T
VIN
L MAX ---------------------------------------------2 I O CRIT
Using the LMAX inductor value calculated using
Equation 4-1 will ensure Discontinuous Conduction
mode operation for output load currents below the
critical current level, IO(CRIT). For example, with an
output voltage of +5V, a standard inductor value of
4.7 µH will ensure Discontinuous Conduction mode
operation with an input voltage of 6V, a switching
frequency of 468 kHz and a critical load current of
150 mA.
The output voltage is set by using a resistor divider
network. The resistor divider is connected between the
inductor output and ground. The divider common point
is connected to the FB pin which is then compared to
an internal 1.25V reference voltage.
The buck regulator will set the BIOCPW bit in the
STAT0 register and send a STATUS_0 message to the
host whenever the input switching current exceeds
2.5A peak (typical). The bit will be cleared when the
peak input switching current drops back below the 2.5A
(typical) limit. This is a warning bit only, no action is
taken to shut down the buck operation. The overcurrent
limit will shorten the buck duty cycle and therefore limit
the maximum power out of the buck regulator.
The buck regulator will set the BUVLOW bit in the
STAT0 register and send a STATUS_0 message to the
host whenever the output voltage drops below 90% of
the rated output voltage. The bit will be cleared when
the output voltage returns to 94% of the rated value.
If the buck regulator output voltage falls below 80% of
rated output voltage, the device will shut down with a
Buck Undervoltage Lockout Fault. The BUVLOF bit in
the STAT0 register will be set and a STATUS_0
message will be sent to the host. The ILIMIT_OUT
signal will transition low to indicate the fault.
The Voltage Supervisor is designed to shut down the
buck regulator when VDD rises above AOVLOSTOP.
When shutting down the buck regulator is not
DS20005339B-page 28
4.2.4
CHARGE PUMP
An unregulated charge pump is utilized to boost the
input to the +12V LDO during low input conditions.
When the input bias to the device (VDD) drops below
CPSTART, the charge pump is activated. When
activated, 2 x VDD is presented to the input of the
+12V LDO, which maintains a minimum of +10V at its
output.
The typical charge pump flying capacitor is a 0.1 µF to
1.0 µF ceramic capacitor.
4.2.5
SUPERVISOR
The bias generator incorporates a voltage supervisor
and a temperature supervisor.
4.2.5.1
Brownout – Configuration Lost
When the device first powers up or when VDD drops
below 3.8V, the brown-out reset warning flag bit
(BORW) in the STAT1 register will be set. The bit is only
a warning indicating that the contents of the configuration registers may have been compromised by a low
supply voltage condition. The host processor should
send new configuration information to the device.
4.2.5.2
Voltage Supervisor
The voltage supervisor protects the device, the
external power MOSFETs and the external
microcontroller from damage caused by overvoltage or
undervoltage of the input supply, VDD.
In the event of an undervoltage condition
(VDD < +5.5V) or an overvoltage condition of the
MCP8025 device (VDD > +20V), the motor drivers are
switched off. The bias generator, the communication
port and the remainder of the motor control unit remain
active. The failure state is flagged on the DE2 pin with
a status message. In extreme overvoltage conditions
(VDD > +32V), all functions are turned off.
In the event of a severe undervoltage condition
(VDD < +4.0V), the buck regulator will be disabled. If
the set point of the buck regulator output voltage is
above the buck undervoltage lockout value, the buck
output voltage will decrease as VDD decreases.
2016 Microchip Technology Inc.
MCP8025/6
4.2.5.3
Temperature Supervisor
An integrated temperature sensor self-protects the
device circuitry. If the temperature rises above the
overtemperature shutdown threshold, all functions are
turned off. Active operation resumes when the
temperature has cooled down below a set hysteresis
value and the fault has been cleared by toggling CE.
It is desirable to signal the microcontroller with a
warning message before the overtemperature
threshold is reached. When the Thermal Warning
4.2.5.4
Internal Function Block Status
Table 4-1 shows the effects of the CE pin, the faults and
the SLEEP bit upon the functional status of the internal
blocks of the MCP8025/6.
Conditions
Buck
LIN, HV_IN1, HV_IN2
12V LDO
Motor Drivers
DE2
Internal
UVLO, OVLO, OTP
INTERNAL FUNCTION BLOCK STATUS
5V LDO
TABLE 4-1:
Temperature set point is exceeded, a warning message
will be sent to the host microcontroller. The
microcontroller should take appropriate actions to
reduce the temperature rise. The method to signal the
microcontroller is through the DE2 pin.
Sleep
CE = 0, SLEEP = 1
—
—
W
—
—
—
—
Standby
(MCP8025)
CE = 0
SLEEP = 0
A
A
R
—
—
A
A
Standby
(MCP8026)
CE = 0
SLEEP = 0
—
A
A
—
—
A
A
System State
Fault
CE = 1, ILIMIT_OUT = 1
A
A
A
A
A
A
A
Driver OTP
TJ > 160°C
—
—
—
—
—
A
A
Operating
Faults
CE = 1
ILIMIT_OUT = 0
Warnings
CE = 1
ILIMIT_OUT = 1
VDD UVLO
VIN 5.5V
—
A
—
—
—
A
A
Buck Input UVLO
VIN 4V
—
—
—
—
—
A
A
Buck Output Brownout
VBUCK < 80% (Brownout)
—
A
—
—
—
A
A
5V LDO UVLO
VOUT5 4V
A
A
R
A
—
A
A
Driver OVLO (MCP8025)
VIN 20V
A
A
A
A
—
A
A
System OVLO
VIN 32V
—
—
—
—
—
A
A
MOSFET UVLO
VHS[A:C] < 8V, VLS[A:C] < 8V
A
A
A
A
—
A
A
MOSFET OCP
VDrain-Source > EXTOC<1:0> setting
A
A
A
A
—
A
A
Buck OCP
IBUCK Input > 2.5A Peak
A
A
A
A
A
A
A
Buck Output
Undervoltage
VBUCK < 90%
A
A
A
A
A
A
A
Driver Temperature
TJ > 72% TSD_MIN
(115°C for 160°C Driver OTP)
A
A
A
A
A
A
A
Config Lost (BORW)
Set at initial power-up
or when VDD < UVLOBK_STOP
A
A
A
A
A
A
A
Legend: “A” = ACTIVE (ON), “—” = INACTIVE (OFF), “W” = WAKEUP (from Sleep), “R” = RECEIVER ONLY
OCP = Overcurrent Protection
OTP = Overtemperature Protection
UVLO = Undervoltage Lockout
OVLO = Overvoltage Lockout
2016 Microchip Technology Inc.
DS20005339B-page 29
MCP8025/6
4.3
Motor Control Unit
The motor control unit is comprised of the following:
• External drive for a 3-phase bridge with
NMOS/NMOS MOSFET pairs
• Back EMF sampler with phase multiplexer and
neutral simulator (MCP8025)
• Motor current sense amplifier and comparator
• Two additional current sense amplifiers
(MCP8026)
4.3.1
MOTOR CURRENT SENSE
CIRCUITRY
The internal motor current sense circuitry consists of an
operational amplifier and a comparator. The amplifier
output is presented to the inverting comparator input
and as an output to the microcontroller. The
non-inverting comparator input is connected to an
internally programmable 8-bit DAC. A selectable motor
current limit threshold may be set with a SET_ILIMIT
message from the host to the MCP8025/6 via the DE2
communication link. The DACREF<7:0> bits in the
CFG1 register contain the DAC current reference
value. The dual-purpose ILIMIT_OUT pin handles the
current limit output as well as system fault outputs. The
8-bit DAC is powered by the 5V supply. The DAC
output voltage ranges from 0.991V to 4.503V. The DAC
has a bit value of (4.503V – 0.991V)/(28 – 1) = 13.77 mV/bit.
A DAC input of 00H yields a DAC output voltage of
0.991V. The default power-up DAC value is 40H
(1.872V). The DAC uses a 100 kHz filter. Input code
to output voltage delay is approximately five time
constants 50 µs. The desired current sense gain is
established with an external resistor network.
Note:
The motor current limit comparator output
is internally ‘OR’d with the DRIVER
FAULT output of the driver logic block.
The microcontroller should monitor the
comparator output and take appropriate
actions. The motor current limit
comparator circuitry does not disable the
motor drivers when an overcurrent
situation occurs. Only one current limit
comparator is provided. The MCP8026
provides three current sense amplifiers
which can be used for implementation of
advanced control algorithms, such as
Field-Oriented Control (FOC).
The comparator output may be employed as a current
limit. Alternatively, the current sense output can be
employed in a chop-chop PWM speed loop for any
situations where the motor is being accelerated, either
positively or negatively. An analog chop-chop speed
loop can be implemented by hysteretic control or fixed
off-time of the motor current. This makes for a very
robust controller, as the motor current is always in
instantaneous control.
DS20005339B-page 30
A sense resistor in series with the bridge ground return
provides a current signal for both feedback and current
limiting. This resistor should be non-inductive to
minimize ringing from high di/dt. Any inductance in the
power circuit represents potential problems in the form
of additional voltage stress and ringing, as well as
increasing switching times. While impractical to
eliminate, careful layout and bypassing will minimize
these effects. The output stage should be as compact
as heat sinking will allow, with wide, short traces
carrying all pulsed currents. Each half-bridge should be
separately bypassed with a low ESR/ESL capacitor,
decoupling it from the rest of the circuit. Some layouts
will allow the input filter capacitor to be split into three
smaller values and serve double duty as the half-bridge
bypass capacitors.
Note:
With a chop-chop control, motor current
always flows through the sense resistor.
When the PWM is off, however, the
flyback diodes or synchronous rectifiers
conduct, causing the current to reverse
polarity through the sense resistor.
The current sense resistor is chosen to establish the
peak current limit threshold, which is typically set 20%
higher than the maximum current command level to
provide overcurrent protection during abnormal
conditions. Under normal circumstances with a
properly compensated current loop, peak current limit
will not be exercised.
The current sense operational amplifier is disabled
when CE = 0.
4.3.2
BACK EMF SAMPLER WITH PHASE
MULTIPLEXER AND NEUTRAL
SIMULATOR (MCP8025)
The commutation loop of a BLDC motor control is a
phase lock loop (PLL) that locks to the rotor’s position.
Note that this inner loop does not attempt to modify the
position of the rotor, but modifies the commutation
times to match whatever position the rotor has. An
outer speed loop changes the rotor velocity, and the
commutation loop locks to the rotor’s position to
commutate the phases at the correct times.
The Back EMF sensor consists of the motor, a
Back EMF sampler, a phase multiplexer and a neutral
simulator.
The Back EMF sampler takes the motor phase
voltages and calculates the neutral point of the motor
by using Equation 4-2.
EQUATION 4-2:
NEUTRAL POINT
A + B + C
NEUTRAL = ---------------------------------------3
2016 Microchip Technology Inc.
MCP8025/6
This allows the microcontroller to compare the
Back EMF signal to the motor’s neutral point without
the need to bring out an extra wire on a WYE wound
motor. For DELTA wound motors, there is no physical
neutral to bring out, so this reference point must be
calculated in any case.
The Back EMF sampler measures the motor phase that
is not driven, i.e. if LSA and HSB are ON, then phase A
is driven low, phase B is driven high and phase C is
sampled. The sampled phase provides a Back EMF
signal that is compared against the neutral of the motor.
The sampler is controlled by the microcontroller via the
MUX1 and MUX2 input signals.
When the BEMF signal crosses the neutral point, the
zero-crossing detector will switch the ZC_OUT signal.
The host controller may use this signal as a
30 degrees-before-commutation reference point. The
host controller must commutate the system after
30 degrees of electrical rotation have occurred.
Different motor control scenarios may increase or
decrease the commutation point by a few degrees.
Internal filtering capacitors are connected after the
phase voltage dividers to help eliminate transients
during the zero-crossing detection.
TABLE 4-2:
PHASE SAMPLER
MUX
Phase Sampled
4.3.3.1
Sensorless Motor Control
Many control algorithms can be implemented with the
MCP8025/6 in conjunction with a microcontroller. The
following discussion provides a starting point for
implementing the MCP8025 or MCP8026 in a
sensorless control application of a 3-phase motor. The
motor is driven by energizing two windings at a time
and
sequencing
the
windings
in
a
six-step-per-electrical-revolution method. This method
leaves one winding unenergized at all times and the
voltage (Back EMF or BEMF) on that unenergized
winding can be monitored to determine the rotor
position.
4.3.3.2
Start-Up Sequence
When the motor being driven is at rest, the BEMF
voltage is equal to zero. The motor needs to be rotating
for the BEMF sensor to lock onto the rotor position and
commutate the motor. The recommended start-up
sequence is to bring the rotor from rest up to a speed
fast enough to allow BEMF sensing. Motor operation is
comprised of five modes: Disabled mode, Bootstrap
mode, Lock or Align mode, Ramp mode and Run
mode. Refer to the commutation state machine in
Table 4-3. The order in which the microcontroller steps
through the commutation state machine determines the
direction the motor rotates.
Disabled Mode (CE = 0)
MUX2
MUX1
0
0
PHASE A
0
1
PHASE B
1
0
PHASE C
Bootstrap Mode
1
1
PHASE C
The high-side driver obtains the high-side biasing
voltage from the +12V LDO, the bootstrap diode and
the bootstrap capacitor. The bootstrap capacitors must
first be charged before the high-side drives may be
used. The bootstrap capacitors are all charged by
activating all three low-side drivers. The active low-side
drivers pull their respective phase nodes low, charging
the bootstrap capacitors to the +12V LDO voltage. The
three low-side drivers should be active for at least
1.2 ms per 1 µF of bootstrap capacitance. This
assumes a +12V voltage change and 30 mA (10 mA
per phase) of current coming from the +12V LDO.
The neutral simulator may be disabled when access to
the motor winding neutral point is available. When
disabling the neutral simulator, the motor neutral is
connected directly to the COMP_REF pin. The actual
motor neutral is then used for zero-crossing detection.
The neutral simulator may be disabled via DE2
communications.
4.3.3
MOTOR CONTROL
The commutation loop of a BLDC motor control is a
phase lock loop (PLL) which locks to the rotor’s
position. Note that this inner loop does not attempt to
modify the position of the rotor, but modifies the
commutation times to match whatever position the
rotor has. An outer speed loop changes the rotor
velocity and the commutation loop locks to the rotor’s
position to commutate the phases at the correct times.
2016 Microchip Technology Inc.
When the driver is disabled (CE = 0), all of the
MOSFET driver outputs are set low.
Lock Mode
Before the motor can be started, the rotor should be in
a known position. In Lock mode, the microcontroller
drives phase B low and phases A and C high. This
aligns the rotor 30 electrical degrees before the center
of the first commutation state. Lock mode must last
long enough to allow the motor and its load to settle into
this position.
DS20005339B-page 31
MCP8025/6
Ramp Mode
Run Mode
At the end of the Lock mode, Ramp mode is entered. In
Ramp mode, the microcontroller steps through the
commutation state machine, increasing linearly, until a
minimum speed is reached. Ramp mode is an
open-loop commutation. No knowledge of the rotor
position is used.
At the end of Ramp mode, Run mode is entered. In Run
mode, the Back EMF sensor is enabled and
commutation is now under the control of the phase lock
loop. Motor speed can be regulated by an outer speed
control loop.
TABLE 4-3:
COMMUTATION STATE MACHINE
Outputs
HSA
HSB
HSC
LSA
LSB
LSC
BEMF
Phase
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
ON
ON
OFF
OFF
ON
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
ON
ON
OFF
ON
OFF
ON
ON
OFF
OFF
OFF
OFF
N/A
N/A
N/A
Phase B
Phase A
Phase C
Phase B
Phase A
Phase C
State
CE = 0
BOOTSTRAP
LOCK
1
2
3
4
5
6
4.3.3.3
PWM Speed Control
The inner commutation loop is a phase-lock loop,
which locks to the rotor’s position. This inner loop does
not attempt to modify the position of the rotor, but
modifies the commutation times to match whatever
position the rotor has. The outer speed loop changes
the rotor velocity and the inner commutation loop locks
to the rotor’s position to commutate the phase at the
correct times.
The outer speed loop pulse-width modulates the motor
drive inverter to produce the desired wave shape and
voltage at the motor. The inductance of the motor then
integrates this pulse-width modulation (PWM) pattern
to produce the desired average current, thus controlling
the desired torque and speed of the motor. For a
trapezoidal BLDC motor drive with six-step
commutation, the PWM is used to generate the
average voltage to produce the desired motor current
and motor speed.
There are two basic methods to pulse-width modulate
the inverter switches. The first method returns the
reactive energy in the motor inductance to the source
by reversing the voltage on the motor winding during
the current decay period. This method is referred to as
fast decay or chop-chop. The second method
circulates the reactive current in the motor with minimal
voltage applied to the inductance. This method is
referred to as slow decay or chop-coast.
DS20005339B-page 32
The preferred control method employs a chop-chop
PWM for any situation where the motor is being
accelerated, either positively or negatively. For
improved efficiency, chop-coast PWM is employed
during steady-state conditions. The chop-chop speed
loop is implemented by hysteretic control, fixed off-time
control or average current mode control of the motor
current. This makes for a very robust controller, as the
motor current is always in instantaneous control.
The motor speed presented to the chop-chop loop is
reduced by approximately 9%. A fixed-frequency PWM
that only modulates the high-side switches implements
the chop-coast loop. The chop-coast loop is presented
with the full motor speed, so, if it is able to control the
speed, the chop-chop loop will never be satisfied and
will remain saturated. The chop-chop remains able to
assume full control if the motor torque is exceeded,
either through a load change or a change in speed that
produces acceleration torque. The chop-coast loop will
remain saturated, with the chop-chop loop in full
control, during start-up and acceleration to full speed.
The bandwidth of the chop-coast loop is set to be
slower than the chop-chop loop so that any transients
will be handled by the chop-chop loop and the
chop-coast loop will only be active in steady-state
operation.
2016 Microchip Technology Inc.
MCP8025/6
4.3.4
EXTERNAL DRIVE FOR A 3-PHASE
BRIDGE WITH NMOS/NMOS
MOSFET PAIRS
Each motor phase is driven with external
NMOS/NMOS MOSFET pairs. These are controlled by
a low-side and a high-side gate driver. The gate drivers
are controlled directly by the digital input pins
PWM[1:3]H/L. A logic high turns the associated gate
driver ON and a logic low turns the associated gate
driver OFF. The PWM[1:3]H/L digital inputs are
equipped with internal pull-down resistors.
The low-side gate drivers are biased by the +12V LDO
output, referenced to ground. The high-side gate
drivers are a floating drive biased by a bootstrap
capacitor circuit. The bootstrap capacitor is charged by
the +12V LDO whenever the accompanying low-side
MOSFET is turned on.
The high-side and low-side driver outputs all go to a low
state whenever there is a fault or when CE = 0,
regardless of the PWM[1:3]H/L inputs.
4.3.4.1
MOSFET Driver Undervoltage Lockout
(UVLO)
The MOSFET UVLO fault detection monitors the
available voltage used to drive the external MOSFET
gates. The fault detection is only active while the driver
is actively driving the external MOSFET gate. Anytime
the driver bias voltage is below the Driver Undervoltage
Lockout (DUVLO) threshold for a period longer than the
one specified by the tDUVLO parameter, the driver will
not turn on when commanded ON. A driver fault will be
indicated to the host microcontroller on the
ILIMIT_OUT open-drain output pin and also via a DE2
communication STATUS_1 message. This is a latched
fault. Clearing the fault requires either removal of
device power or disabling and re-enabling the device
via the device enable input (CE). The EXTUVLO bit in
the CFG0 register is used to enable or disable the
Driver Undervoltage Lockout feature. This protection
feature prevents the external MOSFETs from being
controlled with a gate voltage not suitable to fully
enhance the device.
2016 Microchip Technology Inc.
External MOSFET Short-Circuit Current
Short-circuit protection monitors the voltage across the
external MOSFETs during an ON condition. The
high-side driver voltage is measured from VDD to
PH[1:3]. The low-side driver voltage is measured from
PH[1:3] to PGND. If the voltage rises above a
user-configurable threshold after the external MOSFET
gate voltage has been driven high, all drivers will be
turned OFF. A driver fault will be indicated to the host
microcontroller on the open-drain ILIMIT_OUT output
pin and also via a DE2 communication STATUS_1
message. This is a latched fault. Clearing the fault
requires either removal of device power or disabling
and re-enabling the device via the device enable input
(CE). This protection feature helps detect internal
motor failures such as winding to case shorts.
Note:
MOSFET Driver External Protection
Features
Each driver is equipped with Undervoltage Lockout
(UVLO) and short-circuit protection features.
4.3.4.1.1
4.3.4.1.2
The driver short-circuit protection is
dependent on application parameters. A
configuration message is provided for a
set number of threshold levels. The
MOSFET Driver UVLO and short-circuit
protection features have the option to be
disabled.
The short-circuit voltage may be set via a DE2
SET_CFG_0 message. The EXTOC<1:0> bits in the
CFG0 register are used to select the voltage level for
the short-circuit comparison. If the voltage across the
MOSFET drain-source terminals exceeds the selected
voltage level when the MOSFET is active, a fault will be
triggered. The selectable voltage levels are 250 mV,
500 mV, 750 mV and 1000 mV. The EXTSC bit in the
CFG0 register is used to enable or disable the
MOSFET driver short-circuit detection.
4.3.4.1.3
Fault Pin Output (ILIMIT_OUT)
The dual-purpose ILIMIT_OUT pin is used as a fault
indicator and as an overcurrent indicator when used
with the internal DAC. The pin is capable of sinking a
minimum of 1 mA of current while maintaining less than
50 mV of voltage across the output. An external pull-up
resistor to the logic supply is required.
The open-drain ILIMIT_OUT pin transitions low when a
fault occurs. Table 4-4 lists the faults that activate the
ILIMIT_OUT signal. Warnings do not activate the
ILIMIT_OUT signal. Table 4-5 lists the warnings.
DS20005339B-page 33
MCP8025/6
TABLE 4-4:
ILIMIT_OUT FAULTS
Fault
DE2 Register
Overtemperature
0x85 0x02
Device Input Undervoltage
0x85 0x04
Driver Input Overvoltage
0x85 0x08
Device Input Overvoltage
0x85 0x10
Buck Regulator Output Undervoltage
0x85 0x80
External MOSFET Undervoltage
Lockout
0x86 0x04
External MOSFET Overcurrent
Detection
0x86 0x08
5V LDO Undervoltage Lockout
0x86 0x20
TABLE 4-5:
WARNINGS
Fault
DE2 Register
Temperature Warning
0x85 0x01
Buck Regulator Overcurrent
0x85 0x20
Buck Regulator Undervoltage
0x85 0x40
Brownout – Configuration Lost
0x86 0x10
4.3.4.2
Gate Control Logic
The gate control logic provides level shifting of the
digital inputs, polarity control and cross conduction
protection.
4.3.4.2.1 Cross Conduction Protection
Logic prevents switching on one power MOSFET while
the opposite one in the same half-bridge is already
switched on. If both MOSFETs in the same half-bridge
are commanded ON simultaneously by the digital
inputs, both will be turned off.
4.3.4.2.2 Programmable Dead Time
The gate control logic employs a break-before-make
dead-time delay that is programmable. A configuration
message is provided to configure the driver dead time.
The programmable dead times range from 250 ns to
2000 ns (default) in 250 ns increments. The dead time
allows the PWM inputs to be direct inversions of each
other and still allow proper motor operation. The dead
time internally modifies the PWMH/L gate drive timing
to prevent cross conduction. The DRVDT<2:0> bits in
the CFG2 register are used to set the dead time value.
DS20005339B-page 34
4.3.4.2.3 Programmable Blanking Time
A configuration message is provided to configure the
driver current limit blanking time. The blanking time
allows the system to ignore any current spikes that may
occur when switching the driver outputs. The allowable
blanking times are 500 ns, 1 µs, 2 µs and 4 µs
(default). The blanking time will start after the
dead-time circuitry has timed out. The DRVBT<1:0>
bits in the CFG2 register are used to set the blanking
time value.
The blanking time affects the driver undervoltage
lockout. The driver undervoltage lockout latches the
external MOSFET undervoltage lockout fault if the
undervoltage condition lasts longer than the time
specified by the tDUVLO parameter. The tDUVLO
parameter takes into account the blanking time if
blanking is in progress.
4.4
Chip Enable (CE)
The Chip Enable (CE) pin allows the device to be
disabled by external control. The Chip Enable pin has
four modes of operation.
4.4.1
FAULT CLEARING STATE
The CE pin is used to clear any faults and re-enable the
driver. After toggling the CE pin low to high, the system
requires a minimum time period to re-enable and start
up all the driver blocks. The start-up time is
approximately 35 μs. The maximum pulse time for the
high-low-high transition to clear faults should be less
than 1 ms. If the high-low-high transition is longer than
1 ms, the device will start up from the Standby state.
Any fault status bits that are set will be cleared by the
low-to-high transition of the CE pin if, and only if, the
fault condition has ceased to exist. If the fault condition
still exists, the active fault status bit will remain active.
No additional fault messages will be sent for a fault that
remains active.
4.4.2
WAKE FROM SLEEP MODE
The CE pin is also used to awaken the device from the
Sleep mode state. To wake the device from a Sleep
mode state, the CE pin must be set low for a minimum
of 250 μs. The device will then wake up with the next
rising edge of the CE pin.
The LIN bus may be used to wake the device from the
Sleep mode state. When a LIN wake-up event is
detected on the LIN_BUS pin, the device will wake up.
The MCP8025 will wake up on the rising edge of the
bus after detecting a dominate state lasting > 150 µs
on the bus. The LIN Bus master must provide the
dominate state for > 250 µs to meet the LIN 2.2A
specifications.
2016 Microchip Technology Inc.
MCP8025/6
The HV_IN1 pin may be used to wake the device from
the Sleep mode state. The MCP8026 will wake up on
the rising edge of the pin after detecting a low state
lasting > 250 µs on the pin.
4.4.3
STANDBY STATE
Standby state is entered when the CE pin goes low for
longer than 1 ms and the Sleep configuration bit is
inactive. When Standby mode is entered, the following
subsystems are disabled:
• high-side gate drives (HSA, HSB, HSC), forced
low
• low-side gate drives (LSA, LSB, LSC), forced low
• +12V LDO
• +5V LDO (MCP8026)
• the 30 k pull-up resistor connected to the level
translator is switched out of the circuit to minimize
current consumption (configurable) (MCP8026)
• the 30 k pull-up resistor connected to the LIN
Bus is switched out of the circuit to minimize
current consumption (configurable) (MCP8025)
The buck regulator stays enabled. The DE2
communication port remains active but the port may
only respond to commands. When CE is inactive, the
DE2 port is prevented from initiating communications in
order to conserve power.
The total current consumption of the device when CE is
inactive (device disabled) stays within the Standby
mode input quiescent current limits specified in the
AC/DC Characteristics table.
4.4.4
SLEEP MODE
Sleep mode is entered when both a SLEEP command
is sent to the device via DE2 communication and the
CE pin is low. The two conditions may occur in any
order. The transition to Sleep mode occurs after the last
of the two conditions occurs and the tSLEEP delay time
has elapsed. The SLEEP bit in the CFG0 configuration
register indicates when the device should transition to
a low-power mode. The device will operate normally
until the CE pin is transitioned low by an external
device. At that point in time, the SLEEP bit value
determines whether the device transitions to Standby
mode or low-power Sleep mode. The quiescent current
during Sleep mode will typically be 5 μA. When Sleep
mode is activated, most functions will be shut off,
including the buck regulator. Only the power-on reset
monitor, the voltage translators and the minimal state
machine will remain active to detect a wake-up event.
This indicates that the host processor will be shut down
if the host is using the buck regulator for power. The
device will stay in the low-power Sleep mode until
either of the following conditions is met:
• The HV_IN1 pin transitions high after being in a
low state lasting longer than 250 µs. (MCP8026)
The MCP8025/6 devices are not required to retain
configuration data while in Sleep mode. Sleep mode
will set the BORW bit. When exiting Sleep mode, the
host should send a new configuration message to
configure the device if the default configuration values
are not desired. The same configuration sequence
used during power-up may be used when exiting Sleep
mode. Sleep mode will not be entered if there is a fault
active that will affect the buck regulator output voltage.
This prevents a transition to Sleep mode when the host
is powered by the buck regulator and the regulator is in
an unreliable state.
4.5
Communication Ports
The communication ports provide a means of
communicating to the host system.
4.5.1
LIN BUS TRANSCEIVER (MCP8025)
The MCP8025 provides a physical interface between a
microcontroller and a LIN half-duplex bus. It is intended
for automotive and industrial applications with serial
bus speeds up to 20 kilobaud. The MCP8025 provides
a half-duplex, bidirectional communication interface
between a microcontroller and the serial network bus.
This device will translate the CMOS/TTL logic levels to
LIN level logic and vice versa.
The LIN Bus transceiver circuit provides a LIN
Bus-compliant interface between the LIN Bus and a
LIN-capable UART on an external microcontroller. The
LIN Bus transceiver is load dump protected and
conforms to LIN 2.1.
4.5.1.1
LIN Wake-Up
A LIN wake-up event may be used to wake up the
MCP8025 from Sleep mode. The MCP8025 will wake
up on the rising edge of the LIN bus after detecting a
dominate state lasting > 150 µs on the LIN_BUS pin.
The LIN Bus master must provide the dominate state
for > 250 µs to meet the LIN 2.2A and SAE J2602.
4.5.1.2
FAULT/TXE (MCP8025)
The FAULT/TXE pin is a bidirectional open-drain output
pin. The state of the pin is defined in Table 4-6.
Whenever the FAULT/TXE signal is low, the LIN
transmitter is OFF. The transmitter may be re-enabled
whenever the FAULT/TXE signal returns high, either by
removing the internal fault condition or by the host
returning the FAULT/TXE high.
The FAULT/TXE will go low when there is a mismatch
between the TX input and the LIN_BUS level. This may
be used to detect a bus contention.
• The CE pin is toggled low for a minimum of
250 μs and then transitioned high.
• The LIN_BUS pin receives a LIN wake-up event.
The wake-up event must last at least 250 µs, per
LIN Standard 2.2A. (MCP8025)
2016 Microchip Technology Inc.
DS20005339B-page 35
MCP8025/6
4.5.1.3
The FAULT/TXE pin will go low whenever the internal
circuits have detected a short circuit and have disabled
the LIN_BUS output driver. The MCP8025 limits the
transmitter current to less than 200 mA when a short
circuit is detected. If the host MCU is driving the
FAULT/TXE pin high, then the transmitter will remain
enabled and the fault condition will be overruled. If the
host MCU is driving the pin low or is in High Z mode,
the MCP8025 will drive the pin low and will disable the
LIN transmitter.
TABLE 4-6:
LIN Dominant State Timeout
The MCP8025 has an additional LIN feature, LIN
Dominant State Timeout, that is not in the current LIN
2.0 specification. If the LIN TX pin is externally held low
for more than the time specified by tDOM_TOUT, the
MCP8025 will disable the LIN transmitter. The
FAULT/TXE pin will go low, indicating a LIN Dominant
State Timeout fault. Forcing the FAULT/TXE pin high
will not re-enable the transmitter. The transmitter will
stay disabled until the TX pin is set high again. This
prevents the LIN transceiver from inadvertently locking
up the bus.
FAULT/TXE TRUTH TABLE
FAULT/TXE
TX
In
RX
Out
LIN_BUS
I/O
L
H
L
Definition
External
Input
Driven
Output
VDD
High Z
L
FAULT, TX driven low, LIN_BUS shorted to VDD (Note 1)
H
VDD
H
L
FAULT, Overridden by CPU driving FAULT/TXE high
H
H
VDD
High Z, H
H
OK
H
L
GND
High Z, H
H
OK, data is being received from the LIN_Bus
L
L
GND
High Z, H
H
OK
L
L
GND VDD
High Z, H
L
FAULT, if TX is low longer than tDOM_TOUT
x
x
VDD
L
x
NO FAULT, the CPU is commanding the transceiver to
turn off the transmitter driver
Legend: x = don’t care
Note 1: The FAULT/TXE is valid approximately 25 µs after the TXD falling edge. This helps eliminate false fault
reporting during bus propagation delays.
4.5.2
LEVEL TRANSLATOR (MCP8026)
The level translators are an interface between the
companion microcontroller’s logic levels and the input
voltage levels from the system. Automotive
applications typically drive the inputs from the Engine
Control Unit (ECU) and the ignition key on/off signals.
The level translators are unidirectional translators.
Signals on the high-voltage input are translated to
low-voltage signals on the low-voltage outputs. The
high-voltage HV_IN[1:2] inputs have a configurable
30 k pull up. The pull up is configured via a
SET_CFG_0 message. The PU30K bit in the
CFG0 register controls the state of the pull up. The bit
may only be changed when the CE pin is low. The
low-voltage LV_OUT[1:2] outputs are open-drain
outputs. The outputs are capable of sinking a minimum
of 1 mA of current while maintaining less than 50 mV at
the output.
Note:
The TQFP package has two level
translators. The second level translator
typically interfaces to an ignition key on/off
signal.
The HV_IN1 translator is also used to wake up the
device from the Sleep mode whenever the HV_IN1
input is transitioned to a low level for a minimum of
250 µs followed by a transition to the high voltage level.
DS20005339B-page 36
2016 Microchip Technology Inc.
MCP8025/6
4.5.3
DE2 COMMUNICATIONS PORT
A half-duplex 9600 baud UART interface is available to
communicate with an external host. The port is used to
configure the MCP8025/6 and also for status and fault
messages. The DE2 communication port is described
in detail in Section 4.5.3.1 “Communication
Interface”.
4.5.3.1
Communication Interface
A single-wire, half-duplex, 9600 baud, 8-bit
bidirectional communication interface is implemented
using the open-drain DE2 pin. The interface consists of
eight data bits, one Stop bit and one Start bit. The
implementation of the interface is described in the
following sections.
The DE2 interface is an open-drain interface. The
open-drain output is capable of sinking a minimum of
1 mA of current while maintaining less than 50 mV at
the output.
A 5 k resistor should typically be used between the
host transmit pin and the MCP8025/6 DE2 pin to allow
the MCP8025/6 to drive the DE2 line when the host TX
pin is at an idle high level.
The DE2 communication is active when CE = 0 with
the constraint that the MCP8025/6 devices will not
initiate any messages. The host processor may initiate
messages regardless of the state of the CE pin when
the device is not in Sleep mode. The MCP8025/6
devices will respond to host commands when the CE
pin is low. The time from receiving the last bit of a
command message to sending the first bit of the
response message ranges from DE2RSP to DE2WAIT
corresponding to 0 µs to 3.125 ms.
4.5.3.2
4.5.3.3
Packet Timing
While no data is being transmitted, a logic ‘1’ must be
placed on the open-drain DE2 line by an external
pull-up resistor. A data packet is composed of one Start
bit, which is always a logic ‘0’, followed by eight data
bits and a Stop bit. The Stop bit must always be a logic
‘1’. It takes 10 bits to transmit a byte of data.
The device detects the Start bit by detecting the
transition from logic ‘1’ to logic ‘0’ (note that, while the
data line is idle, the logic level is high). Once the Start
bit is detected, the next data bit’s “center” can be
assured to be 24 ticks minus 2 (worst-case
synchronizer uncertainty) later. From then on, every
next data bit center is 16 clock ticks later. Figure 4-5
illustrates this point.
4.5.3.4
Message Handling
The driver will not transition to Standby mode or Sleep
mode while a message is being received. If a DE2
message is being received or transmitted while the
driver is transitioning from Operational mode to either
Sleep mode (tSLEEP) or Standby mode (tSTANDBY), the
driver will wait until the ongoing message is completed
before changing modes.
Packet Format
Every internal status change will provide a
communication to the microcontroller. The interface
uses a standard UART baud rate of 9600 bits per
second.
In the DE2 protocol, the transmitter and the receiver do
not share a clock signal. A clock signal does not
emanate from one transmitter to the other receiver.
Due to this reason, the protocol is asynchronous. The
protocol uses only one line to communicate, so the
transmit/receive packet must be done in Half-Duplex
mode. A new transmit message is allowed only when a
complete packet has been transmitted.
The host must listen to the DE2 line in order to check
for contentions. In case of contention, the host must
release the line and wait for at least three packet-length
times before initiating a new transfer.
Figure 4-4 illustrates a basic DE2 data packet.
2016 Microchip Technology Inc.
DS20005339B-page 37
MCP8025/6
Message Format
DE2
START
FIGURE 4-4:
B0
B1
B2
B3
B4
B6
B5
B7
STOP
DE2 Packet Format.
Detect start bit by sensing
transition from logic 1 to logic 0
T = 1/Baud Rate (bit-cell period)
T
START
TSTART
B0
B1
B2
B3
B4
B5
B6
B7
STOP
TS
TS = T/16 (oversampled bit-cell period)
Receiver samples the incoming data
using x16 baud rate clock
TSTART = 1.5T – uncertainty on start
worst case: 2x TS)
Detection (worse
FIGURE 4-5:
4.5.4
DE2 Packet Timing.
MESSAGING INTERFACE
A command byte will always have the most significant
bit 7 (MSb) set to ‘1’. Bits 6 and 5 are reserved for future
use and should be set to ‘0’. Bits 4–0 are used for
commands. That allows for 32 possible commands.
4.5.4.1
Sample incoming data
at the bit-cell center
Host to MCP8025/6
Messages sent from the host to the MCP8025/6
devices consist of either one or two eight-bit bytes. The
first byte transmitted is the command byte. The second
byte transmitted, if required, is the data for the
command.
4.5.4.2
MCP8025/6 to Host
A solicited response byte from the MCP8025/6 devices
will always echo the command byte with bit 7 set to ‘0’
(Response) and with bit 6 set to ‘1’ for ‘Acknowledged’
(ACK) or ‘0’ for ‘Not Acknowledged’ (NACK). The
second byte, if required, will be the data for the host
command. Any command that causes an error or is not
supported will receive a NACK response.
The MCP8025/6 devices may send unsolicited
command messages to the host controller. No
message to the host controller requires a response
from the host controller.
If a multi-byte command is sent to the MCP8025/6
devices and no second byte is received by the
MCP8025/6 devices, then a ‘Not Acknowledged’
(NACK) message will be sent back to the host after a
5 ms time-out period.
DS20005339B-page 38
2016 Microchip Technology Inc.
MCP8025/6
4.5.5
4.5.5.1
MESSAGES
SET_CFG_0
The SET_CFG_0 message is sent by the host to the
MCP8025/6 devices to configure the devices. The
SET_CFG_0 message may be sent to the device at any
time. The host is responsible for making sure the
system is in a state that will not be compromised by
sending the SET_CFG_0 message. The SET_CFG_0
message format is indicated in Table 4-7. The
response is indicated in Table 4-8.
4.5.5.2
GET_CFG_0
The GET_CFG_0 message is sent by the host to the
MCP8025/6 devices to retrieve the device
configuration register. The GET_CFG_0 message
format is indicated in Table 4-7. The response is
indicated in Table 4-8.
4.5.5.3
STATUS_0 and STATUS_1
STATUS_0 and STATUS_1 messages are sent by the
host to the MCP8025/6 devices to retrieve the device
STAT0 or STAT1 register. Unsolicited STATUS_0 and
STATUS_1 messages may also be sent to the host by
the MCP8025/6 devices to inform the host of status
changes. The unsolicited STATUS_0 and STATUS_1
messages will only be sent when a status bit changes
to an active state. The STATUS_0 and STATUS_1
message format is indicated in Table 4-7. The
response is indicated in Table 4-8.
4.5.5.5
GET_CFG_1
The GET_CFG_1 message is sent by the host to the
MCP8025/6 devices to retrieve the motor current limit
reference DAC configuration register. The GET_CFG_1
message format is indicated in Table 4-7. The
response is indicated in Table 4-8.
4.5.5.6
SET_CFG_2
The SET_CFG_2 message is sent by the host to the
MCP8025/6 devices to configure the driver current limit
blanking time. The SET_CFG_2 message may be sent
to the device at any time. The host is responsible for
making sure the system is in a state that will not be
compromised by sending the SET_CFG_2 message.
The SET_CFG_2 message format is indicated in
Table 4-7. The response is indicated in Table 4-8.
4.5.5.7
GET_CFG_2
The GET_CFG_2 message is sent by the host to the
MCP8025/6 devices to retrieve the device
Configuration Register 2. The GET_CFG_2 message
format is indicated in Table 4-7. The response is
indicated in Table 4-8.
When a STATUS_0 and STATUS_1 message is sent to
the host in response to a new fault becoming active, the
fault bit will be cleared either by the host issuing a
STATUS_0 and STATUS_1 request message or by the
host toggling the CE pin low then high. The fault bit will
stay active and not be cleared if the fault condition still
exists at the time the host attempted to clear the fault.
The BORW bit in the STAT1 register will be set every
time the device restarts due to a brown-out event, a
Sleep mode wake-up or a normal power-up. When the
bit is set, a single unsolicited message will be sent to
the host indicating a voltage brownout or power-up has
taken place and that the configuration data may have
been lost. The flag is reset by a ‘STATUS_1 ACK’
(01000110 (46H)) from the device in response to a
Host Status Request command.
4.5.5.4
SET_CFG_1
The SET_CFG_1 message is sent by the host to the
MCP8025/6 devices to configure the motor current limit
reference DAC. The SET_CFG_1 message may be
sent to the device at any time. The host is responsible
for making sure the system is in a state that will not be
compromised by sending the SET_CFG_1 message.
The SET_CFG_1 message format is indicated in
Table 4-7. The response is indicated in Table 4-8.
2016 Microchip Technology Inc.
DS20005339B-page 39
MCP8025/6
TABLE 4-7:
DE2 COMMUNICATION COMMANDS TO MCP8025/6 FROM HOST
Command
Byte
SET_CFG_0
1
2
Bit
Value
Description
10000001b (81H) Set Configuration Register 0
7
0
Reserved
6
—
(Always ‘0’ in Sleep mode)
0
Enable Disconnect of 30 k LIN Bus/Level Translator Pull Up when
CE = 0 (Default)
1
Disable Disconnect of 30 k LIN Bus/Level Translator Pull Up when
CE = 0
0
System Enters Standby Mode when CE = 0
1
System Enters Sleep Mode when CE = 0, 30 k LIN Bus/Level
Translator Pull Up Disconnect always enabled
0
Disable Internal Neutral Simulator (Start-Up Default)
1
Enable Internal Neutral Simulator
0
Enable MOSFET Undervoltage Lockout (Start-Up Default)
1
Disable MOSFET Undervoltage Lockout
2
0
Enable External MOSFET Short-Circuit Detection (Start-Up Default)
1
Disable External MOSFET Short-Circuit Detection
1:0
00
Set External MOSFET Overcurrent Limit to 0.250V (Start-Up Default)
01
Set External MOSFET Overcurrent Limit to 0.500V
10
Set External MOSFET Overcurrent Limit to 0.750V
11
Set External MOSFET Overcurrent Limit to 1.000V
5
4
3
GET_CFG_0
1
10000010 (82H)
Get Configuration Register 0
SET_CFG_1
1
10000011 (83H)
Set Configuration Register 1
DAC Motor Current Limit Reference Voltage
2
7:0
00H – FFH
Select DAC Current Reference value
(4.503V – 0.991V)/255 = 13.77 mV/bit
00H = 0.991V
40H = 1.872V (40H x 0.1377 mV/bit + 0.991V) (Start-Up Default)
FFH = 4.503V (FFH x 0.1377 mV/bit + 0.991V)
GET_CFG_1
1
10000100 (84H)
Get Configuration Register 1
Get DAC Motor Current Limit Reference Voltage
STATUS_0
1
10000101 (85H)
Get Status Register 0
STATUS_1
1
10000110 (86H)
Get Status Register 1
10000111 (87H)
Set Configuration register 2
SET_CFG_2
1
2
7:5
00H
4:2
—
1:0
GET_CFG_2
1
DS20005339B-page 40
Reserved
Driver Dead Time (for PWMH/PWML inputs)
000
2000 ns (Default)
001
1750 ns
010
1500 ns
011
1250 ns
100
1000 ns
101
750 ns
110
500 ns
111
250 ns
—
Driver Blanking Time (Ignore Switching Current Spikes)
00
4 µs (Default)
01
2 µs
10
1 µs
11
500 ns
10001000 (88H)
Get Configuration Register 2
2016 Microchip Technology Inc.
MCP8025/6
TABLE 4-8:
MESSAGE
SET_CFG_0
DE2 COMMUNICATION MESSAGES FROM MCP8025/6 TO HOST
BYTE BIT
1
VALUE
DESCRIPTION
7:0 00000001 (01H) Set Configuration Register 0 ‘Not Acknowledged’ (Response)
01000001 (41H) Set Configuration Register 0 ‘Acknowledged’ (Response)
2
7
0
Reserved
6
—
Ignored in Sleep mode
0
Enable Disconnect of 30K LIN Bus/Level Translator Pull Up when
CE = 0 (Default)
1
Disable Disconnect of 30K LIN Bus/Level Translator Pull Up when
CE = 0
0
System Enters Standby Mode when CE = 0
1
System Enters Sleep Mode when CE = 0, 30K LIN Bus/Level
Translator Pull Up Disconnect always enabled
0
Internal Neutral Simulator Disabled (Start-Up Default)
1
Internal Neutral Simulator Enabled
0
Undervoltage Lockout Enabled (Default)
1
Undervoltage Lockout Disabled
0
External MOSFET Overcurrent Detection Enabled (Default)
1
External MOSFET Overcurrent Detection Disabled
00
0.250V External MOSFET Overcurrent Limit (Default)
01
0.500V External MOSFET Overcurrent Limit
10
0.750V External MOSFET Overcurrent Limit
11
1.000V External MOSFET Overcurrent Limit
5
4
3
2
1:0
GET_CFG_0
1
7:0 00000010 (02H) Get Configuration Register 0 ‘Not Acknowledged’ (Response)
01000010 (42H) Get Configuration Register 0 ‘Acknowledged’ (Response)
2
7
0
Reserved
6
—
Ignored in Sleep mode
0
Enable Disconnect of 30K LIN Bus/Level Translator Pull Up when
CE = 0 (Default)
1
Disable Disconnect of 30K LIN Bus/Level Translator Pull Up when
CE = 0
0
System Enters Standby Mode when CE = 0
1
System Enters Sleep Mode when CE = 0, 30K LIN Bus/Level
Translator Pull Up Disconnect always enabled
0
Internal Neutral Simulator Disabled (Start-Up Default)
1
Internal Neutral Simulator Enabled
0
Undervoltage Lockout Enabled
1
Undervoltage Lockout Disabled
0
External MOSFET Overcurrent Detection Enabled
1
External MOSFET Overcurrent Detection Disabled
00
0.250V External MOSFET Overcurrent Limit
01
0.500V External MOSFET Overcurrent Limit
10
0.750V External MOSFET Overcurrent Limit
11
1.000V External MOSFET Overcurrent Limit
5
4
3
2
1:0
2016 Microchip Technology Inc.
DS20005339B-page 41
MCP8025/6
TABLE 4-8:
MESSAGE
SET_CFG_1
DE2 COMMUNICATION MESSAGES FROM MCP8025/6 TO HOST (CONTINUED)
BYTE BIT
1
VALUE
DESCRIPTION
00000011 (03H) Set DAC Motor Current Limit Reference Voltage ‘Not Acknowledged’
(Response)
01000011 (43H) Set DAC Motor Current Limit Reference Voltage ‘Acknowledged’
(Response)
2
GET_CFG_1
7:0
1
00H – FFH
Current DAC Current Reference Value: 13.77 mV/bit + 0.991V
00000100 (04H) Get DAC Motor Current Limit Reference Voltage ‘Not Acknowledged’
(Response)
01000100 (44H) Get DAC Motor Current Limit Reference Voltage ‘Acknowledged’
(Response)
STATUS_0
2
7:0
1
7:0 00000101 (05H) Status Register 0 ‘Not Acknowledged’ (Response)
00H – FFH
Current DAC Current Reference Value: 13.77 mV/bit + 0.991V
01000101 (45H) Status Register 0 ‘Acknowledged’ (Response)
10000101 (85H) Status Register 0 Command to Host (Unsolicited)
2
STATUS_1
1
7:0
00000000
Normal Operation
00000001
Temperature Warning (TJ > 72% TSD_MIN = 115°C) (Default)
00000010
Overtemperature (TJ > 160°C)
00000100
Input Undervoltage (VDD < 5.5V)
00001000
Driver Input Overvoltage (20V < VDDH < 32V)
00010000
Input Overvoltage (VDD > 32V)
00100000
Buck Regulator Overcurrent
01000000
Buck Regulator Output Undervoltage Warning
10000000
Buck Regulator Output Undervoltage (< 80%, Brown-out Error)
7:0 00000110 (06H) Status Register 1 ‘Not Acknowledged’ (Response)
01000110 (46H) Status Register 1 ‘Acknowledged’ (Response)
10000110 (86H) Status Register 1 Command to Host (Unsolicited)
2
DS20005339B-page 42
7:0
00000000
Normal Operation
00000001
Reserved
00000010
Reserved
00000100
External MOSFET Undervoltage Lockout (UVLO)
00001000
External MOSFET Overcurrent Detection
00010000
Brown-out Reset – Config Lost (Start-Up Default = 1)
00100000
+5V LDO Undervoltage Lockout (UVLO)
01000000
Reserved
10000000
Reserved
2016 Microchip Technology Inc.
MCP8025/6
TABLE 4-8:
MESSAGE
SET_CFG_2
DE2 COMMUNICATION MESSAGES FROM MCP8025/6 TO HOST (CONTINUED)
BYTE BIT
1
VALUE
DESCRIPTION
00000111 (07H) Set Configuration Register 2 ‘Not Acknowledged’ (Response)
01000111 (47H) Set Configuration Register 2 ‘Acknowledged’ (Response)
2
7:5
00H
4:2
—
GET_CFG_2
1
Driver Dead Time (for PWMH/PWML inputs)
000
2000 ns (Default)
001
1750 ns
010
1500 ns
011
1250 ns
100
1000 ns
101
750 ns
110
500 ns
111
1:0
Reserved
250 ns
—
Driver Blanking Time (Ignore Switching Current Spikes)
00
4 µs (Default)
01
2 µs
10
1 µs
11
500 ns
00001000 (08H) Get Configuration Register 2 ‘Not Acknowledged’ (Response)
01001000 (48H) Get Configuration Register 2 ‘Acknowledged’ (Response)
2
7:5
00H
4:2
—
1:0
2016 Microchip Technology Inc.
Reserved
Driver Dead Time (for PWMH/PWML inputs)
000
2000 ns (Default)
001
1750 ns
010
1500 ns
011
1250 ns
100
1000 ns
101
750 ns
110
500 ns
111
250 ns
—
Driver Blanking Time (Ignore Switching Current Spikes)
00
4 µs (Default)
01
2 µs
10
1 µs
11
500 ns
DS20005339B-page 43
MCP8025/6
4.6
Register Definitions
REGISTER 4-1:
CFG0: CONFIGURATION REGISTER 0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
PU30K
SLEEP
NEUSIM
EXTUVLO
EXTSC
EXTOC1
EXTOC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6
PU30K: 30K LIN/Level Translator Pull Up (1)
1 = Disable disconnect of 30K Pull Up when CE = 0.
0 = Enable disconnect of 30K Pull Up when CE = 0.
bit 5
SLEEP: Sleep Mode bit
1 = System enters Sleep Mode when CE = 0. Disconnect of 30K LIN/Level Translator Pull Up always
enabled.
0 = System enters Standby Mode when CE = 0.
bit 4
NEUSIM: Neutral Simulator (MCP8025)
1 = Enable Internal Neutral Simulator
0 = Disable Internal Neutral Simulator
bit 3
EXTUVLO: External MOSFET Undervoltage Lockout
1 = Disable
0 = Enable
bit 2
EXTSC: External MOSFET Short-Circuit Detection
1 = Disable
0 = Enable
bit 1-0
EXTOC<1:0>: External MOSFET Overcurrent Limit Value
00 = Overcurrent limit set to 0.250V
01 = Overcurrent limit set to 0.500V
10 = Overcurrent limit set to 0.750V
11 = Overcurrent limit set to 1.000V
Note 1:
Bit may only be changed while in Standby mode.
DS20005339B-page 44
2016 Microchip Technology Inc.
MCP8025/6
REGISTER 4-2:
CFG1: CONFIGURATION REGISTER 1
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DACREF7
DACREF6
DACREF5
DACREF4
DACREF3
DACREF2
DACREF1
DACREF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
DACREF<7:0>: DAC Current Reference Value
(4.503V – 0.991V)/255 = 13.77 mV/bit
00H = 0.991V
40H = 1.872V (40H x 0.1377 mV/bit + 0.991V)
FFH = 4.503V (FFH x 0.1377 mV/bit + 0.991V)
REGISTER 4-3:
CFG2: CONFIGURATION REGISTER 2
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
DRVDT2
DRVDT1
DRVDT0
DRVBL1
DRVBL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-5
Unimplemented: Read as ‘0’
bit 4-2
DRVDT<2:0>: Driver Dead Time Selection bits
000 = 2000 ns
001 = 1750 ns
010 = 1500 ns
011 = 1250 ns
100 = 1000 ns
101 = 750 ns
110 = 500 ns
111 = 250 ns
bit 1-0
DRVB<1:0>: Driver Blanking Time Selection bits
00 = 4000 ns
01 = 2000 ns
10 = 1000 ns
11 = 500 ns
2016 Microchip Technology Inc.
x = Bit is unknown
DS20005339B-page 45
MCP8025/6
REGISTER 4-4:
STAT0: STATUS REGISTER 0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
BUVLOF
BUVLOW
BIOCPW
OVLOF
DOVLOF
UVLOF
OTPF
OTPW
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
BUVLOF: Buck Undervoltage Lockout Fault
1 = Buck output voltage is below 80% of expected value
0 = Buck output voltage is above 80% of expected value
bit 6
BUVLOW: Buck Undervoltage Lockout Warning
1 = Buck output voltage is below 90% of expected value
0 = Buck output voltage is above 90% of expected value
bit 5
BIOCPW: Buck Input Overcurrent Protection Warning
1 = Buck input current is above 2A peak
0 = Buck input current is below 2A peak
bit 4
OVLOF: Input Overvoltage Lockout Fault
1 = VDD Input Voltage > 32V
0 = VDD Input Voltage < 32V
bit 3
DOVLOF: Driver Input Overvoltage Lockout Fault (MCP8025 only, MCP8026 = 0)
1 = 20V < VDDH
0 = VDD < 20V
bit 2
UVLOF: Input Undervoltage Fault
1 = VDD Input Voltage < 5.5V
0 = VDD Input Voltage > 5.5V
bit 1
OTPF: Overtemperature Protection Fault
1 = Device junction temperature is > 160°C
0 = Device junction temperature is < 160°C
bit 0
OTPW: Overtemperature Protection Warning
1 = Device junction temperature is > 115°C
0 = Device junction temperature is < 115°C
DS20005339B-page 46
2016 Microchip Technology Inc.
MCP8025/6
REGISTER 4-5:
STAT1: STATUS REGISTER 1
U-0
U-0
R-0
R-1
R-0
R-0
U-0
U-0
—
—
UVLOF5V
BORW
XOCPF
XUVLOF
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5
UVLOF5V: +5V LDO Undervoltage Lockout
1 = +5V LDO output voltage < 4.0V
0 = +5V LDO output voltage > 4.0V
bit 4
BORW: Brown-out Reset Warning, Configuration Lost
1 = Internal device reset has occurred since last configuration message
0 = No internal device reset has occurred since last configuration message
bit 3
XOCPF: External MOSFET Overcurrent Protection Fault (1)
1 = External MOSFET VDS > CFG0<EXTOC> value
0 = External MOSFET VDS < CFG0<EXTOC> value
bit 2
XUVLOF: External MOSFET Gate Drive Undervoltage Fault
1 = HSX Output Voltage < 8V
0 = HSX Output Voltage > 8V
bit 1-0
Note 1:
Unimplemented: Read as ‘0’
Only valid when CFG0<EXTSC> = 1.
2016 Microchip Technology Inc.
DS20005339B-page 47
MCP8025/6
5.0
APPLICATION INFORMATION
5.1
Component Calculations
5.1.1
CHARGE PUMP CAPACITORS
Transfer
For stability reasons, the +12V LDO and +5V LDO
capacitors must be greater than 4.7 µF, so choose
C 4.7 µF.
5.1.1.3
Charging Path (Flying Capacitor
across CAP1 and CAP2)
VCAP = VDDH (1 – e-T/)
VCAP = 6V (1 – e – [6.67 µs/([7.5 + 3.5 + 20 m] x 180 nF)])
VCAP = 5.79V available for transfer
5.1.1.4
Charge
Transfer Path (Flying and Output
Capacitors)
V12P = VDDH + VCAP – IOUT x dt/C
V12P = 6V + 5.79V – (20 mA x 6.67 µs/180 nF)
V12P = 11.049V
FIGURE 5-1:
Charge Pump.
Let:
5.1.1.5
IOUT = 20 mA
fCP = 75 kHz (charge/discharge in one cycle)
50% duty cycle
VDDH = 6V (worst case)
RDSON = 7.5 (RPMOS), 3.5 (RNMOS)
V12P = 2 x VDDH (ideal)
CESR = 20 m (ceramic capacitors)
VDROP = 100 mV (VOUT ripple)
TCHG = TDCHG = 0.5 x 1/75 kHz = 6.67 µs
5.1.1.1
Flying Capacitor
The flying capacitor should be chosen to charge to a
minimum of 95% (3) of VDDH within one half of a
switching cycle.
3 x = TCHG
= TCHG/3
RC = TCHG/3
C = TCHG/(R x 3)
C = 6.67 µs/([7.5 + 3.5 + 0.02] x 3)
C = 202 nF
Choose a 180 nF capacitor.
5.1.1.2
Charge Pump Output Capacitor
Solve for the charge pump output capacitance,
connected between V12P and ground, that will supply
the 20 mA load for one switch cycle. The +12V LDO
pin on the MCP8025/6 is the “V12P” pin referenced in
the calculations.
C = IOUT x dt/dV
C = IOUT x 13.3 µs/(VDROP + IOUT x CESR)
C = 20 mA x 13.3 µs/(0.1V + 20 mA x 20 m)
Calculate the Flying Capacitor
Voltage Drop in One Cycle while
Supplying 20 mA
dV = IOUT x dt/C
dV = 20 mA x 6.67 µs/180 nF
dV = 0.741V @ 20 mA
The second and subsequent transfer cycles will have
a higher voltage available for transfer, since the
capacitor is not completely depleted with each cycle.
VCAP will then be VCAP – dV after the first transfer,
plus VDDH – (VCAP – dV) times the RC constant. This
repeats for each subsequent cycle, allowing a larger
charge pump capacitor to be used if the system
tolerates several charge transfers before requiring
full-output voltage and current.
Repeating the steps in Section 5.1.1.3, Charging Path
(Flying Capacitor across CAP1 and CAP2) for the
second cycle (and subsequent by re-calculating for
each new value of VCAP after each transfer):
VCAP = (VCAP – dV) + (VDDH – (VCAP – dV)) (1 – e-T/)
VCAP = (5.79V – 0.741V) + (6V – (5.79V – 0.741V) x
(1 – e – [6.67 µs/([7.5 + 3.5 + 20 m] x 180 nF)])
VCAP = 5.049V + 0.951V x 0.96535
VCAP = 5.967V available for transfer on second cycle
5.1.1.6
Charge Pump Results
The maximum charge pump flying capacitor value is
202 nF to maintain a 95% voltage transfer ratio on the
first charge pump cycle. Larger capacitor values may
be used but they will require more cycles to charge to
maximum voltage. The minimum required output
capacitor value is 2.65 µF to supply 20 mA for 13.3 µs
with a 100 mV drop. A larger output capacitor may be
used to cover losses due to capacitor tolerance over
temperature, capacitor dielectric and PCB losses.
C 2.65 µF
DS20005339B-page 48
2016 Microchip Technology Inc.
MCP8025/6
These are approximate calculations. The actual
voltages may vary due to incomplete charging or
discharging of capacitors per cycle due to load
changes. The charge pump calculations assume the
charge pump is able to charge up the external boot
cap within a few cycles.
5.1.2
QRESISTOR = 0.594 nC
QDRIVER = 20 µA x 49.5 µs
QDRIVER = 0.99 nC
Sum all of the energy requirements:
C = (QMOSFET + QRESISTOR + QDRIVER)/VDROP
BOOTSTRAP CAPACITOR
The high-side driver bootstrap capacitor needs to
power the high-side driver and gate for 1/3 of the
motor electrical period for a 3-phase BLDC motor.
Let:
MOSFET driver current = 300 mA
C = (130 nC + 0.594 nC + 0.99 nC)/3V
C = 43.86 nF
Choose a bootstrap capacitor value that is larger than
43.86 nF.
5.1.3
PWM period = 50 µs (20 kHz)
Minimum duty cycle = 1% (500 ns)
Maximum duty cycle = 99% (49.5 µs)
VIN = 12V
BUCK SWITCHER
5.1.3.1
Calculate the Buck Inductor for
Discontinuous Mode Operation
Let:
VIN = 4.3V (worst case is BUVLO)
Minimum gate drive voltage = 8V (VGS)
Total gate charge = 130 nC (80A MOSFET)
VOUT = 3.3V
IOUT = 225 mA
Allowable VGS drop (VDROP) = 3V
fSW = 468 kHz (TSW = 2.137 µs)
Switch RDSON = 100 m
Driver internal bias current = 20 µA (IBIAS)
Solve for the smallest capacitance that can supply:
- 130 nC of charge to the MOSFET gate
- 1 M Gate-Source resistor current
- Driver bias current and switching losses
Solve for maximum inductance value.
LMAX = VOUT x (1 – VOUT/VIN) x TSW/(2 x IOUT)
LMAX = 3.3V x (1 – 3.3V/4.3V) x 2.137 µs/(2 x 225 mA)
LMAX = 3.64 µH
Choose an inductor
3.64 µH
Discontinuous Conduction mode.
QMOSFET = 130 nC
QRESISTOR = [(VGS/R) x TON]
QDRIVER = (IBIAS x TON)
TON = 49.5 µs (99% DC) for worst case
to
ensure
Table 5-1 shows the various maximum inductance
values for a worst case input voltage of 6V and various
output voltages.
QRESISTOR = (12V/1 M) x 49.5 µs
TABLE 5-1:
MAXIMUM INDUCTANCE FOR BUCK DISCONTINUOUS MODE OPERATION
VIN
(worst case)
VOUT
IOUT
Maximum Inductance
4.3V (BUVLO)
3V
250 mA
4.3 µH
4.3V (BUVLO)
3.3V
225 mA
3.6 µH
6V
5.0V
150 mA
5.9 µH
2016 Microchip Technology Inc.
DS20005339B-page 49
MCP8025/6
5.1.3.2
Determine the Peak Switch Current
for the Calculated Inductor
Assuming the V12 capacitor is 4.7 µF, V12 LDO is 12V,
CBOOTSTRAP = 1 µF, the bootstrap voltage when the
12V supply is first turned on will be:
IPEAK = (VS – VO) x D x T/L
IPEAK = (4.3V – 3.3V) x (3.3V/4.3V) x 2.137 µs/3.64 µH
12V x (4.7 µF/(4.7 µF + 3 bootstrap caps charging x
1 µF)) = 7.32V which will trip the gate driver UVLO if the
low-side is turned on at this time.
IPEAK = 450 mA
5.1.3.3
Setting the Buck Output Voltage
The buck output voltage is set by a resistor voltage
divider from the inductor output to ground. The divider
center tap is fed back to the MCP8025 FB pin. The
FB pin is compared to an internal 1.25V reference
voltage. When the FB pin voltage drops below the
reference voltage, the buck duty cycle increases.
When the FB pin rises above the reference voltage,
the buck duty cycle decreases.
CURRENT_REF
By sizing the 12V LDO capacitor to prevent the
bootstrap voltage from dropping below 8V, the UVLO
may be averted.
VBOOTCAP = 12V (Cap12V/(Cap12V + n x CapBOOTSTRAP))
Where "n" is the number of simultaneous bootstrap
caps being charged at the same time.
VBOOTCAP/12V
= Cap12V/(Cap12V + n x CapBOOTSTRAP)
12V/VBOOTCAP
= (Cap12V + n x CapBOOTSTRAP)/
Cap12V
Cap12V x 12V/VBOOTCAP = Cap12V + n x CapBOOT-
VDD
STRAP
+
-
12V/VBOOTCAP x Cap12V – Cap12V = n x CapBOOTSTRAP
Cap12V = (n x CapBOOTSTRAP)/(12V/VBOOTCAP – 1)
Q1
OUTPUT
CONTROL
LOGIC
LX
VDD-12V
Letting VBOOT = 9V, CapBOOTSTRAP = 470 nF and
charging three caps simultaneously:
L1
Cap12V
D1
Schottky
+
+
-
BANDGAP
REFERENCE
-
= (3 x 470 nF)/(12V/9V – 1) = 4.23 µF
Use a 4.7 µF capacitor for the +12V LDO.
Letting VBOOT = 9V, CapBOOTSTRAP = 1 µF and
charging three caps simultaneously:
R1
FB
C1
R2
Cap12V
= (3 x 1 µF)/(12V/9V – 1) = 9.0 µF
Use a 10 µF capacitor for the +12V LDO.
FIGURE 5-2:
Typical Buck Application.
Start with an R2 value of 10 k to 51 k to minimize
current through the divider.
Letting VBOOT = 9V, CapBOOTSTRAP = 1 µF
charging one cap at a time:
Cap12V
and
= (1 x 1 µF)/(12V/9V – 1) = 3.0 µF
Use a 3.3 µF capacitor for the +12V LDO.
VBUCK = 1.25V x (R1 + R2)/R2
5.1.3.4
Start-Up Delay for Bootstrap
Charging
A start-up delay is required whenever the device has
been disabled (CE = 0) and the bootstrap capacitors
have discharged. When the device is re-enabled
(CE = 1), there is a voltage divider between the
+12V LDO capacitor and the bootstrap capacitors. To
prevent a gate drive undervoltage lockout, the
+12V LDO capacitor must be sized to prevent the
bootstrap capacitors from pulling the 12V supply below
the UVLO threshold when the 12V supply is enabled.
DS20005339B-page 50
2016 Microchip Technology Inc.
MCP8025/6
5.2
5.2.1
Device Protection
MOSFET VOLTAGE SUPPRESSION
When a motor shaft is rotating and power is removed,
the magnetism of the motor components will cause the
motor to act like a generator. The current that was
flowing into the motor will now flow out of the motor. As
the motor magnetic field decays, the generator output
will also decay. The voltage across the generator
terminals will be proportional to the generator current
and the circuit impedance of the generator circuit. If
the power supply is part of the return path for the
current and the power supply is disconnected, then the
voltage at the generator terminals will increase until
the current flows. This voltage increase must be
handled external to the driver. A voltage suppression
device must be used to clamp the motor terminal
voltage to a level that will not exceed the maximum
motor operating voltage. A voltage suppressor should
be connected from ground to each motor terminal. The
PCB traces must be capable of carrying the motor
current with minimum voltage and temperature rise.
An additional method is to inactivate the high-side
drivers and to activate the low-side drivers. This allows
current to flow through the low-side external
MOSFETs and prevents the voltage increases at the
power supply terminals. A pure hardware
implementation may be done by connecting a
bidirectional transient voltage suppressor (TVS) from
the gate of each external low-side driver MOSFET to
the drain of the same MOSFET. When the phase
voltage rises above the TVS standoff voltage, the TVS
will start to conduct, pulling up the gate of the low-side
MOSFET. This turns on the MOSFET and creates a
low-voltage current path for the motor windings to
dissipate stored energy. The implementation is a
failsafe mechanism in cases where the supply
becomes disconnected or the controller shuts down
due to a fault or command. The MCP8025/6
overvoltage lockout (OVLO) is 32V, so a 33V TVS
would be used. This allows the MCP8025/6 to shut
down before the TVS forces the low-side gates high,
preventing the MCP8025/6 low-side drivers from
sinking current if they are being driven low. The
MCP8025 may use a lower voltage transzorb due to
the fact that the MCP8025 driver overvoltage lockout
(DOVLO) occurs at a lower voltage.
5.2.2
BOOTSTRAP VOLTAGE
SUPPRESSION
The pins which handle the highest voltage during
motor operation are the bootstrap pins (VBx). The
bootstrap pin voltage is typically 12V higher than the
associated phase voltage. When the high-side
MOSFET is conducting, the phase pin voltage is
typically at VDD and the bootstrap pin voltage is
typically at VDD + 12V. When the phase MOSFETs
switch, current-induced voltage transients occur on the
phase pins. Those induced voltages cause the
2016 Microchip Technology Inc.
bootstrap pin voltages to also increase. Depending on
the magnitude of the phase pin voltage, the bootstrap
pin voltage may exceed the safe operating voltage of
the device. The current-induced transients may be
reduced by slowing down the turn-on and turn-off
times of the MOSFETs. The external MOSFETs may
be slowed down by adding a 10 to 75 resistor in
series with the gate drive. The high-side MOSFETs
may also be slowed down by inserting a 25 resistor
between each bootstrap pin and the associated
bootstrap diode-capacitor junction. Another 25 to
50 resistor is then added between the gate drive and
the MOSFET gate. This results in a high-side turn-on
resistance of 25 plus the resistance of the series
gate resistor. The high-side turn-off resistance only
consists of the series gate resistance and will allow for
a faster shutoff time.
36V TVS devices (40V breakdown voltage) should
also be connected from each bootstrap pin (VBx) to
ground. This will ensure that the bootstrap voltage
does not exceed the 46V absolute maximum voltage
allowed on the pins. The resistors connected between
the bootstrap pins and the bootstrap diode-capacitor
junctions mentioned in the previous paragraph should
also be used in order to limit the TVS current and
reduce the TVS package size.
5.2.3
FLOATING GATE SUPPRESSION
The gate drive pins may float when the supply voltage
is lost or an overvoltage situation shuts down the
driver. When an overvoltage condition exists, the
driver high-side and low-side outputs are high Z. Each
external MOSFET that is connected to the gate driver
should have a gate-to-source resistor to bleed off any
charge that may accumulate due to the high Z state.
This will help prevent inadvertent turn-on of the
MOSFET.
5.2.4
MOSFET BODY DIODE REVERSE
RECOVERY SNUBBER
When motor current is flowing through the external
MOSFET body diodes and the complimentary
MOSFET of the phase pair turns on, the body diode
reverse recovery creates a momentary short-circuit
until the reverse recovery time is complete. When the
body diode reverse recovery is complete, the current
path is opened, causing the phase node voltage to slew
rapidly towards ground or VDD levels. The rapid slew
rate may cause an inversion of the gate-to-source
voltage on the MOSFET that is turning on and result in
that MOSFET turning off.
Adding a drain-to-source snubber slows down the slew
rate of the phase node and results in a more controlled
excursion of the phase node voltage. The snubber
consists of a resistor and a capacitor connected in
series between the drain and source of the MOSFET.
The resistor is chosen to keep the initial snubber
voltage below a few volts when peak motor current is
DS20005339B-page 51
MCP8025/6
flowing through the body diode. The capacitor is then
chosen to provide an RC time constant longer than the
MOSFET body diode reverse recovery time. A
0.1 resistor is typically used along with a 0.1 µF
capacitor to provide an RC of 10 ns.
The power dissipated by the capacitor is calculated by
applying Equation 5-1.
EQUATION 5-1:
SNUBBER CAPACITOR
POWER DISSIPATION
2
P DISS = 2 f C V Dissipation Factor
Where:
f = PWM frequency
C = Capacitance
V = Motor Voltage
Dissipation Factor = 2 f C ESR = ESR X C
The capacitor and resistor form factors are chosen to
handle the dissipated power.
5.3
Related Literature
• AN885,
“Brushless
DC
(BLDC)
Motor
Fundamentals”, DS00885, Microchip Technology
Inc., 2003
• AN1160, “Sensorless BLDC Control with
Back-EMF Filtering Using a Majority Function”,
DS01160, Microchip Technology Inc., 2008
• AN1078, “Sensorless Field Oriented Control of a
PMSM”, DS01078, Microchip Technology Inc.,
2010
DS20005339B-page 52
2016 Microchip Technology Inc.
MCP8025/6
DS20005339B-page 53
Figure 5-3 shows the location of the overvoltage TVS devices, gate resistors, bootstrap resistors and gate-to-source resistors.
+12V
VBA
VBB
VBC
R
R
R
HSA
R
HSB
R
HSC
R
R
A
R
R
PHA
PHB
PHC
B
LSA
R
LSB
R
LSC
R
R
R
R
S
2016 Microchip Technology Inc.
FIGURE 5-3:
Overvoltage Protection.
S
S
C
+
_
VDD
MCP8025/6
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
40-Lead QFN (5x5x0.85 mm)
Example
MCP8025
e3
E/MP^^
1606256
48-Lead TQFP (7x7x1 mm)
Example
MCP8026
EPT1606
256
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS20005339B-page 54
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2016 Microchip Technology Inc.
MCP8025/6
40-Lead Plastic Quad Flat, No Lead Package (MP) - 5x5 mm Body [QFN]
With 3.7x3.7 mm Exposed Pad
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
N
1
2
NOTE 1
E
(DATUM B)
(DATUM A)
2X
0.20 C
2X
TOP VIEW
0.20 C
0.10 C
C
SEATING
PLANE
A1
A
(A3)
SIDE VIEW
0.08 C
0.10
C A B
D2
0.10
C A B
E2
K
2
1
N
L
e
40X b
0.07
0.05
C A B
C
Microchip Technology Drawing C04-047-002A Sheet 1 of 2
2016 Microchip Technology Inc.
DS20005339B-page 55
MCP8025/6
40-Lead Plastic Quad Flat, No Lead Package (MP) - 5x5 mm Body [QFN]
With 3.7x3.7 mm Exposed Pad
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Terminals
N
e
Pitch
A
Overall Height
Standoff
A1
A3
Terminal Thickness
Overall Width
E
E2
Exposed Pad Width
D
Overall Length
D2
Exposed Pad Length
b
Terminal Width
Terminal Length
L
K
Terminal-to-Exposed-Pad
MIN
0.80
0.00
0.15
0.30
0.20
MILLIMETERS
NOM
40
0.40 BSC
0.85
0.02
0.20 REF
5.00 BSC
3.70 BSC
5.00 BSC
3.70 BSC
0.20
0.40
-
MAX
0.90
0.05
0.25
0.50
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-047-002A Sheet 2 of 2
DS20005339B-page 56
2016 Microchip Technology Inc.
MCP8025/6
40-Lead Plastic Quad Flat, No Lead Package (MP) - 5x5 mm Body [QFN]
With 3.7x3.7 mm Exposed Pad
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
E
C2
Y2
Y1
X1
SILK SCREEN
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
X2
Optional Center Pad Width
Optional Center Pad Length
Y2
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X40)
X1
Contact Pad Length (X40)
Y1
MIN
MILLIMETERS
NOM
0.40 BSC
MAX
3.80
3.80
5.00
5.00
0.20
0.80
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2047-002A
2016 Microchip Technology Inc.
DS20005339B-page 57
MCP8025/6
48-Lead Thin Quad Flatpack (PT) - 7x7x1.0 mm Body [TQFP] With Exposed Pad
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
D1/2
D
A
B
NOTE 1
E1 E
A
A
E1/2
E1/4 N
48X TIPS
0.20 C A-B D
12
4X
0.20 H A-B D
D1/4
TOP VIEW
A
0.10 C
C
SEATING
PLANE
A2
0.08 C
SIDE VIEW
A1
D2
H
4X
12
0.20 H A-B D
4X
N
0.20
E2
e
48x b
0.08
e/2
C A-B D
TOP VIEW
Microchip Technology Drawing C04-183A Sheet 1 of 2
DS20005339B-page 58
2016 Microchip Technology Inc.
MCP8025/6
48-Lead Thin Quad Flatpack (PT) - 7x7x1.0 mm Body [TQFP] With Exposed Pad
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
H
c
E
L
T
(L1)
SECTION A-A
Units
Dimension Limits
Number of Leads
N
e
Lead Pitch
Overall Height
A
Standoff
A1
Molded Package Thickness
A2
L
Foot Length
Footprint
L1
I
Foot Angle
Overall Width
E
Overall Length
D
Molded Package Width
E1
Molded Package Length
D1
Exposed Pad Width
E2
Exposed Pad Length
D2
c
Lead Thickness
b
Lead Width
D
Mold Draft Angle Top
E
Mold Draft Angle Bottom
MIN
0.05
0.95
0.45
0°
0.09
0.17
11°
11°
MILLIMETERS
NOM
48
0.50 BSC
1.00
0.60
1.00 REF
3.5°
9.00 BSC
9.00 BSC
7.00 BSC
7.00 BSC
3.50 BSC
3.50 BSC
0.22
12°
12°
MAX
1.20
0.15
1.05
0.75
7°
0.16
0.27
13°
13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-183A Sheet 2 of 2
2016 Microchip Technology Inc.
DS20005339B-page 59
MCP8025/6
48-Lead Thin Quad Flatpack (PT) - 7x7x1.0 mm Body [TQFP] With Thermal Tab
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
E
C2 Y2
Y1
X1
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Optional Center Tab Width
X2
Optional Center Tab Length
Y2
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X48)
X1
Contact Pad Length (X48)
Y1
MIN
MILLIMETERS
NOM
0.50 BSC
3.50
3.50
8.40
8.40
MAX
0.30
1.50
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2183A
DS20005339B-page 60
2016 Microchip Technology Inc.
MCP8025/6
APPENDIX A:
REVISION HISTORY
Revision B (March 2016)
The following is the list of modifications:
• Added Figure 2-17 “Typical Baud Rate Deviation.”
• Corrected resistor values in Section 3.10 “LIN
Transceiver Fault/ Transmit Enable (FAULTn/
TXE)”
• Added Section 4.1 “State Diagrams”
• Added Section 5.1.3.4 “Start-Up Delay for
Bootstrap Charging”
• Added Section 5.2.4 “MOSFET Body Diode
Reverse Recovery Snubber”
Revision A (September 2014)
• Original release of this document.
2016 Microchip Technology Inc.
DS20005339B-page 61
MCP8025/6
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X (1)
-X
X
Device Tape and Reel Temperature Temperature
Warning
Range
Device:
MCP8025:
MCP8025T:
MCP8026:
MCP8026T:
/XX
Package
3-Phase Brushless DC (BLDC) Motor
Gate Driver with Power Module and LIN
Transceiver
3-Phase Brushless DC (BLDC) Motor
Gate Driver with Power Module and LIN
Transceiver (Tape and Reel)
3-Phase Brushless DC (BLDC) Motor
Gate Driver with Power Module
3-Phase Brushless DC (BLDC) Motor
Gate Driver with Power Module (Tape
and Reel)
Examples:
a)
MCP8025-115E/MP:
b)
MCP8025T-115E/MP:
c)
MCP8025-115H/MP:
d)
MCP8025T-115H/MP:
e)
MCP8026-115E/MP:
f)
MCP8026T-115E/MP:
g)
MCP8026-115H/MP:
Tape and
Reel:
T
= Tape and Reel (1)
Blank = Tube
h)
MCP8026T-115H/MP:
Temperature
Warning:
115 = 115°C
i)
MCP8025-115E/PT:
j)
MCP8025T-115E/PT:
Temperature
Range:
E
H
k)
MCP8025-115H/PT:
l)
MCP8025T-115H/PT:
m)
MCP8026-115E/PT:
n)
MCP8026T-115E/PT:
o)
MCP8026-115H/PT:
p)
MCP8026T-115H/PT:
Package:
=
=
-40°C to +125°C (Extended)
-40°C to +150°C (High)
MP = Plastic Quad Flat, No Lead Package – 5x5 mm
Body with 3.5x3.5 mm Exposed Pad, 40-lead
PT = Thin Quad Flatpack – 7x7x1.0 mm Body with
Exposed Pad, 48-lead
Note 1:
DS20005339B-page 62
Extended temperature
40LD 5x5 QFN package
Tape and Reel
Extended temperature
40LD 5x5 QFN package
High temperature
40LD 5x5 QFN package
Tape and Reel
High temperature
40LD 5x5 QFN package
Extended temperature
40LD 5x5 QFN package
Tape and Reel
Extended temperature
40LD 5x5 QFN package
High temperature
40LD 5x5 QFN package
Tape and Reel
High temperature
40LD 5x5 QFN package
Extended temperature
48LD TQFP-EP package
Tape and Reel
Extended temperature
48LD TQFP-EP package
High temperature
48LD TQFP-EP package
Tape and Reel
High Temperature
48LD TQFP-EP package
Extended temperature
48LD TQFP-EP package
Tape and Reel
Extended temperature
48LD TQFP-EP package
High temperature
48LD TQFP-EP package
Tape and Reel
High temperature
48LD TQFP-EP package
Tape and Reel identifier only appears in the
catalog part number description. This identifier is
used for ordering purposes and is not printed on
the device package. Check with your Microchip
Sales Office for package availability with the Tape
and Reel option.
2016 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,
MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,
RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O
are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
ETHERSYNCH, Hyper Speed Control, HyperLight Load,
IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,
BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,
Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2016 Microchip Technology Inc.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2016, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0369-2
DS20005339B-page 63
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
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Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
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Tel: 86-592-2388138
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Tel: 43-7242-2244-39
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Tel: 86-756-3210040
Fax: 86-756-3210049
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Tel: 45-4450-2828
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Tel: 91-80-3090-4444
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Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
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Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
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Tel: 60-3-6201-9857
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Tel: 86-532-8502-7355
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Tel: 86-21-5407-5533
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Taiwan - Kaohsiung
Tel: 886-7-213-7828
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
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Tel: 49-721-625370
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Tel: 49-89-627-144-0
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Italy - Milan
Tel: 39-0331-742611
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Italy - Venice
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
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Poland - Warsaw
Tel: 48-22-3325737
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Tel: 34-91-708-08-90
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07/14/15
DS20005339B-page 64
2016 Microchip Technology Inc.