LM5107 www.ti.com SNVS333D – NOVEMBER 2004 – REVISED MARCH 2013 LM5107 100V / 1.4A Peak Half Bridge Gate Driver Check for Samples: LM5107 FEATURES DESCRIPTION • The LM5107 is a low cost high voltage gate driver, designed to drive both the high side and the low side N-Channel MOSFETs in a synchronous buck or a half bridge configuration. The floating high-side driver is capable of working with rail voltages up to 100V. The outputs are independently controlled with TTL compatible input thresholds. An integrated on chip high voltage diode is provided to charge the high side gate drive bootstrap capacitor. A robust level shifter technology operates at high speed while consuming low power and providing clean level transitions from the control input logic to the high side gate driver. Under-voltage lockout is provided on both the low side and the high side power rails. The device is available in the SOIC and the thermally enhanced WSON packages. 1 • • • • • • • • • • Drives Both a High Side and Low Side NChannel MOSFET High Peak Output Current (1.4A Sink / 1.3A Source) Independent TTL compatible inputs Integrated Bootstrap Diode Bootstrap Supply Voltage to 118V DC Fast Propagation Times (27 ns Typical) Drives 1000 pF Load with 15ns Rise and Fall Times Excellent Propagation Delay Matching (2 ns Typical) Supply Rail Under-Voltage Lockout Low Power Consumption Pin Compatible with ISL6700 TYPICAL APPLICATIONS • • • • Package • • SOIC WSON (4 mm x 4 mm) Current Fed Push-Pull Converters Half and Full Bridge Power Converters Solid State Motor Drives Two Switch Forward Power Converters 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2013, Texas Instruments Incorporated LM5107 SNVS333D – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com Simplified Block Diagram HV HB HO UVLO LEVEL SHIFT DRIVER HS HI VDD UVLO LO DRIVER LI VSS Connection Diagrams VDD 1 8 HB VDD 1 8 HB HI 2 7 HO HI 2 7 HO LI 3 6 HS LI 3 6 HS LO VSS 4 5 LO VSS 4 5 Figure 1. 8-Lead SOIC See D Package Figure 2. 8-Lead WSON See NGT0008A Package PIN DESCRIPTIONS (1) Pin # (1) 2 Name Description Application Information SOIC WSON 1 1 VDD Positive gate drive supply Locally decouple to VSS using low ESR/ESL capacitor located as close to IC as possible. 2 2 HI High side control input The LM5107 HI input is compatible with TTL input thresholds. Unused HI input should be tied to ground and not left open 3 3 LI Low side control input The LM5107 LI input is compatible with TTL input thresholds. Unused LI input should be tied to ground and not left open. 4 4 VSS Ground reference All signals are referenced to this ground. 5 5 LO Low side gate driver output Connect to the gate of the low side N-MOS device. 6 6 HS High side source connection Connect to the negative terminal of the bootstrap capacitor and to the source of the high side N-MOS device. 7 7 HO High side gate driver output Connect to the gate of the low side N-MOS device. 8 8 HB High side gate driver positive supply rail Connect the positive terminal of the bootstrap capacitor to HB and the negative terminal of the bootstrap capacitor to HS. The bootstrap capacitor should be placed as close to IC as possible. For WSON package it is recommended that the exposed pad on the bottom of the LM5107 be soldered to ground plane on the PCB board and the ground plane should extend out from underneath the package to improve heat dissipation. Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LM5107 LM5107 www.ti.com SNVS333D – NOVEMBER 2004 – REVISED MARCH 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) VDD to VSS -0.3V to 18V HB to HS −0.3V to 18V −0.3V to VDD +0.3V LI or HI to VSS LO to VSS −0.3V to VDD +0.3V HO to VSS VHS −0.3V to VHB +0.3V HS to VSS (3) −5V to 100V HB to VSS 118V Junction Temperature -40°C to +150°C Storage Temperature Range −55°C to +150°C ESD Rating HBM (1) (4) 2 kV Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test conditions, see the Electrical Characteristics . If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally not exceed -1V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD - 15V. For example, if VDD = 10V, the negative transients at HS must not exceed -5V. The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. Pin 6 , Pin 7 and Pin 8 are rated at 500V. (2) (3) (4) Recommended Operating Conditions VDD HS 8V to 14V (1) −1V to 100V HB VHS +8V to VHS +14V HS Slew Rate < 50 V/ns −40°C to +125°C Junction Temperature (1) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally not exceed -1V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD - 15V. For example, if VDD = 10V, the negative transients at HS must not exceed -5V. Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LM5107 3 LM5107 SNVS333D – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com Electrical Characteristics Specifications in standard typeface are for TJ = +25°C, and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO. Symbol Parameter Conditions Min (1) Typ Max (1) Units SUPPLY CURRENTS IDD VDD Quiescent Current LI = HI = 0V 0.3 0.6 mA IDDO VDD Operating Current f = 500 kHz 2.1 3.4 mA IHB Total HB Quiescent Current LI = HI = 0V 0.06 0.2 mA IHBO Total HB Operating Current f = 500 kHz 1.6 3.0 mA IHBS HB to VSS Current, Quiescent VHS = VHB = 100V 0.1 10 IHBSO HB to VSS Current, Operating f = 500 kHz 0.5 µA mA INPUT PINS LI and HI VIL Low Level Input Voltage Threshold VIH High Level Input Voltage Threshold RI Input Pulldown Resistance 0.8 1.8 V 1.8 2.2 V 100 180 500 kΩ 6.0 6.9 7.4 V UNDER VOLTAGE PROTECTION VDDR VDD Rising Threshold VDDH VDD Threshold Hysteresis VHBR HB Rising Threshold VHBH HB Threshold Hysteresis VDDR = VDD - VSS 0.5 VHBR = VHB - VHS 5.7 6.6 V 7.1 0.4 V V BOOT STRAP DIODE VDL Low-Current Forward Voltage IVDD-HB = 100 µA VDL = VDD - VHB 0.58 0.9 V VDH High-Current Forward Voltage IVDD-HB = 100 mA VDH = VDD - VHB 0.82 1.1 V RD Dynamic Resistance IVDD-HB = 100 mA 0.8 1.5 Ω LO GATE DRIVER VOLL Low-Level Output Voltage ILO = 100 mA VOHL = VLO – VSS 0.28 0.45 V VOHL High-Level Output Voltage ILO = −100 mA, VOHL = VDD– VLO 0.45 0.75 V IOHL Peak Pullup Current VLO = 0V 1.3 A IOLL Peak Pulldown Current VLO = 12V 1.4 A HO GATE DRIVER VOLH Low-Level Output Voltage IHO = 100 mA VOLH = VHO– VHS 0.28 0.45 V VOHH High-Level Output Voltage IHO = −100 mA VOHH = VHB– VHO 0.45 0.75 V IOHH Peak Pullup Current VHO = 0V 1.3 A IOLH Peak Pulldown Current VHO = 12V 1.4 A SOIC 160 WSON (3) 40 THERMAL RESISTANCE θJA (2) (1) (2) (3) 4 Junction to Ambient °C/W Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). The θJA is not a constant for the package and depends on the printed circuit board design and the operating conditions. 4 layer board with Cu finished thickness 1.5/1/1/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm ground and power planes embedded in PCB. See Application Note AN-1187. Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LM5107 LM5107 www.ti.com SNVS333D – NOVEMBER 2004 – REVISED MARCH 2013 Switching Characteristics Specifications in standard typeface are for TJ = +25°C, and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO. Symbol Parameter Conditions Min (1) Typ Max (1) Units LM5100A tLPHL Lower Turn-Off Propagation Delay (LI Falling to LO Falling) 27 56 ns tHPHL Upper Turn-Off Propagation Delay (HI Falling to HO Falling) 27 56 ns tLPLH Lower Turn-On Propagation Delay (LI Rising to LO Rising) 29 56 ns tHPLH Upper Turn-On Propagation Delay (HI Rising to HO Rising) 29 56 ns tMON Delay Matching: Lower Turn-On and Upper Turn-Off 2 15 ns tMOFF Delay Matching: Lower Turn-Off and Upper Turn-On 2 15 ns tRC, tFC Either Output Rise/Fall Time 15 - ns tPW Minimum Input Pulse Width that Changes the Output tBS Bootstrap Diode Turn-Off Time (1) CL = 1000 pF IF = 100 mA, IR = 100 mA 50 ns 105 ns Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LM5107 5 LM5107 SNVS333D – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics VDD Operating Current vs Frequency 100 HB Operating Current vs Frequency 100 VDD = VHB = 12V VDD = VHB = 12V VSS = VHS = 0V VSS = VHS = 0V 10 10 IDDO (mA) CL = 2200 pF IDDO (mA) CL = 1000 pF CL = 1000 pF CL = 4400 pF CL = 2200 pF CL = 4400 pF 1 1 CL = 0 pF 0.1 CL = 0 pF CL = 470 pF CL = 470 pF 0.1 0.01 1 10 100 1000 1 10 FREQUENCY (kHz) 100 1000 FREQUENCY (kHz) Figure 3. Figure 4. Operating Current vs Temperature Quiescent Current vs Temperature 0.45 2.4 0.40 IDDO 0.35 CL = 0 pF f = 500 kHz 2.0 IDD, IHB (mA) IDDO, IHBO (mA) 2.2 VDD = VHB = 12V 1.8 VSS = VHS = 0V 1.6 IHBO IDDO 0.30 0.25 LI = HI = 0V VDD = VHB = 12V 0.20 VSS = VHS = 0V 0.15 0.10 1.4 IHBO 0.05 0.00 -40 -25 -10 5 20 35 50 65 80 95 110 125 1.2 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (oC) TEMPERATURE (oC) Figure 5. Figure 6. Quiescent Current vs Voltage Propagation Delay vs Temperature 600 44 CL = 0 pF VDD = VHB VDD = VHB = 12V CURRENT (PA) VSS= VHS = 0V PROPAGATION DELAY (ns) 500 LI = HI = 0V IDD 400 300 200 IHB 100 0 8 10 12 14 16 18 VDD, VHB (V) VSS = VHS = 0V 36 turn off 32 tHPLH 28 24 tLPLH turn on 20 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (oC) Figure 7. 6 40 tLPHL tHPHL Figure 8. Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LM5107 LM5107 www.ti.com SNVS333D – NOVEMBER 2004 – REVISED MARCH 2013 Typical Performance Characteristics (continued) LO and HO High Level Output Voltage vs Temperature LO and HO Low Level Output Voltage vs Temperature 0.5 0.9 Output Current : -100 mA 0.8 VSS = VHS = 0V Output Current : -100 mA VSS = VHS = 0V 0.4 0.7 VDD = VHB = 8V 0.6 VOL (V) VOH (V) VDD = VHB = 8V 0.5 0.3 VDD = VHB = 12V 0.4 VDD = VHB = 12V 0.3 0.2 VDD = VHB =16V 0.2 VDD = VHB =16V 0.1 -40 -25 -10 5 20 35 50 65 80 95 110 125 0.1 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (oC) TEMPERATURE (oC) Figure 9. Figure 10. HO and LO Peak Output Current vs Output Voltage Doide Forward Voltage 1.6 1.00E-01 VDD = VHB = 12V VSS = VHS = 0V 25°C 1 1.00E-03 0.8 Pull-up Current -40°C 1.00E-04 0.6 0.4 1.00E-05 0.2 Pull-down Current 0 0 2 4 6 8 10 12 1.00E-06 0.2 VLO, VHO (V) 0.6 0.7 0.8 0.9 Undervoltage Hysteresis vs Temperature VDDR = VDD - VSS 0.48 VHBR = VHB - VHS 0.46 6.8 6.7 0.5 0.50 HYSTERESIS (V) 6.9 0.4 Figure 12. Undervoltage Rising Thresholds vs Temperature 7.0 0.3 FORWARD VOLTAGE Figure 11. THRESHOLD (V) 150°C 1.00E-02 1.2 ID (A) OUTPUT CURRENTS (A) 1.4 VDDR VHBR 6.6 0.44 VDDH 0.42 0.40 0.38 VHBH 0.36 6.5 0.34 6.4 0.32 6.3 -40 -25 -10 5 20 35 50 65 80 95 110 125 0.30 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (oC) TEMPERATURE (oC) Figure 13. Figure 14. Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LM5107 7 LM5107 SNVS333D – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Input Thresholds vs Temperature Input Thresholds vs Supply Voltage 1.92 VDD = 12V 1.95 INPUT THRESHOLD VOLTAGE (V) INPUT THRESHOLD VOLTAGE (V) 2.00 VSS = 0V Rising 1.90 1.85 Falling 1.80 1.75 1.91 1.89 1.88 1.87 1.86 1.85 Falling 1.84 1.83 1.82 1.81 1.70 1.80 -40 -25 -10 5 20 35 50 65 80 95 110 125 8 9 10 11 12 13 14 15 16 VDD (V) TEMPERATURE (oC) Figure 15. 8 Rising 1.90 Figure 16. Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LM5107 LM5107 www.ti.com SNVS333D – NOVEMBER 2004 – REVISED MARCH 2013 Timing Diagram LI LI HI tHPLH tLPLH HI tHPHL tLPHL LO LO HO HO tMON tMOFF Figure 17. Layout Considerations The optimum performance of high and low side gate drivers cannot be achieved without taking due considerations during circuit board layout. Following points are emphasized. 1. A low ESR / ESL capacitor must be connected close to the IC, and between VDD and VSS pins and between HB and HS pins to support high peak currents being drawn from VDD during turn-on of the external MOSFET. 2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be connected between MOSFET drain and ground (VSS). 3. In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances in the source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized. 4. Grounding Considerations: – The first priority in designing grounding connections is to confine the high peak currents from charging and discharging the MOSFET gate in a minimal physical area. This will decrease the loop inductance and minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as possible to the gate driver. – The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground referenced bypass capacitor and low side MOSFET body diode. The bootstrap capacitor is recharged on the cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation. HS Transient Voltages Below Ground The HS node will always be clamped by the body diode of the lower external FET. In some situations, board resistances and inductances can cause the HS node to transiently swing several volts below ground. The HS node can swing below ground provided: 1. HS must always be at a lower potential than HO. Pulling HO more than -0.3V below HS can activate parasitic transistors resulting in excessive current to flow from the HB supply possibly resulting in damage to the IC. The same relationship is true with LO and VSS. If necessary, a Schottky diode can be placed externally between HO and HS or LO and GND to protect the IC from this type of transient. The diode must be placed as close to the IC pins as possible in order to be effective. 2. HB to HS operating voltage should be 15V or less . Hence, if the HS pin transient voltage is -5V, VDD should be ideally limited to 10V to keep HB to HS below 15V. 3. A low ESR bypass capacitor between HB to HS as well as VDD to VSS is essential for proper operation. The Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LM5107 9 LM5107 SNVS333D – NOVEMBER 2004 – REVISED MARCH 2013 www.ti.com capacitor should be located at the leads of the IC to minimize series inductance. The peak currents from LO and HO can be quite large. Any series inductances with the bypass capacitor will cause voltage ringing at the leads of the IC which must be avoided for reliable operation. 10 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LM5107 LM5107 www.ti.com SNVS333D – NOVEMBER 2004 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision C (March 2013) to Revision D • Page Changed layout of National Data Sheet to TI format ............................................................................................................ 9 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LM5107 11 PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) LM5107MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5107 MA LM5107MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5107 MA LM5107SD/NOPB ACTIVE WSON NGT 8 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L5107SD LM5107SDX/NOPB ACTIVE WSON NGT 8 4500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L5107SD (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM5107MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5107SD/NOPB WSON NGT 8 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5107SDX/NOPB WSON NGT 8 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5107MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM5107SD/NOPB WSON NGT 8 1000 210.0 185.0 35.0 LM5107SDX/NOPB WSON NGT 8 4500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA NGT0008A SDC08A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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