ON MC100E431FNR2 3-bit differential flip-flop Datasheet

 SEMICONDUCTOR TECHNICAL DATA
The MC10E/100E431 is a 3-bit flip-flop with differential clock, data
input and data output.
The asynchronous Set and Reset controls are edge-triggered rather
than level controlled. This allows the user to rapidly set or reset the
flip-flop and then continue clocking at the next clock edge, without the
necessity of de-asserting the set/reset signal (as would be the case with a
level controlled set/reset).
The E431 is also designed with larger internal swings, an approach
intended to minimize the time spent crossing the threshold region and
thus reduce the metastability susceptibility window.
The differential input structures are clamped so that the inputs of
unused registers can be left open without upsetting the bias network of
the device. The clamping action will assert the D and the CLK sides of the
inputs. Because of the edge triggered flip-flop nature of the device
simultaneously opening both the clock and data inputs will result in an
output which reaches an unidentified but valid state. Note that the input
clamps only operate when both inputs fall to 2.5V below VCC.
•
•
•
•
3-BIT DIFFERENTIAL
FLIP-FLOP
Edge-Triggered Asynchronous Set and Reset
Differential D, CLK and Q; VBB Reference Available
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
1100MHz Min. Toggle Frequency
Extended 100E VEE Range of – 4.2V to – 5.46V
Pinout: 28-Lead PLCC (Top View)
VBB CLK2 CLK2
25
24
23
D2
D2
R2
S2
22
21
20
19
LOGIC DIAGRAM
CLK1
26
18
Q2
S0
CLK1
27
17
Q2
D0
D0
R1
28
16
VCC
VEE
1
15
Q1
S1
2
14
Q1
D1
3
13
Q0
D1
12
4
5
6
7
8
9
10
D
CLK0
CLK0
D0
D0
R0
S0
Pin
D[0:2], D[0:2]
CLK[0:2], CLK[0:2]
S[0:2]
R[0:2]
VBB
Q[0:2], Q[0:2]
Function
Differential Data Inputs
Differential Clock
Edge Triggered Set Inputs
Edge Triggered Reset Input
VBB Reference Output
Differential Data Outputs
2–1
Q
Q0
Q
Q1
Q0
11
Q
Q1
Q
Q2
Q
Q2
S1
D1
D1
D
VCCO
S
CLK1
R
R1
S2
D2
D2
D
S
CLK2
CLK2
R2
VBB
5/95
 Motorola, Inc. 1996
Q0
R0
* All VCC and VCCO pins are tied together on the die.
PIN NAMES
Q
R
CLK1
CLK0 CLK0
S
REV 3
R
MC10E431 MC100E431
FUNCTION TABLE
Dn
CLKn
Rn
Sn
Qn
L
H
X
X
Z
Z
X
X
L
L
Z
L
L
L
L
Z
L
H
L
H
Z = Low to high transition
X = Don’t Care
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
–40°C
Symbol
VBB
Characteristic
Output Reference
Voltage
10E
100E
IIH
Input HIGH
Current
IEE
Power Supply
Current
10E
100E
VCMR
Min
Typ
0°C
Max
Min
Typ
25°C
Max
Min
85°C
Typ
Max
Min
Typ
Max
Unit
Cond
V
–1.43
–1.38
–1.30
–1.26
–1.38
–1.38
–1.27
–1.26
150
Common Mode
Range
–1.35
–1.38
–1.25
–1.26
–1.31
–1.38
150
150
150
–1.19
–1.26
µA
mA
110
110
–1.5
132
132
110
110
0
–1.5
132
132
110
110
0
132
132
–1.5
110
127
0
132
152
–1.5
0
V
1
1. VCMR is referenced to the most positive side of the differential input signal. Normal specified operation is obtained when the input signals are
within the VCMR range and the input swing is greater than VPP.
AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
–40°C
Symbol
Characteristic
Min
Typ
fMAX
tPLH
tPHL
Maximum Toggle Frequency
1000
1400
CLK (Diff)
CLK (SE)
R
S
410
460
500
500
600
600
725
725
tS
Setup Time
D
R
S
250
1100
1100
D
250
CLK
400
Propagation Delay to Output
tH
tPW
Hold Time
tskew
VPP
Within-Device Skew
Minimum Pulse Width
Minimum Input Swing
0°C to 85°C
Max
Min
Typ
1100
1400
450
400
550
550
600
600
725
725
0
700
700
200
1000
1000
0
700
700
ps
0
200
0
ps
790
840
975
975
400
50
150
Unit
Condition
MHz
750
800
925
925
ps
1
1
ps
50
150
Max
ps
2
mV
3
tr/tf
Rise/Fall Times
250
450
700
275
450
650
ps
20–80%
1. These setup times define the minimum time the CLK or SET/RESET input must wait after the assertion of the RESET/SET input to assure the
proper operation of the flip-flop.
2. Within-device skew is defined as identical transitions on similar paths through a device.
3. Minimum input swing for which AC parameters are guaranteed.
MOTOROLA
2–2
ECLinPS and ECLinPS Lite
DL140 — Rev 4
MC10E431 MC100E431
OUTLINE DIMENSIONS
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776–02
ISSUE D
0.007 (0.180)
B
Y BRK
-N-
T L –M
M
U
0.007 (0.180)
X
G1
M
S
N
T L –M
S
S
N
S
D
Z
-L-
-M-
D
W
28
V
1
C
A
0.007 (0.180)
M
R
0.007 (0.180)
M
T L –M
S
T L –M
S
N
S
N
S
H
S
N
S
0.007 (0.180)
M
T L –M
N
S
S
0.004 (0.100)
G
J
-T-
K
SEATING
PLANE
F
VIEW S
G1
T L –M
S
N
0.007 (0.180)
M
T L –M
S
N
S
VIEW S
S
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIM G1, TRUE POSITION TO BE MEASURED
AT DATUM -T-, SEATING PLANE.
3. DIM R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
ECLinPS and ECLinPS Lite
DL140 — Rev 4
T L –M
K1
E
S
S
VIEW D-D
Z
0.010 (0.250)
0.010 (0.250)
2–3
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485 0.495
0.485 0.495
0.165 0.180
0.090 0.110
0.013 0.019
0.050 BSC
0.026 0.032
0.020
—
0.025
—
0.450 0.456
0.450 0.456
0.042 0.048
0.042 0.048
0.042 0.056
—
0.020
2°
10°
0.410 0.430
0.040
—
MILLIMETERS
MIN
MAX
12.32 12.57
12.32 12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
—
0.64
—
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
—
0.50
2°
10°
10.42 10.92
1.02
—
MOTOROLA
MC10E431 MC100E431
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*MC10E431/D*
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ECLinPS and ECLinPS Lite
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