TI LMP8672MAX/NOPB Single, dual, and quad 40v low noise precision amplifier Datasheet

LMP8671, LMP8672, LMP8674
www.ti.com
SNOSB39B – JULY 2011 – REVISED MARCH 2013
Single, Dual, and Quad 40V Low Noise Precision Amplifiers
Check for Samples: LMP8671, LMP8672, LMP8674
FEATURES
DESCRIPTION
•
•
•
The LMP8671/2/4 combines great precision, low
noise and a large operating voltage range to provide
a high SNR and a wide dynamic range. Its AC
performance allows it to be used over a wide
frequency without degradation. It is the ideal choice
for applications requiring DC precision and low noise
such as precision PLL filters, multi feedback and multi
pole active filters, GPS receivers and precision
control loop systems. The LMP8671/2/4 offers an
extremely high open loop gain of 135dB, low voltage
noise density (2.5nV/√Hz), and a superb linearity of
0.000009%. These characteristics drastically reduce
gain error which is a challenge in accurate systems
requiring higher gains such as data acquisition
systems.
1
2
Output Short Circuit Protection
PSRR and CMRR Exceed 110dB
Best in Class Linearity (135dB)
APPLICATIONS
•
•
•
•
•
Low Noise Industrial Applications Including
Test, Measurement, and Ultrasound
Precision Active Filters
PLL Filters
4-20mA Current Loops
Motor Control
KEY SPECIFICATIONS
•
•
•
•
•
•
•
•
Input Offset Voltage 0.4mV
TC VOS 2μV/°C (max)
Power Supply Voltage Range ±2.5V to ±20V
Voltage Noise Density 2.5nV/√Hz
Slew Rate ±20V/μs
Gain Bandwidth Product 55MHz
Open Loop Gain 135dB
Input Bias Current 10nA
To ensure that the most challenging loads are driven
without compromise, the LMP8671/2/4 has a high
slew rate of ±20V/μs and an output current capability
of ±26mA.
The LMP8671/2 family of high-voltage amplifiers are
available in SOIC-8, the LMP8674 in SOIC-14.
Connection Diagrams
NC
-IN
+IN
V-
NC
-
V+
+
VOUT
NC
Figure 1. See Package Number — D0008A
Figure 2. See Package Number — D0008A
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
LMP8671, LMP8672, LMP8674
SNOSB39B – JULY 2011 – REVISED MARCH 2013
www.ti.com
Figure 3. See Package Number — D0014A
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2) (3)
Power Supply Voltage (VS = V+ - V-)
46V
−65°C to 150°C
Storage Temperature
Input Voltage
(V-) - 0.7V to (V+) + 0.7V
Output Short Circuit (4)
Continuous
Power Dissipation
Internally Limited
ESD Rating (5)
2000V
ESD Rating (6)
Pins 1, 4, 7 and 8
200V
Pins 2, 3, 5 and 6
100V
Junction Temperature
150°C
θJA (SO)
Thermal Resistance
145°C/W
For soldering specifications, http://www.ti.com/lit/SNOA549
(1)
(2)
(3)
(4)
(5)
(6)
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings,
whichever is lower.
Human body model, applicable std. JESD22-A114C.
Machine model, applicable std. JESD22-A115-A.
Operating Ratings
Temperature Range TMIN ≤ TA ≤ TMAX
−40°C ≤ TA ≤ 125°C
±2.5V ≤ VS ≤ ±22V
Supply Voltage Range LMP8671/2/4
2
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SNOSB39B – JULY 2011 – REVISED MARCH 2013
Electrical Characteristics for the LMP8671/2/4 (1)
The following specifications apply for VS = ±20V, RL = 2kΩ, RSOURCE = 10Ω, fIN = 1kHz, TA = 25°C, unless otherwise specified.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
VOS
Offset Voltage
ΔVOS/ΔTemp
Average Input Offset Voltage Drift
vs Temperature
–40°C ≤ TA ≤ 125°C
LMP8671/2/4
Units
(Limits)
Typical (2)
Limit (3)
±100
±400
±750
μV (max)
0.1
2
μV/°C
(max)
10
±75
±95
nA (max)
50
±200
±250
nA (max)
11
±50
±95
nA (max)
25
±100
±125
nA (max)
VCM = 0V
LMP8671/4
IB
Input Bias Current
VCM = 0V
LMP8672
VCM = 0V
LMP8671/4
IOS
Input Offset Current
VCM = 0V
LMP8672
ΔIOS/ΔTemp
Input Bias Current Drift
vs Temperature
VIN-CM
Common-Mode Input Voltage Range
–40°C ≤ TA ≤ 125°C
Differential Input Impedance
0.2
nA/°C
+17.1
–16.9
V (min)
V (min)
30
kΩ
Common Mode Input Impedance
–10V<Vcm<10V
1000
MΩ
Equivalent Input Noise Voltage
20Hz to 20kHz
0.34
0.65
μVRMS
(max)
Equivalent Input Noise Density
f = 1kHz
2.5
4.7
nV/√Hz
(max)
in
Current Noise Density
f = 1kHz
f = 10Hz
1.6
3.1
THD+N
Total Harmonic Distortion + Noise
AV = 1, VOUT = 3Vrms, RL = 600Ω
tS
Settling time
AV = –1, 10V step, CL = 100pF
0.1% error range
GBWP
Gain Bandwidth Product
SR
Slew Rate
PSRR
Average Input Offset Voltage Shift
vs Power Supply Voltage
See
CMRR
Common-Mode Rejection
AVOL
ZIN
en
0.00003
pA/√Hz
0.00009
% (max)
μs
1.2
55
45
MHz (min)
±20
±15
V/μs (min)
125
110
100
dB (min)
–15V≤Vcm≤15V
115
105
100
dB (min)
Open Loop Voltage Gain
–15V ≤ Vout ≤ 15V
RL = 2kΩ
135
125
dB (min)
VOUTMAX
Maximum Output Voltage Swing
RL = 2kΩ
±19.0
±18.8
±18.6
V (min)
IOUT-CC
Instantaneous Short Circuit Current
(1)
(2)
(3)
(4)
(4)
+53
–42
mA
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
Datasheet min/max specification limits are ensured by test or statistical analysis.
PSRR is measured as follows: For VS, VOS is measured at two supply voltages, ±5V and ±20V, PSRR = |20log(ΔVOS/ΔVS)|.
Copyright © 2011–2013, Texas Instruments Incorporated
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Electrical Characteristics for the LMP8671/2/4(1) (continued)
The following specifications apply for VS = ±20V, RL = 2kΩ, RSOURCE = 10Ω, fIN = 1kHz, TA = 25°C, unless otherwise specified.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
LMP8671/2/4
Conditions
Typical (2)
Limit (3)
Units
(Limits)
ROUT
Output Impedance
fIN = 10kHz
Closed-Loop
Open-Loop
0.01
13
IOUT
Output Current
RL = 2kΩ
9.5
9.3
mA (min)
LMP8671
5
6
8
mA (max)
LMP8672
12.5
16
mA (max)
LMP8674
20
22
mA (max)
Ω
IOUT = 0mA
IS
4
Total Quiescent Current
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SNOSB39B – JULY 2011 – REVISED MARCH 2013
Typical Performance Characteristics
0.001
THD+N vs Frequency
+VCC = –VEE = 15V, VO = 3VRMS,
RL = 600Ω
THD+N vs Output Voltage
VCC = 2.5V, VEE = –2.5V, RL = 600 Ω
0.01
0.005
0.0005
THD+N (%)
THD+N (%)
0.002
0.0002
0.0001
0.001
0.0005
0.0002
0.00005
0.0001
0.00005
0.00002
0.00002
0.00001
20
50 100 200 500 1k 2k
0.00001
10m
5k 10k 20k
100m
FREQUENCY (Hz)
1
10 20
VRMS
Figure 4.
Figure 5.
PSRR+ vs Frequency
VCC = 2.5V, VEE = –2.5V,
RL = 2kΩ, VRIPPLE = 200mVPP
PSRR– vs Frequency
VCC = 2.5V, VEE = –2.5V,
RL = 2kΩ, VRIPPLE = 200mVPP
40
-40
50
-50
60
-60
70
PSRR (dB)
PSRR (dB)
-70
-80
-90
80
90
100
-100
110
-110
120
-120
130
-130
140
20
-140
20
100
100
10k 20k
1k
1k
10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
-60
Figure 6.
Figure 7.
PSRR+ vs Frequency
VCC = 15V, VEE = –15V,
RL = 2kΩ, VRIPPLE = 200mVPP
PSRR– vs Frequency
VCC = 15V, VEE = –15V,
RL = 2kΩ, VRIPPLE = 200mVPP
-60
-70
-70
-80
-80
-90
PSRR (dB)
PSRR (dB)
-90
-100
-110
-120
-100
-110
-120
-130
-130
-140
-140
-150
-150
-160
20
100
10k 20k
1k
-160
20
FREQUENCY (Hz)
Figure 8.
100
1k
10k 20k
FREQUENCY (Hz)
Figure 9.
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Typical Performance Characteristics (continued)
PSRR– vs Frequency
VCC = 15V, VEE = –15V,
RL = 600Ω, VRIPPLE = 200mVPP
-40
40
-50
50
-60
60
-70
70
PSRR (dB)
PSRR (dB)
PSRR+ vs Frequency
VCC = 15V, VEE = –15V,
RL = 600Ω, VRIPPLE = 200mVPP
-80
-90
-100
80
90
100
-110
110
-120
120
-130
130
-140
20
100
140
20
10k 20k
1k
100
10k 20k
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 10.
Figure 11.
CMRR vs Frequency
VCC = 15V, VEE = –15V, RL = 600Ω
CMRR vs Frequency
VCC = 15V, VEE = –15V, RL = 2kΩ
0
0
-10
-20
-30
-40
CMRR (dB)
CMRR (dB)
-50
-100
-50
-60
-70
-80
-90
-100
-110
-120
-150
10
-130
100
1k
10k
10
100k
100
100k
FREQUENCY (Hz)
Figure 13.
CMRR vs Frequency
VCC = 2.5V, VEE = –2.5V, RL = 600Ω
CMRR vs Frequency
VCC = 2.5V, VEE = –2.5V, RL = 2kΩ
0
0
-50
-50
-100
-150
10
6
10k
Figure 12.
CMRR (dB)
CMRR (dB)
FREQUENCY (Hz)
1k
100
1k
10k
100k
-100
-150
10
100
1k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 14.
Figure 15.
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SNOSB39B – JULY 2011 – REVISED MARCH 2013
Typical Performance Characteristics (continued)
Output Voltage vs Supply Voltage
THD+N = 1%, RL = 600Ω
12
12
10
10
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Output Voltage vs Supply Voltage
THD+N = 1%, RL = 2kΩ
8
6
4
8
6
4
2
2
0
2.5
4.5
6.5
0
2.5
8.5 10.5 12.5 14.5 16.5 18.5
4.5
SUPPLY VOLTAGE (V)
6.5
8.5 10.5 12.5 14.5 16.5 18.5
SUPPLY VOLTAGE (V)
Figure 16.
Figure 17.
Crosstalk vs Frequency
VCC = 15V, VEE = –15V, RL = 2kΩ
Full Power Bandwidth vs Frequency
2
0
0 dB = 1 VPP
MAGNITUDE (dB)
-2
-4
-6
-8
-10
-12
-14
1
10
100
1k
10k 100k 1M
10M 100M
FREQUENCY (Hz)
Figure 18.
Figure 19.
Gain Phase vs Frequency
Voltage Noise Density vs Frequency
100
160
VS = 30V
140
VCM = 15V
VOLTAGE NOISE (nV/ Hz)
GAIN (dB), PHASE LAG (q
180
120
100
80
60
40
10
20
0
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 20.
Figure 21.
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Typical Performance Characteristics (continued)
Current Noise Density vs Frequency
CURRENT NOISE (pA/ Hz)
100
VS = 30V
VCM = 15V
10
1.5 pA/ Hz
1
1
10
100
10k
1k
100k
FREQUENCY (Hz)
Figure 22.
Offset Voltage Distribution
VCC = ±20V
45
40
Percentage (%)
35
30
25
20
15
10
5
0
0
0
40
0
-0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1
16
12
0
10
80
40
40
0
20
-2
0
-4
0
-6
0
00
-8
0
-1
40
20
-1
60
-1
-1
-4
00
0
Vos (uV)
Figure 23.
TcVos Distribution
VCC = ±20V
80
70
Percentage (%)
60
50
40
30
20
10
0
-2
-1.2 -1.1
-1
0.1
2
TcVos (uV/C)
Figure 24.
8
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SNOSB39B – JULY 2011 – REVISED MARCH 2013
REVISION HISTORY
Changes from Revision A (March 2013) to Revision B
•
Page
Changed layout of National Data Sheet to TI format ............................................................................................................ 8
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PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
LMP8671MA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMP86
71MA
LMP8671MAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMP86
71MA
LMP8672MA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMP86
72MA
LMP8672MAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMP86
72MA
LMP8674MA/NOPB
ACTIVE
SOIC
D
14
55
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMP8674
MA
LMP8674MAX/NOPB
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMP8674
MA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
LMP8671MAX/NOPB
SOIC
D
LMP8672MAX/NOPB
SOIC
LMP8674MAX/NOPB
SOIC
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
5.4
2.0
8.0
12.0
Q1
8
2500
330.0
12.4
6.5
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMP8671MAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LMP8672MAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LMP8674MAX/NOPB
SOIC
D
14
2500
367.0
367.0
35.0
Pack Materials-Page 2
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