ICST ICS83904AG-02T Low skew, 1-to-4 crystal-to-lvcmos/lvttl fanout buffer Datasheet

PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83904-02
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS83904-02 is a low skew, high performance 1-to-4 Crystal Oscillator/Crystal-toHiPerClockS™ LVCMOS Fanout Buffer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS83904-02 has
selectable single ended clock or two crystal-oscillator inputs.
There is an output enable to disable the outputs by placing them
into a high-impedance state.
• Four LVCMOS/LVTTL outputs,
19Ω typical output impedance
ICS
• Two Crystal oscillator input pairs
One LVCMOS/LVTTL clock input
• Crystal input frequencry range: 10MHz - 40MHz
• Output frequency: 200MHz (typical)
• Output Skew: TBD
Guaranteed output and part-to-part skew characteristics
make the ICS83904-02 ideal for those applications demanding
well defined performance and repeatability.
• Part to Part Skew: TBD
• RMS phase jitter @ 25MHz output, using a 25MHz crystal
(100Hz - 1MHz): 0.16ps (typical) @ VDD = VDDO = 3.3V
• RMS phase noise at 25MHz:
Offset
Noise Power
100Hz .............. -118.4 dBc/Hz
1kHz .............. -141.5 dBc/Hz
10kHz .............. -157.2 dBc/Hz
100kHz .............. -157.2 dBc/Hz
• Supply Voltage Modes:
(Core/Output)
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
BLOCK DIAGRAM
OE
CLK_SEL0
• 0°C to 70°C ambient operating temperature
Pullup
• Industrial temperature available upon request
Pulldown
CLK_SEL1 Pulldown
XTAL_IN0
PIN ASSIGNMENT
OSC
0 0
XTAL_OUT0
Q0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDDO
Q0
Q1
GND
Q2
Q3
VDDO
OE
ICS83904-02
XTAL_IN1
OSC
4 LVCMOS Outputs
0 1
XTAL_OUT1
Q3
CLK
CLK_SEL0
XTAL_OUT0
XTAL_IN0
VDD
XTAL_IN1
XTAL_OUT1
CLK_SEL1
CLK
Pulldown
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
1 0
1 1
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
83904AG-02
www.icst.com/products/hiperclocks.html
1
REV. A JULY 8, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83904-02
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
8
Name
CLK_SEL0,
CLK_SEL1
XTAL_OUT0,
XTAL_IN0
VDD
XTAL_IN1,
XTAL_OUT1
CLK
9
OE
1, 7
2, 3
4
5, 6
Type
Description
Clock select inputs. See Table 3, Input Reference Function Table.
Pulldown
LVCMOS / LVTTL interface levels.
Cr ystal oscillator interface. XTAL_IN0 is the input.
XTAL_OUT0 is the output.
Core supply pin.
Cr ystal oscillator interface. XTAL_IN1 is the input.
XTAL_OUT1 is the output.
Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
Output enable. When LOW, outputs are in HIGH impedance state.
Pullup
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
Output supply pins.
Input
Input
Power
Input
Input
Input
10, 16
VDDO
Power
11, 12, 14, 15
Q3, Q2, Q1, Q0
Output
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
13
GND
Power
Power supply ground.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
CPD
Power Dissipation Capacitance
(per output)
ROUT
Output Impedance
VDDO = 3.465V
8
pF
VDDO = 2.625V
7
pF
VDDO = 2.0V
7
pF
VDDO = 3.3V ± 5%
19
Ω
VDDO = 2.5V ± 5%
TBD
Ω
VDDO = 1.8V ± 0.2V
TBD
Ω
TABLE 3. INPUT REFERENCE FUNCTION TABLE
Control Inputs
CLK_SEL1
CLK_SEL0
0
0
Reference
XTAL0 (default)
0
1
XTAL1
1
0
CLK
1
1
CLK
83904AG-02
www.icst.com/products/hiperclocks.html
2
REV. A JULY 8, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83904-02
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDDO + 0.5V
Package Thermal Impedance, θJA
89°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
3.135
3.3
3.465
V
VDDO
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
28
mA
IDDO
Output Supply Current
50
mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
3.135
3.3
3.465
V
VDDO
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
28
mA
IDDO
Output Supply Current
33
mA
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol
Parameter
VDD
Core Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
1.6
1.8
2.0
VDDO
Output Supply Voltage
IDD
Power Supply Current
29
mA
V
IDDO
Output Supply Current
25
mA
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD
VDDO
Core Supply Voltage
2.375
2. 5
2.625
V
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
15
mA
IDDO
Output Supply Current
41
mA
TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
2.375
2.5
2.625
V
1.6
1.8
2.0
V
VDD
Core Supply Voltage
VDDO
Output Supply Voltage
IDD
Power Supply Current
15
mA
IDDO
Output Supply Current
32
mA
83904AG-02
www.icst.com/products/hiperclocks.html
3
REV. A JULY 8, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83904-02
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 4F. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C
Symbol
VIH
VIL
IIH
IIL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
VOH
CLK,
CLK_SEL0:1
OE
CLK,
CLK_SEL0:1
OE
Output HighVoltage
Test Conditions
Minimum
Maximum
Units
VDD = 3.3V ± 5%
2.0
Typical
VDD + 0.3
V
VDD = 2.5V ± 5%
1.7
VDD + 0.3
V
VDD = 3.3V ± 5%
-0.3
0. 8
V
VDD = 2.5V ± 5%
-0.3
0. 7
V
VDD = 3.3V or 2.5V ± 5%
150
µA
VDD = 3.3V or 2.5V ± 5%
5
µA
VDD = 3.3V or 2.5V ± 5%
-5
µA
VDD = 3.3V or 2.5V ± 5%
-150
µA
VDDO = 3.3V ± 5%; NOTE 1
2.6
V
VDDO = 2.5V ± 5%; NOTE 1
1.8
V
VDDO = 1.8V ± 0.2V; NOTE 1
1.5
V
VDDO = 3.3V ± 5%; NOTE 1
VOL
Output Low Voltage
0.5
V
VDDO = 2.5V ± 5%; NOTE 1
0.5
V
VDDO = 1.8V ± 0.2V; NOTE 1
0. 4
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation / cut
Typical Maximum
Units
Fundamental
Frequency
40
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
83904AG-02
10
www.icst.com/products/hiperclocks.html
4
REV. A JULY 8, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83904-02
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 6A. AC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = 0°C TO 70°C
Symbol Parameter
fMAX
tpLH
t sk(o)
t sk(pp)
Output Frequency
Test Conditions
w/External XTAL
tR / tF
odc
Output Duty Cycle
tEN
Output Enable Time; NOTE 5
Typical
Maximum
Units
40
MHz
10
w/External CLK
Propagation Delay, Low-to-High;
NOTE 1
Output Skew; NOTE 2
Par t-to-Par t Skew; NOTE 2, 3
RMS Phase Jitter, Random;
NOTE 2, 4
Output Rise/Fall Time
tjit(Ø)
Minimum
25MHz, Integration Range:
100Hz - 1MHz
20% to 80%
200
MH z
1.8
ns
TBD
ps
TBD
ps
0.16
ps
420
ps
50
%
10
ns
8
ns
Maximum
Units
40
MHz
Output Disable Time; NOTE 5
tDIS
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
TABLE 6B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0°C TO 70°C
Symbol Parameter
fMAX
tpLH
t sk(o)
t sk(pp)
Output Frequency
Test Conditions
w/External XTAL
tR / tF
odc
Output Duty Cycle
tEN
Output Enable Time; NOTE 5
tjit(Ø)
Typical
10
w/External CLK
Propagation Delay, Low-to-High;
NOTE 1
Output Skew; NOTE 2
Par t-to-Par t Skew; NOTE 2, 3
RMS Phase Jitter, Random;
NOTE 2, 4
Output Rise/Fall Time
Minimum
25MHz, Integration Range:
100Hz - 1MHz
20% to 80%
200
MH z
2
ns
TBD
ps
TBD
ps
0.16
ps
440
ps
50
%
Output Disable Time; NOTE 5
tDIS
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
83904AG-02
www.icst.com/products/hiperclocks.html
5
10
ns
8
ns
REV. A JULY 8, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83904-02
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 6C. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter
fMAX
tpLH
t sk(o)
t sk(pp)
Output Frequency
Test Conditions
w/External XTAL
tR / tF
odc
Output Duty Cycle
tEN
Output Enable Time; NOTE 5
Typical
Maximum
Units
40
MHz
10
w/External CLK
Propagation Delay, Low-to-High;
NOTE 1
Output Skew; NOTE 2
Par t-to-Par t Skew; NOTE 2, 3
RMS Phase Jitter, Random;
NOTE 2, 4
Output Rise/Fall Time
tjit(Ø)
Minimum
25MHz, Integration Range:
100Hz - 1MHz
20% to 80%
200
MH z
2.3
ns
TBD
ps
TBD
ps
0.16
ps
490
ps
50
%
10
ns
8
ns
Maximum
Units
40
MHz
Output Disable Time; NOTE 5
tDIS
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
TABLE 6D. AC CHARACTERISTICS, VDD = VDDO = 2.5V ± 5%, TA = 0°C TO 70°C
Symbol Parameter
fMAX
tpLH
t sk(o)
t sk(pp)
Output Frequency
Test Conditions
w/External XTAL
tR / tF
odc
Output Duty Cycle
tEN
Output Enable Time; NOTE 5
tjit(Ø)
Typical
10
w/External CLK
Propagation Delay, Low-to-High;
NOTE 1
Output Skew; NOTE 2
Par t-to-Par t Skew; NOTE 2, 3
RMS Phase Jitter, Random;
NOTE 2, 4
Output Rise/Fall Time
Minimum
25MHz, Integration Range:
100Hz - 1MHz
20% to 80%
200
MH z
2.1
ns
TBD
ps
TBD
ps
0.20
ps
448
ps
50
%
Output Disable Time; NOTE 5
tDIS
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
83904AG-02
www.icst.com/products/hiperclocks.html
6
10
ns
8
ns
REV. A JULY 8, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83904-02
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 6E. AC CHARACTERISTICS, VDD = 2.5V ± 5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter
fMAX
tpLH
t sk(o)
t sk(pp)
Output Frequency
Test Conditions
w/External XTAL
tR / tF
odc
Output Duty Cycle
tEN
Output Enable Time; NOTE 5
tjit(Ø)
Typical
Maximum
Units
40
MHz
10
w/External CLK
Propagation Delay, Low-to-High;
NOTE 1
Output Skew; NOTE 2
Par t-to-Par t Skew; NOTE 2, 3
RMS Phase Jitter, Random;
NOTE 2, 4
Output Rise/Fall Time
Minimum
25MHz, Integration Range:
100Hz - 1MHz
20% to 80%
200
MH z
2.4
ns
TBD
ps
TBD
ps
0.19
ps
490
ps
50
%
Output Disable Time; NOTE 5
tDIS
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
83904AG-02
www.icst.com/products/hiperclocks.html
7
10
ns
8
ns
REV. A JULY 8, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83904-02
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
25MHz
RMS Phase Jitter (Random)
100Hz to 1MHz = 0.16ps (typical)
Raw Phase Noise Data
➤
NOISE POWER dBc
Hz
TYPICAL PHASE NOISE AT 25MHZ
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
OFFSET FREQUENCY (HZ)
83904AG-02
www.icst.com/products/hiperclocks.html
8
REV. A JULY 8, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83904-02
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V±5%
1.25V±5%
SCOPE
VDD,
VDDO
LVCMOS
SCOPE
VDD ,
VDDO
Qx
Qx
LVCMOS
GND
GND
-1.65V±5%
-1.25V±5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.05V±5%
2.4V±0.065V 0.9V±0.1V
1.25V±5%
SCOPE
VDD
VDDO
LVCMOS
SCOPE
VDD
VDDO
Qx
Qx
LVCMOS
GND
GND
-0.9V±0.1V
-1.25V±5%
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
1.6V±0.025V 0.9V±0.1V
Part 1
SCOPE
V DD
VDDO
LVCMOS
V
Qx
DDO
2
Qx
Part 2
GND
Qy
V
DDO
2
tsk(pp)
-0.9V±0.1V
2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
83904AG-02
PART-TO-PART SKEW
www.icst.com/products/hiperclocks.html
9
REV. A JULY 8, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
VDD
CLK
ICS83904-02
80%
80%
tR
tF
2
VDDO
Q0:Q3
Clock
Outputs
2
tpLH
PROPAGATION DELAY
20%
20%
OUTPUT RISE/FALL TIME
V
DDO
2
Q0:Q3
t PW
t
odc =
PERIOD
t PW
x 100%
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
83904AG-02
www.icst.com/products/hiperclocks.html
10
REV. A JULY 8, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83904-02
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
APPLICATION INFORMATION
CRYSTAL INPUT INTERFACE
suitable for most applications. Additional accuracy can be
achieved by adding two small capacitors C1 and C2 as shown in
Figure 1. Typical results using parallel 18pF crystals are shown
in Table 5.
A crystal can be characterized for either series or parallel mode
operation. The ICS83904-02 has a built-in crystal oscillator circuit.
This interface can accept either a series or parallel crystal without
additional components and generate frequencies with accuracy
XTAL_OUT
C1
15p
X1
18pF Parallel Crystal
XTAL_IN
C2
15p
Figure 1. Crystal Input Interface
83904AG-02
www.icst.com/products/hiperclocks.html
11
REV. A JULY 8, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83904-02
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating. Though
not required, but for additional protection, a 1kΩ resister can be
tied from XTAL_IN to ground.
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. We recommend
that there is no trace attached.
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
CLK INPUT:
For applications not requiring the use of the test clock, it can be
left floating. Though not required, but for additional protection, a
1kΩ resister can be tied from the CLK input to ground.
LVHSTL OUTPUT
All unused LVHSTL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
TEST CLK INPUT:
For applications not requiring the use of the test clock, it can be
left floating. Though not required, but for additional protection, a
1kΩ resister can be tied from the TEST_CLK to ground.
LVDS OUTPUT
All unused LVDS outputs should be terminated with 100Ω resister
between the differential pair.
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1kΩ resister can be tied from CLK
to ground.
LVDS – Like OUTPUT
All unused LVDS outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
PCLK/nPCLK INPUT:
For applications not requiring the use of a differential input, both
the PCLK and nPCLK pins can be left floating. Though not
required, but for additional protection, a 1kΩ resister can be tied
from PCLK to ground.
HCSL OUTPUT
All unused HCSL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
SELECT PINS:
All select pins have internal pull-ups and pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resister can be used.
SSTL OUTPUT
All unused SSTL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
83904AG-02
www.icst.com/products/hiperclocks.html
12
REV. A JULY 8, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83904-02
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
FOR
16 LEAD TSSOP
θ JA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
137.1°C/W
89.0°C/W
118.2°C/W
81.8°C/W
106.8°C/W
78.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83904-02 is: 205
83904AG-02
www.icst.com/products/hiperclocks.html
13
REV. A JULY 8, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX
ICS83904-02
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
FOR
16 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
N
Maximum
16
A
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
4.90
E
E1
5.10
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
α
0°
8°
aaa
--
0.10
0.75
Reference Document: JEDEC Publication 95, MO-153
83904AG-02
www.icst.com/products/hiperclocks.html
14
REV. A JULY 8, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83904-02
LOW SKEW, 1-TO-4
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS83904AG-02
83904A02
16 Lead TSSOP
tube
0°C to 70°C
ICS83904AG-02T
83904A02
16 Lead TSSOP
2500 tape & reel
0°C to 70°C
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
83904AG-02
www.icst.com/products/hiperclocks.html
15
REV. A JULY 8, 2005
Similar pages