NB3L553 2.5 V / 3.3 V / 5.0 V 1:4 Clock Fanout Buffer Description The NB3L553 is a low skew 1−to 4 clock fanout buffer, designed for clock distribution in mind. The NB3L553 specifically guarantees low output−to−output skew. Optimal design, layout and processing minimize skew within a device and from device to device. The output enable (OE) pin tri−states the outputs when low. http://onsemi.com MARKING DIAGRAMS* 8 8 Features Input/Output Clock Frequency up to 200 MHz Low Skew Outputs (35 ps) Output Enable Mode Three−States Outputs Operating Range: VDD = 2.375 V to 5.25 V Ideal for Networking Clocks Packaged in 8−pin SOIC Industrial Temperature Range These are Pb−Free Devices 3L553 ALYW G SOIC−8 D SUFFIX CASE 751 1 3N553 A L Y W G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XX MG G • • • • • • • • 1 1 Q1 DFN8 MN SUFFIX CASE 506AA Q2 CLK 1 4 XX = Specific Device Code M = Date Code (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. Q3 Q4 PINOUT OE Figure 1. Block Diagram VDD Q0 Q1 GND 1 8 2 7 3 6 4 5 OE Q3 Q2 ICLK ORDERING INFORMATION Package Shipping † NB3L553DG SOIC−8 (Pb−Free) 98 Units/Rail NB3L553DR2G SOIC−8 (Pb−Free) 2500/Tape & Reel NB3L553MNR4G* DFN−8 (Pb−Free) 1000/Tape & Reel Device *Contact Sales Representative †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2006 March, 2006 − Rev. 0 1 Publication Order Number: NB3L553/D NB3L553 OE Function 0 Disable 1 Enable Table 1. OE, Output Enable Function PIN DESCRIPTION Pin # Name Type Description 1 VDD Power 2 Q0 (LV)CMOS/(LV)TTL Output Clock Output 0 3 Q1 (LV)CMOS/(LV)TTL Output Clock Output 1 4 GND Power 5 ICLK (LV)CMOS/(LV)TTL Input 6 Q2 (LV)CMOS/(LV)TTL Output Clock Output 2 7 Q3 (LV)CMOS/(LV)TTL Output Clock Output 3 8 OE (LV)CMOS/(LV)TTL Input Positive supply voltage (2.375 V to 5.25 V) Negative supply voltage; Connect to ground, 0 V Clock Input. 5.0 V tolerant Output Enable for the clock outputs. Outputs are enabled when HIGH: connect to VDD for normal operation; OE pin has internal pull−up resistor. Three−states outputs when LOW. MAXIMUM RATINGS Symbol VDD Parameter Positive Power Supply Condition 1 Condition 2 Rating Units GND = 0 V − 6.0 V VI Input Voltage − − GND –0.5 ≤ VI ≤ VDD + 0.5 V TA Operating Temperature Range, Industrial − − ≥ −40 to ≤ +85 _C Tstg Storage Temperature Range − − −65 to +150 _C qJA Thermal Resistance (Junction−to−Ambient) 0 LFPM 500 LFPM SOIC−8 190 130 _C/W _C/W qJC Thermal Resistance (Junction−to−Case) (Note 1) SOIC−8 41 to 44 _C/W Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) ATTRIBUTES Characteristic ESD Protection Value Human Body Model Machine Model Charged Device Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2) Flammability Rating Oxygen Index: 28 to 34 Transistor Count > 2 kV > 150 V > TBD kV Level 1 UL−94 code V−0 @ 0.125 in 531 Devices Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test 2. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. http://onsemi.com 2 NB3L553 DC CHARACTERISTICS (VDD = 2.375 V to 2.625 V, GND = 0 V, TA = −40°C to +85°C) (Note 3) Symbol Characteristic IDD Power Supply Current @ 135 MHz, No Load VOH Output HIGH Voltage – IOH = −16 mA VOL Output LOW Voltage – IOL = 16 mA Min Typ Max Unit − 25 TBD mA 2.0 − − V − − 0.4 V VIH, ICLK Input HIGH Voltage, ICLK (VDD÷2)+0.5 − 3.8 V VIL, ICLK Input LOW Voltage, ICLK − − (VDD÷2)−0.5 V VIH, OE Input HIGH Voltage, OE 1.8 − VDD V VIL, OE Input LOW Voltage, OE − − 0.7 V ZO Nominal Output Impedance − 20 − W CIN Input Capacitance, ICLK, OE − 5.0 − pF IOS Short Circuit Current − ± 28 − mA Min Typ Max Unit − 35 TBD mA 2.4 − − V − − 0.4 V DC CHARACTERISTICS (VDD = 3.15 V to 3.45 V, GND = 0 V, TA = −40°C to +85°C) (Note 3) Symbol Characteristic IDD Power Supply Current @ 135 MHz, No Load VOH Output HIGH Voltage – IOH = −25 mA VOL Output LOW Voltage – IOL = 25 mA VOH Output HIGH Voltage – IOH = −12 mA (CMOS level) VDD − 0.4 − − V VIH, ICLK Input HIGH Voltage, ICLK (VDD÷2)+0.7 − 3.8 V VIL, ICLK Input LOW Voltage, ICLK − − (VDD÷2)−0.7 V VIH, OE Input HIGH Voltage, OE 2.0 − VDD V VIL, OE Input LOW Voltage, OE 0 − 0.8 V ZO Nominal Output Impedance − 20 − W CIN Input Capacitance, OE − 5.0 − pF IOS Short Circuit Current − ± 50 − mA Min Typ Max Unit − 45 TBD mA 2.4 − − V − − 0.4 V VDD − 0.4 − − V DC CHARACTERISTICS (VDD = 4.75 V to 5.25 V, GND = 0 V, TA = −40°C to +85°C) (Note 3) Symbol Characteristic IDD Power Supply Current @ 135 MHz, − No Load VOH Output HIGH Voltage – IOH = −35 mA VOL Output LOW Voltage – IOL = 35 mA VOH Output HIGH Voltage – IOH = −12 mA (CMOS level) VIH, ICLK Input HIGH Voltage, ICLK (VDD÷2) + 1 − 5.5 V VIL, ICLK Input LOW Voltage, ICLK − − (VDD÷2) − 1 V VIH, OE Input HIGH Voltage, OE 2.0 − VDD V VIL, OE Input LOW Voltage, OE − − 0.8 V ZO Nominal Output Impedance − 20 − W CIN Input Capacitance, OE − 5.0 − pF IOS Short Circuit Current − ± 80 − mA http://onsemi.com 3 NB3L553 AC CHARACTERISTICS; VDD = 2.5 V +5% (VDD = 2.375 V to 2.625 V, GND = 0 V, TA = −40°C to +85°C) (Note 3) Symbol Characteristic Min Typ Max Unit fin Input Frequency − − 200 MHz tr/tf Output rise and fall times; 0.8 V to 2.0 V − 1.0 1.5 ns tpd Propagation Delay, CLK to Qn (Note 4) 2.2 3.0 5.0 ns tskew Output−to−output skew; (Note 5) − 35 − ps tskew Device−to−device skew, (Note 5) − − 500 ps AC CHARACTERISTICS; VDD = 3.3 V +5% (VDD = 3.15 V to 3.45 V, GND = 0 V, TA = −40°C to +85°C) (Note 3) Symbol Characteristic Min Typ Max Unit − − 200 MHz fin Input Frequency tr/tf Output rise and fall times; 0.8 V to 2.0 V − 0.6 1.0 ns tpd Propagation Delay, CLK to Qn (Note 4) 2.0 2.4 4.0 ns tskew Output−to−output skew; (Note 5) − 35 50 ps tskew Device−to−device skew, (Note 5) − − 500 ps Typ Max Unit AC CHARACTERISTICS; VDD = 5.0 V +5% (VDD = 4.75 V to 5.25 V, GND = 0 V, TA = −40°C to +85°C) (Note 3) Symbol Characteristic Min fin Input Frequency − − 200 MHz tr/tf Output rise and fall times; 0.8 V to 2.0 V − 0.3 0.7 ns tpd Propagation Delay, CLK to Qn (Note 4) 1.8 2.5 4.0 ns tskew Output−to−output skew; (Note 5) − 35 − ps tskew Device−to−device skew, (Note 5) − − 500 ps 3. Outputs loaded with external RL = 33−W series resistor and CL = 15 pF to GND for proper operation. Duty cycle out = duty in. A 0.01 mF decoupling capacitor should be connected between VDD and GND. 4. Measured with rail−to−rail input clock 5. Measured on rising edges at VDD ÷ 2 between any two outputs with equal loading. http://onsemi.com 4 NB3L553 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AG −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 0.25 (0.010) S B 1 M Y M 4 K −Y− G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 5 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8 _ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 NB3L553 PACKAGE DIMENSIONS DFN8 CASE 506AA−01 ISSUE D D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A B PIN ONE REFERENCE 2X 0.10 C 2X 0.10 C ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ TOP VIEW 0.08 C SEATING PLANE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.10 1.30 2.00 BSC 0.70 0.90 0.50 BSC 0.20 −−− 0.25 0.35 A 0.10 C 8X DIM A A1 A3 b D D2 E E2 e K L E (A3) SIDE VIEW A1 C D2 e e/2 4 1 8X L E2 K 8 5 8X b 0.10 C A B 0.05 C NOTE 3 BOTTOM VIEW ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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