MOTOROLA MCM63Z916ZP11 256k x 36 and 512k x 18 bit zbt fast static ram Datasheet

Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
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256K x 36 and 512K x 18 Bit
ZBT Fast Static RAM
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by MCM63Z834/D
MCM63Z834
MCM63Z916
The ZBT RAM is an 8M–bit synchronous fast static RAM designed to provide
Zero Bus Turnaround. The ZBT RAM allows 100% use of bus cycles during
back–to–back read/write and write/read cycles. The MCM63Z834 (organized as
256K words by 36 bits) and the MCM63Z916 (organized as 512K words by 18
bits) are fabricated in Motorola’s high performance silicon gate CMOS technology. This device integrates input registers, an output register, a 2–bit address
counter, and high speed SRAM onto a single monolithic circuit for reduced parts
count in communication applications. Synchronous design allows precise cycle
control with the use of an external positive–edge–triggered clock (CK). CMOS
circuitry reduces the overall power consumption of the integrated functions for
greater reliability.
Addresses (SA), data inputs (DQ), and all control signals except output enable
(G) and linear burst order (LBO) are clock (CK) controlled through positive–
edge–triggered noninverting registers.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (CK) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals. Write data is
supplied to the memory one cycle after the write sequence initiation for the flow–
through device, and two cycles after the write sequence initiation for the pipelined
device.
For flow–through read cycles, the SRAM allows output data to simply flow freely from the memory
array. For pipelined read cycles, the SRAM output data is temporarily stored by an edge–triggered
output register and then released to the output buffers at the next rising edge of clock (CK).
The MCM63Z834 and MCM63Z916 operate from a 3.3 V core power supply and all outputs operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC Standard JESD8–A and
JESD8–5 compatible.
TQ PACKAGE
TQFP
CASE 983A–01
ZP PACKAGE
PBGA
CASE 999–02
• 3.3 V ±5% Core Power Supply, 2.5 V or 3.3 V I/O Supply
• MCM63Z834 / 916–10 = 10 ns Flow–Through Access / 4 ns Pipelined Access (143 MHz)
MCM63Z834 / 916–11 = 11 ns Flow–Through Access / 4.2 ns Pipelined Access (133 MHz)
MCM63Z834 / 916–15 = 15 ns Flow–Through Access / 5 ns Pipelined Access (100 MHz)
• Selectable Read/Write Functionality (Flow–Through/Pipelined)
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Internally Self–Timed Write Cycle
• Two–Cycle Deselect (Pipelined)
• Byte Write Control
• ADV Controlled Burst
• Simplified JTAG
• 100–Pin TQFP and 119–Bump PBGA Packages
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by
Micron Technology, Inc. and Motorola, Inc.
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 2
1/10/00

Motorola, Inc. 2000
MOTOROLA
FAST SRAM
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MCM63Z834•MCM63Z916
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Freescale Semiconductor, Inc.
LOGIC BLOCK DIAGRAM
LBO
BURST
ADDRESS
COUNTER
MEMORY
ARRAY
ADDRESS
REGISTER
SA
DATA–IN
REGISTER
WRITE
ADDRESS
REGISTER
CK
CONTROL
LOGIC
K
WRITE
ADDRESS
REGISTER
K
Freescale Semiconductor, Inc...
CKE
K
DATA–IN
REGISTER*
SE1
SE2
SE3
ADV
SW
CONTROL
REGISTER
SBx
CONTROL
LOGIC
K
DATA–OUT
REGISTER*
G
DQ
* Valid only for pipelined device.
MCM63Z834•MCM63Z916
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MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
DQc
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
FT
VDD
VDD
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQb
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
FT
VDD
VSS
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
DQa
A
1
2
3
4
5
6
7
VDDQ
SA
SA
NC
SA
SA
VDDQ
NC
SE2
SA
ADV
SA
SE3
NC
NC
SA
SA
VDD
SA
SA
NC
DQc
DQc
VSS
NC
VSS
DQb
DQb
DQc
DQc
VSS
SE1
VSS
DQb
DQb
VDDQ
DQc
VSS
G
VSS
DQb VDDQ
DQc
DQc
SBc
SA
SBb
DQb
DQb
DQc
DQc
VSS
SW
VSS
DQb
DQb
B
C
D
E
F
G
H
J
VDDQ VDD
VDD VDD
FT
VDD VDDQ
K
DQd
DQd
VSS
CK
VSS
DQa
DQa
DQd
DQd
SBd
NC
SBa
DQa
DQa
VDDQ
DQd
VSS
CKE
VSS
DQa VDDQ
DQd
DQd
VSS
SA1
VSS
DQa
DQa
DQd
DQd
VSS
SA0
VSS
DQa
DQa
VDD
SA
LBO
VDD
FT
SA
NC
NC
NC
SA
SA
SA
NC
VSS
VDDQ TMS
TDI
TCK
L
M
N
P
R
T
U
TDO TRST VDDQ
LBO
SA
SA
SA
SA
SA1
SA0
NC
NC
VSS
VDD
NC
NC
SA
SA
SA
SA
SA
SA
SA
Freescale Semiconductor, Inc...
SA
SA
SE1
SE2
SBd
SBc
SBb
SBa
SE3
VDD
VSS
CK
SW
CKE
G
ADV
NC
SA
SA
SA
MCM63Z834 PIN ASSIGNMENTS
100–PIN TQFP
TOP VIEW
119–BUMP PGBA
TOP VIEW
Not to Scale
MOTOROLA FAST SRAM
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MCM63Z834•MCM63Z916
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MCM63Z834 TQFP PIN DESCRIPTIONS
Pin Locations
Symbol
Type
85
ADV
Input
Synchronous Load/Advance: Loads a new address into counter when
low. RAM uses internally generated burst addresses when high.
89
CK
Input
Clock: This signal registers the address, data in, and all control signals
except G and LBO.
87
CKE
Input
Clock Enable: Disables the CK input when CKE is high.
DQx
I/O
14, 66
FT
Input
Flow–Through Option Input: This pin must remain in steady state (this
signal is not registered or latched). It must be tied high or low.
Low — flow–through functionality.
High — pipelined functionality.
86
G
Input
Asynchronous Output Enable.
31
LBO
Input
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter.
High — interleaved burst counter.
32, 33, 34, 35, 44, 45, 46, 47, 48, 49,
50, 81, 82, 83, 99, 100
SA
Input
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
37, 36
SA0, SA1
Input
Synchronous Burst Address Inputs: The two LSBs of the address field.
These pins must preset the burst address counter values. These inputs
are registered and must meet setup and hold times.
93, 94, 95, 96
(a) (b) (c) (d)
SBx
Input
Synchronous Byte Write Inputs: Enables write to byte “x”
(byte a, b, c, d) in conjunction with SW. Has no effect on read cycles.
98
SE1
Input
Synchronous Chip Enable: Active low to enable chip.
97
SE2
Input
Synchronous Chip Enable: Active high for depth expansion.
92
SE3
Input
Synchronous Chip Enable: Active low for depth expansion.
88
SW
Input
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins.
Freescale Semiconductor, Inc...
(a) 51, 52, 53, 56, 57, 58, 59, 62, 63
(b) 68, 69, 72, 73, 74, 75, 78, 79, 80
(c) 1, 2, 3, 6, 7, 8, 9, 12, 13
(d) 18, 19, 22, 23, 24, 25, 28, 29, 30
Description
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b, c, d).
15, 16, 41, 65, 91
VDD
Supply
Core Power Supply.
4, 11, 20, 27, 54, 61, 70, 77
VDDQ
Supply
I/O Power Supply.
5, 10, 17, 21, 26, 40, 55, 60, 64, 67,
71, 76, 90
VSS
Supply
Ground.
38, 39, 42, 43, 84
NC
—
MCM63Z834•MCM63Z916
4
No Connection: There is no connection to the chip.
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MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
MCM63Z834 PBGA PIN DESCRIPTIONS
Pin Locations
Symbol
Type
4B
ADV
Input
Synchronous Load/Advance: Loads a new address into counter when
low. RAM uses internally generated burst addresses when high.
4K
CK
Input
Clock: This signal registers the address, data in, and all control signals
except G and LBO.
4M
CKE
Input
Clock Enable: Disables the CK input when CKE is high.
(a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P
(b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H
(c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H
(d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P
DQx
I/O
5J, 5R
FT
Input
Flow–Through Option Input: This pin must remain in steady state (this
signal is not registered or latched). It must be tied high or low.
Low — flow–through functionality.
High — pipelined functionality.
4F
G
Input
Asynchronous Output Enable.
3R
LBO
Input
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter.
High — interleaved burst counter.
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C,
6C, 4G, 2R, 6R, 3T, 4T, 5T
SA
Input
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
4N, 4P
SA1, SA0
Input
Synchronous Burst Address Inputs: The two LSBs of the address field.
These pins must preset the burst address counter values. These inputs
are registered and must meet setup and hold times.
5L, 5G, 3G, 3L
(a) (b) (c) (d)
SBx
Input
Synchronous Byte Write Inputs: Enables write to byte “x” (byte a, b,
c, d) in conjunction with SW. Has no effect on read cycles.
4E
SE1
Input
Synchronous Chip Enable: Active low to enable chip.
2B
SE2
Input
Synchronous Chip Enable: Active high for depth expansion.
6B
SE3
Input
Synchronous Chip Enable: Active low for depth expansion.
4H
SW
Input
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins.
4U
TCK
Input
Boundary Scan Pin, Test Clock: If boundary scan is not used, TCK
must be tied to VDD or VSS.
3U
TDI
Input
Boundary Scan Pin, Test Data In.
5U
TDO
Output
2U
TMS
Input
Boundary Scan Pin, Test Mode Select.
6U
TRST
Input
Boundary Scan Pin, Asynchronous Test Reset. If boundary scan is not
used, TRST must be tied to VSS.
4C, 2J, 3J, 4J, 6J, 1R, 4R
VDD
Supply
Core Power Supply.
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
VDDQ
Supply
I/O Power Supply.
3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H, 3K, 5K,
3M, 5M, 3N, 5N, 3P, 5P, 7T
VSS
Supply
Ground.
4A, 1B, 7B, 1C, 7C, 4D, 4L, 7R,
1T, 2T, 6T
NC
—
MOTOROLA FAST SRAM
Description
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b, c, d).
Boundary Scan Pin, Test Data Out.
No Connection: There is no connection to the chip.
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NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
FT
VDD
VDD
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
NC
VSS
VDDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
SA
NC
NC
VDDQ
VSS
NC
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
FT
VDD
VSS
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
VDDQ
SA
SA
NC
SA
SA
VDDQ
NC
SE2
SA
ADV
SA
SE3
NC
NC
SA
SA
VDD
SA
SA
NC
DQb
NC
VSS
NC
VSS
DQa
NC
NC
DQb
VSS
SE1
VSS
NC
DQa
VDDQ
NC
VSS
G
VSS
DQa
VDDQ
NC
DQb
SBb
SA
VSS
NC
DQa
DQb
NC
VSS
SW
VSS
DQa
NC
A
B
C
D
E
F
G
H
J
VDDQ VDD
VDD VDD
FT
VDD VDDQ
K
NC
DQb
VSS
CK
VSS
NC
DQa
DQb
NC
VSS
NC
SBa
DQa
NC
VDDQ DQb
VSS
CKE
VSS
NC
VDDQ
L
M
N
DQb
NC
VSS
SA1
VSS
DQa
NC
NC
DQb
VSS
SA0
VSS
NC
DQa
VDD
SA
LBO
VDD
FT
SA
NC
NC
SA
SA
NC
SA
SA
VSS
TDI
TCK
P
R
T
U
VDDQ TMS
TDO TRST VDDQ
LBO
SA
SA
SA
SA
SA1
SA0
NC
NC
VSS
VDD
NC
NC
SA
SA
SA
SA
SA
SA
SA
Freescale Semiconductor, Inc...
SA
SA
SE1
SE2
NC
NC
SBb
SBa
SE3
VDD
VSS
CK
SW
CKE
G
ADV
NC
SA
SA
SA
MCM63Z916 PIN ASSIGNMENTS
100–PIN TQFP
TOP VIEW
119–BUMP PGBA
TOP VIEW
Not to Scale
MCM63Z834•MCM63Z916
6
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MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
MCM63Z916 TQFP PIN DESCRIPTIONS
Pin Locations
Symbol
Type
85
ADV
Input
Synchronous Load/Advance: Loads a new address into counter when
low. RAM uses internally generated burst addresses when high.
89
CK
Input
Clock: This signal registers the address, data in, and all control signals
except G and LBO.
87
CKE
Input
Clock Enable: Disables the CK input when CKE is high.
DQx
I/O
14, 66
FT
Input
Flow–Through Option Input: This pin must remain in steady state (this
signal is not registered or latched). It must be tied high or low.
Low — flow–through functionality.
High — pipelined functionality.
86
G
Input
Asynchronous Output Enable.
31
LBO
Input
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter.
High — interleaved burst counter.
32, 33, 34, 35, 44, 45, 46, 47, 48, 49,
50, 80, 81, 82, 83, 99, 100
SA
Input
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
37, 36
SA0, SA1
Input
Synchronous Burst Address Inputs: The two LSBs of the address field.
These pins must preset the burst address counter values. These inputs
are registered and must meet setup and hold times.
93, 94
(a) (b)
SBx
Input
Synchronous Byte Write Inputs: Enables write to byte “x”
(byte a, b) in conjunction with SW. Has no effect on read cycles.
98
SE1
Input
Synchronous Chip Enable: Active low to enable chip.
97
SE2
Input
Synchronous Chip Enable: Active high for depth expansion.
92
SE3
Input
Synchronous Chip Enable: Active low for depth expansion.
88
SW
Input
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins.
15, 16, 41, 65, 91
VDD
Supply
Core Power Supply.
4, 11, 20, 27, 54, 61, 70, 77
VDDQ
Supply
I/O Power Supply.
5, 10, 17, 21, 26, 40, 55, 60, 64, 67,
71, 76, 90
VSS
Supply
Ground.
1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42,
43, 51, 52, 53, 56, 57, 75, 78, 79,
84, 95, 96
NC
—
Freescale Semiconductor, Inc...
(a) 58, 59, 62, 63, 68, 69, 72, 73, 74
(b) 8, 9, 12, 13, 18, 19, 22, 23, 24
MOTOROLA FAST SRAM
Description
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b).
No Connection: There is no connection to the chip.
For More Information On This Product,
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MCM63Z834•MCM63Z916
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Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
MCM63Z916 PBGA PIN DESCRIPTIONS
Pin Locations
Symbol
Type
4B
ADV
Input
Synchronous Load/Advance: Loads a new address into counter when
low. RAM uses internally generated burst addresses when high.
4K
CK
Input
Clock: This signal registers the address, data in, and all control signals
except G and LBO.
4M
CKE
Input
Clock Enable: Disables the CK input when CKE is high.
(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P
(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P
DQx
I/O
5J, 5R
FT
Input
Flow–Through Option Input: This pin must remain in steady state (this
signal is not registered or latched). It must be tied high or low.
Low — flow–through functionality.
High — pipelined functionality.
4F
G
Input
Asynchronous Output Enable.
3R
LBO
Input
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter.
High — interleaved burst counter.
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C,
6C, 4G, 2R, 6R, 2T, 3T, 5T, 6T
SA
Input
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
4N, 4P
SA1, SA0
Input
Synchronous Address Inputs: These pins must be wired to the two
LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.
5L, 3G
(a) (b)
SBx
Input
Synchronous Byte Write Inputs: Enables write to byte “x” (byte a, b) in
conjunction with SW. Has no effect on read cycles.
4E
SE1
Input
Synchronous Chip Enable: Active low to enable chip.
2B
SE2
Input
Synchronous Chip Enable: Active high for depth expansion.
Description
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b).
6B
SE3
Input
Synchronous Chip Enable: Active low for depth expansion.
4H
SW
Input
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins.
4U
TCK
Input
Boundary Scan Pin, Test Clock: If boundary scan is not used, TCK
must be tied to VDD or VSS.
3U
TDI
Input
Boundary Scan Pin, Test Data In.
5U
TDO
Output
2U
TMS
Input
Boundary Scan Pin, Test Mode Select.
6U
TRST
Input
Boundary Scan Pin, Asynchronous Test Reset. If boundary scan is not
used, TRST must be tied to VSS.
4C, 2J, 3J, 4J, 6J, 1R, 4R
VDD
Supply
Core Power Supply.
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
VDDQ
Supply
I/O Power Supply.
3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K,
5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P, 7T
VSS
Supply
Ground.
4A, 1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E,
2F, 1G, 6G, 2H, 7H, 1K, 6K, 2L, 4L, 7L,
6M, 2N, 7N, 1P, 6P, 7R, 1T, 4T
NC
—
MCM63Z834•MCM63Z916
8
Boundary Scan Pin, Test Data Out.
No Connection: There is no connection to the chip.
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TRUTH TABLE
E
SW
SBx
ADV
SA0 –
SAx
1
X
X
X
X
X
0
False
X
X
0
X
L–H
0
True
0
V
0
L–H
0
True
1
X
L–H
0
X
X
V (W)
CK
CKE
L–H
L–H
Input Command
Code
Notes
Hold
H
1, 2
Deselect
D
1, 2
V
Load Address, New Write
W
1, 2, 3,
4, 5
0
V
Load Address, New Read
R
1, 2
1
X
Burst
B
1, 2, 4,
6 7
6,
Freescale Semiconductor, Inc...
X (R, D)
Next Operation
Continue
NOTES:
1. X = don‘t care, 1 = logic high, 0 = logic low, V = valid signal, according to AC Operating Conditions and Characteristics.
2. E = true if SE1 and SE3 = 0, and SE2 = 1.
3. Byte write enables, SBx are evaluated only as new write addresses are loaded.
4. No control inputs except CKE, SBx, and ADV are recognized in a clock cycle where ADV is sampled high.
5. A write with SBx not valid does load addresses.
6. A burst write with SBx not valid does increment address.
7. ADV controls whether the RAM enters burst mode. If the previous cycle was a write, then ADV = 1 results in a burst write. If the previous
cycle is a read, then ADV = 1 results in a burst read. ADV = 1 will also continue a deslect cycle.
ASYNCHRONOUS TRUTH TABLE
Operation
G
I/O Status
Read
L
Data Out (DQx)
Read
H
High–Z
Write
X
High–Z
Deselected
X
High–Z
WRITE TRUTH TABLE
SW
SBa
SBb
SBc
(See Note 1)
SBd
(See Note 1)
Read
H
X
X
X
X
Write Byte a
L
L
H
H
H
Write Byte b
L
H
L
H
H
Write Byte c (See Note 1)
L
H
H
L
H
Write Byte d (See Note 1)
L
H
H
H
L
Write All Bytes
L
L
L
L
L
Cycle Type
NOTE:
1. Valid only for the MCM63Z834.
LINEAR BURST ADDRESS TABLE (LBO = VSS)
1st Address (External)
2nd Address (Internal)
3rd Address (Internal)
4th Address (Internal)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
X . . . X01
X . . . X10
X . . . X11
X . . . X00
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X00
X . . . X01
X . . . X10
INTERLEAVED BURST ADDRESS TABLE (LBO = VDD)
1st Address (External)
2nd Address (Internal)
3rd Address (Internal)
4th Address (Internal)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
X . . . X01
X . . . X00
X . . . X11
X . . . X10
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X10
X . . . X01
X . . . X00
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INPUT COMMAND CODE AND STATE NAME DEFINITION DIAGRAM
INPUT
COMMAND
CODE
D
B
DESELECT
CONTINUE
DESELECT
W
B
NEW WRITE
BURST
WRITE
R
B
NEW READ
BURST
READ
H
HOLD
CK
CKE
E
FALSE
Freescale Semiconductor, Inc...
SA0 – SAx
TRUE
TRUE
VALID
VALID
ADV
SW
SBX
VALID
VALID
NOTE: Cycles are named for their control inputs, not for data I/O state.
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B
B
BURST
READ
D
BURST
WRITE
W
R
R
B
B
D
D
W
NEW
READ
R
R
D
NEW
WRITE
W
W
Freescale Semiconductor, Inc...
B
W
R
DESELECT
KEY:
D
CURRENT
STATE (n)
ƒ
NEXT
STATE (n + 1)
TRANSITION
INPUT
COMMAND
CODE
NOTES:
1. Input command codes (D, W, R, and B) represent control pin inputs
as indicated in the Truth Table.
2. Hold (i.e., CKE sampled high) is not shown simply because
CKE = 1 blocks clock input and therefore, blocks any state change.
Figure 1. ZBT RAM State Diagram
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STATE
n
n+1
n+2
n+3
CK
COMMAND
CODE
ƒ
DQ
CURRENT
STATE
NEXT
STATE
Freescale Semiconductor, Inc...
Figure 2. State Definitions for ZBT RAM State Diagram (Flow–Through)
STATE
n
n+1
n+2
n+3
CK
COMMAND
CODE
ƒ
DQ
CURRENT
STATE
NEXT
STATE
Figure 3. State Definitions for ZBT RAM State Diagram (Pipelined)
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D
B
HIGH–Z
R
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W
D
R
D
B
DATA OUT
(Q VALID)
W
B
W
HIGH–Z
(DATA IN)
R
KEY:
CURRENT
STATE (n)
NEXT STATE
n+1
NOTES:
1. Input command codes (D, W, R, and B) represent control
pin inputs as indicated in the Truth Table.
2. Hold (i.e., CKE sampled high) is not shown simply because CKE = 1 blocks clock input and therefore, blocks
any state change.
ƒ
INPUT
COMMAND
CODE
Figure 4. Data I/O State Diagram (Flow–Through)
STATE
n
n+1
n+2
n+3
CK
COMMAND
CODE
ƒ
DQ
CURRENT
STATE
NEXT
STATE
Figure 5. State Definitions for ZBT RAM State Diagram (Flow–Through)
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INTERMEDIATE
D
B
HIGH–Z
R
W
Freescale Semiconductor, Inc...
INTERMEDIATE
D
R
D
B
DATA OUT
(Q VALID)
INTERMEDIATE
INTERMEDIATE
B
W
HIGH–Z
(DATA IN)
INTERMEDIATE
STATE (n + 1)
CURRENT
STATE (n)
TRANSITION
TRANSITION
INTERMEDIATE
R
INTERMEDIATE
KEY:
W
NEXT STATE
(n + 2)
ƒ
NOTES:
1. Input command codes (D, W, R, and B) represent control pin
inputs as indicated in the Truth Table.
2. Hold (i.e., CKE sampled high) is not shown simply because
CKE = 1 blocks clock input and therefore, blocks any state
change.
INPUT
COMMAND
CODE
Figure 6. Data I/O State Diagram (Pipelined)
STATE
n
n+1
n+2
INTERMEDIATE
STATE
NEXT
STATE
n+3
CK
COMMAND
CODE
ƒ
DQ
STATE NAME
CURRENT
STATE
Figure 7. State Definitions for I/O State Diagram (Pipelined)
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ABSOLUTE MAXIMUM RATINGS (See Note 1)
Rating
Symbol
Value
Unit
VDD
–0.5 to 4.6
V
VDDQ
VSS – 0.5 to VDD
V
2
Vin, Vout
–0.5 to VDD + 0.5
V
2
Input Voltage (Three State I/O)
VIT
VSS – 0.5 to
VDDQ + 0.5
V
2
Output Current (per I/O)
Iout
±20
mA
Package Power Dissipation
PD
1.3
W
Tbias
–10 to 85
°C
Tstg
–55 to 125
°C
Power Supply Voltage
I/O Supply Voltage
Input Voltage Relative to VSS for
Any Pin Except VDD
Temperature Under Bias
Freescale Semiconductor, Inc...
Storage Temperature
Notes
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high–impedance
circuit.
3
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
2. This is a steady–state DC parameter that is in effect after the power supply has
achieved its nominal operating level. Power sequencing is not necessary.
3. Power dissipation capability is dependent upon package characteristics and use
environment. See Package Thermal Characteristics.
PACKAGE THERMAL CHARACTERISTICS
Thermal Resistance
Symbol
Max
Unit
Notes
RθJA
40
25
°C/W
1, 2
Junction to Board (Bottom)
RθJB
17
°C/W
3
Junction to Case (Top)
RθJC
9
°C/W
4
Junction to Ambient (@ 200 lfm)
Single–Layer Board
Four–Layer Board
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883
Method 1012.1).
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DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V ±5%, TA = 0° to 70°C Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS AND DC CHARACTERISTICS: 2.5 V I/O SUPPLY
(Voltages Referenced to VSS = 0 V)
Symbol
Min
Typ
Max
Unit
VDD
3.135
3.3
3.465
V
VDDQ
2.375
2.5
2.9
V
Input Low Voltage
VIL
–0.3
—
0.7
V
Input High Voltage
VIH
1.7
—
VDD + 0.3
V
Input High Voltage I/O Pins
VIH2
1.7
—
VDDQ + 0.3
V
Output Low Voltage (IOL = 2 mA)
VOL
—
—
0.7
V
Output High Voltage (IOL = –2 mA)
VOH
1.7
—
—
V
Parameter
Supply Voltage
Freescale Semiconductor, Inc...
I/O Supply Voltage
RECOMMENDED OPERATING CONDITIONS AND DC CHARACTERISTICS: 3.3 V I/O SUPPLY
(Voltages Referenced to VSS = 0 V)
Symbol
Min
Typ
Max
Unit
VDD
3.135
3.3
3.465
V
I/O Supply Voltage
VDDQ
3.135
3.3
3.465
V
Input Low Voltage
VIL
–0.5
—
0.8
V
Input High Voltage
VIH
2
—
VDD + 0.5
V
Input High Voltage I/O Pins
VIH2
2
—
VDDQ + 0.5
V
Parameter
Supply Voltage
Output Low Voltage (IOL = 8 mA)
VOL
—
—
0.4
V
Output High Voltage (IOH = –8 mA)
VOH
2.4
—
—
V
VIH
VSS
VSS – 1.0 V
20% tKHKH (MIN)
Figure 8. Undershoot Voltage
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DC CHARACTERISTICS AND SUPPLY CURRENTS
Symbol
Min
Typ
Max
Unit
Notes
Input Leakage Current (0 V ≤ Vin ≤ VDD)
Parameter
Ilkg(I)
—
—
±1
µA
1
Output Leakage Current (0 V ≤ Vin ≤ VDDQ)
Ilkg(O)
—
—
±1
µA
IDDA–10
IDDA–11
IDDA–15
—
—
—
—
—
—
TBD
TBD
TBD
mA
2, 3,
4, 5
ISB2
—
—
10
mA
6, 7
ISB4–10
ISB4–11
ISB4–15
—
—
—
—
—
—
TBD
TBD
TBD
mA
5, 6, 8
IDD1
—
—
15
mA
7
AC Supply Current (Device Selected, All Outputs Open,
Freq = Max) Includes Supply Current for Both VDD and VDDQ
CMOS Standby Supply Current (Device Deselected,
Freq = 0, VDD = Max, VDDQ = Max, All Inputs Static
at CMOS Levels)
Clock Running (Device Deselected, Freq = Max, VDD = Max,
All Inputs Toggling at CMOS Levels)
Freescale Semiconductor, Inc...
Hold Supply Current (Device Selected, Freq = Max,
VDD = Max, VDDQ = Max, CKE ≥ VDD – 0.2 V,
All Inputs Static at CMOS Levels)
NOTES:
1. LBO has an internal pull–up will exhibit leakage currents of ±5 µA.
2. Reference AC Operating Conditions and Characteristics for input and timing.
3. All addresses transition simultaneously low (LSB) then high (MSB).
4. Data states are all zero.
5. Flow–through/pipelined current.
6. Device in deselected mode as defined by the Truth Table.
7. CMOS levels for I/Os are VIT ≤ VSS + 0.2 V or ≥ VDDQ – 0.2 V. CMOS levels for other inputs are Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V.
8. TTL levels for I/Os are VIT ≤ VIL or ≥ VIH2. TTL levels for other inputs are Vin ≤ VIL or ≥ VIH.
CAPACITANCE (f = 1.0 MHz, TA = 0° to 70°C, Periodically Sampled Rather Than 100% Tested)
Symbol
Min
Typ
Max
Unit
Input Capacitance
Cin
—
2
4
pF
Input/Output Capacitance
CI/O
—
3
5
pF
Parameter
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AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V ±5%, TA = 0° to 70°C Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . 1.0 V/ns (20% to 80%)
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . See Figure 9 Unless Otherwise Noted
FLOW–THROUGH READ/WRITE CYCLE TIMING (See Notes 1 and 2)
MCM63Z834–10
MCM63Z916–10
MCM63Z834–11
MCM63Z916–11
MCM63Z834–15
MCM63Z916–15
Symbol
Min
Max
Min
Max
Min
Max
Unit
Cycle Time
tKHKH
12
—
15
—
20
—
ns
Clock High Pulse Width
tKHKL
4.8
—
6
—
8
—
ns
3
Clock Low Pulse Width
tKLKH
4.8
—
6
—
8
—
ns
3
Clock Access Time
tKHQV
—
10
—
11
—
15
ns
Output Enable to Output Valid
tGLQV
—
5
—
6
—
7
ns
Clock High to Output Active
tKHQX1
1.5
—
1.5
—
1.5
—
ns
4, 5
Output Hold Time
tKHQX
1.5
—
1.5
—
1.5
—
ns
4
Freescale Semiconductor, Inc...
Parameter
Notes
Output Enable to Output Active
tGLQX
0
—
0
—
0
—
ns
4, 5
Output Disable to Q High–Z
tGHQZ
—
4.5
—
4.5
—
5
ns
4, 5
Clock High to Q High–Z
tKHQZ
1.5
4.5
1.5
4.5
1.5
5
ns
4, 5
Setup Times:
Address
ADV
Data In
Write
Chip Enable
Clock Enable
tADKH
tLVKH
tDVKH
tWVKH
tEVKH
tCVKH
2.5
2.5
2
2.5
2.5
2.5
—
2.5
2.5
2
2.5
2.5
2.5
—
2.5
2.5
2
2.5
2.5
2.5
—
ns
Hold Times:
Address
ADV
Data In
Write
Chip Enable
Clock Enable
tKHAX
tKHLX
tKHDX
tKHWX
tKHEX
tKHCX
0.5
—
0.5
—
0.5
—
ns
NOTES:
1. Write is defined as any SBx and SW low. Chip enable is defined as SE1 low, SE2 high, and SE3 low whenever ADV is low.
2. All read and write cycle timings are referenced from CK or G.
3. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between
data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some
design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is
given in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels.
4. This parameter is sampled and not 100% tested.
5. Measured at ±200 mV from steady state.
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PIPELINED READ/WRITE CYCLE TIMING (See Notes 1 and 2)
MCM63Z834–10
MCM63Z916–10
143 MHz
MCM63Z834–11
MCM63Z916–11
133 MHz
MCM63Z834–15
MCM63Z916–15
100 MHz
Symbol
Min
Max
Min
Max
Min
Max
Unit
Cycle Time
tKHKH
7
—
7.5
—
10
—
ns
Clock High Pulse Width
tKHKL
2.8
—
3
—
4
—
ns
3
Clock Low Pulse Width
tKLKH
2.8
—
3
—
4
—
ns
3
Clock Access Time
tKHQV
—
4
—
4.2
—
5
ns
Parameter
Freescale Semiconductor, Inc...
Output Enable to Output Valid
Notes
tGLQV
—
4
—
4.2
—
5
ns
Clock High to Output Active
tKHQX1
1.5
—
1.5
—
1.5
—
ns
4, 5
Output Hold Time
tKHQX
1.5
—
1.5
—
1.5
—
ns
4
Output Enable to Output Active
tGLQX
0
—
0
—
0
—
ns
4, 5
Output Disable to Q High–Z
tGHQZ
—
3.5
—
3.5
—
3.5
ns
4, 5
Clock High to Q High–Z
tKHQZ
1.5
3.5
1.5
3.5
1.5
3.5
ns
4, 5
Setup Times:
Address
ADV
Data In
Write
Chip Enable
Clock Enable
tADKH
tLVKH
tDVKH
tWVKH
tEVKH
tCVKH
2
2
1.7
2
2
2
—
2
2
1.7
2
2
2
—
2.2
2.2
2
2.2
2.2
2.2
—
ns
Hold Times:
Address
ADV
Data In
Write
Chip Enable
Clock Enable
tKHAX
tKHLX
tKHDX
tKHWX
tKHEX
tKHCX
0.5
—
0.5
—
0.5
—
ns
NOTES:
1. Write is defined as any SBx and SW low. Chip Enable is defined as SE1 low, SE2 high, and SB3 low whenever ADV is low.
2. All read and write cycle timings are referenced from CK or G.
3. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between
data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some
design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given
in the AC test conditions section of the data sheet as 2.5 V/ns, one can easily interpolate timing values to other reference levels.
4. This parameter is sampled and not 100% tested.
5. Measured at ±200 mV from steady state.
OUTPUT
Z0 = 50 Ω
RL = 50 Ω
1.5 V
Figure 9. AC Test Loads
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tKHKH
tKHKL
tKLKH
CK
tAVKH
tKHAX
SA0 – SAx
tWVKH
tKHWX
SW
tWVKH
tKHWX
SBx
Freescale Semiconductor, Inc...
tEVKH
tKHEX
E
tLVKH
tKHLX
ADV
tCVKH
tKHCX
CKE
G
tGLQX
tGLQV
tGHQZ
DQ
Q
tDVKH
tKHDX
DQ
D
tKHQV
tKHQX1
DQ
tKHQX
tKHQZ
Q
Q
Figure 10. AC Timing Parameter Definitions
(Flow–Through)
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tKHKH
tKHKL
tKLKH
CK
tAVKH
tKHAX
SA0 – SAx
tWVKH
tKHWX
SW
tWVKH
tKHWX
SBx
Freescale Semiconductor, Inc...
tEVKH
tKHEX
E
tLVKH
tKHLX
ADV
tCVKH
tKHCX
CKE
G
tGLQX
tGLQV
tGHQZ
DQ
Q
tDVKH
tKHDX
DQ
D
tKHQX
tKHQV
tKHQX1
DQ
tKHQZ
Q
Q
NOTE: E is true if SE1 = SE3 = low and SE2 = high.
tGLQX, tGLQV, and tGHQZ only apply if G is toggled. If G is tied low
tKHQX, tKHQV, and tKHQZ apply.
Figure 11. AC Timing Parameter Definitions
(Pipelined)
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R
COMMAND
CODE
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Q(A0)
W
B
Q(A0)
H
D(B0)
R
C
NOTE: Command code definitions are shown in Truth Table.
DQ
(PIPELINED)
DQ
(FLOW–THROUGH)
A
ADDRESS
CK
D(B0)
Q(C0)
W
D
Q(C0)
D(D0)
D
D(D0)
R
E
Q(E0)
H
W
F
Q(E0)
D(F0)
R
G
D(F0)
Q(G0)
D
READ/WRITE CYCLES WITH HOLD AND DESELECT CYCLES
Freescale Semiconductor, Inc...
Q(G0)
W
H
D(H0)
R
I
D(H0)
Q(I0)
D
J
Q(I0)
Freescale Semiconductor, Inc.
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MOTOROLA FAST SRAM
R
COMMAND
CODE
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Q(A0)
R
B
Q(A0)
Q(B0)
B
Q(B0)
Q(B1)
B
NOTE: Command code definitions are shown in Truth Table.
DQ
(PIPELINED)
DQ
(FLOW–THROUGH)
A
ADDRESS
CK
Q(B1)
Q(B2)
B
Q(B2)
Q(B3)
R
C
Q(B3)
Q(C0)
B
Q(C0)
Q(C1)
B
Q(C1)
Q(C2)
B
READ CYCLES (SINGLE, BURST, AND BURST WRAP–AROUND)
Freescale Semiconductor, Inc...
Q(C2)
Q(C3)
B
Q(C3)
Q(C0)
Q(C0)
Freescale Semiconductor, Inc.
MCM63Z834•MCM63Z916
23
MCM63Z834•MCM63Z916
24
W
COMMAND
CODE
For More Information On This Product,
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D(A0)
W
B
D(A0)
D(B0)
B
D(B0)
D(B1)
B
NOTE: Command code definitions are shown in Truth Table.
DQ
(PIPELINED)
DQ
(FLOW–THROUGH)
A
ADDRESS
CK
D(B1)
D(B2)
B
D(B2)
D(B3)
W
C
D(B3)
D(C0)
B
D(C0)
D(C1)
B
D(C1)
D(C2)
B
WRITE CYCLES (SINGLE, BURST, AND BURST WRAP–AROUND)
Freescale Semiconductor, Inc...
D(C2)
D(C3)
B
D(C3)
D(C0)
D(C0)
Freescale Semiconductor, Inc.
MOTOROLA FAST SRAM
MOTOROLA FAST SRAM
R
COMMAND
CODE
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Q(A0)
W
B
Q(A0)
D(B0)
R
B
D(B0)
Q(B0)
W
C
NOTE: Command code definitions are shown in Truth Table.
DQ
(PIPELINED)
DQ
(FLOW–THROUGH)
A
ADDRESS
CK
Q(B0)
D(C0)
B
D(C0)
D(C1)
R
C
D(C1)
Q(C0)
B
Q(C0)
Q(C1)
D
Q(C1)
W
D
H
D(D0)
R
D
READ, WRITE, READ COHERENCY WITH HOLD, AND DESELECT CYCLES
Freescale Semiconductor, Inc...
D(D0)
Q(D0)
R
E
Q(D0)
Q(E0)
Q(E0)
Freescale Semiconductor, Inc.
MCM63Z834•MCM63Z916
25
Freescale Semiconductor, Inc.
SERIAL BOUNDARY SCAN TEST ACCESS PORT OPERATION
OVERVIEW
The serial boundary scan test access port (TAP) on this
RAM is designed to operate in a manner consistent with
IEEE Standard 1149.1–1990 (commonly referred to as
JTAG), but does not implement all of the functions required
for IEEE 1149.1 compliance. Certain functions have been
modified or eliminated because their implementation places
extra delays in the RAMs critical speed path. Nevertheless,
the RAM supports the standard TAP controller architecture
(the TAP controller is the state machine that controls the
TAPs operation) and can be expected to function in a manner
that does not conflict with the operation of devices with IEEE
Standard 1149.1 compliant TAPs. The TAP operates using a
3.3 V tolerant logic level signaling.
DISABLING THE TEST ACCESS PORT
It is possible to use this device without utilizing the TAP. To
disable the TAP controller without interfering with normal
operation of the device, TRST should be tied low and TCK,
TDI, and TMS should be pulled through a resistor to 3.3 V.
TDO should be left unconnected.
TAP DC OPERATING CHARACTERISTICS
Freescale Semiconductor, Inc...
(TA = 0° to 70°C, Unless Otherwise Noted)
Symbol
Min
Max
Unit
Input Logic Low
VIL1
–0.5
0.8
V
Input Logic High
VIH1
2
3.6
V
Parameter
Notes
Ilkg
—
±10
µA
1
Output Logic Low
VOL1
—
0.4
V
2
Output Logic High
VOH1
2.4
—
V
Input Leakage Current
NOTES:
1. 0 V ≤ Vin ≤ VDDQ for all logic input pins.
2. For VOL = 0.4 V, 14 mA ≤ IOL ≤ 28 mA.
MCM63Z834•MCM63Z916
26
For More Information On This Product,
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MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
TAP AC OPERATING CONDITIONS AND CHARACTERISTICS
(TA = 0° to 70°C, Unless Otherwise Noted)
AC TEST CONDITIONS
Parameter
Input Timing Reference Level
Input Pulse Levels
Value
Unit
1.5
V
0 to 3.0
V
1
V/ns
Output Timing Reference Level
1.5
V
Output Load (See Figure 6 Unless Otherwise Noted)
—
—
Input Rise/Fall Time (20% to 80%)
TAP CONTROLLER TIMING
Parameter
Freescale Semiconductor, Inc...
TCK Cycle Time
Symbol
Min
Max
Unit
tTHTH
60
—
ns
TCK Clock High Time
tTH
25
—
ns
TCK Clock Low Time
tTL
25
—
ns
TDO Access Time
tTLQV
1
10
ns
TRST Pulse Width
tTSRT
40
—
ns
Notes
Setup Times
Capture
TDI
TMS
tCS
tDVTH
tMVTH
5
5
5
—
ns
1
Hold Times
Capture
TDI
TMS
tCH
tTHDX
tTHMX
13
14
14
—
ns
1
NOTE:
1. tCS and tCH define the minimum pauses in RAM I/O transitions to assure accurate pad data capture.
TAP CONTROLLER TIMING DIAGRAM
tTHTH
tTLTH
TEST CLOCK
(TCK)
tTHTL
tTHMX
tMVTH
TEST MODE SELECT
(TMS)
tTHDX
tDVTH
TEST DATA IN
(TDI)
tTLQV
TEST DATA OUT
(TDO)
MOTOROLA FAST SRAM
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MCM63Z834•MCM63Z916
27
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
MCM63Z834 BOUNDARY SCAN ORDER
Bit No.
Signal Name
Bump ID
Bit No.
Signal Name
Bump ID
1
SA
4T
36
SBa
5L
2
SA
5T
37
SEb
5G
3
SA
3B
38
SBc
3G
4
SA
6R
39
SBd
3L
5
SA
5B
40
SE2
2B
6
SA
5C
41
SE1
4E
7
SA
5A
42
SA
2A
8
DQa
6P
43
SA
2C
9
DQa
7N
44
DQc
2D
10
DQa
6M
45
DQc
1E
11
DQa
7L
46
DQc
2F
12
DQa
6K
47
DQc
1G
13
DQa
7P
48
DQc
2H
14
DQa
6N
49
DQc
1D
15
DQa
7K
50
DQc
2E
16
DQa
6L
51
DQc
2G
17
VOL
Internal
52
DQc
1H
18
DQb
6H
53
FT
5R
54
DQd
2K
55
DQd
2M
56
DQd
1L
57
DQd
1N
58
DQd
2P
59
DQd
1K
60
DQd
2L
19
DQb
7G
20
DQb
6F
21
DQb
7E
22
DQb
6D
23
DQb
7H
24
DQb
6G
25
DQb
6E
26
DQb
7D
27
SA
6C
61
DQd
2N
28
SA
6A
62
DQd
1P
29
SA
4G
63
LBO
3R
30
ADV
4B
64
SA
3A
31
G
4F
65
SA
3C
32
CKE
4M
66
SA
2R
33
SW
4H
67
SA
3T
34
CK
4K
68
SA1
4N
35
SE3
6B
69
SA0
4P
MCM63Z834•MCM63Z916
28
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MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
MCM63Z916 BOUNDARY SCAN ORDER
Bit No.
Signal Name
Bump ID
Bit No.
Signal Name
Bump ID
1
SA
6T
26
CK
4K
2
SA
5T
27
SE3
6B
3
SA
3B
28
SBa
5L
4
SA
6R
29
SBb
3G
5
SA
5B
30
SB2
2B
6
SA
5C
31
SE1
4E
7
SA
5A
32
SA
2A
8
DQa
7P
33
SA
2C
9
DQa
6N
34
DQb
1D
10
DQa
7K
35
DQb
2E
11
DQa
6L
36
DQb
2G
12
VOL
Internal
37
DQb
1H
13
DQa
6H
38
FT
5R
14
DQa
7G
39
DQb
2K
15
DQa
6F
40
DQb
2M
16
DQa
7E
41
DQb
1L
17
DQa
6D
42
DQb
1N
18
SA
2T
43
DQb
2P
19
SA
6C
44
LBO
3R
20
SA
6A
45
SA
3A
21
SA
4G
46
SA
3C
22
ADV
4B
47
SA
2R
23
G
4F
48
SA
3T
24
CKE
4M
49
SA1
4N
25
SW
4H
50
SA0
4P
MOTOROLA FAST SRAM
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MCM63Z834•MCM63Z916
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Freescale Semiconductor, Inc.
TEST ACCESS PORT PINS
TCK — TEST CLOCK (INPUT)
Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge
of TCK.
TMS — TEST MODE SELECT (INPUT)
The TMS input is sampled on the rising edge of TCK. This
is the command input for the TAP controller state machine.
An undriven TMS input will not produce the same result as a
logic 1 input level (not IEEE 1149.1 compliant).
Freescale Semiconductor, Inc...
TDI — TEST DATA IN (INPUT)
The TDI input is sampled on the rising edge of TCK. This is
the input side of the serial registers placed between TDI and
TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and
the instruction that is currently loaded in the TAP instruction
register (refer to Figure 13). An undriven TDI pin will not produce the same result as a logic 1 input level (not IEEE 1149.1
compliant).
TDO — TEST DATA OUT (OUTPUT)
Output that is active depending on the state of the TAP
state machine (refer to Figure 13). Output changes in
response to the falling edge of TCK. This is the output side of
the serial registers placed between TDI and TDO.
TRST — TAP RESET
The TRST is an asynchronous input that resets the TAP
controller and preloads the instruction register with the
IDCODE command. This type of reset does not affect the
operation of the system logic. The reset affects test logic
only.
TEST ACCESS PORT REGISTERS
OVERVIEW
The various TAP registers are selected (one at a time) via
the sequences of 1s and 0s input to the TMS pin as the TCK
is strobed. Each of the TAPs registers are serial shift registers that capture serial input data on the rising edge of TCK
and push serial data out on the subsequent falling edge of
TCK. When a register is selected, it is “placed” between the
TDI and TDO pins.
The boundary scan register is identical in length to the
number of active input and I/O connections on the RAM (not
counting the TAP pins). This also includes a number of place
holder locations (always set to a logic 0) reserved for density
upgrade address pins. There are a total of 67 bits in the case
of the x36 device and 48 bits in the case of the x18 device.
The boundary scan register, under the control of the TAP
controller, is loaded with the contents of the RAMs I/O ring
when the controller is in capture–DR state and then is placed
between the TDI and TDO pins when the controller is moved
to shift–DR state.
The Bump/Bit Scan Order table describes which device
bump connects to each boundary scan register location. The
first column defines the bit’s position in the boundary scan
register. The shift register bit nearest TDO (i.e., first to be
shifted out) is defined as bit 1. The second column is the
name of the input or I/O at the bump and the third column is
the bump number.
IDENTIFICATION (ID) REGISTER
The ID register is a 32–bit register that is loaded with a device and vendor specific 32–bit code when the controller is
put in capture–DR state with the IDCODE command loaded
in the instruction register. The code is loaded from a 32–bit
on–chip ROM. It describes various attributes of the RAM as
indicated below. The register is then placed between the TDI
and TDO pins when the controller is moved into shift–DR
state. Bit 0 in the register is the LSB and the first to reach
TDO when shifting begins.
ID Register Presence Indicator
Bit No.
0
Value
1
Motorola JEDEC ID Code (Compressed Format, per
IEEE Standard 1149.1–1990
Bit No.
11
10
9
8
7
6
5
4
3
2
1
Value
0
0
0
0
0
0
0
1
1
1
0
Reserved For Future Use
Bit No.
17
16
15
14
13
12
Value
x
x
x
x
x
x
Device Width
INSTRUCTION REGISTER
The instruction register holds the instructions that are
executed by the TAP controller when it is moved into the run
test/idle or the various data register states. The instructions
are 3 bits long. The register can be loaded when it is placed
between the TDI and TDO pins. The parallel outputs of the
instruction register are automatically preloaded with the
IDCODE instruction when TRST is asserted or whenever the
controller is placed in the test–logic–reset state. The two
least significant bits of the serial instruction register are
loaded with a binary “or” pattern in the capture–IR state.
BYPASS REGISTER
The bypass register is a single bit register that can be
placed between TDI and TDO. It allows serial test data to be
passed through the RAMs TAP to another device in the scan
chain with as little delay as possible.
MCM63Z834•MCM63Z916
30
BOUNDARY SCAN REGISTER
Bit No.
22
21
20
19
18
256K x 36
0
0
1
0
0
512K x 18
0
0
0
1
1
Bit No.
27
26
25
24
23
256K x 36
0
0
1
1
0
512K x 18
0
0
1
1
1
Device Depth
Revision Number
Bit No.
31
30
29
28
Value
0
0
0
0
Figure 12. ID Register Bit Meanings
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MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
TAP CONTROLLER INSTRUCTION SET
Freescale Semiconductor, Inc...
OVERVIEW
There are two classes of instructions defined in the IEEE
Standard 1149.1–1990; the standard (public) instructions
and device specific (private) instructions. Some public
instructions, are mandatory for IEEE 1149.1 compliance.
Optional public instructions must be implemented in prescribed ways.
Although the TAP controller in this device follows the IEEE
1149.1 conventions, it is not IEEE 1149.1 compliant because
some of the mandatory instructions are not fully implemented. The TAP on this device may be used to monitor all
input and I/O pads, but can not be used to load address,
data, or control signals into the RAM or to preload the I/O
buffers. In other words, the device will not perform IEEE
1149.1 EXTEST, INTEST, or the preload portion of the
SAMPLE/PRELOAD command.
When the TAP controller is placed in capture–IR state, the
two least significant bits of the instruction register are loaded
with 01. When the controller is moved to the shift–IR state
the instruction register is placed between TDI and TDO. In
this state, the desired instruction is serially loaded through
the TDI input (while the previous contents are shifted out at
TDO). For all instructions, the TAP executes newly loaded
instructions only when the controller is moved to update–IR
state. The TAP instruction sets for this device are listed in the
following tables.
STANDARD (PUBLIC) INSTRUCTIONS
BYPASS
The BYPASS instruction is loaded in the instruction register when the bypass register is placed between TDI and
TDO. This occurs when the TAP controller is moved to the
shift–DR state. This allows the board level scan path to be
shortened to facilitate testing of other devices in the scan
path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is an IEEE 1149.1 mandatory public
instruction. When the SAMPLE/PRELOAD instruction is
loaded in the instruction register, moving the TAP controller
out of the capture–DR state loads the data in the RAMs input
and I/O buffers into the boundary scan register. Because the
RAM clock(s) are independent from the TAP clock (TCK), it is
MOTOROLA FAST SRAM
possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable
inputs will not harm the device, repeatable results can not be
expected. RAM input signals must be stabilized for long
enough to meet the TAPs input data capture setup plus hold
time (tCS plus tCH). The RAMs clock inputs need not be
paused for any other TAP operation except capturing the I/O
ring contents into the boundary scan register.
Moving the controller to shift–DR state then places the
boundary scan register between the TDI and TDO pins.
Because the PRELOAD portion of the command is not
implemented in this device, moving the controller to the
update–DR state with the SAMPLE/PRELOAD instruction
loaded in the instruction register has the same effect as the
pause–DR command. This functionality is not IEEE 1149.1
compliant.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It
is to be executed whenever the instruction register, whatever
length it may be in the device, is loaded with all logic 0s.
EXTEST is not implemented in this device.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded
into the ID register when the controller is in capture–DR
mode and places the ID register between the TDI and TDO
pins in shift–DR mode. The IDCODE instruction is the default
instruction loaded in at TRST assertion and any time the
controller is placed in the test–logic–reset state.
THE DEVICE SPECIFIC (PUBLIC) INSTRUCTION
SAMPLE–Z
If the HIGH–Z instruction is loaded in the instruction register, all DQ pins are forced to an inactive drive state
(High–Z) and the bypass register is connected between TDI
and TDO when the TAP controller is moved to the shift–DR
state.
THE DEVICE SPECIFIC (PRIVATE) INSTRUCTION
NO OP
Do not use these instructions; they are reserved for future
use.
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31
Freescale Semiconductor, Inc.
STANDARD AND DEVICE SPECIFIC (PUBLIC) INSTRUCTION CODES
Instruction
Code*
Description
IDCODE
001**
Preloads ID register and places it between TDI and TDO. Does not affect RAM operation.
HIGH–Z
010
Captures I/O ring contents. Places the bypass register between TDI and TDO. Forces all DQ pins
to High–Z. NOT IEEE 1149.1 COMPLIANT.
BYPASS
011
Places bypass register between TDI and TDO. Does not affect RAM operation. NOT IEEE 1149.1
COMPLIANT.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not
affect RAM operation.
Does not implement IEEE 1149.1 Preload function. NOT IEEE 1149.1 COMPLIANT.
* Instruction codes expressed in binary, MSB on left, LSB on right.
** Default instruction automatically loaded when TRST asserted or in test–logic–reset state.
STANDARD (PRIVATE) INSTRUCTION CODES
Freescale Semiconductor, Inc...
Instruction
Code*
Description
NO OP
000
Do not use these instructions; they are reserved for future use.
NO OP
101
Do not use these instructions; they are reserved for future use.
NO OP
110
Do not use these instructions; they are reserved for future use.
NO OP
111
Do not use these instructions; they are reserved for future use.
* Instruction codes expressed in binary, MSB on left, LSB on right.
1
TEST–LOGIC
RESET
0
0
RUN–TEST/
IDLE
1
SELECT
DR–SCAN
SELECT
IR–SCAN
1
0
1
1
0
1
CAPTURE–DR
CAPTURE–IR
0
0
SHIFT–IR
SHIFT–DR
0
1
0
1
1
1
EXIT1–DR
EXIT1–IR
0
0
PAUSE–DR
PAUSE–IR
0
1
0
EXIT2–DR
0
EXIT2–IR
1
1
UPDATE–DR
1
0
1
0
UPDATE–IR
1
0
NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK.
Figure 13. TAP Controller State Diagram
MCM63Z834•MCM63Z916
32
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MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
ORDERING INFORMATION
(Order by Full Part Number)
MCM
63Z834
63Z916
XX
X
X
Motorola Memory Prefix
Blank = Trays, R = Tape and Reel
Part Number
Speed (10 = 10 ns Flow–Through or 143 MHz Pipelined,
11 = 11 ns Flow–Through or 133 MHz Pipelined,
15 = 15 ns Flow–Through or 100 MHz Pipelined)
Package (TQ = TQFP, ZP = PBGA)
MCM63Z834TQ11
MCM63Z834TQ11R
MCM63Z916TQ11
MCM63Z916TQ11R
MCM63Z834TQ15
MCM63Z834TQ15R
MCM63Z916TQ15
MCM63Z916TQ15R
MCM63Z834ZP10
MCM63Z834ZP10R
MCM63Z916ZP10
MCM63Z916ZP10R
MCM63Z834ZP11
MCM63Z834ZP11R
MCM63Z916ZP11
MCM63Z916ZP11R
MCM63Z834ZP15
MCM63Z834ZP15R
MCM63Z916ZP15
MCM63Z916ZP15R
Freescale Semiconductor, Inc...
Full Part Numbers — MCM63Z834TQ10
MCM63Z834TQ10R
MCM63Z916TQ10
MCM63Z916TQ10R
MOTOROLA FAST SRAM
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MCM63Z834•MCM63Z916
33
Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
TQ PACKAGE
TQFP
CASE 983A–01
e
4X
0.20 (0.008) H A–B D
2X 30 TIPS
e/2
0.20 (0.008) C A–B D
–D–
80
51
B
50
81
–A–
–X–
B
E/2
X=A, B, OR D
–B–
VIEW Y
E1 E
BASE
METAL
PLATING
Freescale Semiconductor, Inc...
c
31
100
1
30
D1/2
0.13 (0.005)
0.20 (0.008) C A–B D
A
2
0.10 (0.004) C
–H–
–C–
3
SEATING
PLANE
VIEW AB
S
S
1
A2
L2
L
L1
GAGE PLANE
VIEW AB
MCM63Z834•MCM63Z916
34
C A–B
S
D
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –A–, –B– AND –D– TO BE DETERMINED
AT DATUM PLANE –H–.
5. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE –C–.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS D1 AND B1 DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –H–.
7. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE b DIMENSION TO EXCEED 0.45
(0.018).
0.25 (0.010)
R2
R1
M
SECTION B–B
2X 20 TIPS
A1
c1
b
D/2
D1
D
0.05 (0.002)
ÉÉÉÉ
ÇÇÇÇ
ÇÇÇÇ
ÉÉÉÉ
ÇÇÇÇ
b1
E1/2
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DIM
A
A1
A2
b
b1
c
c1
D
D1
E
E1
e
L
L1
L2
S
R1
R2
1
2
3
MILLIMETERS
MIN
MAX
–––
1.60
0.05
0.15
1.35
1.45
0.22
0.38
0.22
0.33
0.09
0.20
0.09
0.16
22.00 BSC
20.00 BSC
16.00 BSC
14.00 BSC
0.65 BSC
0.45
0.75
1.00 REF
0.50 REF
0.20
–––
0.08
–––
0.08
0.20
0_
7_
0_
–––
11 _
13 _
11 _
13 _
INCHES
MIN
MAX
–––
0.063
0.002
0.006
0.053
0.057
0.009
0.015
0.009
0.013
0.004
0.008
0.004
0.006
0.866 BSC
0.787 BSC
0.630 BSC
0.551 BSC
0.026 BSC
0.018
0.030
0.039 REF
0.020 REF
0.008
–––
0.003
–––
0.003
0.008
0_
7_
0_
–––
11 _
13 _
11 _
13 _
MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
ZP PACKAGE
7 x 17 BUMP PBGA
CASE 999–02
0.20
4X
119X
E
C
B
D
Freescale Semiconductor, Inc...
E2
e
6X
M
A B C
A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
D1
16X
M
0.15
7 6 5 4 3 2 1
D2
b
0.3
DIM
A
A1
A2
A3
D
D1
D2
E
E1
E2
b
e
e
E1
TOP VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. ALL DIMENSIONS IN MILLIMETERS.
3. DIMENSION b IS THE MAXIMUM SOLDER BALL
DIAMETER MEASURED PARALLEL TO DATUM A.
4. DATUM A, THE SEATING PLANE, IS DEFINED BY
THE SPHERICAL CROWNS OF THE SOLDER
BALLS.
BOTTOM VIEW
MILLIMETERS
MIN
MAX
–––
2.40
0.50
0.70
1.30
1.70
0.80
1.00
22.00 BSC
20.32 BSC
19.40
19.60
14.00 BSC
7.62 BSC
11.90
12.10
0.60
0.90
1.27 BSC
0.25 A
A3
0.35 A
0.20 A
A
A2
A1
SIDE VIEW
SEATING
PLANE
A
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are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
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Mfax is a trademark of Motorola, Inc.
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MCM63Z834/D
MCM63Z834•MCM63Z916
35