TI1 NE555 Precision timing circuits capable of producing accurate time delays or oscillation Datasheet

NA555, NE555, SA555, SE555
www.ti.com
SLFS022H – SEPTEMBER 1973 – REVISED JUNE 2010
PRECISION TIMERS
Check for Samples: NA555, NE555, SA555, SE555
FEATURES
1
•
•
Timing From Microseconds to Hours
Astable or Monostable Operation
•
•
Adjustable Duty Cycle
TTL-Compatible Output Can Sink or Source up
to 200 mA
NA555...D OR P PACKAGE
NE555...D, P, PS, OR PW PACKAGE
SA555...D OR P PACKAGE
SE555...D, JG, OR P PACKAGE
(TOP VIEW)
1
8
2
7
3
6
4
5
VCC
DISCH
THRES
CONT
NC
GND
NC
VCC
NC
NC
TRIG
NC
OUT
NC
4
3 2 1 20 19
18
5
17
6
16
7
15
14
9 10 11 12 13
8
NC
DISCH
NC
THRES
NC
NC
RESET
NC
CONT
NC
GND
TRIG
OUT
RESET
SE555...FK PACKAGE
(TOP VIEW)
NC – No internal connection
DESCRIPTION/ORDERING INFORMATION
These devices are precision timing circuits capable of producing accurate time delays or oscillation. In the
time-delay or monostable mode of operation, the timed interval is controlled by a single external resistor and
capacitor network. In the astable mode of operation, the frequency and duty cycle can be controlled
independently with two external resistors and a single external capacitor.
The threshold and trigger levels normally are two-thirds and one-third, respectively, of VCC. These levels can be
altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is
set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the
threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all other inputs
and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes
low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground.
The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of
5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1973–2010, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are
tested unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
NA555, NE555, SA555, SE555
SLFS022H – SEPTEMBER 1973 – REVISED JUNE 2010
www.ti.com
ORDERING INFORMATION (1)
VTHRES MAX
VCC = 15 V
TA
PACKAGE (2)
PDIP – P
11.2 V
NE555P
Tube of 75
NE555D
Reel of 2500
NE555DR
Reel of 2000
NE555PSR
Tube of 150
NE555PW
Reel of 2000
NE555PWR
Tube of 50
SA555P
Tube of 75
SA555D
Reel of 2000
SA555DR
Tube of 50
NA555P
Tube of 75
NA555D
Reel of 2000
NA555DR
Tube of 50
SE555P
Tube of 75
SE555D
Reel of 2500
SE555DR
CDIP – JG
Tube of 50
SE555JG
SE555JG
LCCC – FK
Tube of 55
SE555FK
SE555FK
SOP – PS
TSSOP – PW
PDIP – P
–40°C to 85°C
11.2 V
SOIC – D
PDIP – P
–40°C to 105°C
11.2 V
SOIC – D
PDIP – P
–55°C to 125°C
(1)
(2)
10.6
TOP-SIDE MARKING
Tube of 50
SOIC – D
0°C to 70°C
ORDERABLE PART NUMBER
SOIC – D
NE555P
NE555
N555
N555
SA555P
SA555
NA555P
NA555
SE555P
SE555D
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Table 1. FUNCTION TABLE
(1)
2
RESET
TRIGGER
VOLTAGE (1)
THRESHOLD
VOLTAGE (1)
OUTPUT
DISCHARGE
SWITCH
Low
Irrelevant
Irrelevant
Low
On
High
<1/3 VCC
Irrelevant
High
Off
High
>1/3 VCC
>2/3 VCC
Low
On
High
>1/3 VCC
<2/3 VCC
As previously established
Voltage levels shown are nominal.
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Copyright © 1973–2010, Texas Instruments Incorporated
Product Folder Link(s): NA555 NE555 SA555 SE555
NA555, NE555, SA555, SE555
www.ti.com
SLFS022H – SEPTEMBER 1973 – REVISED JUNE 2010
FUNCTIONAL BLOCK DIAGRAM
VCC
8
6
THRES
2
TRIG
CONT
5
Î
Î
Î Î
Î
Î Î
Î Î
RESET
4
Î
Î
Î
Î
Î
Î
Î
R1
R
3
OUT
1
S
7
DISCH
1
GND
A.
Pin numbers shown are for the D, JG, P, PS, and PW packages.
B.
RESET can override TRIG, which can override THRES.
Copyright © 1973–2010, Texas Instruments Incorporated
Product Folder Link(s): NA555 NE555 SA555 SE555
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NA555, NE555, SA555, SE555
SLFS022H – SEPTEMBER 1973 – REVISED JUNE 2010
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Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
VCC
Supply voltage (2)
VI
Input voltage
IO
Output current
qJA
Package thermal impedance (3)
18
CONT, RESET, THRES, TRIG
(4)
qJC
Package thermal impedance (5)
TJ
Operating virtual junction temperature
Tstg
(1)
(2)
(3)
(4)
(5)
(6)
MAX
(6)
UNIT
V
VCC
V
±225
mA
D package
97
P package
85
PS package
95
PW package
149
FK package
5.61
JG package
14.5
°C/W
°C/W
150
°C
Case temperature for 60 s
FK package
260
°C
Lead temperature 1, 6 mm (1/16 in) from case for 60 s
JG package
300
°C
150
°C
Storage temperature range
–65
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to GND.
Maximum power dissipation is a function of TJ(max), qJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) - TA)/qJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
The package thermal impedance is calculated in accordance with JESD 51-7.
Maximum power dissipation is a function of TJ(max), qJC, and TC. The maximum allowable power dissipation at any allowable case
temperature is PD = (TJ(max) - TC)/qJC. Operating at the absolute maximum TJ of 150°C can affect reliability.
The package thermal impedance is calculated in accordance with MIL-STD-883.
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage
VI
Input voltage
IO
Output current
TA
4
Operating free-air temperature
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MIN
MAX
NA555, NE555, SA555
4.5
16
SE555
4.5
18
CONT, RESET, THRES, and TRIG
UNIT
V
VCC
V
±200
mA
NA555
–40
105
NE555
0
70
SA555
–40
85
SE555
–55
125
°C
Copyright © 1973–2010, Texas Instruments Incorporated
Product Folder Link(s): NA555 NE555 SA555 SE555
NA555, NE555, SA555, SE555
www.ti.com
SLFS022H – SEPTEMBER 1973 – REVISED JUNE 2010
Electrical Characteristics
VCC = 5 V to 15 V, TA = 25°C (unless otherwise noted)
PARAMETER
MIN
THRES voltage level
10
10.6
8.8
10
11.2
4
2.4
3.3
4.2
30
250
30
250
5
5.2
4.5
5
5.6
1.1
1.67
2.2
0.5
2
0.7
1
4.8
TA = –55°C to 125°C
3
1.45
6
1.67
TA = –55°C to 125°C
1.9
0.3
0.5
0.9
0.7
1
TA = –55°C to 125°C
0.3
1.1
RESET at VCC
0.1
0.4
0.1
0.4
RESET at 0 V
–0.4
–1
–0.4
–1.5
20
100
20
100
10
10.4
9
10
11
2.6
3.3
4
0.1
0.25
0.4
0.75
2
2.5
9.6
TA = –55°C to 125°C
CONT voltage
(open circuit)
9.6
2.9
VCC = 5 V
TA = –55°C to 125°C
VCC = 15 V, IOL = 10 mA
VCC = 15 V, IOL = 50 mA
VCC = 15 V, IOL = 100 mA
VCC = 5 V, IOL = 5 mA
Output low, No load
Supply current
Output high, No load
3.8
0.1
0.15
0.4
mA
V
mA
nA
V
0.5
1
2
TA = –55°C to 125°C
2.2
2.7
V
2.5
TA = –55°C to 125°C
2.5
0.35
0.1
0.2
0.15
0.25
TA = –55°C to 125°C
0.1
0.35
0.15
0.4
0.8
13
13.3
12.75
13.3
12
12.5
3
TA = –55°C to 125°C
V
3.8
TA = –55°C to 125°C
TA = –55°C to 125°C
nA
0.2
VCC = 15 V, IOH = –200 mA
VCC = 5 V, IOL = –100 mA
3.3
TA = –55°C to 125°C
VCC = 5 V, IOL = 8 mA
VCC = 15 V, IOL = –100 mA
10.4
2.9
VCC = 15 V, IOL = 200 mA
VCC = 5 V, IOL = 3.5 mA
V
1.9
TRIG at 0 V
VCC = 15 V
(1)
MAX
3.3
DISCH switch off-state
current
High-level output voltage
TYP
2.7
VCC = 5 V
Low-level output voltage
MIN
9.4
TRIG voltage level
RESET current
MAX
VCC = 5 V
VCC = 15 V
RESET voltage level
TYP
UNIT
VCC = 15 V
THRES current (1)
TRIG current
NA555
NE555
SA555
SE555
TEST CONDITIONS
12.5
3.3
2.75
V
3.3
2
VCC = 15 V
10
12
10
VCC = 5 V
3
5
3
15
6
VCC = 15 V
9
10
9
13
VCC = 5 V
2
4
2
5
mA
This parameter influences the maximum value of the timing resistors RA and RB in the circuit of Figure 12. For example,
when VCC = 5 V, the maximum value is R = RA + RB ≉ 3.4 MΩ, and for VCC = 15 V, the maximum value is 10 MΩ.
Copyright © 1973–2010, Texas Instruments Incorporated
Product Folder Link(s): NA555 NE555 SA555 SE555
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NA555, NE555, SA555, SE555
SLFS022H – SEPTEMBER 1973 – REVISED JUNE 2010
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Operating Characteristics
VCC = 5 V to 15 V, TA = 25°C (unless otherwise noted)
MIN
(3)
Initial error of timing
interval (2)
Each timer, monostable
Temperature coefficient of
timing interval
Each timer, monostable (3)
TA = 25°C
Each timer, astable (5)
Each timer, astable
TYP
MAX
0.5
(4)
1.5
1.5
TA = MIN to MAX
(5)
(3)
Supply-voltage sensitivity of Each timer, monostable
(5)
timing interval
Each timer, astable
NA555
NE555
SA555
SE555
TEST
CONDITIONS (1)
PARAMETER
30
0.05
TYP
MAX
1
3
2.25
100 (4)
90
TA = 25°C
MIN
UNIT
50
ppm/
°C
150
0.2 (4)
0.15
0.1
%
0.5
0.3
%/V
Output-pulse rise time
CL = 15 pF,
TA = 25°C
100
200 (4)
100
300
ns
Output-pulse fall time
CL = 15 pF,
TA = 25°C
100
200 (4)
100
300
ns
(1)
(2)
(3)
(4)
(5)
6
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
Timing interval error is defined as the difference between the measured value and the average value of a random sample from each
process run.
Values specified are for a device in a monostable circuit similar to Figure 9, with the following component values: RA = 2 kΩ to 100 kΩ,
C = 0.1 mF.
On products compliant to MIL-PRF-38535, this parameter is not production tested.
Values specified are for a device in an astable circuit similar to Figure 12, with the following component values: RA = 1 kΩ to 100 kΩ,
C = 0.1 mF.
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Copyright © 1973–2010, Texas Instruments Incorporated
Product Folder Link(s): NA555 NE555 SA555 SE555
NA555, NE555, SA555, SE555
www.ti.com
SLFS022H – SEPTEMBER 1973 – REVISED JUNE 2010
TYPICAL CHARACTERISTICS
Data for temperatures below 0°C and above 70°C are applicable for SE555 circuits only.
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LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
4
2
1
0.7
0.4
0.2
0.1
0.07
10
7
VCC = 5 V
TA = −55°C
TA = 25°C
TA = 125°C
0.04
VOL − Low-Level Output Voltage − V
VOL − Low-Level Output Voltage − V
10
7
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.02
VCC = 10 V
4
2
TA = 25°C
1
0.7
TA= −55°C
TA = 125°C
0.4
0.2
0.1
0.07
0.04
0.02
0.01
0.01
1
2
4
7
10
20
40
70 100
1
IOL − Low-Level Output Current − mA
2
4
Figure 1.
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TA = −55°C
1
0.7
TA = 25°C
0.2
TA = 125°C
0.1
0.07
0.04
1.6
1.2
0.8
0.6
0.4
0.2
4
7
10
20
40
70 100
TA = 125°C
1
0.01
IOL − Low-Level Output Current − mA
TA = 25°C
1.4
0.02
2
70 100
TA = −55°C
1.8
2
1
40
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2.0
VCC = 15 V
0.4
20
DROP BETWEEN SUPPLY VOLTAGE AND OUTPUT
vs
HIGH-LEVEL OUTPUT CURRENT
( VCC − VOH) − Voltage Drop − V
VOL − Low-Level Output Voltage − V
4
10
Figure 2.
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
10
7
7
IOL − Low-Level Output Current − mA
0
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ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
VCC = 5 V to 15 V
1
2
4
7 10
20
40
70 100
IOH − High-Level Output Current − mA
Figure 3.
Figure 4.
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NA555, NE555, SA555, SE555
SLFS022H – SEPTEMBER 1973 – REVISED JUNE 2010
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TYPICAL CHARACTERISTICS (continued)
Data for temperatures below 0°C and above 70°C are applicable for SE555 circuits only.
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
NORMALIZED OUTPUT PULSE DURATION
(MONOSTABLE OPERATION)
vs
SUPPLY VOLTAGE
10
Pulse Duration Relative to Value at VCC = 10 V
Output Low,
No Load
9
I CC − Supply Current − mA
8
TA = 25°C
7
6
5
TA = −55°C
4
TA = 125°C
3
2
1
0
5
6
7
8
9
10
11
12
13
14
15
1.015
1.010
1.005
1
0.995
0.990
0.985
0
VCC − Supply Voltage − V
5
10
15
20
VCC − Supply Voltage − V
Figure 5.
Figure 6.
PROPAGATION DELAY TIME
vs
LOWEST VOLTAGE LEVEL
OF TRIGGER PULSE
NORMALIZED OUTPUT PULSE DURATION
(MONOSTABLE OPERATION)
vs
FREE-AIR TEMPERATURE
1000
VCC = 10 V
900
TA = 125°C
1.010
t PD – Propagation Delay Time – ns
Pulse Duration Relative to Value at TA = 255C
1.015
1.005
1
0.995
0.990
800
700
TA = 70°C
600
500
TA = 25°C
400
300
TA = 0°C
200
TA = –55°C
100
0
0.985
−75
−50
−25
0
25
50
75
TA − Free-Air Temperature − °C
100 125
0
0.05 0.1 0.15
0.2 0.25 0.3 0.35
Lowest Level of Trigger Pulse – ×VCC
Figure 7.
8
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0.4
Figure 8.
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Product Folder Link(s): NA555 NE555 SA555 SE555
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SLFS022H – SEPTEMBER 1973 – REVISED JUNE 2010
APPLICATION INFORMATION
Monostable Operation
For monostable operation, any of these timers can be connected as shown in Figure 9. If the output is low,
application of a negative-going pulse to the trigger (TRIG) sets the flip-flop (Q goes low), drives the output high,
and turns off Q1. Capacitor C then is charged through RA until the voltage across the capacitor reaches the
threshold voltage of the threshold (THRES) input. If TRIG has returned to a high level, the output of the threshold
comparator resets the flip-flop (Q goes high), drives the output low, and discharges C through Q1.
VCC
(5 V to 15 V)
RA
Î
Î
Î
4
7
6
Input
2
5
8
CONT
VCC
RL
RESET
DISCH
OUT
3
Output
THRES
TRIG
GND
1
Pin numbers shown are for the D, JG, P, PS, and PW packages.
Figure 9. Circuit for Monostable Operation
Monostable operation is initiated when TRIG voltage falls below the trigger threshold. Once initiated, the
sequence ends only if TRIG is high for at least 10 µs before the end of the timing interval. When the trigger is
grounded, the comparator storage time can be as long as 10 µs, which limits the minimum monostable pulse
width to 10 µs. Because of the threshold level and saturation voltage of Q1, the output pulse duration is
approximately tw = 1.1RAC. Figure 11 is a plot of the time constant for various values of RA and C. The threshold
levels and charge rates both are directly proportional to the supply voltage, VCC. The timing interval is, therefore,
independent of the supply voltage, so long as the supply voltage is constant during the time interval.
Applying a negative-going trigger pulse simultaneously to RESET and TRIG during the timing interval discharges
C and reinitiates the cycle, commencing on the positive edge of the reset pulse. The output is held low as long
as the reset pulse is low. To prevent false triggering, when RESET is not used, it should be connected to VCC.
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NA555, NE555, SA555, SE555
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
SLFS022H – SEPTEMBER 1973 – REVISED JUNE 2010
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10
RA = 9.1 kΩ
CL = 0.01 µF
RL = 1 kΩ
See Figure 9
RA = 10 MΩ
tw − Output Pulse Duration − s
1
Voltage − 2 V/div
Input Voltage
ÏÏÏÏÏÏ
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Output Voltage
RA = 1 MΩ
10−1
10−2
10−3
RA = 100 kΩ
RA = 10 kΩ
10−4
RA = 1 kΩ
10−5
Capacitor Voltage
0.001
0.01
0.1
1
10
100
C − Capacitance − µF
Time − 0.1 ms/div
Figure 10. Typical Monostable Waveforms
Figure 11. Output Pulse Duration vs Capacitance
Astable Operation
As shown in Figure 12, adding a second resistor, RB, to the circuit of Figure 9 and connecting the trigger input to
the threshold input causes the timer to self-trigger and run as a multivibrator. The capacitor C charges through
RA and RB and then discharges through RB only. Therefore, the duty cycle is controlled by the values of RA and
RB.
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
This astable connection results in capacitor C charging and discharging between the threshold-voltage level
(≉0.67 × VCC) and the trigger-voltage level (≉0.33 × VCC). As in the monostable circuit, charge and discharge
times (and, therefore, the frequency and duty cycle) are independent of the supply voltage.
VCC
(5 V to 15 V)
RB
Î
Î
Î
0.01 µF
Open
(see Note A) 5
CONT
4
RESET
7
DISCH
6
2
8
VCC
RL
3
OUT
Output
THRES
t
H
TRIG
GND
C
Output Voltage
tL
1
Pin numbers shown are for the D, JG, P, PS, and PW packages.
NOTE A: Decoupling CONT voltage to ground with a capacitor can
improve operation. This should be evaluated for individual
applications.
Figure 12. Circuit for Astable Operation
10
RL = 1 kW
See Figure 12
Voltage − 1 V/div
RA
RA = 5 kW
RB = 3 kW
C = 0.15 µF
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Capacitor Voltage
Time − 0.5 ms/div
Figure 13. Typical Astable Waveforms
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Other useful relationships are shown below.
period + t ) t + 0.693 (R ) 2R ) C
H
L
A
B
1.44
frequency [
(R ) 2R ) C
A
B
t
Output driver duty cycle +
R
L
B
+
t )t
R
)
2R
H
L
A
B
Output waveform duty cycle
t
R
H + 1–
B
+
t )t
R ) 2R
H
L
A
B
t
R
B
Low-to-high ratio + L +
t
R
)
R
H
A
B
f − Free-Running Frequency − Hz
Figure 12 shows typical waveforms generated during astable operation. The output high-level duration tH and
low-level duration tL can be calculated as follows:
100 k
t + 0.693 (R ) R C
H
A
B)
RA + 2 RB = 1 kΩ
t + 0.693 (R C
RA + 2 RB = 10 kΩ
L
B)
10 k
RA + 2 RB = 100 kΩ
1k
100
10
1
RA + 2 RB = 1 MΩ
RA + 2 RB = 10 MΩ
0.1
0.001
0.01
0.1
1
10
100
C − Capacitance − µF
Figure .
Figure 14. Free-Running Frequency
Missing-Pulse Detector
The circuit shown in Figure 15 can be used to detect a missing pulse or abnormally long spacing between
consecutive pulses in a train of pulses. The timing interval of the monostable circuit is retriggered continuously by
the input pulse train as long as the pulse spacing is less than the timing interval. A longer pulse spacing, missing
pulse, or terminated pulse train permits the timing interval to be completed, thereby generating an output pulse
as shown in Figure 16.
4
RESET
Input
2
8
VCC
OUT
0.01 µF
3
TRIG
DISCH
5
RL
CONT
THRES
7
6
GND
VCC = 5 V
RA = 1 kΩ
C = 0.1 µF
See Figure 15
RA
Output
Voltage − 2 V/div
VCC (5 V to 15 V)
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Output Voltage
C
1
Input Voltage
A5T3644
Capacitor Voltage
Time − 0.1 ms/div
Pin numbers shown are shown for the D, JG, P, PS, and PW packages.
Figure 15. Circuit for Missing-Pulse Detector
Figure 16. Completed Timing Waveforms for
Missing-Pulse Detector
Copyright © 1973–2010, Texas Instruments Incorporated
Product Folder Link(s): NA555 NE555 SA555 SE555
Submit Documentation Feedback
11
NA555, NE555, SA555, SE555
SLFS022H – SEPTEMBER 1973 – REVISED JUNE 2010
www.ti.com
Frequency Divider
By adjusting the length of the timing cycle, the basic circuit of Figure 9 can be made to operate as a frequency
divider. Figure 17 shows a divide-by-three circuit that makes use of the fact that retriggering cannot occur during
the timing cycle.
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
Voltage − 2 V/div
VCC = 5 V
RA = 1250 Ω
C = 0.02 µF
See Figure 9
Input Voltage
Output Voltage
Capacitor Voltage
Time − 0.1 ms/div
Figure 17. Divide-by-Three Circuit Waveforms
12
Submit Documentation Feedback
Copyright © 1973–2010, Texas Instruments Incorporated
Product Folder Link(s): NA555 NE555 SA555 SE555
NA555, NE555, SA555, SE555
www.ti.com
SLFS022H – SEPTEMBER 1973 – REVISED JUNE 2010
Pulse-Width Modulation
The operation of the timer can be modified by modulating the internal threshold and trigger voltages, which is
accomplished by applying an external voltage (or current) to CONT. Figure 18 shows a circuit for pulse-width
modulation. A continuous input pulse train triggers the monostable circuit, and a control signal modulates the
threshold voltage. Figure 19 shows the resulting output pulse-width modulation. While a sine-wave modulation
signal is shown, any wave shape could be used.
VCC (5 V to 15 V)
2
RL
8
RESET
Clock
Input
RA = 3 kΩ
C = 0.02 µF
RL = 1 kΩ
See Figure 18
VCC
OUT
TRIG
RA
Modulation Input Voltage
3
Output
Voltage − 2 V/div
4
7
DISCH
Modulation
5
Input
(see Note A)
CONT
THRES
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
6
GND
C
1
Clock Input Voltage
Output Voltage
Pin numbers shown are for the D, JG, P, PS, and PW packages.
NOTE A: The modulating signal can be direct or capacitively coupled
to CONT. For direct coupling, the effects of modulation source
voltage and impedance on the bias of the timer should be
considered.
Figure 18. Circuit for Pulse-Width Modulation
Capacitor Voltage
Time − 0.5 ms/div
Figure 19. Pulse-Width-Modulation Waveforms
Copyright © 1973–2010, Texas Instruments Incorporated
Product Folder Link(s): NA555 NE555 SA555 SE555
Submit Documentation Feedback
13
NA555, NE555, SA555, SE555
SLFS022H – SEPTEMBER 1973 – REVISED JUNE 2010
www.ti.com
Pulse-Position Modulation
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
As shown in Figure 20, any of these timers can be used as a pulse-position modulator. This application
modulates the threshold voltage and, thereby, the time delay, of a free-running oscillator. Figure 21 shows a
triangular-wave modulation signal for such a circuit; however, any wave shape could be used.
RA = 3 kΩ
RB = 500 Ω
RL = 1 kΩ
See Figure 20
VCC (5 V to 15 V)
RESET
2
RL
8
VCC
OUT
3
Output
TRIG
DISCH
Modulation
Input 5
(see Note A)
RA
CONT
THRES
7
6
RB
GND
Pin numbers shown are for the D, JG, P, PS, and PW packages.
NOTE A: The modulating signal can be direct or capacitively coupled
to CONT. For direct coupling, the effects of modulation
source voltage and impedance on the bias of the timer
should be considered.
Figure 20. Circuit for Pulse-Position Modulation
Submit Documentation Feedback
Modulation Input Voltage
Output Voltage
C
14
Voltage − 2 V/div
4
Capacitor Voltage
Time − 0.1 ms/div
Figure 21. Pulse-Position-Modulation Waveforms
Copyright © 1973–2010, Texas Instruments Incorporated
Product Folder Link(s): NA555 NE555 SA555 SE555
NA555, NE555, SA555, SE555
www.ti.com
SLFS022H – SEPTEMBER 1973 – REVISED JUNE 2010
Sequential Timer
Many applications, such as computers, require signals for initializing conditions during start-up. Other
applications, such as test equipment, require activation of test signals in sequence. These timing circuits can be
connected to provide such sequential control. The timers can be used in various combinations of astable or
monostable circuit connections, with or without modulation, for extremely flexible waveform control. Figure 22
shows a sequencer circuit with possible applications in many systems, and Figure 23 shows the output
waveforms.
VCC
4
RESET
2
8
VCC
3
OUT
TRIG
S
DISCH
5
0.01
µF
CONT
4
RESET
RA 33 kΩ
2
TRIG
0.001
µF
7
CA = 10 µF
RA = 100 kΩ
RB
CONT
0.01
µF
Output A
THRES
GND
1
CB
4
RESET
33 kΩ
2
0.001
µF
DISCH 7
5
6
THRES
GND
1
CA
8
VCC
3
OUT
DISCH
5
6
0.01
µF
CONT
THRES
GND
1
CC
CC = 14.7 µF
RC = 100 kΩ
Output B
CB = 4.7 µF
RB = 100 kΩ
TRIG
8
VCC
3
OUT
RC
7
6
Output C
Pin numbers shown are for the D, JG, P, PS, and PW packages.
NOTE A: S closes momentarily at t = 0.
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏ
ÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏ
ÏÏÏÏÏÏÏ ÏÏÏÏÏ
ÏÏÏ
ÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏ
ÏÏÏ
ÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏ
ÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏ
ÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
ÏÏ
ÏÏÏÏ
ÏÏ ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏ
ÏÏ ÏÏÏÏÏ
ÏÏÏ
ÏÏÏ
ÏÏÏ
ÏÏÏ
Figure 22. Sequential Timer Circuit
See Figure 22
Voltage − 5 V/div
Output A
twA
twA = 1.1 RACA
twB
Output B
twB = 1.1 RBCB
Output C
twC
twC = 1.1 RCCC
t=0
t − Time − 1 s/div
Figure 23. Sequential Timer Waveforms
Copyright © 1973–2010, Texas Instruments Incorporated
Product Folder Link(s): NA555 NE555 SA555 SE555
Submit Documentation Feedback
15
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
JM38510/10901BPA
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510
/10901BPA
M38510/10901BPA
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510
/10901BPA
NA555D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
NA555
NA555DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
NA555
NA555DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
NA555
NA555DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
NA555
NA555P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 105
NA555P
NA555PE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 105
NA555P
NE555D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
NE555
NE555DE4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
NE555
NE555DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
NE555
NE555DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
NE555
NE555DRE4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
NE555
NE555DRG3
PREVIEW
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
0 to 70
NE555
NE555DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
NE555
NE555P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
NE555P
NE555PE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
NE555P
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
NE555PSLE
OBSOLETE
SO
PS
8
TBD
Call TI
Call TI
0 to 70
NE555PSR
ACTIVE
SO
PS
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
N555
NE555PSRE4
ACTIVE
SO
PS
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
N555
NE555PSRG4
ACTIVE
SO
PS
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
N555
NE555PW
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
N555
NE555PWE4
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
N555
NE555PWG4
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
N555
NE555PWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
N555
NE555PWRE4
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
N555
NE555PWRG4
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
N555
NE555Y
OBSOLETE
TBD
Call TI
Call TI
0 to 70
SA555D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
SA555
SA555DE4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
SA555
SA555DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
SA555
SA555DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
SA555
SA555DRE4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
SA555
SA555DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
SA555
SA555P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
SA555P
SA555PE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
SA555P
0
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
SE555D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
SE555
SE555DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
SE555
SE555DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
SE555
SE555DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
SE555
SE555FKB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
SE555FKB
SE555JG
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
SE555JG
SE555JGB
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
-55 to 125
SE555JGB
SE555N
OBSOLETE
PDIP
N
8
TBD
Call TI
Call TI
-55 to 125
SE555P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-55 to 125
SE555P
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Addendum-Page 3
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SE555, SE555M :
• Catalog: SE555
• Military: SE555M
• Space: SE555-SP, SE555-SP
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
NA555DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
NA555DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
NE555DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
NE555DRG4
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
NE555DRG4
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
NE555PSR
SO
PS
8
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
NE555PWR
TSSOP
PW
8
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
SA555DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SA555DRG4
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SE555DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SE555DRG4
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
NA555DR
SOIC
D
8
2500
340.5
338.1
20.6
NA555DR
SOIC
D
8
2500
367.0
367.0
35.0
NE555DR
SOIC
D
8
2500
340.5
338.1
20.6
NE555DRG4
SOIC
D
8
2500
340.5
338.1
20.6
NE555DRG4
SOIC
D
8
2500
367.0
367.0
35.0
NE555PSR
SO
PS
8
2000
367.0
367.0
38.0
NE555PWR
TSSOP
PW
8
2000
367.0
367.0
35.0
SA555DR
SOIC
D
8
2500
340.5
338.1
20.6
SA555DRG4
SOIC
D
8
2500
340.5
338.1
20.6
SE555DR
SOIC
D
8
2500
367.0
367.0
35.0
SE555DRG4
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
0.063 (1,60)
0.015 (0,38)
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification.
Falls within MIL STD 1835 GDIP1-T8
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