LINER LTC6655 Dual serial 18-bit softspan iout dac Datasheet

LTC2758
Dual Serial 18-Bit
SoftSpan IOUT DACs
Description
Features
n
n
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Maximum 18-Bit INL Error: ±1 LSB Over Temperature
Program or Pin-Strap Six Output Ranges:
0V to 5V, 0V to 10V, –2.5V to 7.5V, ±2.5V, ±5V, ±10V
Guaranteed Monotonic Over Temperature
Glitch Impulse 0.4nV • s (3V), 2nV • s (5V)
18-Bit Settling Time: 2.1µs
2.7V to 5.5V Single Supply Operation
1µA Maximum Supply Current
Voltage-Controlled Offset and Gain Trims
Serial Interface with Readback of All Registers
Clear and Power-On-Reset to 0V Regardless of
Output Range
48-Pin 7mm × 7mm LQFP Package
Applications
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The LTC®2758 is a dual 18-bit multiplying serial-input,
current-output digital-to-analog converter. LTC2758A
provides full 18-bit performance (INL and DNL of ±1LSB
maximum) over temperature without any adjustments.
18-bit monotonicity is guaranteed in all performance
grades. This SoftSpan™ DAC operates from a single 3V
to 5V supply and offers six output ranges (up to ±10V)
that can be programmed through the 3-wire SPI serial
interface or pin-strapped for operation in a single range.
Any on-chip register (including DAC output-range settings) can be read for verification in just one instruction
cycle; and if you change register content, the altered
register will be automatically read back during the next
instruction cycle.
Voltage-controlled offset and gain adjustments are also
provided; and the power-on reset circuit and CLR pin both
reset the DAC outputs to 0V regardless of output range.
Instrumentation
Medical Devices
Automatic Test Equipment
Process Control and Industrial Automation
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
Typical Application
Dual 18-Bit VOUT DAC with Software-Selectable Ranges
REFERENCE
5V
–
+
GEADJA ROFSA REFA
RCOMA
0.4
RINA
RFBA
VDD
IOUT1A
0.1µF
DAC A
4
IOUT2A
VOSADJA
LTC2758
RFBB
IOUT1B
DAC B
GND
LT1012
RCOMB
+
–
GAIN B
ADJUST
IOUT2B
VOSADJB
GEADJB ROFSB REFB
0V TO 10V RANGE
0.8
0.6
5V
SPI WITH
READBACK
1.0
INL (LSB)
GAIN A
ADJUST
LT1012
LTC2758 Integral Nonlinearity
27pF
–
+
VOUTA
LT1468
OFFSET A ADJUST
27pF
–
+
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
VOUTB
LT1468
0
65536
131072
CODE
196608
262143
2758 TA01b
OFFSET B ADJUST
RINB
2758 TA01a
REFERENCE
5V
For more information www.linear.com/LTC2758
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1
LTC2758
Absolute Maximum Ratings
Pin Configuration
(Notes 1, 2)
48
47
46
45
44
43
42
41
40
39
38
37
ROFSA
ROFSA
RFBA
RFBA
IOUT1A
VOSADJA
VOSADJB
IOUT1B
RFBB
RFBB
ROFSB
ROFSB
TOP VIEW
REF A 1
REF A 2
RCOMA 3
GEADJA 4
RINA 5
RINA 6
GND 7
IOUT2AS 8
IOUT2AF 9
GND 10
CS/LD 11
SDI 12
36
35
34
33
32
31
30
29
28
27
26
25
REF B
REF B
RCOMB
GEADJB
RINB
RINB
GND
IOUT2BS
IOUT2BF
GND
LDAC
S2
SCK 13
SRO 14
GND 15
VDD 16
GND 17
GND 18
CLR 19
RFLAG 20
DNC 21
M-SPAN 22
S0 23
S1 24
IOUT1X , IOUT2X to GND.............................................±0.3V
RINX, RCOMX , REFX, RFBX , ROFSX , VOSADJX ,
GEADJX to GND........................................................ ±18V
VDD to GND................................................... –0.3V to 7V
Digital Inputs to GND.................................... –0.3V to 7V
Digital Outputs to GND ......–0.3V to VDD +0.3V (max 7V)
Operating Temperature Range
LTC2758C................................................. 0°C to 70°C
LTC2758I..............................................–40°C to 85°C
Maximum Junction Temperature........................... 150°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................... 300°C
LX PACKAGE
48-LEAD (7mm × 7mm) PLASTIC LQFP
TJMAX = 150°C, θJA = 53°C/W
order information
http://www.linear.com/product/LTC2758#orderinfo
LEAD FREE FINISH
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2758BCLX#PBF
LTC2758LX
48-Lead (7mm × 7mm) Plastic LQFP
0°C to 70°C
LTC2758BILX#PBF
LTC2758LX
48-Lead (7mm × 7mm) Plastic LQFP
–40°C to 85°C
LTC2758ACLX#PBF
LTC2758LX
48-Lead (7mm × 7mm) Plastic LQFP
0°C to 70°C
LTC2758AILX#PBF
LTC2758LX
48-Lead (7mm × 7mm) Plastic LQFP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
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LTC2758
Electrical Characteristics
VDD = 5V, V(RINX) = 5V unless otherwise specified. The l denotes the
specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
LTC2758B
TYP
MAX
MIN
LTC2758A
TYP
MAX
UNITS
Static Performance
Resolution
l
18
18
18
Bits
18
Bits
Monotonicity
l
DNL
Differential Nonlinearity
l
±1
±0.2
±1
LSB
INL
Integral Nonlinearity
l
±2
±0.5
±1
LSB
GE
Gain Error
All Output Ranges
±6
±32
Gain Error Temperature Coefficient
∆Gain/∆Temp
Bipolar Zero Error
All Bipolar Ranges
l
Unipolar Zero-Scale Error
Unipolar Ranges (Note 3)
l
PSR
Power Supply Rejection
VDD = 5V, ±10%
VDD = 3V, ±10%
l
l
ILKG
IOUT1 Leakage Current
TA = 25°C
TMIN to TMAX
l
BZE
±48
l
±0.25
Bipolar Zero Temperature Coefficient
±0.25
±36
±1
±3.2
±0.03
±3.2
LSB
±1.6
±4
±0.1
±0.3
±0.8
±2
LSB/V
LSB/V
±2
±5
±0.05
±2
±5
±0.2
±0.03
LSB
ppm/°C
±24
±0.2
±0.05
LSB
ppm/°C
nA
nA
VDD = 5V, V(RINX) = 5V unless otherwise specified. The l denotes specifications that apply over the full operating temperature range,
otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Analog Pins
Reference Inverting Resistors
(Note 4)
l
16
20
kΩ
RREF
DAC Input Resistance
(Notes 5, 6)
l
8
10
kΩ
RFB
Feedback Resistors
(Note 6)
l
8
10
kΩ
(Note 6)
l
16
20
kΩ
l
1024
1280
kΩ
l
2048
ROFS
Bipolar Offset Resistors
RVOSADJ
Offset Adjust Resistors
RGEADJ
Gain Adjust Resistors
CIOUT1
Output Capacitance
2560
kΩ
Full-Scale
Zero-Scale
90
40
pF
Output Settling Time
Span Code = 0000, 10V Step. To ±0.0004%
FS (Note 7)
2.1
μs
Glitch Impulse
VDD = 5V (Note 8)
VDD = 3V (Note 8)
2
0.4
nV•s
nV•s
Digital-to-Analog Glitch Impulse
VDD = 5V (Note 9)
VDD = 3V (Note 9)
2.6
0.6
nV•s
nV•s
Reference Multiplying BW
0V to 5V Range,
Code = Full Scale, –3dB Bandwidth
1
MHz
Multiplying Feedthrough Error
0V to 5V Range, VREF = ±10V, 10kHz
Sine Wave
0.4
mV
Dynamic Performance
THD
Analog Crosstalk
(Note 10)
–109
dB
Total Harmonic Distortion
(Note 11) Multiplying
–110
dB
Output Noise Voltage Density
(Note 12) at IOUT1
13
nV/√Hz
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LTC2758
Electrical Characteristics
VDD = 5V, V(RINX) = 5V unless otherwise specified. The l denotes the
specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply
VDD
Supply Voltage
IDD
VDD Supply Current
Digital Inputs = 0V or VDD
l
VIH
Digital Input High Voltage
3.3V ≤ VDD ≤ 5.5V
2.7V ≤ VDD < 3.3V
l
l
VIL
Digital Input Low Voltage
4.5V < VDD ≤ 5.5V
2.7V ≤ VDD ≤ 4.5V
l
l
IIN
Digital Input Current
VIN = GND to VDD
CIN
Digital Input Capacitance
VOH
VOL
l
2.7
0.5
5.5
V
2
μA
Digital Inputs
2.4
2
V
V
0.8
0.6
V
V
l
±1
µA
VIN = 0V (Note 13)
l
6
pF
IOH = 200µA
2.7V ≤ VDD ≤ 5.5V
l
IOL = 200µA
2.7V ≤ VDD ≤ 5.5V
l
Hysteresis Voltage
0.1
V
Digital Outputs
timing Characteristics
otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
VDD – 0.4
V
0.4
V
The l denotes specifications that apply over the full operating temperature range,
CONDITIONS
MIN
TYP
MAX
UNITS
VDD = 4.5V to 5.5V
t1
SDI Valid to SCK Set-Up
l
7
ns
t2
SDI Valid to SCK Hold
l
7
ns
t3
SCK High Time
l
11
ns
t4
SCK Low Time
l
11
ns
t5
CS/LD Pulse Width
l
9
ns
t6
LSB SCK High to CS/LD High
l
4
ns
t7
CS/LD Low to SCK Positive Edge
l
4
ns
t8
CS/LD High to SCK Positive Edge
l
4
ns
t9
SRO Propagation Delay
t10
CLR Pulse Width Low
l
36
ns
t11
LDAC Pulse Width Low
l
15
ns
t12
CLR Low to RFLAG Low
CLOAD = 10pF (Note 13)
l
50
ns
t13
CS/LD High to RFLAG High
CLOAD = 10pF (Note 13)
l
40
ns
SCK Frequency
50% Duty Cycle (Note 14)
l
40
MHz
CLOAD = 10pF
18
l
ns
VDD = 2.7V to 3.3V
t1
SDI Valid to SCK Set-Up
9
ns
t2
SDI Valid to SCK Hold
(Note 13)
t3
SCK High Time
CL = 10pF
l
9
ns
l
15
ns
t4
SCK Low Time
l
15
ns
t5
CS/LD Pulse Width
l
12
ns
t6
LSB SCK High to CS/LD High
l
5
ns
4
l
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LTC2758
timing Characteristics
otherwise specifications are at TA = 25°C.
The l denotes specifications that apply over the full operating temperature range,
SYMBOL
PARAMETER
t7
CS/LD Low to SCK Positive Edge
CONDITIONS
l
MIN
5
ns
t8
CS/LD High to SCK Positive Edge
l
5
ns
t9
SRO Propagation Delay
CLOAD = 10pF
TYP
MAX
26
l
UNITS
ns
t10
CLR Pulse Width Low
l
t11
LDAC Pulse Width Low
l
t12
CLR Low to RFLAG Low
CLOAD = 10pF (Note 13)
l
70
ns
t13
CS/LD High to RFLAG high
CLOAD = 10pF (Note 13)
l
60
ns
SCK Frequency
50% Duty Cycle (Note 14)
l
25
MHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 3: Calculation from feedback resistance and IOUT1 leakage current
specifications; not production tested. In most applications, unipolar zeroscale error is dominated by contributions from the output amplifier.
Note 4: Input resistors measured from RINX to RCOMX ; feedback resistors
measured from RCOMX to REFX.
Note 5: DAC input resistance is independent of code.
Note 6: Parallel combination of the resistances from the specified pin to
IOUT1X and from the specified pin to IOUT2X.
Note 7: Using LT1468 with CFEEDBACK = 27pF. A ±0.0004% settling time
of 1.8µs can be achieved by optimizing the time constant on an individual
basis. See Application Note 120, 1ppm Settling Time Measurement for a
Monolithic 18-Bit DAC.
60
ns
20
ns
Note 8: Measured at the major carry transition, 0V to 5V range. Output
amplifier: LT1468; CFB = 50pF.
Note 9: Full-scale transition; REF = 0V.
Note 10: Analog Crosstalk is defined as the AC voltage ratio VOUTB/VREFA ,
expressed in dB. REFB is grounded, and DAC B is set to 0V-5V span and
zero-, mid- or full- scale code. VREFA is a 3VRMS, 1kHz sine wave.
Note 11: REF = 6VRMS at 1kHz. 0V to 5V range. DAC code = FS. Output
amplifier = LT1468.
Note 12: Calculation from Vn = √4kTRB, where k = 1.38E-23 J/°K
(Boltzmann constant), R = resistance (Ω), T = temperature (°K), and B =
bandwidth (Hz). 0V to 5V Range; zero-, mid-, or full-scale.
Note 13: Guaranteed by design; not production tested.
Note 14: When using SRO, maximum SCK frequency fMAX is limited by
SRO propagation delay t9 as follows:
⎛
⎞
1
fMAX = ⎜
⎟ , where tS is the setup time of the receiving device.
⎝ 2 (t 9 + tS )⎠
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5
LTC2758
Typical Performance Characteristics
VDD = 5V, V(RINX) = 5V, TA = 25°C, unless otherwise noted.
Integral Nonlinearity (INL)
1.0
0V TO 10V RANGE
0.8
0.8
0.6
0.6
0.4
0.4
0.4
0.2
0.2
0.2
0
–0.2
INL (LSB)
0.6
0
–0.2
0
–0.2
–0.4
–0.4
–0.4
–0.6
–0.6
–0.6
–0.8
–0.8
–0.8
–1.0
–1.0
–1.0
65536
131072
CODE
196608
262143
0
65536
131072
CODE
196608
2758 G02
INL vs Temperature
0.8
DNL vs Temperature
1.0
0V TO 10V RANGE
0.6
0.8
DNL (LSB)
0
–INL
0
–0.6
–0.6
–0.8
–0.8
–1.0
–40
–20
0
20
40
TEMPERATURE (°C)
60
+DNL
–0.2
–0.4
–DNL
16
±0.15ppm/°C TYP
0.8
0.6
8
INL (LSB)
BZE (LSB)
4
0
–4
±5V
±10V
±2.5V
–2.5V TO 7.5V
–12
–16
–40
–20
0
20
40
TEMPERATURE (°C)
60
80 85
2758 G07
6
16
12
–20
0
20
40
TEMPERATURE (°C)
60
0
–40
80 85
–20
0
20
40
TEMPERATURE (°C)
60
DNL vs Reference Voltage
1.0
±5V RANGE
0.8
0.4
0.4
0.2
0.2
0
–0.2
–INL
–INL
–0.2
–0.4
–0.6
–0.6
–0.8
–0.8
4
6
8
10
2758 G08
+DNL
+DNL
–DNL
–DNL
0
–0.4
–1.0
–10 –8 –6 –4 –2 0 2
V(RIN) (V)
±5V RANGE
0.6
+INL
+INL
80 85
2758 G06
INL vs Reference Voltage
12
–8
20
±2.5V
±5V
±10V
0V TO 5V
0V TO 10V
–2.5V TO 7.5V
2758 G05
1.0
2758 G03
4
2758 G04
Bipolar Zero Error
vs Temperature
–10V
TO
10V
8
–1.0
–40
80 85
±0.25ppm/°C TYP
24
0.2
–0.4
0V
–5V
0V
TO
TO
TO
5V
5V
10V
OUTPUT RANGE
28
0.4
0.2
–0.2
0V TO 10V RANGE
0.6
+INL
0.4
–2.5V –2.5V
TO
TO
2.5V 7.5V
Gain Error vs Temperature
32
GE (LSB)
1.0
262143
DNL (LSB)
0
2758 G01
INL (LSB)
INL vs Output Range
1.0
0V TO 10V RANGE
0.8
DNL (LSB)
INL (LSB)
Differential Nonlinearity (DNL)
1.0
–1.0
–10 –8 –6 –4 –2 0 2
V(RIN) (V)
4
6
8
10
2758 G09
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LTC2758
Typical Performance Characteristics
VDD = 5V, V(RINX) = 5V, TA = 25°C, unless otherwise noted.
INL vs VDD
1.0
1.0
0V TO 10V RANGE
0.8
0.8
+INL
–20
0.4
DNL (LSB)
0.2
0
–INL
–0.2
0.2
+DNL
0
–0.2
–DNL
–0.4
–0.4
–0.6
–0.6
–0.8
–0.8
–1.0
2.5
–1.0
2.5
3
3.5
4
4.5
VDD (V)
5
5.5
ATTENUATION (dB)
0.4
ALL BITS ON
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0V TO 10V RANGE
0.6
0.6
INL (LSB)
Multiplying Frequency Response
vs Digital Code
DNL vs VDD
–40
–60
–80
–100
ALL BITS OFF
3
3.5
4
4.5
VDD (V)
5
–140
100
5.5
Settling Full-Scale Step
Mid-Scale Glitch (VDD = 3V)
1M
GATED
SETTLING
WAVEFORM
100µV/DIV
(AVERAGED)
2nV•s TYP
CS/LD
5V/DIV
VOUT
5mV/DIV
(AVERAGED)
VOUT
5mV/DIV
(AVERAGED)
2758 G13
2758 G14
500ns/DIV
0V TO 5V RANGE
LT1468 OUTPUT AMPLIFIER
CFEEDBACK = 50pF
RISING MAJOR CARRY TRANSITION.
FALLING TRANSITION IS SIMILAR OR BETTER.
Logic Threshold
vs Supply Voltage
Supply Current
vs Logic Input Voltage
LOGIC THRESHOLD (V)
4
3
2
VDD = 5V
1
Supply Current
vs Update Frequency
2
100
1.75
10
1.5
SUPPLY CURRENT (mA)
CLR, LDAC, SDI, SCK,
CS/LD TIED TOGETHER
RISING
1.25
2758 G15
500ns/DIV
0V TO 5V RANGE
LT1468 OUTPUT AMPLIFIER
CFEEDBACK = 50pF
RISING MAJOR CARRY TRANSITION.
FALLING TRANSITION IS SIMILAR OR BETTER.
LT1468 AMP; CFEEDBACK = 20pF
0V TO 10V STEP
VREF = –10V; SPAN CODE = 0000
tSETTLE = 1.8µs to 0.0004% (18 BITS)
10M
Mid-Scale Glitch (VDD = 5V)
CS/LD
5V/DIV
CS/LD
5V/DIV
SUPPLY CURRENT (mA)
100k
10k
FREQUENCY (Hz)
2758 G12
0.4nV•s TYP
5
1k
2758 G11
2758 G10
500ns/DIV
0V TO 5V OUTPUT RANGE
LT1468 OUTPUT AMPLIFIER
CFEEDBACK = 15pF
–120
FALLING
1
0.75
ALTERNATING ZERO-SCALE
AND FULL-SCALE
1
VDD = 5V
0.1
VDD = 3V
0.01
0.001
VDD = 3V
0
0
1
3
4
2
DIGITAL INPUT VOLTAGE (V)
5
2758 G16
0.5
2.5
3
3.5
4
4.5
VDD (V)
5
5.5
2758 G17
0.0001
1
100
10k
1M
SCK FREQUENCY (Hz)
100M
2758 G18
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7
LTC2758
Pin Functions
REFA (Pins 1, 2): Feedback Resistor for the DAC A Reference Inverting Amplifier, and Reference Input for DAC A.
The 20k feedback resistor is connected internally from
REFA to RCOMA. For normal operation tie this pin to the
output of the DAC A reference inverting amplifier (see
Typical Application). Typically –5V; accepts up to ±15V.
Pins 1 and 2 are internally shorted together.
RCOMA (Pin 3): Virtual Ground Point for the DAC A Reference Amplifier Inverting Resistors. The 20k reference
inverting resistors are connected internally from RINA to
RCOMA and from RCOMA to REFA, respectively (see Block
Diagram). For normal operation tie RCOMA to the negative
input of the external reference inverting amplifier (see
Typical Application).
GEADJA (Pin 4): Gain Adjust Pin for DAC A. This control pin
can be used to null gain error or to compensate for reference
errors. The gain change expressed in LSB is the same for
any output range. See System Offset and Gain Adjustments
in the Operation section. Tie to ground if not used.
RINA (Pins 5, 6): Input Resistor for the DAC A External
Reference Inverting Amplifier. The 20k input resistor is
connected internally from RINA to RCOMA. For normal operation tie RINA to the external positive reference voltage
(see Typical Application). Either or both of these precisionmatched resistor sets (each set comprising RINX, RCOMX
and REFX) may be used to invert positive references to
provide the negative voltages needed by the DACs. Typically 5V; accepts up to ±15V. Pins 5 and 6 are internally
shorted together.
GND (Pins 7, 10, 15, 17, 18, 27, 30): Ground; tie to
ground.
IOUT2AS, IOUT2AF (Pins 8, 9): DAC A Current Output
Complement Sense and Force Pins. Tie to ground via a
clean, low-impedance path. These pins may be used with
a precision ground buffer amp as a Kelvin sensing pair
(see the Applications Information section).
CS/LD (Pin 11): Synchronous Chip Select and Load Input
Pin.
SDI (Pin 12): Serial Data Input. Data is clocked in on the
rising edge of the serial clock (SCK) when CS/LD is low.
SCK (Pin 13): Serial Clock Input.
8
SRO (Pin 14): Serial Readback Output. Data is clocked out
on the falling edge of SCK. Readback data begins clocking
out after the last address bit A0 is clocked in. SRO is an
active output only when the chip is selected (i.e., when
CS/LD is low). Otherwise SRO presents a high-impedance
output in order to allow other parts to control the bus.
VDD (Pin 16): Positive Supply Input; 2.7V ≤ VDD ≤ 5.5V. Bypass with a 0.1μF low-ESR ceramic capacitor to ground.
CLR (Pin 19): Asynchronous Clear Input. When this pin is
low, all DAC registers (both code and span) are cleared to
zero. All DAC outputs are cleared to zero volts.
RFLAG (Pin 20): Reset Flag Output. An active low output
is asserted when there is a power-on reset or a clear event.
Returns high when an Update command is executed.
DNC (Pin 21): Do Not Connect.
M-SPAN (Pin 22): Manual Span Control Pin. M-SPAN is
used in conjunction with pins S2, S1 and S0 (Pins 25, 24
and 23) to configure all DACs for operation in a single,
fixed output range.
To configure the part for manual-span use, tie M-SPAN
directly to VDD. The DAC output range is then set via
hardware pin strapping of pins S2, S1 and S0 (rather than
through the SPI port); and Write and Update commands
have no effect on the active output span.
To configure the part for SoftSpan use, tie M-SPAN directly
to GND. The output ranges are then individually controllable through the SPI port; and pins S2, S1 and S0 have
no effect.
See Manual Span Configuration in the Operation section. MSPAN must be connected either directly to GND (SoftSpan
configuration) or to VDD (manual-span configuration).
S0 (Pin 23): Span Bit 0 Input. In Manual Span mode (MSPAN tied to VDD), Pins S0, S1 and S2 are pin-strapped
to select a single fixed output range for all DACs. These
pins should be tied to either GND or VDD even if they are
unused.
S1 (Pin 24): Span Bit 1 Input. In Manual Span mode (MSPAN tied to VDD), Pins S0, S1 and S2 are pin-strapped to
select a single fixed output range for all DACs. These pins
should be tied to either GND or VDD even if they are unused.
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LTC2758
Pin Functions
S2 (Pin 25): Span Bit 2 Input. In Manual Span mode (MSPAN tied to VDD), Pins S0, S1 and S2 are pin-strapped to
select a single fixed output range for all DACs. These pins
should be tied to either GND or VDD even if they are unused.
LDAC (Pin 26): Asynchronous DAC Load Input. When
LDAC is a logic low, all DACs are updated (CS/LD must
be high).
IOUT2BF, IOUT2BS (Pins 28, 29): DAC B Current Output
Complement Force and Sense Pins. Tie to ground via a
clean, low-impedance path. These pins may be used with
a precision ground buffer amp as a Kelvin sensing pair
(see the Applications Information section).
RINB (Pins 31, 32): Input Resistor for the DAC B External
Reference Inverting Amplifier. The 20k input resistor is
connected internally from RINB to RCOMB. For normal operation tie RINB to the external positive reference voltage
(see Typical Application). Either or both of these precisionmatched resistor sets (each set comprising RINX, RCOMX
and REFX) may be used to invert positive references to
provide the negative voltages needed by the DACs. Typically 5V; accepts up to ±15V. Pins 31 and 32 are internally
shorted together.
GEADJB (Pin 33): Gain Adjust Pin for DAC B. This control
pin can be used to null gain error or to compensate for
reference errors. The gain change expressed in LSB is
the same for any output range. See System Offset and
Gain Adjustments in the Operation section. Tie to ground
if not used.
RCOMB (Pin 34): Virtual Ground Point for the DAC B Reference Amplifier Inverting Resistors. The 20k reference
inverting resistors are connected internally from RINB to
RCOMB and from RCOMB to REFB, respectively (see Block
Diagram). For normal operation tie RCOMB to the negative
input of the external reference inverting amplifier (see
Typical Application).
REFB (Pins 35, 36): Feedback Resistor for the DAC B
Reference Inverting Amplifier, and Reference Input for
DAC B. The 20k feedback resistor is connected internally
from REFB to RCOMB. For normal operation tie this pin to
the output of the DAC B reference inverting amplifier (see
Typical Application). Typically –5V; accepts up to ±15V.
Pins 35 and 36 are internally shorted together.
ROFSB (Pins 37, 38): Bipolar Offset Resistor for DAC B.
These pins provide the translation of the output voltage
range for bipolar spans. Accepts up to ±15V; for normal
operation tie to the positive reference voltage at RINB (Pins
31, 32). Pins 37 and 38 are internally shorted together.
RFBB (Pins 39, 40): DAC B Feedback Resistor. For normal
operation tie to the output of the I/V converter amplifier for
DAC B (see Typical Application). The DAC output current
from IOUT1B flows through the feedback resistor to the
RFBB pins. Pins 39 and 40 are internally shorted together.
IOUT1B (Pin 41): DAC B Current Output. This pin is a virtual
ground when the DAC is operating and should reside at
0V. For normal operation tie to the negative input of the
I/V converter amplifier for DAC B (see Typical Application).
VOSADJB (Pin 42): DAC B Offset Adjust Pin. This voltagecontrol pin can be used to null unipolar offset or bipolar
zero error. The offset change expressed in LSB is the same
for any output range. See System Offset and Gain Adjustments in the Operation section. Tie to ground if not used.
VOSADJA (Pin 43): DAC A Offset Adjust Pin. This voltagecontrol pin can be used to null unipolar offset or bipolar
zero error. The offset change expressed in LSB is the same
for any output range. See System Offset and Gain Adjustments in the Operation section. Tie to ground if not used.
IOUT1A (Pin 44): DAC A Current Output. This pin is a virtual
ground when the DAC is operating and should reside at
0V. For normal operation tie to the negative input of the
I/V converter amplifier for DAC A (see Typical Application).
RFBA (Pins 45, 46): DAC A Feedback Resistor. For normal
operation tie to the output of the I/V converter amplifier for
DAC A (see Typical Application). The DAC output current
from IOUT1A flows through the feedback resistor to the
RFBA pins. Pins 45 and 46 are internally shorted together.
ROFSA (Pins 47, 48): Bipolar Offset Resistor for DAC A.
This pin provides the translation of the output voltage
range for bipolar spans. Accepts up to ±15V; for normal
operation tie to the positive reference voltage at RINA
(Pins 5, 6). Pins 47 and 48 are internally shorted together.
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9
LTC2758
Block Diagram
16
VDD
31,32
RINB
5,6
RINA
4
3
2.56M
GEADJA
RCOMA
2.56M
20k
20k
RCOMB
LTC2758
1,2
REFA
GEADJB
37,38
ROFSB
47,48
ROFSA
45,46
RFBA
44
8
9
43
34
35,36
REFB
20k
20k
33
CODE REGISTERS
18
DAC A
18-BIT WITH
SPAN SELECT
IOUT1A
IOUT2AS
DAC REG
CODE REGISTERS
INPUT REG
INPUT REG
SPAN REGISTERS
3
DAC REG
IOUT2AF
DAC REG
SPAN REGISTERS
INPUT REG
INPUT REG
DAC REG
39,40
RFBB
18
DAC B
18-BIT WITH
SPAN SELECT
3
IOUT1B
IOUT2BS
IOUT2BF
VOSADJA
VOSADJB
POWER-ON
RESET
7, 10, 15, 17,
18, 27, 30
GND
41
29
28
42
CONTROL AND READBACK LOGIC
22
M-SPAN
23
S0
24
S1
25
S2
20
RFLAG
19
CLR
11
CS/LD
12
SDI
13
SCK
26
LDAC
14
SRO
2758 BD
timing diagram
t1
t2
t3
1
SCK
t6
t4
2
31
32
t8
SDI
LSB
t5
t7
CS/LD
t11
LDAC
t9
SRO
10
Hi-Z
LSB
2758 TD
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LTC2758
Operation
Output Ranges
VDD
The LTC2758 is a dual, current-output, serial-input precision
multiplying DAC with selectable output ranges. Ranges can
either be programmed in software for maximum flexibility
(each of the DACs can be programmed to any one of six
output ranges) or hardwired through pin-strapping. Two
unipolar ranges are available (0V to 5V and 0V to 10V), and
four bipolar ranges (±2.5V, ±5V, ±10V and –2.5V to 7.5V).
These ranges are obtained when an external precision 5V
reference is used. The output ranges for other reference
voltages are easy to calculate by observing that each range
is a multiple of the external reference voltage. The ranges
can then be expressed: 0 to 1×, 0 to 2×, ±0.5×, ±1×, ±2×,
and –0.5× to 1.5×.
Manual Span Configuration
Multiple output ranges are not needed in some applications. To configure the LTC2758 to operate in a single span
without additional operational overhead, tie the M-SPAN
pin directly to VDD. The active output range for all DACs is
then set via hardware pin strapping of pins S2, S1 and S0
(rather than through the SPI port); and Write and Update
commands have no effect on the active output span. See
Figure 1 and Table 3.
Tie the M-SPAN pin to ground for normal SoftSpan
operation.
Input and DAC Registers
The LTC2758 has 5 internal registers for each DAC, a total
of 10 registers (see Block Diagram). Each DAC channel
has two sets of double-buffered registers, one set for
the code data, and one for the output range of the DAC,
plus one readback register. Double buffering provides the
LTC2758
VDD
M-SPAN
DAC A
–
+
±10V
DAC B
–
+
±10V
S2
S1
S0
CS/LD SDI
SCK
2754 F01
Figure 1. Using M-SPAN to Configure the LTC2758
for Single-Span Operation (±10V Range Shown)
capability to simultaneously update the span (output range)
and code, which allows smooth voltage transitions when
changing output ranges. It also permits the simultaneous
updating of multiple DACs.
Each set of double-buffered registers comprises an Input
register and a DAC register.
Input register: The Write operation shifts data from the
SDI pin into a chosen Input register. The Input registers
are holding buffers; Write operations do not affect the
DAC outputs.
DAC register: The Update operation copies the contents
of an Input register to its associated DAC register. The
contents of a DAC register directly updates the associated
DAC output voltage or output range.
Note that updates always include both Code and Span
register sets; but the values held in the DAC registers will
only change if the associated Input register values have
previously been altered via a Write operation.
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11
LTC2758
Operation
Serial Interface
When the CS/LD pin is taken low, the data on the SDI pin
is loaded into the shift register on the rising edge of the
clock (SCK pin). The loading sequence required for the
LTC2758 is one byte consisting of a 4-bit command word
(C3 C2 C1 C0) and a 4-bit address word (A3 A2 A1 A0),
then three bytes (24 bits) of data.
When writing a code, the code data is left (MSB) justified;
so that the 24-bit data field consists of 18 code bits followed by 6 don’t-care bits.
When writing an output range, the span data should occupy the last 4 bits of the second data byte, ordered S3
through S0. Figure 2 shows the SDI input word syntax
for writing.
When CS/LD is low, the SRO pin (Serial Readback Output)
is an active output. The readback data begins after the
command (C3-C0) and address (A3-A0) words have been
shifted in to SDI. SRO outputs a logic low from the falling
edge of CS/LD until the Readback data begins.
When CS/LD is high, the SRO pin presents a high impedance (three-state) output.
LDAC is an asynchronous update pin. When LDAC is
taken low, all DACs are updated with code and span data
(data in the Input buffers is copied into the DAC buffers).
CS/LD must be high during this operation; otherwise
LDAC is locked out and will have no effect. The use of
LDAC is functionally identical to the “Update All DACs”
serial input command.
The codes for the command (C3-C0) are defined in Table 1;
Table 2 defines the codes for the address (A3-A0).
Readback
In addition to the Code and Span register sets, each DAC
has one Readback register associated with it. Every instruction cycle, the contents of one of the on-chip registers is
copied into a Readback register and serially shifted out
through the SRO pin.
Readback data always appears in the 24-bit data field,
starting on the falling SCK edge immediately after the last
address bit is shifted in on SDI. When reading a code, code
12
data occupies the first 18 bits of the 24-bit field; and the
span bits are the last four bits of the second data byte
when checking the output range. In both cases, all other
bits in the 24-bit data field are filled by zeros. Figure 2
shows the input and readback sequences.
The data outputted by SRO is always in the same position
and sequence as the input data. Note, however, that this
means that the SRO data shifts out one-half clock cycle
earlier than the corresponding bit shifting in on SDI. For
example, code bit D9, which is shifted in to SDI on the
rising edge of SCK clock 17, is clocked out of SRO on the
falling edge of clock 16. This allows D9 to be clocked to an
external microprocessor on the rising edge of clock 17.
For Read commands, the requested data is shifted out
of SRO in the 3-byte (24-bit) data field immediately after
the command/address byte. There is no instruction-cycle
latency for Read commands; the data shifts out in the same
instruction cycle in which it was requested.
For non-read (i.e., Write and/or Update) commands, SRO
automatically shifts out the contents of the buffer that
was acted upon in the preceding command. This “rolling
readback” default mode of operation can dramatically reduce the number of instruction cycles needed, since most
commands can be verified during subsequent commands
with no additional overhead. A conceptual flow diagram
is shown in Figure 3. Table 1 shows, for each antecedent command, which register (‘readback pointer’) will be
copied into the Readback register and outputted from SRO
during the following instruction cycle.
Span Readback in Manual Span Configuration
If a Span DAC register is chosen for readback, SRO responds by outputting the actual output span; this is true
whether the LTC2758 is configured for SoftSpan (M-SPAN
tied to GND) or manual span (M-SPAN tied to VDD).
In SoftSpan configuration, SRO outputs the span code
from the Span DAC register (programmed through the
SPI port). In manual span configuration, the active output
range is controlled by pins S2, S1 and S0, so SRO outputs
the logic values of these pins. The span code bits S2, S1
and S0 always appear in the same order and positions in
the SRO output sequence; see Figure 2.
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LTC2758
Operation
Table 1. Command Codes
C3
CODE
C2
C1
C0
COMMAND
READBACK POINTER–
CURRENT INPUT WORD W0
READBACK POINTER–
NEXT INPUT WORD W+1
0
0
1
0
Write Span DAC n
Set by Previous Command
Input Span Register DAC n
0
0
1
1
Write Code DAC n
Set by Previous Command
Input Code Register DAC n
0
1
0
0
Update DAC n
Set by Previous Command
DAC Span Register DAC n
0
1
0
1
Update All DACs
Set by Previous Command
DAC Code Register DAC n
0
1
1
0
Write Span DAC n
Update DAC n
Set by Previous Command
DAC Span Register DAC n
0
1
1
1
Write Code DAC n
Update DAC n
Set by Previous Command
DAC Code Register DAC n
1
0
0
0
Write Span DAC n
Update All DACs
Set by Previous Command
DAC Span Register DAC n
1
0
0
1
Write Code DAC n
Update All DACs
Set by Previous Command
DAC Code Register DAC n
1
0
1
0
Read Input Span Register DAC n
Input Span Register DAC n
1
0
1
1
Read Input Code Register DAC n
Input Code Register DAC n
1
1
0
0
Read DAC Span Register DAC n
DAC Span Register DAC n
1
1
0
1
Read DAC Code Register DAC n
DAC Code Register DAC n
1
1
1
1
No Operation
Set by Previous Command
DAC Code Register DAC n
–
System Clear
–
DAC Span Register DAC A
–
Initial Power-Up or Power Interrupt
–
DAC Span Register DAC A
Codes not shown are reserved–do not use
Table 2. Address Codes
Table 3. Span Codes
A3
A2
A1
A0
n
S3
S2
S1
S0
0
0
0
×
DAC A
×
0
0
0
Unipolar 0V to 5V
0
0
1
×
DAC B
×
0
0
1
Unipolar 0V to 10V
1
1
1
×
All DACs (Note 1)
×
0
1
0
Bipolar –5V to 5V
×
0
1
1
Bipolar –10V to 10V
×
1
0
0
Bipolar –2.5V to 2.5V
×
1
0
1
Bipolar –2.5V to 7.5V
Codes not shown are reserved–do not use. × = Don’t Care.
Note 1. If readback is taken using the All DACs address, the LTC2758
defaults to DAC A.
SPAN
Codes not shown are reserved–do not use. × = Don’t Care.
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13
LTC2758
operation
Examples
1. Load DAC A with 0V to 10V range, output at zero
volts; and DAC B with ±10V range, output at zero
volts. Note the DAC outputs should change at the
same time.
a) CS/LD↓. Clock SDI:
00101111 00000000 00000011 00000000
b) CS/LD↑
Span Input register- Range of DACs set to bipolar ±10V.
c) CS/LD↓. Clock SDI:
00100000 00000000 00000001 00000000
d) CS/LD↑
Span Input register- Range of DAC A set to unipolar
0V to 10V.
e) CS/LD↓. Clock SDI:
00111111 10000000 00000000 00XXXXXX
f) CS/LD↑
Code Input register- Code of all DACs set to mid-scale.
2. Load DAC B with ±2.5V range with its output at zero
volts. Use readback to check Input register contents
before updating the DAC output (i.e., before copying
Input register contents into DAC registers). Note that
after power-on, the code in Input registers is zero.
a) CS/LD↓. Clock SDI:
00110010 10000000 00000000 00XXXXXX
b) CS/LD↑
Code Input register- DAC B set to mid-scale.
c) CS/LD↓. Clock SDI:
00100010 00000000 00000100 00000000
Data out on SRO:
10000000 00000000 00000000
Verifies Code Input register- DAC B set to mid-scale.
d) CS/LD↑
Span Input register- Range of DAC B set to Bipolar
±2.5V range.
h) CS/LD↑
Code Input register- Code of DAC A set to zero.
e) CS/LD↓. Clock SDI:
10100010 XXXXXXXX XXXXXXXX XXXXXXXX
Data Out on SRO:
00000000 00000100 00000000
Verifies Span Input register- DAC B set to Bipolar
±2.5V Range.
CS/LD↑
i) CS/LD↓. Clock SDI:
01001111 XXXXXXXX XXXXXXXX XXXXXXXX
f) CS/LD↓. Clock SDI:
01000010 XXXXXXXX XXXXXXXX XXXXXXXX
j) CS/LD↑
Update all DACs for both Code and Range.
g) CS/LD↑
Update DAC B for both Code and Range
k) Alternatively steps i and j could be replaced with
LDAC .
h) Alternatively steps f and g could be replaced with
LDAC .
g) CS/LD↓. Clock SDI:
00110000 00000000 00000000 00XXXXXX
14
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LTC2758
operation
System Offset and Reference Adjustments
Many systems require compensation for overall system
offset. This may be an order of magnitude or more greater
than the offset of the LTC2758, which is so low as to be
dominated by external output amplifier errors even when
using the most precise op amps.
The offset adjust pins VOSADJX can be used to null unipolar
offset or bipolar zero error. The offset change expressed
in LSB is the same for any output range:
⎛ 5V ⎞
⎜⎝ V ⎟⎠
REF
A 5V control voltage applied to VOSADJX produces ΔVOS =
–2048 LSB in any output range, assuming a 5V reference
voltage at RINX.
In voltage terms, the offset delta is attenuated by a factor
of 32, 64 or 128, depending on the output range. (These
functions hold regardless of reference voltage.)
ΔVOS = –(1/128)VOSADJX
ΔVOS = –(1/64)VOSADJX
ΔVOS = –(1/32)VOSADJX
[0V to 5V, ±2.5V spans]
[0V to 10V, ±5V, –2.5V to
7.5V spans]
[±10V span]
The gain error adjust pins GEADJX can be used to null
gain error or to compensate for reference errors. The
gain error change expressed in LSB is the same for any
output range:
∆GE =
V(GE ADJX )
• 2048
V(RINX )
The gain-error delta is non-inverting for positive reference
voltages.
Note that this pin compensates the gain by altering the
inverted reference voltage V(REFX). In voltage terms, the
V(REFX) delta is inverted and attenuated by a factor of
128.
ΔV(REFX) = –(1/128)GEADJX
The nominal input range of these pins is ±5V; other voltages of up to ±15V may be used if needed. However, do
not use voltages divided down from power supplies; reference-quality, low-noise inputs are required to maintain
the best DAC performance.
The VOSADJX pins have an input impedance of 1.28MΩ.
These pins should be driven with a Thevenin-equivalent
impedance of 10k or less to preserve the settling performance of the LTC2758. They should be shorted to GND
if not used.
The GEADJX pins have an input impedance of 2.56MΩ, and
are intended for use with fixed reference voltages only.
They should be shorted to GND if not used.
Power-On Reset and Clear
When power is first applied to the LTC2758, all DACs
power-up in unipolar 5V mode (S3 S2 S1 S0 = 0000). All
internal DAC registers are reset to 0 and the DAC outputs
initialize to zero volts.
If the part is configured for manual span operation, all
DACs will be set into the pin-strapped range at the first
Update command. This allows the user to simultaneously
update span and code for a smooth voltage transition into
the chosen output range.
When the CLR pin is taken low, a system clear results.
The DAC buffers are reset to 0 and the DAC outputs are
all reset to zero volts. The Input buffers are left intact, so
that any subsequent Update command (including the use
of LDAC) restores the addressed DACs to their respective
previous states.
If CLR is asserted during an instruction, i.e., when CS/LD
is low, the instruction is aborted. Integrity of the relevant
Input buffers is not guaranteed under these conditions,
therefore the contents should be checked using readback
or replaced.
The RFLAG pin is used as a flag to notify the system of a
loss of data integrity. The RFLAG output is asserted low
at power-up, system clear, or if the supply VDD dips below
approximately 2V; and stays asserted until any valid Update
command is executed.
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15
16
SRO
SDI
SRO
C3
SDI
0
0
0
C1
3
C1
0
0
0
COMMAND
C2
READBACK SPAN
Hi-Z
WRITE SPAN
C3
2
COMMAND
C2
READBACK CODE
Hi-Z
WRITE CODE
1
SCK
CS/LD
0
C0
0
C0
4
0
A3
0
A3
5
A1
A1
0
0
0
ADDRESS
A2
0
ADDRESS
A2
6
7
0
A0
0
A0
8
0
X
D17
D17
9
0
X
D16
D16
10
0
X
0
X
D14
D14
12
0
X
D13
D13
X
D12
D12
14
X
D11
D11
15
0
0
12 DON’T-CARE
13
0
X
D10
D10
D9
17
D8
18
0
X
D9
0
X
D8
19
D7
0
X
D7
18-BIT DAC CODE
16
0
X
D6
D6
20
S3
S3
D5
D5
21
Figure 2. Serial Input and Output Sequences
D15
D15
11
S2
23
S1
D3
D3
S1
SPAN
S2
D4
D4
22
S0
S0
D2
D2
24
0
X
D1
D1
25
0
X
D0
D0
26
0
X
0
X
X
0
X
X
29
0
X
30
X
0
0
0
X
0
6 DON’T-CARE
28
8 DON’T-CARE
27
0
X
0
X
31
0
X
0
X
32
2758 F02
LTC2758
operation
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LTC2758
Operation
SDI
WRITE CODE
DAC A
WRITE CODE
DAC B
WRITE SPAN
DAC A
WRITE SPAN
DAC B
UPDATE
ALL DACs
...
SRO
...
READ
CODE INPUT
REGISTER DAC A
READ
CODE INPUT
REGISTER DAC B
READ
SPAN INPUT
REGISTER DAC A
READ
SPAN INPUT
REGISTER DAC B
READ
CODE DAC
REGISTER DAC A
2758 F03
Figure 3. Rolling Readback
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17
LTC2758
Applications Information
Op Amp Selection
Table 4. Coefficients for the Equations of Table 5
Because of the extremely high accuracy of the 18-bit
LTC2758, careful thought should be given to op amp
selection in order to achieve the exceptional performance
of which the part is capable. Fortunately, the sensitivity of
INL and DNL to op amp offset has been greatly reduced
compared to previous generations of multiplying DACs.
Tables 4 and 5 contain equations for evaluating the effects of op amp parameters on the LTC2758’s accuracy
when programmed in a unipolar or bipolar output range.
These are the changes the op amp can cause to the INL,
DNL, unipolar offset, unipolar gain error, bipolar zero and
bipolar gain error.
OUTPUT RANGE
A1
A2
A3
5V
1.1
2
1
10V
2.2
3
0.5
±5V
2
2
1
A4
A5
1
1.5
1
1.5
±10V
4
4
0.83
1
2.5
±2.5V
1
1
1.4
1
1
–2.5V to 7.5V
1.9
3
0.7
0.5
1.5
Table 6 contains a partial list of LTC precision op amps
recommended for use with the LTC2758. The easy-to-use
design equations simplify the selection of op amps to meet
the system’s specified error budget. Select the amplifier
from Table 6 and insert the specified op amp parameters
in Table 5. Add up all the errors for each category to determine the effect the op amp has on the accuracy of the
part. Arithmetic summation gives an (unlikely) worst-case
effect. A root-sum-square (RMS) summation produces a
more realistic estimate.
Table 5. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in All Output Ranges (Circuit of Page 1). Subscript 1
Refers to Output Amp, Subscript 2 Refers to Reference Inverting Amp.
UNIPOLAR
BIPOLAR GAIN
BIPOLAR ZERO
UNIPOLAR GAIN
DNL (LSB)
INL (LSB)
OFFSET (LSB)
ERROR (LSB)
ERROR (LSB)
ERROR (LSB)
5V
5V
5V
5V
5V
5V
VOS1 (mV) VOS1 • 12.1• V
VOS1 •3.1• V
A3•VOS1 •52.4 • V
A3•VOS1 •78.6 • V
VOS1 •52.4 • V
VOS1 • 52.4• V
REF
REF
REF
REF
REF
REF
5V
5V
5V
5V
5V
5V
IB1 (nA) IB1 •0.0012• V
IB1 •0.00032 • V
IB1 •0.524• V
IB1 •0.524• V
IB1 •0.0072 • V
IB1 •0.0072• V
REF
REF
REF
REF
REF
REF
66
6
524
524
AVOL1 (V/mV)
A1• A
A2 • A
0
0
A5•
A5•
AVOL1
AVOL1
VOL1
VOL1
5V
5V
5V
0
0
0
A4•VOS2 •52.4 •
V
V
VOS2 (mV)
•104.8•
•104.8•
VREF
VREF OS2
VREF OS2
5V
5V
5V
0
0
0
IB2 (nA)
A4•IB2 •0.524 •
IB2 •1.048•
IB2 •1.048•
VREF
VREF
VREF
524
524
0
0
0
AVOL2 (V/mV)
A4• 262
AVOL2
AVOL2
AVOL2
OP AMP
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
( )
Table 6. Partial List of LTC Precision Amplifiers Recommended for Use with the LTC2758 with Relevant Specifications
AMPLIFIER SPECIFICATIONS
AMPLIFIER
VOS
µV
IB
nA
A VOL
V/mV
VOLTAGE
NOISE
nV/√Hz
CURRENT
NOISE
pA/√Hz
SLEW
RATE
V/µs
GAIN BANDWIDTH
PRODUCT
MHz
tSETTLING
with LTC2758
µs
POWER
DISSIPATION
mW
LTC1150
10
0.05
5600
90
0.0018
3
2.5
10ms
24
LT1001
25
2
800
10
0.12
0.25
0.8
120
46
LT1012
25
0.1
2000
14
0.02
0.2
1
120
11.4
LT1097
50
0.35
2500
14
0.008
0.2
0.7
120
11
LT1468
75
10
5000
5
0.6
22
90
2.1
117
18
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LTC2758
Applications Information
Op amp offset contributes mostly to DAC output offset
and gain error, and has minimal effect on INL and DNL.
For example, consider the LTC2758 in unipolar 5V output
range. (Note that for this example, the LSB size is 19µV.)
An op amp offset of 35µV will cause 1.8LSB of output
offset, and 1.8LSB of gain error; but 0.4LSB of INL, and
just 0.1LSB of DNL.
While not directly addressed by the simple equations in
Tables 4 and 5, temperature effects can be handled just as
easily for unipolar and bipolar applications. First, consult
an op amp’s data sheet to find the worst-case VOS and IB
over temperature. Then, plug these numbers in the VOS
and IB equations from Table 5 and calculate the temperature-induced effects.
For applications where fast settling time is important, Application Note 120, 1ppm Settling Time Measurement for
a Monolithic 18-Bit DAC, offers a thorough discussion of
18-bit DAC settling time and op amp selection.
Recommendations
For DC or low-frequency applications, the LTC1150 is the
simplest 18-bit accurate output amplifier. An auto-zero
amp, its exceptionally low offset (10µV max) and offset
drift (0.01µV/°C) make nulling unnecessary. For swings
above 8V, use an LT1010 buffer to boost the load current
capability. The settling of auto-zero amps is a special case;
see Application Note 120, 1ppm Settling Time Measurement
for a Monolithic 18-Bit DAC, Appendix E, for details.
The LT1012 and LT1001 are good intermediate output-amp
solutions that achieve moderate speed and good accuracy.
They are also excellent choices for the reference inverting
amplifier in fixed-reference applications.
For high speed applications, the LTC1468 settles in 2.1µs.
Note that the 75µV max offset will degrade the INL at the
DAC output by up to 0.9LSB. For high-speed applications
demanding higher precision, the amplifier offset can be
nulled with a digital potentiometer.
The Typical Application on the last page shows a composite
output amplifier that achieves fast settling (8µs) and very
low offset (3µV max) without offset nulling. This circuit
offers high open-loop gain (1000V/mV min), low input
bias current (0.15nA max), fast slew rate (25V/µs min),
and a high gain-bandwidth product (30MHz typ). The high
speed path consists of an LTC6240HV, which is an 18MHz
ultralow bias current amplifier, followed by an LT1360, a
50MHz fast-slewing amplifier which provides additional
gain and the ability to swing to ±10V at the output. Compensation is taken from the output of the LTC6240HV,
allowing the use of a much larger compensation capacitor
than if taken after the gain-of-five stage. An LTC2054HV
auto-zero amplifier senses the voltage at IOUT1 and drives
the non-inverting input of the LTC6240HV to eliminate the
offset of the high speed path. The 100:1 attenuator and
input filter reduce the low frequency noise in this stage
while maintaining low DC offset.
Precision Voltage Reference Considerations
Much in the same way selecting an operational amplifier
for use with the LTC2758 is critical to the performance of
the system, selecting a precision voltage reference also
requires due diligence. The output voltage of the LTC2758
is directly affected by the voltage reference; thus, any
voltage reference error will appear as a DAC output voltage error.
There are three primary error sources to consider
when selecting a precision voltage reference for 18-bit
applications: output voltage initial tolerance, output voltage
temperature coefficient and output voltage noise.
Initial reference output voltage tolerance, if uncorrected,
generates a full-scale error term. Choosing a reference
with low output voltage initial tolerance, like the LT1236
(±0.05%), minimizes the gain error caused by the reference;
however, a calibration sequence that corrects for system
zero- and full-scale error is always recommended.
A reference’s output voltage temperature coefficient affects
not only the full-scale error, but can also affect the circuit’s
INL and DNL performance. If a reference is chosen with
a loose output voltage temperature coefficient, then the
DAC output voltage along its transfer characteristic will
be very dependent on ambient conditions. Minimizing
the error due to reference temperature coefficient can be
achieved by choosing a precision reference with a low
output voltage temperature coefficient and/or tightly controlling the ambient temperature of the circuit to minimize
temperature gradients.
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For more information www.linear.com/LTC2758
19
LTC2758
Applications Information
Table 7. Partial List of LTC Precision References Recommended
for Use with the LTC2758 with Relevant Specifications
INITIAL
TOLERANCE
TEMPERATURE
DRIFT
0.1Hz to 10Hz
NOISE
LT1019A-5,
LT1019A-10
±0.05% max
5ppm/°C max
12µVP-P
LT1236A-5,
LT1236A-10
±0.05% max
5ppm/°C max
3µVP-P
LT1460A-5,
LT1460A-10
±0.075% max
10ppm/°C max
20µVP-P
LT1790A-2.5
±0.05% max
10ppm/°C max
12µVP-P
LTC6652A-5
±0.05% max
5ppm/°C max
2.8ppmP-P
LTC6655A-2.5
LTC6655A-5
±0.025% max
2ppm/°C max
0.25ppmP-P
REFERENCE
As precision DAC applications move to 18-bit performance, reference output voltage noise may contribute a
dominant share of the system’s noise floor. This in turn can
degrade system dynamic range and signal-to-noise ratio.
Care should be exercised in selecting a voltage reference
with as low an output noise voltage as practical for the
system resolution desired. Precision voltage references
like the LT1236 or LTC6655 produce low output noise in
the 0.1Hz to 10Hz region, well below the 18-bit LSB level
in 5V or 10V full-scale systems. However, as the circuit
bandwidths increase, filtering the output of the reference
may be required to minimize output noise.
20
Grounding
As with any high-resolution converter, clean grounding
is important. A low-impedance analog ground plane is
necessary, as are star grounding techniques. Keep the
board layer used for star ground continuous to minimize
ground resistances; that is, use the star-ground concept
without using separate star traces. The IOUT2 pins are
of particular concern; INL will be degraded by the codedependent currents carried by the IOUT2XF and IOUT2XS
pins if voltage drops to ground are allowed to develop.
The best strategy here is to tie the pins to the star ground
plane by multiple vias located directly underneath the part.
Alternatively, the pins may be routed to the star ground
point if necessary; join the force and sense pins together
at the part and route one trace for each channel of no more
than 30 squares of 1oz copper.
In the rare case in which neither of these alternatives is
practicable, a force/sense amplifier should be used as a
ground buffer (see Figure 4). Note, however, that the voltage offset of the ground buffer amp directly contributes to
the effects on accuracy specified in Table 5 under ‘VOS1’.
The combined effects of the offsets can be calculated by
substituting the total offset from IOUT1X to IOUT2XS for
VOS1 in the equations.
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LTC2758
Applications Information
ALTERNATE AMPLIFIER FOR OPTIMUM SETTLING TIME PERFORMANCE
IOUT2AS 8
6
1
+
2
IOUT2AF
1000pF
LT1468
ZETEX
BAT54S
200Ω
200Ω
2
9
3
6
LT1012
+
9
–
IOUT2AF
8
–
IOUT2AS
1
2
3
ZETEX*
BAT54S
3
2
3
*SCHOTTKY BARRIER DIODE
VREF
5V
47, 48 ROFSA
RFBA 45, 46
5, 6 RINA
+
4
LT1012
–
6
3
15pF
GEADJA
DAC A
3 RCOMA
2
IOUT1A 44
2
–
IOUT2A 8, 9
3
+
LT1468
6
VOUTA
VOSADJA 43
150pF
1, 2 REFA
–
+
DAC B
LTC2758
2758 F05
Figure 4. Optional Circuits for Driving IOUT2 from GND with a Force/Sense Amplifier
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For more information www.linear.com/LTC2758
21
LTC2758
Package Description
Please refer to http://www.linear.com/product/LTC2758#packaging for the most recent package drawings.
LX Package
48-Lead Plastic LQFP (7mm × 7mm)
(Reference LTC DWG # 05-08-1760 Rev A)
7.15 – 7.25
9.00 BSC
5.50 REF
7.00 BSC
48
0.50 BSC
1
2
48
SEE NOTE: 4
1
2
9.00 BSC
5.50 REF
7.00 BSC
7.15 – 7.25
0.20 – 0.30
A
A
PACKAGE OUTLINE
C0.30 – 0.50
1.30 MIN
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
1.60
1.35 – 1.45 MAX
11° – 13°
R0.08 – 0.20
GAUGE PLANE
0.25
0° – 7°
11° – 13°
0.09 – 0.20
1.00 REF
0.50
BSC
0.17 – 0.27
0.05 – 0.15
0.45 – 0.75
SECTION A – A
COMPONENT
PIN “A1”
TRAY PIN 1
BEVEL
22
XXYY
LTCXXXX
LX-ES
Q_ _ _ _ _ _
e3
NOTE:
1. PACKAGE DIMENSIONS CONFORM TO JEDEC #MS-026 PACKAGE OUTLINE
2. DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.25mm ON ANY SIDE, IF PRESENT
4. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER
5. DRAWING IS NOT TO SCALE
LX48 LQFP 0113 REV A
PACKAGE IN TRAY LOADING ORIENTATION
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LTC2758
Revision History
REV
DATE
DESCRIPTION
PAGE NUMBER
A
09/13
Fixed RCOMA (Pin 3) description
8
Updated Typical Application
24
B
11/16
Updated amplifier part numbers
19
2758fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC2758
23
LTC2758
Typical Application
Composite Amplifier Circuit Achieves Both Fast Settling and 18-Bit Precision with No Adjustments
12V
IN
15V
OUT
LTC6655-5
0.1µF
+
–
10µF
LT1012
–15V
47, 48 5, 6
ROFSA
37, 38
RINA ROFSB
34
31, 32
RCOMB RINB
3
RCOMA
16 V
DD
10k
26 LDAC
10k
19
43
4
42
33
22
25
24
23
100pF
1, 2, 35, 36
REFA, REFB
45, 46
RFBA
44 1k
IOUT1A
VOUTA
10k
10k
CLR
1µF
IOUT2A
8, 9
5V
5V
–
+
LTC2054HV 1k
–5V
1µF
VOSADJA
–
+
100pF
LTC6240HV
–5V
5pF
10Ω
15V
+
–
LT1360
–15V
4.02k
GEADJA
1k
LTC2758
VOSADJB
GEADJB
RFBB
M-SPAN
IOUT1B
39, 40
41
VOUTB
1k
10k
10k
S2
S1
1µF
S0
IOUT2B
CS/LD
11
SDI
SCK
12
SRO
13
14
GND
28, 29
5V
5V
–
+
LTC2054HV 1k
–5V
1µF
7, 10, 15, 17,
18, 27, 30
–
+
100pF
LTC6240HV
–5V
10Ω
15V
+
–
5pF
LT1360
–15V
4.02k
1k
2758 TA02
SPI BUS
Related Parts
PART NUMBER DESCRIPTION
COMMENTS
LTC2757
Single Parallel 18-Bit IOUT SoftSpan DAC
±1LSB INL/DNL, Software-Selectable Ranges, 7mm × 7mm LQFP-48 Package
LTC1592
Single Serial 16-/14-/12-Bit IOUT SoftSpan DACs
±1LSB INL, DNL, Software-Selectable Ranges, 16-Lead SSOP Package
LTC2752
Dual Serial 16-Bit IOUT SoftSpan DAC
±1LSB INL/DNL, Software-Selectable Ranges, 7mm × 7mm LQFP-48 Package
LTC2754-12
Quad Serial 16-/12-Bit IOUT SoftSpan DACs
±1LSB INL/DNL, Software-Selectable Ranges, 7mm × 8mm QFN-52 Package
LTC2704-12
Quad Serial 16-/14-/12-Bit VOUT SoftSpan DACs
±1LSB INL/DNL, Software-Selectable Ranges, Integrated Amplifiers
LTC6655
Low Drift Precision Buffered Reference
0.025% Max Tolerance, 2ppm/°C Max, 0.25ppmP-P 0.1Hz to 10Hz Noise
LT1236
Precision Reference
0.05% Max Tolerance, 5ppm/°C Max, 3µVP-P 0.1Hz to 10Hz Noise
References
LT1460
Micropower Precision Series Reference
0.075% Max Tolerance, 10ppm/°C Max, 20µVP-P 0.1Hz to 10Hz Noise
LT1790
Micropower Low Dropout Reference
0.05% Max Tolerance, 10ppm/°C Max, 12µVP-P 0.1Hz to 10Hz Noise
LTC6652
Precision Low Drift Low Noise Buffered Reference
0.05% Max Tolerance, 5ppm/°C Max, 2.1ppmP-P 0.1Hz to 10Hz Noise
LTC1150
Zero-Drift Op Amp with Internal Capacitors
10µV Max Offset, ±16V High Voltage Operation, 1.8µVP-P Noise
LT1012
Precision Op Amp
25µV Max Offset, 100pA Max Input Current, 0.5µVP-P Noise, 380µA Supply Current
LT1001
Precision Op Amp
25µV Max Offset, 0.3µVP-P Noise, High Output Drive
LT1468
Single 16-Bit Accurate Op Amp
900ns Settling, 90MHz GBW, 22V/μs Slew Rate, 75µV Max Offset
Amplifiers
24
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC2758
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC2758
LT 1116 REV B • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2011