TI1 bq294682 Single-cell protector for li-ion battery Datasheet

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bq2946xx Single-Cell Protector for Li-Ion Batteries
1 Features
3 Description
•
The bq2946xx family of products is a secondary-level
overvoltage monitor and protector for Li-Ion battery
pack systems. The cell is monitored for overvoltage
condition and triggers an internal counter once the
OVP threshold is exceeded; after a fixed set delay,
the out is transitioned to a high level. The output is
reset (goes low) if the cell voltage drops below the
set threshold minus the hysteresis.
1
•
•
•
•
•
•
•
Single-Cell Overvoltage Monitor for Secondary
Protection
Fixed Programmable Delay Timer
Fixed Overvoltage Protection (OVP) Threshold
– Available Range of 3.85 V to 4.6 V
Fixed OVP Delay Option: 4 s or 6.5 s
High-Accuracy OVP:
± 10 mV
Low Power Consumption ICC ≈ 1 µA
(VCELL(ALL) < VPROTECT)
Low Leakage Current per Cell Input < 100 nA
Small Package Footprint
– 6-Pin SON
Device Information(1)
PART NUMBER
BODY SIZE (NOM)
bq294602
bq294604
SON (6)
bq294682
2.00 mm × 2.00 mm
bq294624
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
PACKAGE
Second-Level Protection in Li-Ion Battery Packs
in:
– Tablets
– Slates
– Portable Equipment and Instrumentation
Simplified Schematic
Pack +
RVD
bq2946xx
NC
OUT
V1
VDD
VSS
VSS
RIN
VCELL
CVD
CIN
Pack –
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq294602, bq294604, bq294682, bq294624
SLUSAS0D – DECEMBER 2011 – REVISED APRIL 2017
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Options.......................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 7
8.1 Overview ................................................................... 7
8.2 Functional Block Diagram ......................................... 7
8.3 Feature Description................................................... 7
8.4 Device Functional Modes.......................................... 8
9
Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Application .................................................. 10
9.3 System Example ..................................................... 11
10 Power Supply Recommendations ..................... 12
11 Layout................................................................... 12
11.1 Layout Guidelines ................................................. 12
11.2 Layout Example .................................................... 12
12 Device and Documentation Support ................. 13
12.1
12.2
12.3
12.4
12.5
12.6
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
13
13
13 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (July 2015) to Revision D
Page
•
Added bq294624 in Device Information ................................................................................................................................ 1
•
Added the bq294624 device into production .......................................................................................................................... 3
•
Added Receiving Notification of Documentation Updates section ....................................................................................... 13
Changes from Revision B (March 2012) to Revision C
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Added Overvoltage to description .......................................................................................................................................... 1
•
Changed bullets to consolidate feature item .......................................................................................................................... 1
•
Added Fixed OVP Delay Option to Features ........................................................................................................................ 1
•
Changed wording of description ............................................................................................................................................ 1
•
Added the bq294682 device into production ......................................................................................................................... 3
Changes from Revision A (February 2012) to Revision B
•
Page
Added a second ICC Test Condition........................................................................................................................................ 5
Changes from Original (December 2011) to Revision A
•
2
Page
Added the bq294604 device into production .......................................................................................................................... 3
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5 Device Options
TA
–40°C to +110°C
(1)
PART NUMBER
OVP (V)
bq294602
4.35
DELAY TIME (s)
4
bq294604
4.35
6.5
bq294622 (1)
4.45
4
bq294624
4.45
6.5
bq294682
4.225
4
bq294684 (1)
4.225
6.5
Product Preview only.
6 Pin Configuration and Functions
DRV Package
6-Pin SON
Top View
NC
1
6
OUT
V1
2
5
VDD
VSS
3
4
VSS
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
NC
1
—
No connection
OUT
6
OA
Output drive for external N-channel FET.
Thermal Pad
—
VSS pin to be connected to the PWRPAD on the printed-circuit-board (PCB) for proper
operation.
V1
2
IA
Sense input for positive voltage of the cell.
VSS
3
P
Electrically connected to IC ground and negative terminal of the cell.
VSS
4
P
Electrically connected to IC ground and negative terminal of the cell.
VDD
5
P
Power supply
PWRPAD
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Supply voltage
VDD–VSS
–0.3
30
V
Input voltage
V1–VSS
–0.3
8
V
Output voltage
OUT–VSS
–0.3
30
V
See Thermal
Information
Continuous total power dissipation, PTOT
Functional temperature
–65
Lead temperature (soldering, 10 s), TSOLDER
Storage temperature, Tstg
(1)
–65
110
°C
300
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Supply voltage, VDD (1)
Input voltage
V1–VSS
Operating ambient temperature, TA
(1)
MIN
MAX
UNIT
3
8
V
0
5
V
–40
110
°C
See Typical Application.
7.4 Thermal Information
bq2946xx
THERMAL METRIC (1)
DRV (SON)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
186.4
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
90.4
°C/W
RθJB
Junction-to-board thermal resistance
110.7
°C/W
ψJT
Junction-to-top characterization parameter
96.7
°C/W
ψJB
Junction-to-board characterization parameter
90
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
n/a
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
Typical values stated where TA = 25°C and VDD = 4 V, MIN/MAX values stated where TA = –40°C to +110°C and VDD = 4 V
(unless otherwise noted)
TEST NO.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE PROTECTION THRESHOLD VCx
1.0
bq294602, fixed delay 4 s, V1 > VOV
4.35
1.1
bq294604, fixed delay 6.5 s, V1 > VOV
4.35
1.2
bq294622, fixed delay 4 s, V1 > VOV (1)
4.45
bq294624, fixed delay 6.5 s, V1 > VOV
4.45
VOV
1.3
V(PROTECT) –
Overvoltage Detection
1.4
bq294682, fixed delay 4 s, V1 > VOV
1.5
bq294684, fixed delay 6.5 s, V1 > VOV
1.6
VHYS
Overvoltage Detection
Hysteresis
1.7
VOA
OV Detection Accuracy TA = 25°C
VOA –DRIFT
TA
OV Detection Accuracy TA
due to Temperature
TA
TA
1.8
V
4.225
(1)
4.225
250
= –40°C
= 0°C
= 60°C
= 110°C
300
400
V
–10
10
mV
–40
–20
–24
–54
44
20
24
54
mV
SUPPLY AND LEAKAGE CURRENT
1.9
ICC
Supply Current
(V1–VSS) = 4.0 V (see Figure 7 for
reference)
1
(V1–VSS) = 2.8 V with TA = –40°C to +60°C
1.10
IIN
Input Current at V1
Pins
Measured at V1 = 4.0 V
(V1–VSS) = 4.0 V
TA = 0°C to 60°C (see Figure 7 for
reference)
2
µA
1.25
–0.1
0.1
µA
OUTPUT DRIVE OUT
1.11
1.12
VOUT
Output Drive Voltage
1.13
(V1–VSS) > VOV
VDD = V1, IOH = 100 µA, TA = –40°C to
+110°C
3
VDD – 0.3
V
(V1–VSS) < VOV, IOL = 100 µA, TA = 25°C
TA = –40°C to +110°C
250
400
mV
1.5
3
mA
2
5
kΩ
1.14
IOUT(Short)
OUT Short Circuit
Current
OUT = 0 V, (V1–VSS) > VOV
1.15
tR
Output Rise Time
CL = 1 nF, VOH(OUT) = 0 V to 5 V (2)
1.16
ZO
Output Impedance
5
µs
FIXED DELAY TIMER
1.17
tDELAY
Fault Detection Delay
Time
1.18
tDELAY_CTM
Fault Detection Delay
Time in Test Mode
(1)
(2)
Fixed Delay, bq2946x2
3.2
4
4.8
Fixed Delay, bq2946x4
5.2
6.5
7.8
Fixed Delay (Internal settings)
15
s
ms
Product Preview only.
Specified by design. Not 100% tested in production.
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1.3
4.38
1.2
4.37
Overvoltage Threshold (V)
ICC Current (PA)
7.6 Typical Characteristics
1.1
1
0.9
0.8
Min
Max
Mean
4.36
4.35
4.34
4.33
4.32
0.7
-40
-20
0
20
40
60
Temperature (qC)
80
100
4.31
-40
120
-20
0
D001
Figure 1. ICC Current Consumption vs Temperature
20
40
60
Temperature (qC)
80
100
120
D002
Figure 2. bq294602 Overvoltage Threshold (OVT) vs
Temperature
-3.85
325
324
-3.9
Output Current (mA)
Hysteresis (mV)
323
322
321
320
319
318
-3.95
-4
-4.05
317
316
315
-40
-20
0
20
40
60
Temperature (qC)
80
100
Figure 3. Hysteresis VHYS vs Temperature
6
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120
D003
-4.1
-40
-20
0
20
40
60
Temperature (qC)
80
100
120
D004
Figure 4. Output Current IOUT vs Temperature
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8 Detailed Description
8.1 Overview
The bq2946xx is a second-level overvoltage (OV) protector for a single cell. The cell voltage is compared to a
protection voltage threshold, VOV. The protection threshold is preprogrammed at the factory with a range from
3.85 V to 4.65 V. When the OVP is triggered, the OUT pin goes high to activate an external N-channel FET,
which conducts a low-impedance path to blow a fuse.
8.2 Functional Block Diagram
PACK +
R VD
CVD
VDD
REG
Enable Monitoring
V1
RIN
CIN
VSS
INT_EN
VOV
Delay
Timer
OSC
OUT
PWRPAD
PACK –
8.3 Feature Description
Cell Voltage (V)
V1–VSS)
The method of overvoltage detection is comparing the cell voltage to an OVP threshold voltage VOV. Once the
cell voltage exceeds the programmed fixed value VOV, the delay timer circuit is activated. This delay (tDELAY) is
fixed for 4 seconds for the bq294602 device. When these conditions are satisfied, the OUT terminal is
transitioned to a high level. This output (OUT) is released to a low condition if the cell input (V1) is below the
OVP threshold minus the VHYS.
VOV
VOV – VHYS
t DELAY
OUT (V)
Figure 5. Timing for Overvoltage Sensing
8.3.1 Sense Positive Input for V1
This is an input to sense single battery cell voltage. A series resistor and a capacitor across the cell is required
for noise filtering and stable voltage monitoring.
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Feature Description (continued)
8.3.2 Output Drive, OUT
The gate of an external N-channel MOSFET is connected to this terminal. This output transitions to a high level
when an overvoltage condition is detected and after the programmed delay timer. The OUT will reset to a low
level if the cell voltage falls below the VOV threshold before the fixed delay timer expires.
8.3.3 Supply Input, VDD
This terminal is the unregulated input power source for the IC. A series resistor is connected to limit the current,
and a capacitor is connected to ground for noise filtering.
8.3.4 Thermal Pad, PWRPAD
For correct operation, the power pad (PWRPAD) is connected to the VSS terminal on the PCB.
8.4 Device Functional Modes
8.4.1 NORMAL Mode
When the cell voltage is below the overvoltage threshold, VOV, the device operates in NORMAL mode. The OUT
pin is inactive and is low.
8.4.2 OVERVOLTAGE Mode
OVERVOLTAGE mode is detected if the cell voltage exceeds the overvoltage threshold, VOV, for configured OV
delay time. The OUT pin is activated, internally pulled high, after a delay time, tDELAY. An external FET then
turns on, shorting the fuse to ground, which allows the battery and/or charger power to blow the fuse. When the
cell voltages fall below (VOV – VHYS), the device returns to NORMAL mode.
8.4.3 Customer Test Mode
Customer Test Mode (CTM) helps reduce test time for checking the overvoltage delay timer parameter once the
circuit is implemented in the battery pack. To enter CTM, VDD should be set to at least 10 V higher than V1 (see
Figure 6). The delay timer is greater than 10 ms, but considerably shorter than the timer delay in normal
operation. To exit CTM, remove the VDD to V1 voltage differential of 10 V so that the decrease in this value
automatically causes an exit.
CAUTION
Avoid exceeding any Absolute Maximum Voltages on any pins when placing the part
into CTM. Also avoid exceeding Absolute Maximum Voltage for the cell voltage
(V1–VSS). Stressing the pins beyond the rated limits may cause permanent damage to
the device.
Figure 6 shows the timing for the CTM.
8
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Device Functional Modes (continued)
VDD – Test Pin (V1) = 10 V
VDD
Test Pin (V1)
t DELAY > 10 ms
OUT (V)
Figure 6. Timing for Customer Test Mode
Figure 7 shows the measurement for current consumption for the product for both VDD and Vx.
bq2946xx
IIN
1 NC
OUT 6
2 V1
VDD 5
3 VSS
ICC
VSS 4
PWRPAD
3.6 V
Figure 7. Configuration for IC Current Consumption Test
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The bq2946xx devices are a family of second-level protectors used for overvoltage protection of the single-cell
battery pack in the application. The OUT pin drives a NMOS FET that connects the fuse to ground in the event of
a fault condition. This provides a shorted path to use the battery and/or charger power to blow the fuse and cut
the power path.
9.1.1 Application Configuration
Changes to the ranges stated in Table 1 may impact the accuracy of the cell measurements. Figure 8 shows
each external component.
NOTE
Connect VSS (pins 3 and 4) externally to the CELL– terminal.
9.2 Typical Application
Pack +
RVD
bq2946xx
NC
OUT
V1
VDD
VSS
VSS
RIN
VCELL
CVD
CIN
Pack –
Figure 8. Application Configuration Schematic
NOTE
Connect VSS (pins 3 and 4) externally to the CELL– terminal.
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the input parameters.
Table 1. Parameters
10
PARAMETER
EXTERNAL COMPONENT
MIN
NOM
MAX
Voltage monitor filter resistance
RIN
900
1000
1100
Voltage monitor filter capacitance
CIN
0.01
0.1
Supply voltage filter resistance
RVD
100
Supply voltage filter capacitance
CVD
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Ω
µF
1K
0.1
UNIT
Ω
µF
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9.2.2 Detailed Design Procedure
1. Determine the overvoltage protection and delay. Select a device with the corresponding thresholds.
2. Follow the application schematic (see Figure 8) to connect the device.
3. Ensure both Vss pins are connected to the CELL– terminal on the PCB layout.
9.2.3 Application Curves
325
4.38
324
323
4.36
Hysteresis (mV)
Overvoltage Threshold (V)
4.37
Min
Max
Mean
4.35
4.34
4.33
322
321
320
319
318
317
4.32
4.31
-40
316
-20
0
20
40
60
Temperature (qC)
80
100
315
-40
120
-20
0
20
40
60
Temperature (qC)
D002
Figure 9. OVT vs Temperature
80
100
120
D003
Figure 10. VHYS vs Temperature
9.3 System Example
Pack +
100
bq2946xx
NC
OUT
V1
VDD
VSS
VSS
1K
VCELL
0.1 µF
0.1 µF
Pack –
Figure 11. 1-Cell Configuration With Fixed Delay
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10 Power Supply Recommendations
The maximum power of this device is 8 V on VDD.
11 Layout
11.1 Layout Guidelines
1. Ensure the RC filters for the V1 and VDD pins are placed as close as possible to the target terminal,
reducing the tracing loop area.
2. The VSS pin should be routed to the CELL– terminal.
3. Ensure the trace connecting the fuse to the gate, source of the NFET to the Pack is sufficient to withstand
the current during a fuse blown event.
11.2 Layout Example
Place the RC filters close to the
device terminals
Power Trace Line
Pack +
NC
OUT
VDD
V2
Pack ±
PWPD
VCELL
VSS
VSS
Ensure trace can support sufficient current
flow for fuse blow
Connect the VSS pins to the CELL- side
Figure 12. Layout Schematic
12
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 2. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
bq294602
Click here
Click here
Click here
Click here
Click here
bq294604
Click here
Click here
Click here
Click here
Click here
bq294682
Click here
Click here
Click here
Click here
Click here
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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1-May-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ294602DRVR
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
4602
BQ294602DRVT
ACTIVE
WSON
DRV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
4602
BQ294604DRVR
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
4604
BQ294604DRVT
ACTIVE
WSON
DRV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
4604
BQ294624DRVR
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
4624
BQ294624DRVT
ACTIVE
WSON
DRV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
4624
BQ294682DRVR
ACTIVE
WSON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
4682
BQ294682DRVT
ACTIVE
WSON
DRV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
4682
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
1-May-2017
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Apr-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
BQ294602DRVR
WSON
DRV
6
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294602DRVR
WSON
DRV
6
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294602DRVT
WSON
DRV
6
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294602DRVT
WSON
DRV
6
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294604DRVR
WSON
DRV
6
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294604DRVR
WSON
DRV
6
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294604DRVT
WSON
DRV
6
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294604DRVT
WSON
DRV
6
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294624DRVR
WSON
DRV
6
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294624DRVT
WSON
DRV
6
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294682DRVR
WSON
DRV
6
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
BQ294682DRVT
WSON
DRV
6
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Apr-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ294602DRVR
WSON
DRV
6
3000
210.0
185.0
35.0
BQ294602DRVR
WSON
DRV
6
3000
210.0
185.0
35.0
BQ294602DRVT
WSON
DRV
6
250
210.0
185.0
35.0
BQ294602DRVT
WSON
DRV
6
250
210.0
185.0
35.0
BQ294604DRVR
WSON
DRV
6
3000
210.0
185.0
35.0
BQ294604DRVR
WSON
DRV
6
3000
210.0
185.0
35.0
BQ294604DRVT
WSON
DRV
6
250
210.0
185.0
35.0
BQ294604DRVT
WSON
DRV
6
250
210.0
185.0
35.0
BQ294624DRVR
WSON
DRV
6
3000
210.0
185.0
35.0
BQ294624DRVT
WSON
DRV
6
250
210.0
185.0
35.0
BQ294682DRVR
WSON
DRV
6
3000
210.0
185.0
35.0
BQ294682DRVT
WSON
DRV
6
250
210.0
185.0
35.0
Pack Materials-Page 2
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