Microchip MCP1826T-3302E/DB 1000 ma, low voltage, low quiescent current ldo regulator Datasheet

MCP1826/MCP1826S
1000 mA, Low Voltage, Low Quiescent Current
LDO Regulator
Features
Description
• 1000 mA Output Current Capability
• Input Operating Voltage Range: 2.3V to 6.0V
• Adjustable Output Voltage Range: 0.8V to 5.0V
(MCP1826 only)
• Standard Fixed Output Voltages:
- 0.8V, 1.2V, 1.8V, 2.5V, 3.0V, 3.3V, 5.0V
• Other Fixed Output Voltage Options Available
Upon Request
• Low Dropout Voltage: 250 mV Typical at 1000 mA
• Typical Output Voltage Tolerance: 0.5%
• Stable with 1.0 µF Ceramic Output Capacitor
• Fast response to Load Transients
• Low Supply Current: 120 µA (typ)
• Low Shutdown Supply Current: 0.1 µA (typ)
(MCP1826 only)
• Fixed Delay on Power Good Output
(MCP1826 only)
• Short Circuit Current Limiting and
Overtemperature Protection
• TO-263-5 (DDPAK-5), TO-220-5, SOT-223-5
Package Options (MCP1826).
• TO-263-3 (DDPAK-3), TO-220-3, SOT-223-3
Package Options (MCP1826S).
The MCP1826/MCP1826S is a 1000 mA Low Dropout
(LDO) linear regulator that provides high current and
low output voltages. The MCP1826 comes in a fixed or
adjustable output voltage version, with an output
voltage range of 0.8V to 5.0V. The 1000 mA output current capability, combined with the low output voltage
capability, make the MCP1826 a good choice for new
sub-1.8V output voltage LDO applications that have
high current demands. The MCP1826S is a 3-pin fixed
voltage version.
Applications
•
•
•
•
•
•
High-Speed Driver Chipset Power
Networking Backplane Cards
Notebook Computers
Network Interface Cards
Palmtop Computers
2.5V to 1.XV Regulators
© 2007 Microchip Technology Inc.
The MCP1826/MCP1826S is stable using ceramic
output capacitors that inherently provide lower output
noise and reduce the size and cost of the entire
regulator solution. Only 1 µF of output capacitance is
needed to stabilize the LDO.
Using CMOS construction, the quiescent current
consumed by the MCP1826/MCP1826S is typically
less than 120 µA over the entire input voltage range,
making it attractive for portable computing applications
that demand high output current. The MCP1826
versions have a Shutdown (SHDN) pin. When shut
down, the quiescent current is reduced to less than
0.1 µA.
On the MCP1826 fixed output versions the scaleddown output voltage is internally monitored and a
power good (PWRGD) output is provided when the
output is within 92% of regulation (typical). The
PWRGD delay is internally fixed at 200 µs (typical).
The overtemperature and short circuit current-limiting
provide additional protection for the LDO during system
fault conditions.
DS22057A-page 1
MCP1826/MCP1826S
Package Types
MCP1826
DDPAK-5
MCP1826S
TO-220-5
Fixed/Adjustable
DDPAK-3
1
2
TO-220-3
3
1
1 2 3 4 5
2
3
1 2 3 4 5
SOT-223-5
SOT-223-3
6
4
1
2
3
4
1
5
2
3
Pin
Fixed
Adjustable
Pin
1
SHDN
SHDN
1
VIN
2
VIN
VIN
2
GND (TAB)
3
GND (TAB)
GND (TAB)
3
VOUT
4
VOUT
VOUT
4
GND (TAB)
5
PWRGD
ADJ
6
GND (TAB)
GND (TAB)
DS22057A-page 2
© 2007 Microchip Technology Inc.
MCP1826/MCP1826S
Typical Application
MCP1826 Fixed Output Voltage
PWRGD
R1
100 kΩ
On
SHDN
Off
VIN = 2.3V to 2.8V
1
VIN
VOUT = 1.8V @ 1000 mA
VOUT
GND
C1
4.7 µF
C2
1 µF
MCP1826 Adjustable Output Voltage
VADJ
R1
40 kΩ
On
R2
20 kΩ
SHDN
Off
VIN = 2.3V to 2.8V
VIN
1
VOUT
C1
4.7 µF
GND
© 2007 Microchip Technology Inc.
VOUT = 1.2V @ 1000 mA
C2
1 µF
DS22057A-page 3
MCP1826/MCP1826S
Functional Block Diagram - Adjustable Output
PMOS
VIN
VOUT
Undervoltage
Lock Out
(UVLO)
ISNS
Cf
Rf
SHDN
ADJ/SENSE
Overtemperature
Sensing
+
Driver w/limit
and SHDN
EA
–
SHDN
VREF
V IN
SHDN
Reference
Soft-Start
Comp
TDELAY
GND
92% of VREF
DS22057A-page 4
© 2007 Microchip Technology Inc.
MCP1826/MCP1826S
Functional Block Diagram - Fixed Output (3-Pin)
PMOS
VIN
VOUT
Undervoltage
Lock Out
(UVLO)
Sense
ISNS
Cf
Rf
SHDN
Overtemperature
Sensing
+
Driver w/limit
and SHDN
EA
–
SHDN
VREF
V IN
SHDN
Reference
Soft-Start
Comp
TDELAY
GND
92% of VREF
© 2007 Microchip Technology Inc.
DS22057A-page 5
MCP1826/MCP1826S
Functional Block Diagram - Fixed Output (5-Pin)
PMOS
VIN
VOUT
Undervoltage
Lock Out
(UVLO)
Sense
ISNS
Cf
Rf
SHDN
Overtemperature
Sensing
+
Driver w/limit
and SHDN
EA
–
SHDN
VREF
V IN
SHDN
Reference
Soft-Start
Comp
GND
TDELAY
PWRGD
92% of VREF
DS22057A-page 6
© 2007 Microchip Technology Inc.
MCP1826/MCP1826S
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VIN ....................................................................................6.5V
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Maximum Voltage on Any Pin .. (GND – 0.3V) to (VDD + 0.3)V
Maximum Power Dissipation......... Internally-Limited (Note 6)
Output Short Circuit Duration ................................ Continuous
Storage temperature .....................................-65°C to +150°C
Maximum Junction Temperature, TJ ........................... +150°C
ESD protection on all pins (HBM/MM) ........... ≥ 4 kV; ≥ 300V
AC/DC CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX), Note 1, VR=1.8V for Adjustable Output,
IOUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C.
Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C
Parameters
Sym
Min
Typ
Max
Input Operating Voltage
VIN
2.3
Input Quiescent Current
Iq
Input Quiescent Current for
SHDN Mode
Maximum Output Current
6.0
V
Note 1
—
120
220
µA
IL = 0 mA, VOUT = 0.8V to
5.0V
ISHDN
—
0.1
3
µA
SHDN = GND
IOUT
1000
—
—
mA
VIN = 2.3V to 6.0V
VR = 0.8V to 5.0V, Note 1
Line Regulation
ΔVOUT/
(VOUT x ΔVIN)
—
±0.05
±0.20
%/V
(Note 1) ≤ VIN ≤ 6V
Load Regulation
ΔVOUT/VOUT
-1.0
±0.5
1.0
%
IOUT = 1 mA to 1000 mA,
(Note 4)
IOUT_SC
—
2.2
—
A
RLOAD < 0.1Ω, Peak Current
Output Short Circuit Current
Units
Conditions
Adjust Pin Characteristics (Adjustable Output Only)
Adjust Pin Reference Voltage
VADJ
0.402
0.410
0.418
V
VIN = 2.3V to VIN = 6.0V,
IOUT = 1 mA
Adjust Pin Leakage Current
IADJ
-10
±0.01
+10
nA
VIN = 6.0V, VADJ = 0V to 6V
TCVOUT
—
40
—
ppm/°C
Note 3
V
Note 2
Adjust Temperature Coefficient
Fixed-Output Characteristics (Fixed Output Only)
Voltage Regulation
Note 1:
2:
3:
4:
5:
6:
7:
VOUT
VR - 2.5%
VR ±0.5% VR + 2.5%
The minimum VIN must meet two conditions: VIN ≥ 2.3V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX).
VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output
voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1.
TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the
temperature range. VOUT-LOW is the lowest voltage measured over the temperature range.
Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is
tested over a load range from 1 mA to the maximum specified output current.
Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
nominal value that was measured with an input voltage of VIN = VOUT(MAX) + VDROPOUT(MAX).
The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power
dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained
junction temperatures above 150°C can impact device reliability.
The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the
desired junction temperature. The test time is small enough such that the rise in the junction temperature over the
ambient temperature is not significant.
© 2007 Microchip Technology Inc.
DS22057A-page 7
MCP1826/MCP1826S
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX), Note 1, VR=1.8V for Adjustable Output,
IOUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C.
Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C
Parameters
Sym
Min
Typ
Max
Units
VDROPOUT
—
250
400
mV
VPWRGD_VIN
1.0
—
6.0
V
1.2
—
6.0
Conditions
Dropout Characteristics
Dropout Voltage
Note 5, IOUT = 1000 mA,
VIN(MIN) = 2.3V
Power Good Characteristics
PWRGD Input Voltage Operating Range
TA = +25°C
TA = -40°C to +125°C
For VIN < 2.3V, ISINK = 100 µA
PWRGD Threshold Voltage
(Referenced to VOUT)
%VOUT
VPWRGD_TH
Falling Edge
89
92
95
VOUT < 2.5V Fixed,
VOUT = Adj.
90
92
94
VOUT >= 2.5V Fixed
VPWRGD_HYS
1.0
2.0
3.0
%VOUT
PWRGD Output Voltage Low
VPWRGD_L
—
0.2
0.4
V
IPWRGD SINK = 1.2 mA,
ADJ = 0V
PWRGD Leakage
PWRGD_LK
—
1
—
nA
VPWRGD = VIN = 6.0V
TPG
—
125
—
µs
Rising Edge
RPULLUP = 10 kΩ
TVDET-PWRGD
—
200
—
µs
VOUT = VPWRGD_TH + 20 mV
to VPWRGD_TH - 20 mV
Logic High Input
VSHDN-HIGH
45
—
—
%VIN
Logic Low Input
VSHDN-LOW
—
—
15
%VIN
SHDNILK
-0.1
±0.001
+0.1
µA
VIN = 6V, SHDN =VIN,
SHDN = GND
TOR
—
100
—
µs
SHDN = GND to VIN
VOUT = GND to 95% VR
eN
—
2.0
—
µV/√Hz
PWRGD Threshold Hysteresis
PWRGD Time Delay
Detect Threshold to PWRGD
Active Time Delay
Shutdown Input
SHDN Input Leakage Current
VIN = 2.3V to 6.0V
VIN = 2.3V to 6.0V
AC Performance
Output Delay From SHDN
Output Noise
Note 1:
2:
3:
4:
5:
6:
7:
IOUT = 200 mA, f = 1 kHz,
COUT = 10 µF (X7R Ceramic),
VOUT = 2.5V
The minimum VIN must meet two conditions: VIN ≥ 2.3V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX).
VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output
voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1.
TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the
temperature range. VOUT-LOW is the lowest voltage measured over the temperature range.
Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is
tested over a load range from 1 mA to the maximum specified output current.
Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
nominal value that was measured with an input voltage of VIN = VOUT(MAX) + VDROPOUT(MAX).
The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power
dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained
junction temperatures above 150°C can impact device reliability.
The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the
desired junction temperature. The test time is small enough such that the rise in the junction temperature over the
ambient temperature is not significant.
DS22057A-page 8
© 2007 Microchip Technology Inc.
MCP1826/MCP1826S
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX), Note 1, VR=1.8V for Adjustable Output,
IOUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C.
Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C
Parameters
Sym
Min
Typ
Max
Units
Power Supply Ripple Rejection
Ratio
PSRR
—
60
—
dB
f = 100 Hz, COUT = 4.7 µF,
IOUT = 100 µA,
VINAC = 100 mV pk-pk,
CIN = 0 µF
Thermal Shutdown Temperature
TSD
—
150
—
°C
IOUT = 100 µA, VOUT = 1.8V,
VIN = 2.8V
Thermal Shutdown Hysteresis
ΔTSD
—
10
—
°C
IOUT = 100 µA, VOUT = 1.8V,
VIN = 2.8V
Note 1:
2:
3:
4:
5:
6:
7:
Conditions
The minimum VIN must meet two conditions: VIN ≥ 2.3V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX).
VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output
voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1.
TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the
temperature range. VOUT-LOW is the lowest voltage measured over the temperature range.
Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is
tested over a load range from 1 mA to the maximum specified output current.
Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
nominal value that was measured with an input voltage of VIN = VOUT(MAX) + VDROPOUT(MAX).
The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power
dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained
junction temperatures above 150°C can impact device reliability.
The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the
desired junction temperature. The test time is small enough such that the rise in the junction temperature over the
ambient temperature is not significant.
TEMPERATURE SPECIFICATIONS
Parameters
Sym
Min
Typ
Max
Units
Conditions
Operating Junction Temperature Range
TJ
-40
—
+125
°C
Steady State
Maximum Junction Temperature
TJ
—
—
+150
°C
Transient
Storage Temperature Range
TA
-65
—
+150
°C
θJA
—
31.4
—
°C/W
θJC
—
3.0
—
°C/W
θJA
—
29.4
—
°C/W
θJC
—
2.0
—
°C/W
Temperature Ranges
Thermal Package Resistances
Thermal Resistance, 3L-DDPAK
Thermal Resistance, 3L-TO-220
Thermal Resistance, 3L-SOT-223
Thermal Resistance, 5L-DDPAK
Thermal Resistance, 5L-TO-220
Thermal Resistance, 5L-SOT-223
© 2007 Microchip Technology Inc.
θJA
—
62
—
°C/W
θJC
—
15.0
—
°C/W
θJA
—
31.2
—
°C/W
θJC
—
3.0
—
°C/W
θJA
—
29.3
—
°C/W
θJC
—
2.0
—
°C/W
θJA
—
62
—
°C/W
θJC
—
15.0
—
°C/W
4-Layer JC51 Standard
Board
4-Layer JC51 Standard
Board
EIA/JEDEC JESD51-751-7
4 Layer Board
4-Layer JC51 Standard
Board
4-Layer JC51 Standard
Board
EIA/JEDEC JESD51-751-7
4 Layer Board
DS22057A-page 9
MCP1826/MCP1826S
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VOUT + 0.6V, Fixed output.
0.10
VOUT = 1.2V Adj
IOUT = 0 mA
130
120
130
130°C
°C
110
+90
+90°C
°C
Line Regulation (%/V)
Quiescent Current (μA)
140
+25
+25°C
°C
100
0°C
-45°C
90
0.08
VOUT = 1.2V Adj
VIN = 2.3V to 6.0V
IOUT = 100 mA
IOUT = 50 mA
0.07
0.06
0.05
IOUT = 250 mA
0.04
IOUT = 1000 mA
0.03
80
2
3
4
Input Voltage (V)
5
-45
6
-20
5
0.15
VOUT = 1.2V Adj
Load Regulation (%)
170
160
150
VIN = 5.0V
140
VIN = 3.3V
130
120
110
VIN = 2.3V
100
80
105
130
IOUT = 1.0 mA to 1000 mA
VOUT = 3.3V
0.10
0.05
VOUT = 1.8V
0.00
VOUT = 0.8V
VOUT = 5.0V
-0.05
-0.10
-0.15
0
250
500
750
1000
-45
-20
5
30
55
80
105
130
Temperature (°C)
Load Current (mA)
FIGURE 2-2:
Ground Current vs. Load
Current (Adjustable Version).
0.411
VOUT = 1.2V Adj
IOUT = 0 mA
VIN = 5.0V
VIN = 4.0V
FIGURE 2-5:
Load Regulation vs.
Temperature (Adjustable Version).
Adjust Pin Voltage (V)
Quiescent Current (μA)
55
FIGURE 2-4:
Line Regulation vs.
Temperature (Adjustable Version).
180
140
135
130
125
120
115
110
105
100
95
90
85
30
Temperature (°C)
FIGURE 2-1:
Quiescent Current vs. Input
Voltage (Adjustable Version).
Ground Current (μA)
IOUT = 1 mA
0.09
VIN = 5.0V
VIN = 3.0V
VIN = 2.3V
VOUT = 1.2V
IOUT = 1.0 mA
VIN = 6.0V
0.410
VIN = 5.0V
0.409
0.408
VIN = 2.3V
0.407
0.406
-45
-20
5
30
55
80
105
Temperature (°C)
FIGURE 2-3:
Quiescent Current vs.
Junction Temperature (Adjustable Version).
DS22057A-page 10
130
-45
-20
5
30
55
80
105
130
Temperature (°C)
FIGURE 2-6:
Adjust Pin Voltage vs.
Temperature (Adjustable Version).
© 2007 Microchip Technology Inc.
MCP1826/MCP1826S
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VOUT + 0.6V, Fixed output.
150
Quiescent Current (μA)
Dropout Voltage (V)
0.30
0.25
0.20
VOUT = 5.0V Adj
0.15
VOUT = 2.5V Adj
0.10
0.05
0.00
0
200
400
600
800
VOUT = 0.8V
IOUT = 0 mA
140
130
+130°C
120
+90°C
+25°C
110
0°C
100
-45°C
90
1000
2
3
4
Input Voltage (V)
Load Current (mA)
FIGURE 2-7:
Dropout Voltage vs. Load
Current (Adjustable Version).
0.31
VOUT = 5.0V Adj
0.28
0.25
VOUT = 2.5V Adj
0.22
0.19
VOUT = 2.5V
IOUT = 0 mA
140
130
+130°C
120
+90°C
110
+25°C
0°C
100
-45°C
90
80
-45
-20
5
30
55
80
105
130
3
3.5
4
Temperature (°C)
170.0000
FIGURE 2-11:
Voltage.
200
150.0000
Ground Current (μA)
VOUT = 2.5V
IOUT= 0 mA
160.0000
VIN = 6.0V
140.0000
130.0000
120.0000
VIN = 5.0V
VIN = 3.9V
110.0000
4.5
5
5.5
6
Input Voltage (V)
FIGURE 2-8:
Dropout Voltage vs.
Temperature (Adjustable Version).
Power Good Time Delay (µS)
6
Quiescent Current vs. Input
150
IOUT = 1.0A
Quiescent Current (μA)
Dropout Voltage (V)
0.34
FIGURE 2-10:
Voltage.
5
VIN = 3.1V
100.0000
Quiescent Current vs. Input
VIN = 2.3V for VR=0.8V
VIN = 3.9V for VR=3.3V
180
160
VOUT=3.3V
140
120
VOUT=0.8V
100
80
60
-45
-20
5
30
55
80
105
130
0
Temperature (°C)
FIGURE 2-9:
Power Good (PWRGD)
Time Delay vs. Temperature.
© 2007 Microchip Technology Inc.
250
500
750
1000
Load Current (mA)
FIGURE 2-12:
Current.
Ground Current vs. Load
DS22057A-page 11
MCP1826/MCP1826S
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VOUT + 0.6V, Fixed output.
0.040
IOUT = 0 mA
125
Line Regulation (%/V)
Quiescent Current (μA)
130
120
115
110
VOUT = 2.5V
105
100
95
VOUT = 0.8V
90
IOUT = 1 mA
0.035
0.030
IOUT = 50 mA
0.025
IOUT = 250 mA
0.020
IOUT = 1000 mA
-20
5
30
55
80
105
130
-45
-20
5
Temperature (°C)
FIGURE 2-13:
Temperature.
FIGURE 2-16:
Temperature.
Quiescent Current vs.
Load Regulation (%)
0.40
VIN = 4.0V
VIN = 6.0V
VIN = 3.0V
0.20
VIN = 5.0V
55
80
105
130
Line Regulation vs.
0.30
VR = 0.8V
0.30
30
Temperature (°C)
0.50
ISHDN (μA)
IOUT = 500 mA
0.015
-45
VIN = 2.3V
0.10
0.00
VOUT = 0.8V
VIN = 2.3V
IOUT = 1 mA to 1000 mA
0.20
0.10
0.00
-0.10
-0.20
-0.30
-45
-20
5
30
55
80
105
-45
130
-20
5
Temperature (°C)
0.10
IOUT = 50 mA
IOUT = 100 mA
0.06
0.04
IOUT = 1A
0.02
80
105
130
0.00
IOUT = 1 mA to 1000 mA
-0.05
IOUT = 500mA
0.00
Load Regulation (%)
0.08
55
FIGURE 2-17:
Load Regulation vs.
Temperature (VOUT < 2.5V Fixed).
VOUT = 0.8V
VIN = 2.3V to 6.0V
IOUT = 1 mA
30
Temperature (°C)
ISHDN vs. Temperature.
FIGURE 2-14:
Line Regulation (%/V)
VR = 2.5V
VIN = 3.1 to 6.0V
VOUT = 2.5V
-0.10
-0.15
-0.20
VOUT = 5.0V
-0.25
-0.30
-0.35
-0.40
-45
-20
5
30
55
80
105
Temperature (°C)
FIGURE 2-15:
Temperature.
DS22057A-page 12
Line Regulation vs.
130
-45
-20
5
30
55
80
105
130
Temperature (°C)
FIGURE 2-18:
Load Regulation vs.
Temperature (VOUT ≥ 2.5V Fixed).
© 2007 Microchip Technology Inc.
MCP1826/MCP1826S
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VOUT + 0.6V, Fixed output.
10.000
0.25
VOUT = 2.5V
Noise (mV/ √Hz)
Dropout Voltage (V)
0.30
0.20
0.15
VOUT = 5.0V
0.10
VR=0.8V, VIN=2.3V
1.000
IOUT=200 mA
VR=3.3V, VIN=4.1V
0.100
0.05
0.010
0.01
0.00
0
200
400
600
800
1000
0.1
Load Current (mA)
FIGURE 2-19:
Current.
Dropout Voltage vs. Load
0.30
-20
VOUT = 2.5V
0.26
VOUT = 5.0V
-30
-40
VR=1.2V Adj
COUT=10 μF ceramic X7R
VIN=3.1V
CIN=0 μF
IOUT=10 mA
-50
-60
0.22
-70
0.20
-45
-20
5
30
55
80
105
-80
0.01
130
0.1
Temperature (°C)
FIGURE 2-20:
Temperature.
1000
-10
0.28
0.24
100
0
IOUT = 1000 mA
0.32
1
10
Frequency (kHz)
FIGURE 2-22:
Output Noise Voltage
Density vs. Frequency.
PSRR (dB)
Dropout Voltage (V)
0.34
Dropout Voltage vs.
1
10
Frequency (kHz)
100
1000
FIGURE 2-23:
Power Supply Ripple
Rejection (PSRR) vs. Frequency (Adjustable).
0
2.00
1.80
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
VOUT = 0.8V
-10
-20
PSRR (dB)
Short Circuit Current (A)
COUT=1 μF ceramic X7R
CIN=10 μF ceramic
-30
-40
VR=3.3V Fixed
COUT=22 μF ceramic X7R
VIN=3.9V
CIN=0 μF
IOUT=10 mA
-50
-60
-70
0
1
2
3
4
5
6
Input Voltage (V)
FIGURE 2-21:
Input Voltage.
Short Circuit Current vs.
© 2007 Microchip Technology Inc.
-80
0.01
0.1
1
10
Frequency (kHz)
100
1000
FIGURE 2-24:
Power Supply Ripple
Rejection (PSRR) vs. Frequency.
DS22057A-page 13
MCP1826/MCP1826S
.Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VOUT + 0.6V, Fixed output.
FIGURE 2-25:
2.5V (Adj.) Startup from VIN.
FIGURE 2-28:
FIGURE 2-26:
Shutdown.
2.5V (Adj.) Startup from
FIGURE 2-29:
Dynamic Load Response
(10 mA to 1000 mA).
FIGURE 2-27:
Timing.
Power Good (PWRGD)
FIGURE 2-30:
Dynamic Load Response
(100 mA to 1000 mA).
DS22057A-page 14
Dynamic Line Response.
© 2007 Microchip Technology Inc.
MCP1826/MCP1826S
3.0
PIN DESCRIPTION
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
3-Pin Fixed
Output
5-Pin Fixed
Output
Adjustable
Output
Name
Description
Shutdown Control Input (active-low)
—
1
1
SHDN
1
2
2
VIN
2
3
3
GND
Ground
Regulated Output Voltage
Input Voltage Supply
3
4
4
VOUT
—
5
—
PWRGD
—
—
5
ADJ
Voltage Adjust/Sense Input
EP
Exposed Pad of the Package (ground potential)
Exposed Pad
3.1
PIN FUNCTION TABLE
Exposed Pad Exposed Pad
Shutdown Control Input (SHDN)
Power Good Output
3.5
Power Good Output (PWRGD)
The SHDN input is used to turn the LDO output voltage
on and off. When the SHDN input is at a logic-high
level, the LDO output voltage is enabled. When the
SHDN input is pulled to a logic-low level, the LDO
output voltage is disabled. When the SHDN input is
pulled low, the PWRGD output also goes low and the
LDO enters a low quiescent current shutdown state
where the typical quiescent current is 0.1 µA.
The PWRGD output is an open-drain output used to
indicate when the LDO output voltage is within 92%
(typically) of its nominal regulation value. The PWRGD
threshold has a typical hysteresis value of 2%. The
PWRGD output is delayed by 200 µs (typical) from the
time the LDO output is within 92% + 3% (max hysteresis) of the regulated output value on power-up. This
delay time is internally fixed.
3.2
3.6
Input Voltage Supply (VIN)
Output Voltage Adjust Input (ADJ)
Connect the unregulated or regulated input voltage
source to VIN. If the input voltage source is located
several inches away from the LDO, or the input source
is a battery, it is recommended that an input capacitor
be used. A typical input capacitance value of 1 µF to
10 µF should be sufficient for most applications.
For adjustable applications, the output voltage is
connected to the ADJ input through a resistor divider
that sets the output voltage regulation value. This
provides the user the capability to set the output
voltage to any value they desire within the 0.8V to 5.0V
range of the device.
3.3
3.7
Ground (GND)
Connect the GND pin of the LDO to a quiet circuit
ground. This will help the LDO power supply rejection
ratio and noise performance. The ground pin of the
LDO only conducts the quiescent current of the LDO
(typically 120 µA), so a heavy trace is not required.
For applications have switching or noisy inputs tie the
GND pin to the return of the output capacitor. Ground
planes help lower inductance and voltage spikes
caused by fast transient load currents and are
recommended for applications that are subjected to
fast load transients.
3.4
Exposed Pad (EP)
The DDPAK and TO-220 package have an exposed tab
on the package. A heat sink may may be mount to the
tab to aid in the removal of heat from the package
during operation. The exposed tab is at the ground
potential of the LDO.
Regulated Output Voltage (VOUT)
The VOUT pin is the regulated output voltage of the
LDO. A minimum output capacitance of 1.0 µF is
required for LDO stability. The MCP1826/MCP1826S is
stable with ceramic, tantalum and aluminum-electrolytic capacitors. See Section 4.3 “Output Capacitor”
for output capacitor selection guidance.
© 2007 Microchip Technology Inc.
DS22057A-page 15
MCP1826/MCP1826S
4.0
DEVICE OVERVIEW
EQUATION 4-2:
The MCP1826/MCP1826S is a high output current,
Low Dropout (LDO) voltage regulator. The low dropout
voltage of 300 mV typical at 1000 mA of current makes
it ideal for battery-powered applications. Unlike other
high output current LDOs, the MCP1826/MCP1826S
only draws a maximum of 220 µA of quiescent current.
The MCP1826 has a shutdown control input and a
power good output.
4.1
The 5-pin MCP1826 LDO is available with either a fixed
output voltage or an adjustable output voltage. The
output voltage range is 0.8V to 5.0V for both versions.
The 3-pin MCP1826S LDO is available as a fixed
voltage device.
4.1.1
ADJUST INPUT
The adjustable version of the MCP1826 uses the ADJ
pin (pin 5) to get the output voltage feedback for output
voltage regulation. This allows the user to set the
output voltage of the device with two external resistors.
The nominal voltage for ADJ is 0.41V.
Figure 4-1 shows the adjustable version of the
MCP1826. Resistors R1 and R2 form the resistor
divider network necessary to set the output voltage.
With this configuration, the equation for setting VOUT is:
EQUATION 4-1:
VOUT
=
LDO Output Voltage
VADJ
=
ADJ Pin Voltage
(typically 0.41V)
VOUT
SHDN
1 2 3 4 5
R1
ADJ
C2
1 µF
VIN
C1
4.7 µF
GND
R2
FIGURE 4-1:
Typical adjustable output
voltage application circuit.
The allowable resistance value range for resistor R2 is
from 10 kΩ to 200 kΩ. Solving the equation for R1
yields the following equation:
DS22057A-page 16
LDO Output Voltage
VADJ
=
ADJ Pin Voltage
(typically 0.41V)
Output Current and Current
Limiting
The MCP1826/MCP1826S also incorporates an output
current limit. If the output voltage falls below 0.7V due
to an overload condition (usually represents a shorted
load condition), the output current is limited to 2.2A
(typical). If the overload condition is a soft overload, the
MCP1826/MCP1826S will supply higher load currents
of up to 2.5A. The MCP1826/MCP1826S should not be
operated in this condition continuously as it may result
in failure of the device. However, this does allow for
device usage in applications that have higher pulsed
load currents having an average output current value of
1000 mA or less.
Output Capacitor
The MCP1826/MCP1826S requires a minimum output
capacitance of 1 µF for output voltage stability. Ceramic
capacitors are recommended because of their size,
cost and environmental robustness qualities.
MCP1826-ADJ
On
=
The MCP1826/MCP1826S LDO is tested and ensured
to supply a minimum of 1000 mA of output current. The
MCP1826/MCP1826S has no minimum output load, so
the output load current can go to 0 mA and the LDO will
continue to regulate the output voltage to within
tolerance.
4.3
Off
VOUT
Output overload conditions may also result in an overtemperature shutdown of the device. If the junction
temperature rises above 150°C, the LDO will shut
down the output voltage. See Section 4.8 “Overtemperature Protection” for more information on
overtemperature shutdown.
R1 + R2
V OUT = V ADJ ⎛ ------------------⎞
⎝ R2 ⎠
Where:
Where:
4.2
LDO Output Voltage
V OUT – V ADJ
R 1 = R 2 ⎛ --------------------------------⎞
⎝
⎠
V ADJ
Aluminum-electrolytic and tantalum capacitors can be
used on the LDO output as well. The Equivalent Series
Resistance (ESR) of the electrolytic output capacitor
must be no greater than 1 ohm. The output capacitor
should be located as close to the LDO output as is
practical. Ceramic materials X7R and X5R have low
temperature coefficients and are well within the
acceptable ESR range required. A typical 1 µF X7R
0805 capacitor has an ESR of 50 milli-ohms.
Larger LDO output capacitors can be used with the
MCP1826/MCP1826S
to
improve
dynamic
performance and power supply ripple rejection
performance. A maximum of 22 µF is recommended.
Aluminum-electrolytic capacitors are not recommended for low-temperature applications of ≤ 25°C.
© 2007 Microchip Technology Inc.
MCP1826/MCP1826S
4.4
Input Capacitor
Low input source impedance is necessary for the LDO
output to operate properly. When operating from
batteries, or in applications with long lead length
(> 10 inches) between the input source and the LDO,
some input capacitance is recommended. A minimum
of 1.0 µF to 4.7 µF is recommended for most
applications.
For applications that have output step load
requirements, the input capacitance of the LDO is very
important. The input capacitance provides the LDO
with a good local low-impedance source to pull the
transient currents from in order to respond quickly to
the output load step. For good step response
performance, the input capacitor should be of
equivalent (or higher) value than the output capacitor.
The capacitor should be placed as close to the input of
the LDO, as is practical. Larger input capacitors will
also help reduce any high-frequency noise on the input
and output of the LDO and reduce the effects of any
inductance that exists between the input source
voltage and the input capacitance of the LDO.
VPWRGD_TH
VOUT
TPG
VOH
PWRGD
VOL
FIGURE 4-2:
VIN
Power Good Output (PWRGD)
The PWRGD output is used to indicate when the output
voltage of the LDO is within 92% (typical value, see
Section 1.0 “Electrical Characteristics” for Minimum
and Maximum specifications) of its nominal regulation
value.
As the output voltage of the LDO rises, the PWRGD
output will be held low until the output voltage has
exceeded the power good threshold plus the hysteresis
value. Once this threshold has been exceeded, the
power good time delay is started (shown as TPG in the
Electrical Characteristics table). The power good time
delay is fixed at 200 µs (typical). After the time delay
period, the PWRGD output will go high, indicating that
the output voltage is stable and within regulation limits.
Power Good Timing.
TOR
30 µs
4.5
TVDET_PWRGD
70 µs
TPG
SHDN
VOUT
PWRGD
FIGURE 4-3:
Shutdown.
Power Good Timing from
If the output voltage of the LDO falls below the power
good threshold, the power good output will transition
low. The power good circuitry has a 170 µs delay when
detecting a falling output voltage, which helps to
increase noise immunity of the power good output and
avoid false triggering of the power good output during
fast output transients. See Figure 4-2 for power good
timing characteristics.
4.6
When the LDO is put into Shutdown mode using the
SHDN input, the power good output is pulled low
immediately, indicating that the output voltage will be
out of regulation. The timing diagram for the power
good output when using the shutdown input is shown in
Figure 4-3.
The SHDN input will ignore low-going pulses (pulses
meant to shut down the LDO) that are up to 400 ns in
pulse width. If the shutdown input is pulled low for more
than 400 ns, the LDO will enter Shutdown mode. This
small bit of filtering helps to reject any system noise
spikes on the shutdown input signal.
The power good output is an open-drain output that can
be pulled up to any voltage that is equal to or less than
the LDO input voltage. This output is capable of sinking
1.2 mA (VPWRGD < 0.4V maximum).
On the rising edge of the SHDN input, the shutdown
circuitry has a 30 µs delay before allowing the LDO
output to turn on. This delay helps to reject any false
turn-on signals or noise on the SHDN input signal. After
© 2007 Microchip Technology Inc.
Shutdown Input (SHDN)
The SHDN input is an active-low input signal that turns
the LDO on and off. The SHDN threshold is a
percentage of the input voltage. The typical value of
this shutdown threshold is 30% of VIN, with minimum
and maximum limits over the entire operating
temperature range of 45% and 15%, respectively.
DS22057A-page 17
MCP1826/MCP1826S
the 30 µs delay, the LDO output enters its soft-start
period as it rises from 0V to its final regulation value. If
the SHDN input signal is pulled low during the 30 µs
delay period, the timer will be reset and the delay time
will start over again on the next rising edge of the
SHDN input. The total time from the SHDN input going
high (turn-on) to the LDO output being in regulation is
typically 100 µs. See Figure 4-4 for a timing diagram of
the SHDN input.
TOR
400 ns (typ)
30 µs
70 µs
SHDN
VOUT
FIGURE 4-4:
Diagram.
Shutdown Input Timing
4.7
Dropout Voltage and Undervoltage
Lockout
Dropout voltage is defined as the input-to-output
voltage differential at which the output voltage drops
2% below the nominal value that was measured with a
VR + 0.5V differential applied. The MCP1826/
MCP1826S LDO has a very low dropout voltage
specification of 300 mV (typical) at 1000 mA of output
current. See Section 1.0 “Electrical Characteristics”
for maximum dropout voltage specifications.
The MCP1826/MCP1826S LDO operates across an
input voltage range of 2.3V to 6.0V and incorporates
input Undervoltage Lockout (UVLO) circuitry that keeps
the LDO output voltage off until the input voltage
reaches a minimum of 2.00V (typical) on the rising
edge of the input voltage. As the input voltage falls, the
LDO output will remain on until the input voltage level
reaches 1.82V (typical).
Since the MCP1826/MCP1826S LDO undervoltage
lockout activates at 1.82V as the input voltage is falling,
the dropout voltage specification does not apply for
output voltages that are less than 1.8V.
For high-current applications, voltage drops across the
PCB traces must be taken into account. The trace
resistances can cause significant voltage drops
between the input voltage source and the LDO. For
applications with input voltages near 2.3V, these PCB
trace voltage drops can sometimes lower the input
voltage enough to trigger a shutdown due to
undervoltage lockout.
4.8
Overtemperature Protection
The MCP1826/MCP1826S LDO has temperaturesensing circuitry to prevent the junction temperature
from exceeding approximately 150°C. If the LDO
junction temperature does reach 150°C, the LDO
output will be turned off until the junction temperature
cools to approximately 140°C, at which point the LDO
output will automatically resume normal operation. If
the internal power dissipation continues to be
excessive, the device will again shut off. The junction
temperature of the die is a function of power dissipation, ambient temperature and package thermal
resistance. See Section 5.0 “Application Circuits/
Issues” for more information on LDO power
dissipation and junction temperature.
DS22057A-page 18
© 2007 Microchip Technology Inc.
MCP1826/MCP1826S
5.0
APPLICATION CIRCUITS/
ISSUES
5.1
Typical Application
In addition to the LDO pass element power dissipation,
there is power dissipation within the MCP1826/
MCP1826S as a result of quiescent or ground current.
The power dissipation as a result of the ground current
can be calculated using the following equation:
The MCP1826/MCP1826S is used for applications that
require high LDO output current and a power good
output.
EQUATION 5-2:
P I ( GND ) = V IN ( MAX ) × I VIN
Where:
VOUT = 2.5V @ 1000 mA
MCP1826-2.5
On
Off
SHDN
1 2 3 4 5
R1
10 kΩ
C2
10 µF
VIN
3.3V
C1
4.7 µF
GND
FIGURE 5-1:
5.1.1
Typical Application Circuit.
APPLICATION CONDITIONS
Package Type = TO-220-5
VIN maximum = 3.465V
VIN minimum = 3.135V
VDROPOUT (max) = 0.350V
VOUT (typical) = 2.5V
IOUT = 1000 mA maximum
PDISS (typical) = 0.965W
Temperature Rise = 28.27°C
Power Calculations
5.2.1
=
Power dissipation due to the
quiescent current of the LDO
VIN(MAX)
=
Maximum input voltage
IVIN
=
Current flowing in the VIN pin
with no LDO output current
(LDO quiescent current)
PWRGD
Input Voltage Range = 3.3V ± 5%
5.2
PI(GND
POWER DISSIPATION
The internal power dissipation within the MCP1826/
MCP1826S is a function of input voltage, output
voltage, output current and quiescent current.
Equation 5-1 can be used to calculate the internal
power dissipation for the LDO.
EQUATION 5-1:
P LDO = ( V IN ( MAX ) ) – V OUT ( MIN ) ) × I OUT ( MAX ) )
The total power dissipated within the MCP1826/
MCP1826S is the sum of the power dissipated in the
LDO pass device and the P(IGND) term. Because of the
CMOS construction, the typical IGND for the MCP1826/
MCP1826S is 120 µA. Operating at a maximum VIN of
3.465V results in a power dissipation of 0.12 milli-Watts
for a 2.5V output. For most applications, this is small
compared to the LDO pass device power dissipation
and can be neglected.
The maximum continuous operating junction
temperature specified for the MCP1826/MCP1826S is
+125°C. To estimate the internal junction temperature
of the MCP1826/MCP1826S, the total internal power
dissipation is multiplied by the thermal resistance from
junction to ambient (RθJA) of the device. The thermal
resistance from junction to ambient for the TO-220-5
package is estimated at 29.3°C/W.
EQUATION 5-3:
T J ( MAX ) = P TOTAL × Rθ JA + T AMAX
TJ(MAX) = Maximum continuous junction
temperature
PTOTAL = Total device power dissipation
RθJA = Thermal resistance from junction to
ambient
TAMAX = Maximum ambient temperature
Where:
PLDO
=
LDO Pass device internal
power dissipation
VIN(MAX)
=
Maximum input voltage
VOUT(MIN)
=
LDO minimum output voltage
© 2007 Microchip Technology Inc.
DS22057A-page 19
MCP1826/MCP1826S
The maximum power dissipation capability for a
package can be calculated given the junction-toambient thermal resistance and the maximum ambient
temperature for the application. Equation 5-4 can be
used to determine the package maximum internal
power dissipation.
EQUATION 5-4:
P D ( MAX )
( T J ( MAX ) – T A ( MAX ) )
= --------------------------------------------------Rθ JA
PD(MAX) = Maximum device power dissipation
TJ(MAX) = maximum continuous junction
temperature
TA(MAX) = maximum ambient temperature
5.3
Typical Application
Internal power dissipation, junction temperature rise,
junction temperature and maximum power dissipation
is calculated in the following example. The power
dissipation as a result of ground current is small
enough to be neglected.
5.3.1
POWER DISSIPATION EXAMPLE
Package
Package Type = TO-220-5
Input Voltage
VIN = 3.3V ± 5%
LDO Output Voltage and Current
VOUT = 2.5V
RθJA = Thermal resistance from junction-toambient
IOUT = 1000 mA
Maximum Ambient Temperature
EQUATION 5-5:
T J ( RISE ) = P D ( MAX ) × Rθ JA
TA(MAX) = 60°C
Internal Power Dissipation
PLDO(MAX) = (VIN(MAX) – VOUT(MIN)) x IOUT(MAX)
TJ(RISE) = Rise in device junction temperature
over the ambient temperature
PLDO = ((3.3V x 1.05) – (2.5V x 0.975))
x 1000 mA
PD(MAX) = Maximum device power dissipation
PLDO = 1.028 Watts
RθJA = Thermal resistance from junction-toambient
EQUATION 5-6:
T J = T J ( RISE ) + T A
TJ = Junction temperature
TJ(RISE) = Rise in device junction temperature
over the ambient temperature
TA = Ambient temperature
5.3.1.1
Device Junction Temperature Rise
The internal junction temperature rise is a function of
internal power dissipation and the thermal resistance
from junction-to-ambient for the application. The
thermal resistance from junction-to-ambient (RθJA) is
derived from EIA/JEDEC standards for measuring
thermal resistance. The EIA/JEDEC specification is
JESD51. The standard describes the test method and
board specifications for measuring the thermal
resistance from junction to ambient. The actual thermal
resistance for a particular application can vary
depending on many factors such as copper area and
thickness. Refer to AN792, “A Method to Determine
How Much Power a SOT23 Can Dissipate in an Application” (DS00792), for more information regarding this
subject.
TJ(RISE) = PTOTAL x RθJA
TJRISE = 1.028 W x 29.3°C/W
TJRISE = 30.12°C
DS22057A-page 20
© 2007 Microchip Technology Inc.
MCP1826/MCP1826S
5.3.1.2
Junction Temperature Estimate
To estimate the internal junction temperature, the
calculated temperature rise is added to the ambient or
offset temperature. For this example, the worst-case
junction temperature is estimated below:
TJ = TJRISE + TA(MAX)
TJ = 30.12°C + 60.0°C
TJ = 90.12°C
5.3.1.3
Maximum Package Power
Dissipation at 60°C Ambient
Temperature
TO-220-5 (29.3° C/W RθJA):
PD(MAX) = (125°C – 60°C) / 29.3°C/W
PD(MAX) = 2.218W
DDPAK-5 (31.2°C/Watt RθJA):
PD(MAX) = (125°C – 60°C)/ 31.2°C/W
PD(MAX) = 2.083W
From this table, you can see the difference in maximum
allowable power dissipation between the TO-220-5
package and the DDPAK-5 package.
© 2007 Microchip Technology Inc.
DS22057A-page 21
MCP1826/MCP1826S
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
3-Lead DDPAK (MCP1826S)
XXXXXXXXX
XXXXXXXXX
YYWWNNN
1
2
Example:
MCP1826S
e3
0.8EEB^^
0730256
3
1
3-Lead SOT-223 (MCP1826S)
1826S08
EDB0730
256
3-Lead TO-220 (MCP1826S)
Example:
XXXXXXXXX
XXXXXXXXX
YYWWNNN
MCP1826S
12EAB^^
e3
0730256
1
1
2
3
Legend: XX...X
Y
YY
WW
NNN
e3
*
DS22057A-page 22
3
Example:
XXXXXXX
XXXYYWW
NNN
Note:
2
2
3
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2007 Microchip Technology Inc.
MCP1826/MCP1826S
Package Marking Information (Continued)
5-Lead DDPAK (MCP1826)
XXXXXXXXX
XXXXXXXXX
YYWWNNN
MCP1826
e3
1.0EET^^
0730256
1 2 3 4 5
1 2 3 4 5
5-Lead SOT-223 (MCP1826)
XXXXXXX
XXXYYWW
NNN
5-Lead TO-220 (MCP1826)
Example:
1826-08
EDC0730
256
Example:
XXXXXXXXX
XXXXXXXXX
YYWWNNN
MCP1826
e3
08EAT^^
0730256
1 2 3 4 5
1 2 3 4 5
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Example:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2007 Microchip Technology Inc.
DS22057A-page 23
MCP1826/MCP1826S
DS22057A-page 24
© 2007 Microchip Technology Inc.
MCP1826/MCP1826S
© 2007 Microchip Technology Inc.
DS22057A-page 25
MCP1826/MCP1826S
DS22057A-page 26
© 2007 Microchip Technology Inc.
MCP1826/MCP1826S
© 2007 Microchip Technology Inc.
DS22057A-page 27
MCP1826/MCP1826S
DS22057A-page 28
© 2007 Microchip Technology Inc.
MCP1826/MCP1826S
© 2007 Microchip Technology Inc.
DS22057A-page 29
MCP1826/MCP1826S
NOTES:
DS22057A-page 30
© 2007 Microchip Technology Inc.
MCP1826/MCP1826S
APPENDIX A:
REVISION HISTORY
Revision A (August 2007)
• Original Release of this Document.
© 2007 Microchip Technology Inc.
DS22057A-page 31
MCP1826/MCP1826S
NOTES:
DS22057A-page 32
© 2007 Microchip Technology Inc.
MCP1826/MCP1826S
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
XX
X
X
X/
XX
Output Feature Tolerance Temp. Package
Voltage Code
Device:
MCP1826: 1000 mA Low Dropout Regulator
MCP1826T: 1000 mA Low Dropout Regulator
Tape and Reel
MCP1826S: 1000 mA Low Dropout Regulator
MCP1826ST: 1000 mA Low Dropout Regulator
Tape and Reel
Output Voltage *:
08
12
18
25
30
33
50
ADJ
=
=
=
=
=
=
=
=
0.8V “Standard”
1.2V “Standard”
1.8V “Standard”
2.5V “Standard”
3.0V “Standard”
3.3V “Standard”
5.0V “Standard”
Adjustable Output Voltage ** (MCP1826 only)
*Contact factory for other output voltage options
** When ADJ is used, the “extra feature code” and
“tolerance” columns do not apply. Refer to examples.
Extra Feature Code:
0
= Fixed
Tolerance:
2
= 2.0% (Standard)
Temperature:
E
= -40°C to +125°C
Package Type:
AB
AT
DB
DC
EB
ET
=
=
=
=
=
=
Examples:
a)
b)
c)
d)
e)
f)
g)
h)
i)
MCP1826-0802E/XX:
MCP1826-1002E/XX:
MCP1826-1202E/XX:
MCP1826-1802E/XX
MCP1826-2502EXX:
MCP1826-3002E/XX:
MCP1826-3302E/XX
MCP1826-5002E/XX:
MCP1826-ADJE/XX:
a)
b)
c)
d)
e)
f)
g)
h)
MCP1826S-0802E/XX:0.8V LDO Regulator
MCP1826S-1002E/XX:1.0V LDO Regulator
MCP1826S-1202E/XX 1.2V LDO Regulator
MCP1826S-1802E/XX 1.8V LDO Regulator
MCP1826S-2502E/XX 2.5V LDO Regulator
MCP1826S-2502E/XX 3.0V LDO Regulator
MCP1826S-3302E/XX 3.3V LDO Regulator
MCP1826S-5002E/XX 5.0V LDO Regulator
XX =
=
=
=
=
=
0.8V LDO Regulator
1.0V LDO Regulator
1.2V LDO Regulator
1.8V LDO Regulator
25V LDO Regulator
3.0V LDO Regulator
3.3V LDO Regulator
5.0V LDO Regulator
ADJ LDO Regulator
AB for 3LD TO-220 package
AT for 5LD TO-220 package
DB for 3LD SOT-223 package
DC for 5LD SOT-223 package
EB for 3LD DDPAK package
ET for 5LD DDPAK package
Plastic Transistor Outline, TO-220, 3-lead
Plastic Transistor Outline, TO-220, 5-lead
Plastic Transistor Outline, SOT-223, 3-lead
Plastic Transistor Outline, SOT-223, 5-lead
Plastic, DDPAK, 3-lead
Plastic, DDPAK, 5-lead
Note: ADJ (Adjustable) only available in 5-lead version.
© 2007 Microchip Technology Inc.
DS22057A-page 33
MCP1826/MCP1826S
NOTES:
DS22057A-page 34
© 2007 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The
Embedded Control Solutions Company are registered
trademarks of Microchip Technology Incorporated in the
U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
WiperLock and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2007 Microchip Technology Inc.
DS22057A-page 35
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-4182-8400
Fax: 91-80-4182-8422
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Fuzhou
Tel: 86-591-8750-3506
Fax: 86-591-8750-3521
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Penang
Tel: 60-4-646-8870
Fax: 60-4-646-5086
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
China - Shunde
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
06/25/07
DS22057A-page 36
© 2007 Microchip Technology Inc.