Cypress CY2DL814ZXIT Comlinkâ ¢ sery Datasheet

ComLink™ Series
CY2DL814
1:4 Clock Fanout Buffer
Features
Description
• Low-voltage operation
The Cypress CY2 series of network circuits is produced using
advanced 0.35-micron CMOS technology, achieving the
industry’s fastest logic.
• VDD = 3.3V
• 1:4 Fanout
The Cypress CY2DL814 fanout buffer features a single
LVDS-, LVPECL-, or LVTTL-compatible input and four LVDS
output pairs.
• Single-input configurable for
— LVDS, LVPECL, or LVTTL
Designed for data-communication clock management applications, the fanout from a single input reduces loading on the
input clock.
— Four differential pairs of LVDS outputs
• Drives 50- or 100-ohm load (selectable)
• Low input capacitance
The CY2DL814 is ideal for both level translations from single
ended to LVDS and/or for the distribution of LVDS-based clock
signals. The Cypress CY2DL814 has configurable input and
output functions. The input can be selectable for
LVPECL/LVTTL or LVDS signals while the output driver’s
support standard and high drive LVDS. Drive either a 50-ohm
or 100-ohm line with a single part number/device.
• 85 ps typical output-to-output skew
• <4 ns typical propagation delay
• Does not exceed Bellcore 802.3 standards
• Operation at ⇒ 350 MHz – 700 Mbps
• Industrial versions available
• Packages available include TSSOP/SOIC
Block Diagram
EN1
EN2
EN1
CONFIG
Q1A
Q1B
CNTRL
VDD
GND
Q2A
Q2B
IN+
IN-
IN+
INEN2
LVDS /
LVPECL /
LVTTL
Q3A
Q3B
CONFIG
1
2
3
4
5
6
7
8
CY2DL814
Pin Configuration
16
15
14
13
12
11
10
9
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
16-pin TSSOP/SOIC
Q4A
Q4B
OUTPUT
CNTRL
LVDS
Cypress Semiconductor Corporation
Document #: 38-07057 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised June 20, 2005
ComLink™ Series
CY2DL814
Pin Description
Pin Number
Pin Name
Pin Standard Interface
Description
6,7
IN+, IN–
Configurable
3
CNTRL
LVTTL/LVCMOS
Converts into a High drive driver from a standard LVDS.
Standard drive (logic = 0)
B/High drive/Bus (logic = 1)
2
CONFIG
LVTTL/LVCMOS
Converts inputs (IN+/IN–), (EN, EN#) from the default
LVPECL/LVDS (logic = 0)
To LVTTL/LVCMOS (logic = 1)
Enable/disable logic. See Table 1 below for details.
Differential input pair or single line.
LVPECL default. See config below.
1,8
EN1, EN2
LVTTL/LVCMOS
16,15,14,13
12,11,10,9
Q1A, Q1B, Q2A,
Q2B,
Q3A, Q3B, Q4A,
Q4B
LDVS
4
VDD
POWER
Positive supply voltage
5
GND
POWER
Ground
Differential outputs.
Maximum Ratings[1, 2]
Storage Temperature: ................................ –65°C to + 150°C
(Outputs only) ........................................ –0.3V to VDD + 0.3V
Ambient Temperature:................................... –40°C to +85°C
DC Input Voltage ................................... –0.3V to VDD + 0.3V
Supply Voltage to Ground Potential
(Inputs and VCC only)....................................... –0.3V to 4.6V
Power Dissipation........................................................ 0.75W
DC Output Voltage................................. –0.3V to VDD + 0.9V
Supply Voltage to Ground Potential
Table 1. EN1 EN2 Function Table–Differential Input Mode
Enable Logic
Input
EN1
EN2
IN+
H
X
H
X
X
L
X
L
L
H
Outputs
IN–
QnA
QnB
H
L
H
L
L
H
L
H
H
L
H
L
L
H
L
H
X
X
Z
Z
Table 2. Output Drive Control for Standard and Bus/B/High Drive B
CNTRL Pin 3 Binary Value
Drive STD
Impedance
0
Standard
100 ohm
Output Voltage Value
50 ohm
V = 1/2 * V0
1
High Drive/Bus/B
100 ohm
V = 2 * V0
50 ohm
V = V0
V0 = Voutput
Notes:
1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Document #: 38-07057 Rev. *B
Page 2 of 8
ComLink™ Series
CY2DL814
Table 3. Input Receiver Configuration for Differential or LVTTL/LVCMOS
CONFIG
Pin 2
Binary Value
Input Receiver Family
Input Receiver Type
1
LVTTL in LVCMOS
Single-ended, Non-inverting, Inverting, Void of Bias Resistors
0
LVDS
Low-voltage Differential Signaling
LVPECL
Low-voltage Pseudo (Positive) Emitter Coupled Logic
Table 4. Function Control of the TTL Input Logic Used to Accept or Invert the Input Signal
LVTTL/LVCMOS Input Logic
Input Condition
Ground
Input Logic
Output Logic Q Pins, Q1A or Q1
Input
True
Input
Invert
Input
True
Input
Invert
IN– Pin 7
IN+ Pin 6
VCC
IN– Pin 7
IN+ Pin 6
Ground
IN+ Pin 6
IN– Pin 7
VCC
IN+ Pin 6
IN– Pin 7
Table 5. Power Supply Characteristics
Typ.
Max.
Unit
ICCD
Parameter
Dynamic Power Supply Current
Description
VDD = Max.
Input toggling 50% Duty Cycle,
Outputs Open
Test Conditions
Min.
1.5
2.0
mA/MHz
IC
Total Power Supply Current
VDD = Max.
Input toggling 50% Duty Cycle,
Outputs Open
fL=100 MHz
90
100
mA
Min.
Typ.
Max. Unit
Table 6. D.C Electrical Characteristics: 3.3V–LVDS Input
Parameter
Description
Conditions
VID
Magnitude of Differential Input Voltage
VIC
Common-mode of Differential Input Voltage IVIDI (min. and max.)
100
IVIDI/2
VIH
Input High Voltage
Guaranteed Logic High Level
VIL
Input Low Voltage
Guaranteed Logic Low Level
IIH
Input High Current
VDD = Max.
VIN = VDD
IIL
Input Low Current
VDD = Max.
VIN = VSS
II
Input High Current
VDD = Max., VIN = VDD(max.)
Config/Cntrl Pins
600
2.4–(IVIDI/2)
2
mV
V
V
0.8
V
±10
±20
µA
±10
±20
µA
±20
µA
Table 7. D.C Electrical Characteristics: 3.3V–LVPECL Input
Parameter
Description
VID
Differential Input Voltage p-p
VCM
Common-mode Voltage
Conditions
Min.
Guaranteed Logic High Level
Typ.
Max.
Unit
400
2600
mV
1.65
2.25
V
IIH
Input High Current
VDD = Max.
VIN = VDD
±10
±20
µA
IIL
Input Low Current
VDD = Max.
VIN = VSS
±10
±20
µA
II
Input High Current
VDD = Max., VIN = VDD(Max.)
±20
µA
Document #: 38-07057 Rev. *B
Page 3 of 8
ComLink™ Series
CY2DL814
Table 8. D.C Electrical Characteristics: 3.3V–LVTTL/LVCMOS Input
Parameter
Description
Conditions
VIH
Input High Voltage
Guaranteed Logic High Level
VIL
Input Low Voltage
Guaranteed Logic Low Level
Min.
Typ.
Max.
Unit
2
V
0.8
V
IIH
Input High Current
VDD= Max.
VIN = 2.7V
1
µA
IIL
Input Low Current
VDD= Max.
VIN = 0.5V
–1
µA
II
Input High Current
VDD = Max., VIN = VDD(Max.)
20
µA
VIK
Clamp Diode Voltage
VDD = Min., IIN = –18 mA
–1.2
V
VH
Input Hysteresis
–0.7
80
mV
Table 9. D.C Electrical Characteristics: 3.3V–LVDS OUTPUT
Parameter
Description
Conditions
Typ.
Max.
Unit
I VOD I
Differential output voltage p-p VDD = 3.3V, VIN = VIH, or VIL
0.25
–
0.45
V
VOC(SS)
Steady-state common-mode
output voltage
–
–
226
mV
Delta
VOC(SS)
Change in VOC(SS) between
logic states
–50
3
50
mV
VOC(PP)
Peak to peak common mode
output voltage
–
–
150
mV
IOS
Output short circuit
–
–
–20
mA
–
–
1475
mV
925
–
–
mV
Voh
Output voltage high
Vol
Output voltage low
RL = 100 ohm
Min.
QA = 0V or QB = 0V
RL = 100 ohm
Table 10.AC Parameters
Parameter
Rise Time
Description
Conditions
CL–10 pF
Pin control (pin 3) logic is “FALSE”
defaulting to 100 ohm output drivers. RL and CL to GND
Differential 20% to 80%
3 CL = Cintrinsic and Cexternal
Min. Typ. Max. Unit
RL = 100 ohm
Fall Time
Rise Time
Pin control (pin 3) logic is “True”
defaulting to 50 ohm output drivers.
Differential 20% to 80%
CL–10 pF
RL and CL to GND
3 CL = Cintrinsic and Cexternal
RL = 50 ohm
Output boost
Fall Time
–
–
1.4
ns
–
–
1.4
ns
–
350
600
ps
–
350
600
ps
Table 11.AC Switching Characteristics @ 3.3 V (VDD = 3.3V ±5%, Temperature = –40°C to +85°C)
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
IN [+,-] to Q[A,B] Data and Clock Speed
tPLH
Propagation Delay – Low to High
3
4
5
ns
tPHL
Propagation Delay – High to Low
3
4
5
ns
Tpd
Propagation Delay
3
4
5
ns
VOD = 100 mV
IN [1,2] to Q[A,B] Control Speed
TPe
Enable (EN) to functional operation
–
–
6
ns
Tpd
Functional operation to Disable
–
–
5
ns
Q[A,B] Output Skews
tSK(0)
Output Skew: Skew between outputs of the same
package (in phase)
–
0.085
0.2
ns
tSK(p)
Pulse Skew: Skew between opposite transitions of the
same output (tPHL–tPLH)
–
0.2
–
ns
tSK(t)
Package Skew: Skew between outputs of different
VID = 100 mV
packages at the same power supply voltage, temperature and package type. Same input signal level and
output load.
–
–
1
ns
Document #: 38-07057 Rev. *B
Page 4 of 8
ComLink™ Series
CY2DL814
Table 12.High Frequency Parametrics
Min.
Typ.
Max.
Unit
Fmax
Parameter
Maximum frequency
VDD = 3.3V
Description
50% duty cycle tW(50–50)
Standard Load Circuit.
Conditions
–
–
400
MHz
Fmax(20)
Maximum frequency
VDD = 3.3V
20% duty cycle tW(50–50)
LVPECL Input
VIN = VIH(Max.)/VIL(Min.)
VOUT = VOH(Min.)/VOL (Max.) (Limit)
–
–
200
MHz
TW
Minimum pulse
VDD = 3.3V
LVPECL Input
VIN = VIH(Max.)/VIL(Min.) F= 100 MHz
VOUT = VOH(Min.)/VOL(Max.)(Limit)
1
–
–
ns
A
TPA
Pulse
50
10pF
Generator
TPC
B
50
TPB
Standard Termination
V1A
V1B
1.4 V
1.2 V CM
0V Differential
1.0 V
V0Y
1.4 V
1.2 V CM
0V Differential
1.0 V
V0Z
TPLH
TPHL
80%
0V Differential
V0Y - V0Z
20%
tR
tF
Figure 1. Differential Receiver to Driver Propagation Delay and Driver Transition Time[3, 4, 5, 6]
A
TPA
50
Pulse
Generator
TPC
B
50
TPB
VOC
Standard Termination
VI(A)
2.0V
VI(B)
1.6V
VOD
Next Device
Figure 2. Test Circuit and Voltage Definitions for the Driver Common-mode Output Voltage[3, 4, 5, 6]
Notes:
3. All input pulses are supplied by a frequency generator with the following characteristics: tR and tF ≤ 1 ns; pulse rerate = 50 Mpps; pulse width = 10 ± 0.2 ns.
4. RL= 50 ohm ± 1% Zline = 50 ohm 6”.
5. CL includes instrumentation and fixture capacitance within 6 mm of the UT.
6. TPA and B are used for prop delay and Rise/Fall measurements. TPC is used for VOC measurements only and is otherwise connected to VDD- 2.
Document #: 38-07057 Rev. *B
Page 5 of 8
ComLink™ Series
CY2DL814
A
TPA
Pulse
Generator
50
10pF
TPC
B
50
TPB
Standard Termination
VI(A)
1.4V
VI(B)
1.0V
100%
80%
0.0V
20%
0%
tF
tR
Figure 3. Test Circuit and Voltage Definitions for the Differential Output Signal[3, 4, 5, 6]
IN P U T A
LV P E C L &
LV D S
LVCM OS / LVTTL
IN P U T B
GND
In C o n fig
In C o n fig
1
0
L V T T L /L V C M O S
Figure 4. LVCMOS/LVTTL Single-ended Input Value[7]
L V D S /L V P E C L
Figure 5. LVPECL or LVDS Differential Input Value[8]
Ordering Information
Part Number
Package Type
Product Flow
CY2DL814ZI
16-pin TSSOP
Industrial, –40°C to 85°C
CY2DL814ZIT
16-pin TSSOP–Tape and Reel
Industrial, –40°C to 85°C
CY2DL814SI
16-pin SOIC
Industrial, –40°C to 85°C
CY2DL814SIT
16-pin SOIC–Tape and Reel
Industrial, –40°C to 85°C
CY2DL814ZC
16-pin TSSOP
Commercial, 0°C to 70 °C
CY2DL814ZCT
16-pin TSSOP–Tape and Reel
Commercial, 0°C to 70 °C
CY2DL814SC
16-pin SOIC
Commercial, 0°C to 70 °C
CY2DL814SCT
16-pin SOIC–Tape and Reel
Commercial, 0°C to 70 °C
CY2DL814ZXI
16-pin TSSOP
Industrial, –40°C to 85°C
CY2DL814ZXIT
16-pin TSSOP–Tape and Reel
Industrial, –40°C to 85°C
Lead-free
CY2DL814SXI
16-pin SOIC
Industrial, –40°C to 85°C
CY2DL814SXIT
16-pin SOIC–Tape and Reel
Industrial, –40°C to 85°C
CY2DL814ZXC
16-pin TSSOP
Commercial, 0°C to 70 °C
CY2DL814ZXCT
16-pin TSSOP–Tape and Reel
Commercial, 0°C to 70 °C
CY2DL814SXC
16-pin SOIC
Commercial, 0°C to 70 °C
CY2DL814SXCT
16-pin SOIC–Tape and Reel
Commercial, 0°C to 70 °C
Notes:
7. LVCMOS/LVTTL single ended input value. Ground either input: when on the B side then non-inversion takes place. If A side is grounded, the signal becomes
the complement of the input on B side. See Table 4.
8. LVPECL or LVDS differential input value.
Document #: 38-07057 Rev. *B
Page 6 of 8
ComLink™ Series
CY2DL814
Package Drawing and Dimensions
16 Lead (150 Mil) SOIC
16-Lead (150-Mil) SOIC S16.15
PIN 1 ID
8
1
DIMENSIONS IN INCHES[MM] MIN.
MAX.
REFERENCE JEDEC MS-012
PACKAGE WEIGHT 0.15gms
0.150[3.810]
0.157[3.987]
0.230[5.842]
0.244[6.197]
PART #
S16.15 STANDARD PKG.
9
SZ16.15 LEAD FREE PKG.
16
0.386[9.804]
0.393[9.982]
0.010[0.254]
0.016[0.406]
SEATING PLANE
X 45°
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.016[0.406]
0.035[0.889]
0°~8°
0.0138[0.350]
0.0192[0.487]
0.004[0.102]
0.0098[0.249]
51-85068-*B
16-lead TSSOP 4.40 mm Body Z16.173
PIN 1 ID
DIMENSIONS IN MM[INCHES] MIN.
MAX.
1
REFERENCE JEDEC MO-153
6.25[0.246]
6.50[0.256]
PACKAGE WEIGHT 0.05 gms
PART #
4.30[0.169]
4.50[0.177]
Z16.173
STANDARD PKG.
ZZ16.173 LEAD FREE PKG.
16
0.65[0.025]
BSC.
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
0.25[0.010]
BSC
GAUGE
PLANE
0°-8°
0.076[0.003]
0.85[0.033]
0.95[0.037]
4.90[0.193]
5.10[0.200]
0.05[0.002]
0.15[0.006]
SEATING
PLANE
0.50[0.020]
0.70[0.027]
0.09[[0.003]
0.20[0.008]
51-85091-*A
ComLink is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document
are the trademarks of their respective holders.
Document #: 38-07057 Rev. *B
Page 7 of 8
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
ComLink™ Series
CY2DL814
Document Title: ComLink™ Series CY2DL814 1:4 Clock Fanout Buffer
Document Number: 38-07057
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
115362
07/10/02
EHX
Description of Change
New Data Sheet
*A
122744
12/14/02
RBI
Added power up requirements to maximum ratings information.
*B
384077
See ECN
RGL
Added Lead-free devices
Added typical values
Document #: 38-07057 Rev. *B
Page 8 of 8
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