NJRC NJW1109D Headphone amplifier with electronic volume Datasheet

NJW1109
Headphone Amplifier with Electronic Volume
■ PACKAGE OUTLINE
■ GENERAL DESCRIPTION
The NJW1109 is a headphone amplifier with electronic volume. It
includes widely gain adjustable volume, +20 to –80 dB, and mute
2
function. These are controlled by I C bus. The NJW1109 is
suitable for headphone output on TV set.
NJW1109D
■ FEATURES
● Operating Voltage
● Electronic Volume
2
● I C Bus Interface
● Bi-CMOS Technology
● Package Outline
NJW1109M
NJW1109V
7.5 to 10 V
+20dB to -80dB / 0.5dB step, Mute
DIP14, DMP14, SSOP14
■ BLOCK DIAGRAM
CAPa
SDA SCL
2
IC
Interface
ADR
IN a
VOL
OUTa
IN b
VOL
OUTb
Bias
CAPb
Vref
V+ GND
■ PIN FUNCTION
1
7
14
8
No.
1
SYMBOL
No.
8
SYMBOL
2
OUTb
Bch Output
9
Vref
Reference voltage stabilized
capacitor connect terminal
3
N.C.
No Connect
10
INa
Ach Input
4
CAPb
11
CAPa
5
INb
Balance control click noise
absorbing capacitor connect
terminal
Bch Input
12
N.C.
Volume control click noise
absorbing capacitor connect
terminal
No Connect
6
ADR
I2C Bus Slave Address
Select
13
OUTa
Ach Output
7
SDA
I2C Bus Data Input
14
GND
Ground
V+
FUNCTION
Power Supply
SCL
FUNCTION
I2C Bus Clock Input
–1–
NJW1109
■ ABSOLUTE MAXIMUM RATING (Ta=25°°C)
PARAMETER
SYMBOL
+
Supply Voltage
V
Power Dissipation
PD
RATING
UNIT
V
mW
°C
Operating Temperature Range
Topr
12
500 (DIP14)
500* (DMP14)
440* (SSOP14)
-20 to +75
Storage Temperature Range
Tstg
-40 to +125
°C
*(Note) EIA/JEDEC STANDARD Test board(76.2 x 114.3 x 1.6mm, 2layers, FR-4)mounting
■ ELECTRICAL CHARACTERISTICS
(V =9V, VIN=-20dBV, f=1kHz, RL=100Ω, VOL = 0dB , Ta=25°C)
●POWER SUPPLY
+
PARAMETER
SYMBOL
TEST CONDITION
+
Operating Voltage
V
Operating Current
ICC
Reference Voltage
VREF
No Signal
MIN.
TYP.
MAX.
UNIT
7.5
9
10
V
-
5
8
mA
4.0
4.5
5.0
V
MIN.
TYP.
MAX.
UNIT
18
20
22
dB
●AMPLIFIER
PARAMETER
SYMBOL
TEST CONDITION
Volume Maximum Gain
GVMAX
VOL = +20dB setting
Volume Minimum Gain
GVMIN
VOL = -80dB setting
Voltage Gain Channel Balance
∆Gv
VOL = 0dB setting
Maximum Input Voltage
VIM
Output Power
PO
Total Harmonic Distortion
Channel Separation
THD
CS
VOL = -10dB setting
THD=3%
VOL = 10dB, THD=10%
VOL = 0dB setting
Rg=600Ω, Vin = 0dBV
-80
-1.5
8.9
(2.8)
70
0
9.5
(3.0)
100
1.5
-
dB
dBV
(Vrms)
mW
-
0.1
1
%
70
80
-
dB
-90
-85
(56)
-95
(18)
-
dB
dBV
-
-100
-95
(18)
-105
(5.6)
70
MIN.
TYP.
MAX.
UNIT
+
Mute Level
Mute
VOL = Mute, Vin = 0dBV
-
Output Noise Voltage 1
VNO1
Rg=0Ω, A-Weighted
-
Output Noise Voltage 2
Power Supply Ripple Rejection
VNO2
PSRR
VOL = Mute
Rg=0Ω, A-Weighted
Vripple=-20dBV, Rg=0Ω
-
-
(µVrms)
dBV
(µVrms)
dB
●CONTROL
PARAMETER
SYMBOL
TEST CONDITION
High Level Input Voltage
VADRH
High : Slave Address 84H
V /2
-
-
V
Low Level Input Voltage
VADRL
Low : Slave Address 80H
-
-
1.0
V
–2–
NJW1109
2
■ I C BUS CHARACTERISTICS
(SDA, SCL)
2
I C BUS Load Conditions: Pull up resistance 4kΩ (Connected to +5V), Load capacitance 200pF (Connected to GND)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Low Level Input Voltage
VIL
0.0
-
1.5
V
High Level Input Voltage
VIH
2.5
-
5.0
V
Hysteresis of Schmitt trigger inputs
Vhys
0.25
-
-
V
LOW level output voltage (3mA at SDA pin)
VOL
0
-
0.4
V
Output fall time from VIHmin to VILmax with
a bus capacitance from 10pF to 400pF
tof
20+0.1Cb
-
250
ns
Pulse width of spikes which must be suppressed by the input filter
tSP
0
-
50
ns
Input current each I/O pin with an input voltage between 0.1VDD
and 0.9VDDmax
Ii
-10
-
10
µA
Capacitance for each I/O pin
Ci
-
-
10
pF
fSCL
-
-
400
kHz
tHD:STA
0.6
-
-
µs
LOW period of the SCL clock
tLOW
1.3
-
-
µs
HIGH period of the SCL clock
tHIGH
0.6
-
-
µs
Set-up time for a repeated START condition
tSU:STA
0.6
-
-
µs
Data hold time
tHD:DAT
0
-
0.9
µs
Data set-up time
tSU:DAT
100
-
-
ns
Rise time of both SDA and SCL signals
tr
-
-
300
ns
Fall time of both SDA and SCL signals
tf
-
-
300
ns
tSU:STO
0.6
-
-
µs
Bus free time between a STOP and START condition
tBUF
1.3
-
-
µs
Capacitive load for each bus line
Cb
-
-
400
pF
Noise margin at the LOW level
VnL
0.5
-
-
V
Noise margin at the HIGH level
VnH
1
-
-
V
SCL clock frequency
Hold time (repeated) START condition.
Set-up time for STOP condition
Cb ; total capacitance of one bus line in pF.
SDA
tf
tr
tHD:STA
tf
tSU:DAT
tSP
tBUF
tr
SCL
tHD:STA
tSU:STA
S
tLOW
tHD:DAT
tHIGH
tSU:STO
Sr
P
S
–3–
NJW1109
■TERMINAL DESCRIPTION
No.
SYMBOL
FUNCTION
5
INb
Bch Input
10
INa
Ach Input
2
OUTb
Bch Output
13
OUTa
Ach Output
EQUIVALENT CIRCUIT
VOLTAGE
17k
V+/2
V+/2
12k
4
CAPb
Balance control click noise
absorbing capacitor connect
terminal
11
CAPa
Volume control click noise
absorbing capacitor connect
terminal
–4–
8k
3.8V
8k
3.1V
NJW1109
■TERMINAL DESCRIPTION
No.
SYMBOL
FUNCTION
EQUIVALENT CIRCUIT
VOLTAGE
4k
2
6
ADR
I C Bus Slave Address
Select
-
12k
4k
2
7
SDA
I C Bus Data Input
8
SCL
I C Bus Clock Input
-
2
12k
200k
9
Vref
1.3k
Reference voltage stabilized
capacitor connect terminal
V+/2
200k
1
V+
Power Supply
-
-
14
GND
Ground
-
-
–5–
NJW1109
■ TEST CIRCUIT
TEST CIRCUIT
1 (GVMAX, GVMIN, ∆Gv, VIM, PO, THD, Mute)
Input B
Output B
100Ω
VADRL VADRH
BPF:400Hz to 30KHz
100µF
0.47µF
V+
1µF
7
6
5
4
3
2
1
SDA
ADR
INb
CAPb
NC
OUTb
V+
OUTa GND
10µF
VOL
2
I C Bus
Interface
VOL
Bias
SCL
Vref
INa
CAPa
NC
8
9
10
11
12
10µF
13
14
100µF
0.47µF
Output A
1µF
100 Ω
Input A
–6–
BPF:400Hz to 30KHz
NJW1109
TEST CIRCUIT
2 (Icc, VREF, VNO1,VNO2)
Input B
Output B
100Ω
VADRL VADRH
A-Weighted
100µF
0.47µF
V+
1µF
[Icc]
7
6
5
4
3
2
1
SDA
ADR
INb
CAPb
NC
OUTb
V+
OUTa GND
10µF
VOL
2
I C Bus
Interface
VOL
Bias
SCL
Vref
INa
CAPa
NC
8
9
10
11
12
[VREF]
13
14
100µF
10µF
0.47µF
Output A
1µF
100 Ω
Input A
A-Weighted
–7–
NJW1109
TEST CIRCUIT
3 (CS)
Input B
Output B
Rg=600 Ω
VADRL VADRH
100 Ω
BPF:400Hz to 30KHz
100µF
1µF
V+
0.47µF
7
6
5
4
3
2
1
SDA
ADR
INb
CAPb
NC
OUTb
V+
OUTa GND
10µF
VOL
Rg=600 Ω
2
I C Bus
Interface
VOL
Bias
SCL
Vref
INa
CAPa
NC
8
9
10
11
12
0.47µF
13
14
100µF
10µF
Output A
1µF
BPF:400Hz to 30KHz
Rg=600 Ω
–8–
Input A
100 Ω
NJW1109
TEST CIRCUIT
4 (PSRR)
Input B
VADRL VADRH
Output B
100 Ω
Rg=0 Ω
BPF:400Hz to 30KHz
100µF
1µF
0.47µF
7
6
5
4
3
2
1
SDA
ADR
INb
CAPb
NC
OUTb
V+
OUTa GND
10µF
V+
VOL
2
I C Bus
Interface
VOL
Bias
SCL
Vref
INa
CAPa
NC
8
9
10
11
12
0.47µF
10µF
13
14
100µF
Output A
Rg=0 Ω
1µF
100 Ω
BPF:400Hz to 30KHz
Input A
–9–
NJW1109
■ APPLICATION CIRCUIT
Input B
30Ω
30Ω
Output B
100µF
0.47µF
1µF
V+
7
6
5
4
3
2
1
SDA
ADR
INb
CAPb
NC
OUTb
V+
OUTa GND
10µF
VOL
2
I C Bus
Interface
VOL
Bias
SCL
Vref
INa
CAPa
NC
8
9
10
11
12
10µF
13
14
100µF
0.47µF
30 Ω
30 Ω
Output A
1µF
Input A
Mute
Mute
– 10 –
NJW1109
2
■ DEFINITION OF I C REGISTER
2
● I C BUS FORMAT
MSB
S
LSB
Slave Address
1bit
8bit
MSB
LSB
A
Select Address
1bit
8bit
MSB
A
1bit
LSB
Data
A
P
8bit
1bit 1bit
S: Starting Term
A: Acknowledge Bit
P: Ending Term
● SLAVE ADDRESS
MSB
LSB
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
80H (ADR = Low)
84H (ADR = High)
● SELECT ADDRESS
The auto-increment function cycles the select address as follows.
00H→01H→00H
Select
Address
BIT
D7
D6
D5
D4
00H
01H
D3
D2
D1
D0
VOL
CHS
BAL
Don’t Care
!CONTROL REGISTER DEFAULT VALUE
Control register default value is all “0”.
Select
Address
BIT
D7
D6
D5
D4
D3
D2
D1
D0
00H
0
0
0
0
0
0
0
0
01H
0
0
0
0
0
0
0
0
D5
D4
D3
D2
D1
D0
D2
D1
D0
!CONTROL COMMAND TABLE
a) Master Volume
Select
Address
BIT
D7
D6
00H
VOL
•VOL : Master Volume
Attenuation level : +20 to –80dB(0.5dB/step), MUTE
b) Balance
BIT
Select
Address
D7
01H
CHS
D6
D5
D4
BAL
D3
Don’t Care
•CHS : Balance channel select
“0” : Ach “Bch is attenuated”
“1” : Bch “Ach is attenuated”
•BAL : Ach and Bch Ach and Bch Balance
Balance Level : 0 to –30dB (1dB/Step) , MUTE
– 11 –
NJW1109
!CONTROL COMMAND TABLE
a) Master Volume (Select Address: 00H)
Volume level : +20 to –80dB(0.5dB/step), MUTE
VOL
Gain(dB)
HEX
D7
D6
D5
D4
D3
D2
D1
D0
20
FF
1
1
1
1
1
1
1
1
19.5
FE
1
1
1
1
1
1
1
0
19
FD
1
1
1
1
1
1
0
1
18.5
FC
1
1
1
1
1
1
0
0
18
FB
1
1
1
1
1
0
1
1
17.5
FA
1
1
1
1
1
0
1
0
17
F9
1
1
1
1
1
0
0
1
16.5
F8
1
1
1
1
1
0
0
0
16
F7
1
1
1
1
0
1
1
1
15.5
F6
1
1
1
1
0
1
1
0
15
F5
1
1
1
1
0
1
0
1
14.5
F4
1
1
1
1
0
1
0
0
14
F3
1
1
1
1
0
0
1
1
13.5
F2
1
1
1
1
0
0
1
0
13
F1
1
1
1
1
0
0
0
1
12.5
F0
1
1
1
1
0
0
0
0
12
EF
1
1
1
0
1
1
1
1
11.5
EE
1
1
1
0
1
1
1
0
11
ED
1
1
1
0
1
1
0
1
10.5
EC
1
1
1
0
1
1
0
0
10
EB
1
1
1
0
1
0
1
1
9.5
EA
1
1
1
0
1
0
1
0
9
E9
1
1
1
0
1
0
0
1
8.5
E8
1
1
1
0
1
0
0
0
8
E7
1
1
1
0
0
1
1
1
7.5
E6
1
1
1
0
0
1
1
0
7
E5
1
1
1
0
0
1
0
1
6.5
E4
1
1
1
0
0
1
0
0
6
E3
1
1
1
0
0
0
1
1
5.5
E2
1
1
1
0
0
0
1
0
5
E1
1
1
1
0
0
0
0
1
4.5
E0
1
1
1
0
0
0
0
0
4
DF
1
1
0
1
1
1
1
1
3.5
DE
1
1
0
1
1
1
1
0
3
DD
1
1
0
1
1
1
0
1
・・・
・・・
・・・
・・・
・・・
・・・
・・・
・・・
・・・
・・・
-79.5
38
0
0
1
1
1
0
0
0
-80
37
0
0
1
1
0
1
1
1
・・・
・・・
・・・
・・・
・・・
・・・
・・・
・・・
・・・
・・・
Mute
00
0
0
0
0
0
0
0
0
– 12 –
NJW1109
b) Balance (Select Address: 01H)
Balance level : 0 to –30dB(1dB/step), MUTE
Channel Setting (CHS)
D7
Attenuated Bch Gain
Attenuated Ach Gain
0
1
D6
D5
BAL
D4
D3
D2
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
-11
-12
-13
-14
-15
-16
-17
-18
-19
-20
-21
-22
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
-23
-24
1
1
0
1
1
0
1
0
1
0
-25
-26
-27
-28
-29
-30
MUTE
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Gain(dB)
– 13 –
NJW1109
[CAUTION]
The specifications on this data book are only
given for information, without any guarantee
as regards either mistakes or omissions. The
application circuits in this data book are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
– 14 –
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