LINER LTC2615IGN Octal 16-/14-/12-bit rail-to-rail dacs in 16-lead ssop Datasheet

LTC2605/LTC2615/LTC2625
Octal 16-/14-/12-Bit
Rail-to-Rail DACs in 16-Lead SSOP
DESCRIPTIO
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FEATURES
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The LTC®2605/LTC2615/LTC2625 are octal 16-, 14and 12-bit, 2.7V to 5.5V rail-to-rail voltage-output DACs in
16-lead narrow SSOP packages. They have built-in
high performance output buffers and are guaranteed
monotonic.
Smallest Pin-Compatible Octal DACs:
LTC2605: 16 Bits
LTC2615: 14 Bits
LTC2625: 12 Bits
Guaranteed Monotonic Over Temperature
400kHz I2C Interface
Wide 2.7V to 5.5V Supply Range
Low Power Operation: 250µA per DAC at 3V
Individual Channel Power-Down to 1µA, Max
Ultralow Crosstalk Between DACs (<10µV)
High Rail-to-Rail Output Drive (±15mA, Min)
Double-Buffered Digital Inputs
27 Selectable Addresses
LTC2605/LTC2615/LTC2625: Power-On Reset to
Zero Scale
LTC2605-1/LTC2615-1/LTC2625-1: Power-On Reset
to Midscale
Tiny 16-Lead Narrow SSOP Package
These parts establish new board-density benchmarks
for 16- and 14-bit DACs and advance performance
standards for output drive, crosstalk and load regulation
in single-supply, voltage-output multiples.
The parts use the 2-wire I2C compatible serial interface.
The LTC2605/LTC2615/LTC2625 operate in both the
standard mode (maximum clock rate of 100kHz) and the
fast mode (maximum clock rate of 400kHz).
The LTC2605/LTC2615/LTC2625 incorporate a power-on
reset circuit. During power-up, the voltage outputs rise
less than 10mV above zero scale; and after power-up, they
stay at zero scale until a valid write and update take place.
The power-on reset circuit resets the LTC2605-1/
LTC2615-1/LTC2625-1 to midscale. The voltage output
stays at midscale until a valid write and update
takes place.
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APPLICATIO S
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Mobile Communications
Process Control and Industrial Automation
Instrumentation
Automatic Test Equipment
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
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BLOCK DIAGRA
16 VCC
REGISTER
REGISTER
REGISTER
6
DAC F
DAC D
REGISTER
REF
REGISTER
5
REGISTER
VOUT D
DAC C
REGISTER
15 VOUT H
14 VOUT G
Differential Nonlinearity (LTC2605)
1.0
VCC = 5V
VREF = 4.096V
0.8
0.6
0.4
DAC E
13 VOUT F
12 VOUT E
DNL (LSB)
4
DAC G
REGISTER
VOUT C
REGISTER
DAC B
REGISTER
3
REGISTER
VOUT B
DAC H
REGISTER
DAC A
REGISTER
2
REGISTER
VOUT A
REGISTER
1
REGISTER
GND
0.2
0
–0.2
–0.4
–0.6
11
CA0
10
CA1
9
SDA
32-BIT SHIFT REGISTER
CA2
7
SCL
8
–0.8
–1.0
0
16384
32768
CODE
49152
65535
2605 G02
2-WIRE INTERFACE
2605/15/25 BD
2605f
1
LTC2605/LTC2615/LTC2625
W W
W
AXI U
U
ABSOLUTE
RATI GS
(Note 1)
Any Pin to GND ........................................... – 0.3V to 6V
Any Pin to VCC .............................................– 6V to 0.3V
Maximum Junction Temperature .......................... 125°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
Operating Temperature Range
LTC2605C/LTC2615C/LTC2625C ............. 0°C to 70°C
LTC2605C-1/LTC2615C-1/LTC2625C-1 ... 0°C to 70°C
LTC2605I/LTC2615I/LTC2625I ............ – 40°C to 85°C
LTC2605I-1/LTC2615I-1/LTC2625I-1 .. – 40°C to 85°C
U
W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
GND
1
16 VCC
VOUT A
2
15 VOUT H
VOUT B
3
14 VOUT G
VOUT C
4
13 VOUT F
VOUT D
5
12 VOUT E
REF
6
11 CA0
CA2
7
10 CA1
SCL
8
9
ORDER PART NUMBER
GN PART MARKING
LTC2605CGN
LTC2605CGN-1
LTC2605IGN
LTC2605IGN-1
LTC2615CGN
LTC2615CGN-1
LTC2615IGN
LTC2615IGN-1
LTC2625CGN
LTC2625CGN-1
LTC2625IGN
LTC2625IGN-1
2605
26051
2605I
26O5I1
2615
26151
2615I
2615I1
2625
26251
2625I
2625I1
SDA
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 150°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded,
unless otherwise noted.
SYMBOL
PARAMETER
LTC2625/-1
MIN TYP MAX
CONDITIONS
LTC2615/-1
MIN TYP MAX
LTC2605/-1
MIN TYP MAX
UNITS
DC Performance
●
12
14
16
Bits
(Note 2)
●
12
14
16
Bits
DNL
Differential Nonlinearity (Note 2)
●
INL
Integral Nonlinearity
(Note 2)
●
Load Regulation
VREF = VCC = 5V, Midscale
IOUT = 0mA to 15mA Sourcing
IOUT = 0mA to 15mA Sinking
●
●
VREF = VCC = 2.7V, Midscale
IOUT = 0mA to 7.5mA Sourcing
IOUT = 0mA to 7.5mA Sinking
Resolution
Monotonicity
±0.5
±1
LSB
±4
±16
±18
±64
LSB
0.02 0.125
0.03 0.125
0.07
0.10
0.5
0.5
0.3
0.4
2
2
LSB/mA
LSB/mA
●
●
0.04
0.07
0.25
0.25
0.15
0.20
1
1
0.6
0.8
4
4
LSB/mA
LSB/mA
±1
±4
±1
ZSE
Zero-Scale Error
Code = 0
●
1.7
9
1.7
9
1.7
9
mV
VOS
Offset Error
(Note 4)
●
±1
±9
±1
±9
±1
±9
mV
±5
VOS Temperature
Coefficient
GE
Gain Error
Gain Temperature
Coefficient
●
±0.1
±8
±5
±0.7
±0.1
±8
±5
±0.7
±0.1
±8
µV/°C
±0.7
%FSR
ppm/°C
2605f
2
LTC2605/LTC2615/LTC2625
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded,
unless otherwise noted. (Note 9)
SYMBOL
PARAMETER
CONDITIONS
PSR
Power Supply Rejection
VCC ±10%
–80
ROUT
DC Output Impedance
VREF = VCC = 5V, Midscale; –15mA ≤ IOUT ≤ 15mA
●
VREF = VCC = 2.7V, Midscale; –7.5mA ≤ IOUT ≤ 7.5mA ●
0.02
0.03
DC Crosstalk (Note 10)
Due to Full Scale Output Change (Note 11)
Due to Load Current Change
Due to Powering Down (per Channel)
±10
±3.5
±7
Short-Circuit Output Current
VCC = 5.5V, VREF = 5.5V
Code: Zero Scale; Forcing Output to VCC
Code: Full Scale; Forcing Output to GND
●
●
15
15
34
34
60
60
mA
mA
VCC = 2.7V, VREF = 2.7V
Code: Zero Scale; Forcing Output to VCC
Code: Full Scale; Forcing Output to GND
●
●
7.5
7.5
20
27
50
50
mA
mA
ISC
MIN
TYP
MAX
UNITS
dB
0.15
0.15
Ω
Ω
µV
µV/mA
µV
Reference Input
Input Voltage Range
Resistance
Normal Mode
●
0
●
11
Capacitance
IREF
16
VCC
V
20
kΩ
1
µA
5.5
V
4.0
3.2
1.0
1.0
mA
mA
µA
µA
90
Reference Current, Power Down Mode DAC Powered Down
●
0.001
pF
Power Supply
VCC
Positive Supply Voltage
For Specified Performance
●
ICC
Supply Current
VCC = 5V (Note 3)
VCC = 3V (Note 3)
DAC Powered Down (Note 3) VCC = 5V
DAC Powered Down (Note 3) VCC = 3V
●
●
●
●
2.7
2.50
2.00
0.38
0.16
Digital I/O (Note 9)
VIL
Low Level Input Voltage
(SDA and SCL)
●
VIH
High Level Input Voltage
(SDA and SCL)
●
VIL(CA)
Low Level Input Voltage (CA0 to CA2)
See Test Circuit 1
●
VIH(CA)
High Level Input Voltage (CA0 to CA2)
See Test Circuit 1
●
RINH
Resistance from CAn (n = 0,1,2)
to VCC to Set CAn = VCC
See Test Circuit 2
●
10
kΩ
RINL
Resistance from CAn (n = 0,1,2)
to GND to Set CAn = GND
See Test Circuit 2
●
10
kΩ
RINF
Resistance from CAn (n = 0,1,2)
to VCC or GND to Set CAn = FLOAT
See Test Circuit 2
●
2
VOL
Low Level Output Voltage
Sink Current = 3mA
●
0
0.4
V
tOF
Output Fall Time
VO = VIH(MIN) to VO = VIL(MAX),
CB = 10pF to 400pF (Note 7)
● 20 + 0.1CB
250
ns
tSP
Pulse Width of Spikes Surpassed
by Input Filter
●
50
ns
IIN
Input Leakage
0.1VCC ≤ VIN ≤ 0.9VCC
●
1
µA
CIN
I/O Pin Capacitance
(Note 12)
●
10
pF
CB
Capacitance Load for Each Bus Line
●
400
pF
CCAn
External Capacitive Load on
Address Pins CA0, CA1 and CA2
●
10
pF
0.3VCC
0.7VCC
V
0.15VCC
0.85VCC
0
V
V
V
MΩ
2605f
3
LTC2605/LTC2615/LTC2625
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded,
unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
LTC2625/-1
MIN TYP MAX
LTC2615/-1
MIN TYP MAX
LTC2605/-1
MIN TYP MAX
UNITS
AC Performance
tS
Settling Time (Note 5)
±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
7
7
9
7
9
10
µs
µs
µs
Settling Time for 1LSB Step
(Note 6)
±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
2.7
2.7
4.8
2.7
4.8
5.2
µs
µs
µs
Voltage Output Slew Rate
0.80
0.80
0.80
V/µs
Capacitive Load Driving
1000
1000
1000
pF
Glitch Impulse
At Midscale Transition
Multiplying Bandwidth
en
12
12
12
nV • s
180
180
180
kHz
Output Voltage Noise Density
At f = 1kHz
At f = 10kHz
120
100
120
100
120
100
nV/√Hz
nV/√Hz
Output Voltage Noise
0.1Hz to 10Hz
15
15
15
µVP-P
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TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (See Figure 1) (Notes 8, 9)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
400
kHz
VCC = 2.7V to 5.5V
fSCL
SCL Clock Frequency
●
0
tHD(STA)
Hold Time (Repeated) Start Condition
●
0.6
µs
tLOW
Low Period of the SCL Clock Pin
●
1.3
µs
tHIGH
High Period of the SCL Clock Pin
●
0.6
µs
tSU(STA)
Set-Up Time for a Repeated Start Program
●
0.6
µs
tHD(DAT)
Data Hold Time
●
0
tSU(DAT)
Data Set-Up Time
●
100
tr
Rise Time of Both SDA and SCL Signals
(Note 7)
●
20 + 0.1CB
300
ns
tf
Fall Time of Both SDA and SCL Signals
(Note 7)
●
20 + 0.1CB
300
ns
tSU(STO)
Set-Up Time for Stop Condition
●
0.6
µs
tBUF
Bus Free Time Between a Stop and Start Condition
●
1.3
µs
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: Linearity and monotonicity are defined from code kL to code
2N – 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF),
rounded to the nearest whole code. For VREF = 4.096V and N = 16,
kL = 256 and linearity is defined from code 256 to code 65,535.
Note 3: SDA, SCL at 0V or VCC, CA0, CA1 and CA2 floating.
Note 4: Inferred from measurement at code 256 (LTC2605/LTC2605-1),
code 64 (LTC2615/LTC2615-1) or code 16 (LTC2625/LTC2625-1) and
at full scale.
Note 5: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4 scale to 3/4 scale
and 3/4 scale to 1/4 scale. Load is 2kΩ in parallel with 200pF to GND.
0.9
µs
ns
Note 6: VCC = 5V, VREF = 4.096V. DAC is stepped ±1LSB between half
scale and half scale – 1. Load is 2kΩ in parallel with 200pF to GND.
Note 7: CB = capacitance of one bus line in pF.
Note 8: All values refer to VIH(MIN) and VIL(MAX) levels.
Note 9: These specifications apply to LTC2605/LTC2605-1, LTC2615/
LTC2615-1 and LTC2625/LTC2625-1.
Note 10: DC Crosstalk is measured with VCC = 5V and VREF = 4096V, with
the measured DAC at midscale, unless otherwise noted.
Note 11: RL = 2kΩ to GND or VCC.
Note 12: Guaranteed by design and not production tested.
2605f
4
LTC2605/LTC2615/LTC2625
ELECTRICAL CHARACTERISTICS
Test Circuit 1
Test Circuit 2
VDD
100Ω
CAn
RINH/RINL/RINF
VIH(CAn)/VIL(CAn)
2605/15/25 EC01
2605/15/25 EC02
GND
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TYPICAL PERFOR A CE CHARACTERISTICS
LTC2605
Differential Nonlinearity (DNL)
Integal Nonlinearity (INL)
32
1.0
VCC = 5V
VREF = 4.096V
24
INL vs Temperature
32
VCC = 5V
VREF = 4.096V
0.8
VCC = 5V
VREF = 4.096V
24
0.6
16
0.4
0
–8
0.2
INL (LSB)
8
DNL (LSB)
INL (LSB)
16
0
–0.2
INL (POS)
8
0
–8
INL (NEG)
–0.4
–16
–0.6
–24
–32
–16
–24
–0.8
0
16384
32768
CODE
49152
–1.0
65535
0
16384
32768
CODE
49152
–10 10
30
50
TEMPERATURE (°C)
70
32
VCC = 5V
VREF = 4.096V
90
2605 G03
INL vs VREF
DNL vs Temperature
0.8
–30
2605 G02
2605 G01
1.0
–32
–50
65535
DNL vs VREF
1.5
VCC = 5.5V
VCC = 5.5V
24
1.0
0.6
16
0
–0.2
0
–8
DNL (NEG)
0.5
INL (POS)
8
DNL (LSB)
DNL (POS)
0.2
INL (LSB)
DNL (LSB)
0.4
INL (NEG)
DNL (POS)
0
DNL (NEG)
–0.5
–0.4
–16
–0.6
–1.0
–50
–1.0
–24
–0.8
–30
–10 10
30
50
TEMPERATURE (°C)
70
90
2605 G04
–32
0
1
2
3
VREF (V)
4
5
2605 G05
–1.5
0
1
2
3
VREF (V)
4
5
2605 G06
2605f
5
LTC2605/LTC2615/LTC2625
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TYPICAL PERFOR A CE CHARACTERISTICS
LTC2605
Settling to ±1LSB
Settling of Full-Scale Step
VOUT
100µV/DIV
VOUT
100µV/DIV
SCL
2V/DIV
12.3µs
9.7µs
9TH CLOCK
OF 3RD DATA
BYTE
9TH CLOCK OF
3RD DATA BYTE
SCR
2V/DIV
2605 G07
2µs/DIV
5µs/DIV
2605 G08
SETTLING TO ±1LSB
VCC = 5V, VREF = 4.096V
CODE 512 TO 65535 STEP
AVERAGE OF 2048 EVENTS
VCC = 5V, VREF = 4.096V
1/4-SCALE TO 3/4-SCALE STEP
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
LTC2615
Integral Nonlinearity (INL)
8
1.0
VCC = 5V
VREF = 4.096V
6
Settling to ±1LSB
Differential Nonlinearity (DNL)
VCC = 5V
VREF = 4.096V
0.8
0.6
4
0.4
DNL (LSB)
INL (LSB)
2
0
–2
VOUT
100µV/DIV
0.2
0
SCL
2V/DIV
–0.2
–0.4
–4
–0.6
–6
–8
0
4096
8192
CODE
12288
16383
8.9µs
2605 G11
2µs/DIV
–0.8
–1.0
9TH CLOCK
OF 3RD DATA
BYTE
0
4096
8192
CODE
12288
2605 G09
VCC = 5V, VREF = 4.096V
1/4-SCALE TO 3/4-SCALE STEP
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
16383
2605 G10
LTC2625
Integral Nonlinearity (INL)
2.0
VCC = 5V
VREF = 4.096V
1.5
Settling to ±1LSB
Differential Nonlinearity (DNL)
1.0
VCC = 5V
VREF = 4.096V
0.8
0.6
1.0
6.8µs
DNL (LSB)
INL (LSB)
0.4
0.5
0
–0.5
VOUT
1mV/DIV
0.2
0
SCL
2V/DIV
–0.2
–0.4
–1.0
–0.6
–1.5
–2.0
2µs/DIV
–0.8
0
1024
2048
CODE
3072
4095
2605 G12
–1.0
9TH CLOCK
OF 3RD DATA
BYTE
0
1024
2048
CODE
3072
4095
2605 G14
VCC = 5V, VREF = 4.096V
1/4-SCALE TO 3/4-SCALE STEP
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
2605 G13
2605f
6
LTC2605/LTC2615/LTC2625
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2605/LTC2615/LTC2625
Current Limiting
CODE = MIDSCALE
0.08
∆VOUT (mV)
0
0.2
0
–0.4
VREF = VCC = 5V
–0.06
VREF = VCC = 5V
–0.2
VREF = VCC = 3V
–0.04
2
0.4
0.02
–0.02
CODE = MIDSCALE
0.6
VREF = VCC = 3V
0.04
Offset Error vs Temperature
3
0.8
VREF = VCC = 5V
0.06
∆VOUT (V)
Load Regulation
1.0
OFFSET ERROR (mV)
0.10
VREF = VCC = 3V
–0.6
–0.10
–40 –30 –20 –10 0
10
IOUT (mA)
20
30
–1.0
–35
40
–25
–15
–5
5
IOUT (mA)
15
25
–3
–50
35
3
90
2
0.2
OFFSET ERROR (mV)
GAIN ERROR (%FSR)
1.0
70
3
0.3
2.5
1.5
–10 10
30
50
TEMPERATURE (°C)
Offset Error vs VCC
0.4
2.0
–30
2605 G17
Gain Error vs Temperature
Zero-Scale Error vs Temperature
ZERO-SCALE ERROR (mV)
–1
2606 G16
2605 G15
0.1
0
–0.1
1
0
–1
–0.2
0.5
–2
–0.3
0
–50
–30
–10 10
30
50
TEMPERATURE (°C)
70
90
–0.4
–50
–30
–10 10
30
50
TEMPERATURE (°C)
70
90
–3
2.5
Gain Error vs VCC
400
0.2
350
0.1
300
ICC (nA)
450
0.3
–0.1
3.5
4
VCC (V)
4.5
5
5.5
2605 G20
Large-Signal Response
ICC Shutdown vs VCC
0.4
0
3
2605 G19
2605 G18
GAIN ERROR (%FSR)
0
–2
–0.8
–0.08
1
VOUT
0.5V/DIV
250
200
VREF = VCC = 5V
1/4-SCALE TO 3/4-SCALE
150
–0.2
100
–0.3
–0.4
2.5
2.5µs/DIV
50
3
3.5
4
VCC (V)
4.5
5
5.5
2605 G21
0
2.5
3
3.5
4
VCC (V)
4.5
5
2605 G23
5.5
2605 G22
2605f
7
LTC2605/LTC2615/LTC2625
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2605/LTC2615/LTC2625
Midscale Glitch Impulse
Headroom at Rails
vs Output Current
Power-On Reset Glitch
5.0
5V SOURCING
4.5
TRANSITION FROM
MS-1 TO MS
4.0
VOUT
10mV/DIV
3.5
9TH CLOCK
OF 3RD DATA
BYTE
SCL
2V/DIV
VOUT (V)
VCC
1V/DIV
TRANSITION FROM
MS TO MS-1
4mV PEAK
VOUT
10mV/DIV
2.5
2.0
1.5
5V SINKING
1.0
2605 G24
2.5µs/DIV
3V SOURCING
3.0
3V SINKING
2605 G25
250µs/DIV
0.5
0
0
1
2
3
4 5 6
IOUT (mA)
7
8
9
10
2605 G26
Multiplying Bandwidth
Supply Current vs Logic Voltage
Power-On Reset to Midscale
2.8
VREF = VCC
0
VCC = 5V
SWEEP SCL
AND SDA 0V
TO VCC AND
VCC TO 0V
2.7
2.6
1V/DIV
VCC
2.4
–6
–9
–12
–15
dB
ICC (mA)
2.5
–3
2.3
–21
2.1
–24
–27
2.0
0
VOUT
3
2
LOGIC VOLTAGE (V)
1
4
–30
5
–33
2605 G28
–36
2605 G27
500µs/DIV
–18
2.2
VCC = 5V
VREF (DC) = 2V
VREF (AC) = 0.2VP-P
CODE = FULL SCALE
1k
1M
10k
100k
FREQUENCY (Hz)
2605 G29
Output Voltage Noise,
0.1Hz to 10Hz
Short-Circuit Output Current vs
VOUT (Sinking)
Short-Circuit Output Current vs
VOUT (Sourcing)
0mA
0
1
2
3
4 5 6
SECONDS
7
8
9
–10mA
30mA
–20mA
20mA
–30mA
10mA
–40mA
10mA/DIV
10mA/DIV
VOUT
10µV/DIV
40mA
0mA
VCC = 5.5V
VREF = 5.6V
CODE = FULL SCALE
VOUT SWEPT VCC TO 0V
VCC = 5.5V
VREF = 5.6V
CODE = 0
VOUT SWEPT 0V TO VCC
10
–50mA
2605 G30
0
1
2
3
4
5
1V/DIV
2605 G31
0 1
1V/DIV
2
3
4
5
2605 G32
2605f
8
LTC2605/LTC2615/LTC2625
U
U
U
PIN FUNCTIONS
GND (Pin 1): Analog Ground.
REF (Pin 6): Reference Voltage Input. 0V ≤ VREF ≤ VCC.
SDA (Pin 9): Serial Data Bidirectional Pin. Data is shifted
into the SDA pin and acknowledged by the SDA pin. This is
a high impedance pin while data is shifted in. It is an opendrain N-channel output during acknowledgment. This pin
requires a pull-up resistor or current source to VCC.
CA2 (Pin 7): Chip Address Bit 2. Tie this pin to VCC, GND
or leave it floating to select an I2C slave address for the part
(Table 2).
CA1 (Pin 10): Chip Address Bit 1. Tie this pin to VCC, GND
or leave it floating to select an I2C slave address for the part
(Table 2).
SCL (Pin 8): Serial Clock Input Pin. Data is shifted into the
SDA pin at the rising edges of the clock. This high
impedance pin requires a pull-up resistor or current
source to VCC.
CA0 (Pin 11): Chip Address Bit 0. Tie this pin to VCC, GND
or leave it floating to select an I2C slave address for the part
(Table 2).
VOUT A to VOUT H (Pins 2-5 and 12-15): DAC Analog
Voltage Output. The output range is 0V to VREF.
VCC (Pin 16): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.
W
BLOCK DIAGRA
DAC
REGISTER
INPUT
REGISTER
INPUT
REGISTER
VOUT B
3
DAC B
DAC
REGISTER
INPUT
REGISTER
INPUT
REGISTER
VOUT C
4
DAC C
DAC
REGISTER
INPUT
REGISTER
INPUT
REGISTER
VOUT D
5
DAC D
INPUT
REGISTER
INPUT
REGISTER
REF
6
DAC
REGISTER
DAC A
DAC H
15 VOUT H
DAC
REGISTER
2
DAC G
14 VOUT G
DAC
REGISTER
VOUT A
DAC F
13 VOUT F
DAC
REGISTER
1
DAC
REGISTER
16 VCC
GND
DAC E
12 VOUT E
11
CA0
10
CA1
9
SDA
32-BIT SHIFT REGISTER
CA2
7
SCL
8
2-WIRE INTERFACE
2605/15/25 BD01
WU
W
TI I G DIAGRA
SDA
tf
tLOW
tSU(DAT)
tr
tf
tHD(STA)
tSP
tr
tBUF
SCL
S
tHD(STA)
tHD(DAT)
tHIGH
tSU(STA)
S
tSU(STO)
P
S
2605/15/25 TD01
ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS
Figure 1
2605f
9
LTC2605/LTC2615/LTC2625
U
OPERATIO
Power-On Reset
The LTC2605/LTC2615/LTC2625 clear the outputs to
zero scale when power is first applied, making system
initialization consistent and repeatable. The LTC2605-1/
LTC2615-1/LTC2625-1 set the voltage outputs to midscale
when power is first applied.
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2605/
LTC2615/LTC2625 contain circuitry to reduce the
power-on glitch: the analog outputs typically rise less
than 10mV above zero scale during power on if the
power supply is ramped to 5V in 1ms or more. In general,
the glitch amplitude decreases as the power supply ramp
time is increased. See Power-On Reset Glitch in the
Typical Performance Characteristics section.
Power Supply Sequencing
The voltage at REF (Pin 6) should be kept within the range
– 0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum
Ratings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at VCC (Pin 16) is in transition.
Transfer Function
The digital-to-analog transfer function is
⎛ k⎞
VOUT(IDEAL) = ⎜ N ⎟ VREF
⎝2 ⎠
Table 1.
COMMAND*
C3 C2 C1 C0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
1
1
1
1
Write to Input Register n
Update (Power Up) DAC Register n
Write to Input Register n, Update (Power Up) All n
Write to and Update (Power Up) n
Power Down n
No Operation
*Address and command codes not shown are reserved and should not be used.
where k is the decimal equivalent of the binary DAC input
code, N is the resolution and VREF is the voltage at REF
(Pin 6).
Serial Digital Interface
The LTC2605/LTC2615/LTC2625 communicate with a
host using the standard 2-wire digital interface. The
Timing Diagram (Figure 1) shows the timing relationship
of the signals on the bus. The two bus lines, SDA and SCL,
must be high when the bus is not in use. External pull-up
resistors or current sources are required on these lines.
The value of these pull-up resistors is dependent on the
power supply and can be obtained from the I2C specifications. For an I2C bus operating in the fast mode, an active
pull-up will be necessary if the bus capacitance is greater
than 200pF.
The LTC2605/LTC2615/LTC2625 are receive-only (slave)
devices. The master can write to the LTC2605/LTC2615/
LTC2625. The LTC2605/LTC2615/LTC2625 do not
respond to a read from the master.
The START (S) and STOP (P) Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communication to a slave device by transmitting a START condition.
A START condition is generated by transitioning SDA from
high to low while SCL is high.
When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while SCL
is high. The bus is then free for communication with
another I2C device.
ADDRESS (n)*
A3 A2 A1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
1
1
A0
0
1
0
1
0
1
0
1
1
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
All DACs
2605f
10
LTC2605/LTC2615/LTC2625
U
OPERATIO
WRITE WORD PROTOCOL FOR LTC2605/LTC2615/LTC2625
S
SLAVE ADDRESS
W
A
1ST DATA BYTE
2ND DATA BYTE
A
A
3RD DATA BYTE
A
P
INPUT WORD
INPUT WORD (LTC2605)
C3
C2
C1 C0
A3
A2
A1
A0
1ST DATA BYTE
D15 D14 D13 D12 D11 D10 D9
D8 D7 D6 D5
2ND DATA BYTE
D4
D3
D2
D1 D0
3RD DATA BYTE
INPUT WORD (LTC2615)
C3
C2
C1 C0
A3
A2
A1
A0
1ST DATA BYTE
D13 D12 D11 D10 D9
D8
D7
D6 D5 D4 D3
2ND DATA BYTE
D2
D1
D0
X
X
X
X
3RD DATA BYTE
INPUT WORD (LTC2625)
C3
C2
C1 C0
A3
A2
1ST DATA BYTE
A1
A0
D11 D10 D9
D8
D7
D6
D5
D4 D3 D2 D1
2ND DATA BYTE
D0
X
X
3RD DATA BYTE
2605/2615/2625 O01
Figure 2
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the latest
byte of information was received. The Acknowledge
related clock pulse is generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge
clock pulse. The slave-receiver must pull down the SDA
during the Acknowledge clock pulse so that it remains a
stable LOW during the HIGH period of this clock pulse. The
LTC2605/LTC2615/LTC2625 respond to a write by a master in this manner. The LTC2605/LTC2615/LTC2625 do
not acknowledge a read (it retains SDA HIGH during the
period of the Acknowledge clock pulse).
Chip Address
The state of CA0, CA1 and CA2 decides the slave address
of the part. The pins CA0, CA1 and CA2 can be each set to
any one of three states: VCC, GND or FLOAT. This results
in 27 selectable addresses for the part. The addresses
corresponding to the states of CA0, CA1 and CA2 and the
global address are shown in Table 2.
In addition to the address selected by the address pins, the
parts also respond to a global address. This address allows
a common write to all LTC2605, LTC2615 and LTC2625
parts to be accomplished with one 3-byte write transaction
on the I2C bus. The global address is a 7-bit hardwired
address and is not selectable by CA0, CA1 and CA2. The
maximum capacitive load allowed on the address pins
(CA0, CA1 and CA2) is 10pF.
Write Word Protocol
The master initiates communication with the LTC2605/
LTC2615/LTC2625 with a START condition and a 7-bit
slave address followed by the Write bit (W) = 0. The
LTC2605/LTC2615/LTC2625 acknowledges by pulling the
SDA pin low at the 9th clock if the 7-bit slave address
matches the address of the parts (set by CA0, CA1 and
CA2) or the global address. The master then transmits
three bytes of data. The LTC2605/LTC2615/LTC2625
acknowledges each byte of data by pulling the SDA line low
at the 9th clock of each data byte transmission. After
receiving three complete bytes of data, the LTC2605/
LTC2615/LTC2625 executes the command specified in
the 24-bit input word.
If more than three data bytes are transmitted after a valid
7-bit slave address, the LTC2605/LTC2615/LTC2625 do
not acknowledge the extra bytes of data (SDA is high
during the 9th clock).
The format of the three data bytes is shown in Figure 2. The first
byte of the input word consists of the 4-bit command and 4bit DAC address. The next two bytes consist of the 16-bit data
word. The 16-bit data word consists of the 16-, 14- or 12-bit
input code, MSB to LSB, followed by 0, 2 or 4 don’t care bits
(LTC2605, LTC2615 and LTC2625 respectively). A typical I2C
write transaction is shown in Figure 3.
2605f
11
LTC2605/LTC2615/LTC2625
U
OPERATIO
The command (C3-C0) and address (A3-A0) assignments
are shown in Table 1. The first four commands in the table
consist of write and update operations. A write operation
loads the 16-bit data word from the 32-bit shift register
into the input register of the selected DAC, n. An update
operation copies the data word from the input register to
the DAC register. Once copied into the DAC register, the
data word becomes the active 16-, 14- or 12-bit input
code, and is converted to an analog voltage at the DAC
output. The update operation also powers up the selected
DAC if it had been in power-down mode. The data path and
registers are shown in the block diagram.
Table 2. Slave Address Map
CA2
CA1
CA0
GND GND GND
GND GND FLOAT
GND GND
VCC
GND FLOAT GND
GND FLOAT FLOAT
GND FLOAT VCC
GND
VCC
GND
GND
VCC FLOAT
GND
VCC
VCC
FLOAT GND GND
FLOAT GND FLOAT
FLOAT GND
VCC
FLOAT FLOAT GND
FLOAT FLOAT FLOAT
FLOAT FLOAT VCC
FLOAT VCC
GND
FLOAT VCC FLOAT
FLOAT VCC
VCC
VCC
GND GND
VCC
GND FLOAT
VCC
GND
VCC
VCC FLOAT GND
VCC FLOAT FLOAT
VCC FLOAT VCC
VCC
VCC
GND
VCC
VCC FLOAT
VCC
VCC
VCC
GLOBAL ADDRESS
SA6
SA5
SA4
SA3
SA2
SA1
SA0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Power Down Mode
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever less
than eight outputs are needed. When in power-down, the
buffer amplifiers and reference inputs are disabled and
draw essentially zero current. The DAC outputs are put into
a high-impedance state, and the output pins are passively
pulled to ground through individual 90k resistors. When
all eight DACs are powered down, the bias generation
circuit is also disabled. Input- and DAC- registers are not
disturbed during power-down.
Any channel or combination of channels can be put into
power-down mode by using command 0100 b in
combination with the appropriate DAC address, (n). The
16-bit data word is ignored. The supply and reference
currents are reduced by approximately 1/8 for each DAC
powered down; the effective resistance at REF (Pin 6) rises
accordingly, becoming a high-impedance input (typically
>1GΩ) when all eight DACs are powered down.
Normal operation can be resumed by executing any command which includes a DAC update, as shown in Table 1.
The selected DAC is powered up as its voltage output
is updated.
There is an initial delay as the DAC powers up before it
begins its usual settling behavior. If less than eight DACs
are in a powered-down state prior to the updated
command, the power-up delay is 5µs. If, on the other
hand, all eight DACs are powered down, then the bias
generation circuit is also disabled and must be restarted.
In this case, the power-up delay is greater: 12µs for
VCC = 5V, 30µs for VCC = 3V.
Voltage Outputs
Each of the eight rail-to-rail amplifiers contained in these
parts has guaranteed load regulation when sourcing or
sinking up to 15mA at 5V (7.5mA at 3V).
Load regulation is a measure of the amplifier’s ability
to maintain the rated voltage accuracy over a wide range
of load conditions. The measured change in output voltage
per milliampere of forced load current change is
expressed in LSB/mA.
2605f
12
LTC2605/LTC2615/LTC2625
U
OPERATIO
DC output impedance is equivalent to load regulation and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The amplifier’s DC output
impedance is 0.020Ω when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by the
30Ω typical channel resistance of the output devices;
e.g., when sinking 1mA, the minimum output voltage =
30Ω • 1mA = 30mV. See the graph Headroom at Rails vs
Output Current in the Typical Performance Characteristics
section.
The amplifiers are stable driving capacitive loads of up
to 1000pF.
Board Layout
The excellent load regulation and DC crosstalk performance of these devices is achieved in part by keeping
“signal” and “power” grounds separated internally and by
reducing shared internal resistance to just 0.005Ω.
The GND pin functions both as the node to which the
reference and output voltages are referred and as a return
path for power currents in the device. Because of this,
careful thought should be given to the grounding scheme
and board layout in order to ensure rated performance.
The PC board should have separate areas for the analog
and digital sections of the circuit. This keeps digital signals
away from sensitive analog signals and facilitates the use
of separate digital and analog ground planes which have
minimal capacitive and resistive interaction with each other.
Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the device’s ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shield it from noise. Analog ground should be a continuous and uninterrupted plane, except for necessary lead
pads and vias, with signal traces on another layer.
The GND pin of the part should be connected to analog
ground. Resistance from the GND pin to system star
ground should be as low as possible. Resistance here will
add directly to the effective DC output impedance of the
device (typically 0.020Ω), and will degrade DC crosstalk.
Note that the LTC2605/LTC2615/LTC2625 are no more
susceptible to these effects than other parts of their type;
on the contrary, they allow layout-based performance
improvements to shine rather than limiting attainable
performance with excessive internal resistance.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is
limited to voltages within the supply range.
Since the analog outputs of the device cannot go below
ground, they may limit for the lowest codes as shown in
Figure 4b. Similarly, limiting can occur near full scale
when the REF pin is tied to VCC. If VREF = VCC and the DAC
full-scale error (FSE) is positive, the output for the highest
codes limits at VCC as shown in Figure 4c. No full-scale
limiting can occur if VREF is less than VCC – FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting
can occur.
2605f
13
14
2
1
SCL
VOUT
SA5
SA6
SA5
SDA
START
SA6
3
SA4
4
SA3
SA3
5
SA2
SA2
6
SA1
SA1
SLAVE ADDRESS
SA4
7
SA0
SA0
8
WR
9
1
C3
2
C2
C2
3
C1
C1
4
C0
C0
5
A3
A3
COMMAND
6
A2
A2
7
A1
A1
8
A0
A0
9
ACK
1
D15
2
D14
3
D13
4
5
D11
MS DATA
D12
6
D10
7
D9
8
D8
9
ACK
1
D7
2
D6
3
D5
Figure 3. Typical LTC2605 Input Waveform—Programming DAC Output for Full Scale
ACK
C3
4
5
D3
LS DATA
D4
6
D2
7
D1
8
D0
9
ACK
2605/15/25 O02
ZERO-SCALE
VOLTAGE
FULL-SCALE
VOLTAGE
STOP
LTC2605/LTC2615/LTC2625
U
OPERATIO
2605f
LTC2605/LTC2615/LTC2625
U
OPERATIO
VREF = VCC
VREF = VCC
POSITIVE
FSE
OUTPUT
VOLTAGE
OUTPUT
VOLTAGE
INPUT CODE
(c)
OUTPUT
VOLTAGE
0
0V
NEGATIVE
OFFSET
32, 768
INPUT CODE
(a)
65, 535
INPUT CODE
(b)
2605/15/25 O05
Figure 4. Effects of Rail-to-Rail Operation on a DAC Transfer Curve. (a) Overall Transfer Function, (b) Effect
of Negative Offset for Codes Near Zero Scale, (c) Effect of Positive Full-Scale Error for Codes Near Full Scale
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 .005
16 15 14 13 12 11 10 9
.254 MIN
.009
(0.229)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 .0015
.150 – .157**
(3.810 – 3.988)
.0250 TYP
RECOMMENDED SOLDER PAD LAYOUT
1
.015 .004
× 45°
(0.38 0.10)
.007 – .0098
(0.178 – 0.249)
2 3
4
5 6
7
.053 – .068
(1.351 – 1.727)
8
.004 – .0098
(0.102 – 0.249)
0 – 8 TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.008 – .012
(0.203 – 0.305)
.0250
(0.635)
BSC
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN16 (SSOP) 0502
2605f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC2605/LTC2615/LTC2625
U
TYPICAL APPLICATIO
Demonstration Circuit—LTC2428 20-Bit ADC Measures Key Performance Parameters
ADDRESS SELECTION
VCC
VCC
VCC
VREF
VCC
C1
0.1µF
C2
0.1µF
6
REF
11
10
7
VCC
CA0
VOUT A
CA1
VOUT B
CA2
VOUT C
VOUT D
VCC
VOUT E
10k
10k
9
I2C
BUS
8
VOUT F
SDA
VOUT G
SCL
VOUT H
16
2
3
4
5
12
13
14
15
GND
1
U2
LTC2605CGN
TP3
DAC A
TP4
DAC B
TP5
DAC C
TP6
DAC D
DAC OUTPUTS
TP7
DAC E
VREF
TP8
DAC F
TP10
DAC H
2
VOUT
VIN
6
1
C6
0.1µF
4.096V
4
9
2
3 JP2
VREF
TP11
VREF
C7
4.7µF
6.3V
U5
LT1461ACS8-4
2
3
VIN
VOUT
6
SHDN
GND
C9
0.1µF
4
7
4
MUXOUT
ADCIN
3
JP1
ON/OFF
3
2
2
8
DISABLE
ADC
1
VCC VCC
FSSET
VREF
5V
GND
C5
0.1µF
R8
22
C10
100pF
U4
LT1236ACS8-5
VCC
C4
0.1µF
R5
7.5k
TP9
DAC G
VIN
VCC
VCC
CH0
10
CH1
11
CH2
12
CH3
13
CH4
14
CH5
15
CH6
17
CH7
5
ZSSET
CSADC
CSMUX
4-/8-CHANNEL
MUX
+
20-BIT
ADC
SCK
–
DIN
CLK
SD0
1
5VREF
C8 REGULATOR
1µF
16V
TP12
VCC
2
3 JP3
TP13
GND
VCC
FO
GND GND GND GND GND GND GND
1
U3
LTC2428CG
6
16
18
22
27
28
23
20
R6
7.5k
CS
25
19
SCK
21
SPI
BUS
24
26
R7
7.5k
2605 TA01
5V
RELATED PARTS
PART NUMBER
LTC1458/LTC1458L
DESCRIPTION
Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality
LTC1654
LTC1655/LTC1655L
LTC1657/LTC1657L
LTC1660/LTC1665
LTC1821
LTC2600/LTC2610/
LTC2620
LTC2601/LTC2611/
LTC2621
LTC2602/LTC2612/
LTC2622
LTC2604/LTC2614/
LTC2624
LTC2606/LTC2616/
LTC2626
Dual 14-Bit Rail-to-Rail VOUT DAC
Single 16-Bit VOUT DAC with Serial Interface in SO-8
Parrallel 5V/3V 16-Bit VOUT DAC
Octal 10-/8-Bit VOUT DAC in 16-Pin Narrow SSOP
Parallel 16-Bit Voltage Output DAC
Octal 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP
Single 16-/14-/12-Bit VOUT DACs in 10-Lead DFN
Dual 16-/14-/12-Bit VOUT DACs in 8-Lead MSOP
Quad 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP
Single 16-/14-/12-Bit VOUT DACs with I2C Interface in 10-Lead DFN
COMMENTS
LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.096V
LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
Programmable Speed/Power, 3.5µs/750µA, 8µs/450µA
VCC = 5V(3V), Low Power, Deglitched
Low Power, Deglitched, Rail-to-Rail VOUT
VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output
Precision 16-Bit Settling in 2µs for 10V Step
250µA per DAC, 2.5V–5.5V Supply Range, Rail-to-Rail
Output, SPI Interface
300µA per DAC, 2.5V–5.5V Supply Range, Rail-to-Rail
Output, SPI Interface
300µA per DAC, 2.5V–5.5V Supply Range, Rail-to-Rail
Output, SPI Interface
250µA per DAC, 2.5V–5.5V Supply Range, Rail-to-Rail
Output, SPI Interface
270µA per DAC, 2.7V–5.5V Supply Range, Rail-to-Rail
Output, I2C Interface
2605f
16
Linear Technology Corporation
LT/LWI/TP 0405 500 • PRINTED IN THE USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
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© LINEAR TECHNOLOGY CORPORATION 2005