Aplus APE12716 Very low cost voice and melody synthesizer with 4-bits cpu Datasheet

A
PLUS MAKE YOUR PRODUCTION A-PLUS
APExx16 Series
DATA SHEET
APLUS
INTEGRATED CIRCUITS INC.
Address:
3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei,
Taiwan 115, R.O.C.
(115)台北市南港區成功路㆒段 32 號 3 樓之 10.
Sales E-mail:
[email protected]
TEL: 886-2-2782-9266
Technology E-mail:
[email protected]
FAX: 886-2-2782-9255
WEBSITE : http: //www.aplusinc.com.tw
APExx16 Series
1.0 General Description
The APExx16 series are very low cost voice and melody synthesizer with 4-bits CPU. They have various
features including 4-bits ALU, ROM, RAM, I/O ports, timers, clock generator, voice and melody
synthesizer, and PWM (Direct drive) or D/A current outputs, etc. The audio synthesizer contains one
voice-channel and two melody-channels. Furthermore, they consist of 27 instructions in these devices.
With CMOS technology and halt function can minimize power dissipation. Their architectures are similar
to RISC, with two stages of instruction pipeline. They allow all instructions to be executed in a single
cycle, except for program branches and data table read instructions (which need two instruction cycles).
2.0 Features
(1) Single power supply can operate from 2.4V to 5.5V at 4MHz or 8MHz.
(2) Program ROM: 16k x 10 bits ( APE8416 /APE10616 /APE12716 are 64k x 10 bits )
(3) 1 set of 16-bits DPR can access up to 64k x 10 bits melody data memory space, and 1 set of 19-bits
VPR can access up to 512k x 10 bits voice data memory space.
Product
Voice Duration (sec) Voice Pointer (VPR) ROM Size (10-bits)
APE1016
10
15-bits
32k
APE1516
15
16-bits
48k
APE2016
20
16-bits
64k
APE3116
31
17-bits
96k
APE4116
41
17-bits
128k
APE6316
63
18-bits
192k
APE8416
84
18-bits
256k
APE10616
106
19-bits
320k
APE12716
127
19-bits
384k
(4) Data Registers:
a). 128 x 4-bits data RAM (00-7Fh)
b). Unbanked special function registers (SFR) range: 00h-2Fh
(5) I/O Ports:
a). PRA: 4-bits I/O Port A (10h) can be programmed to input/output individually. (Register control)
b). PRB: 4-bits I/O Port B (13h) can be configured to input/output individually. (Mask option)
c). PRC: 4-bits I/O Port C (14h) can be programmed to input/output individually. (Register control)
d). PRD: 4-bits I/O Port D (15h) can be programmed to input/output individually. (Register control)
(6) On-chip clock generator: Resistive Clock Drive (RM) or Crystal oscillator (HM)
(7) Timer: 1-set Voice Interrupt (Timer0: a 9-bits auto-reload timer/counter).
(8) Stack: 2-level subroutine nesting.
(9) Built-in 4 Level Volume Control can be programmed.
1
Rev 1.1
2003/9/2
APExx16 Series
(10) Built-in 8 Level DAC current output can be configured. (Mask option)
(11) Built-in IR Carry Output: Port B[1] can be configured as IR pin by 38k / 56kHz. (Mask option)
(12) External Reset: Port B[3] can be configured as reset pin. (Mask opton)
(13) HALT and Release from HALT function to reduce power consumption
(14) Watch Dog Timer (WDT)
(15) Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles
(16) Number of instruction: 27
(17) DAC: 1 channel voice and dual tone melody synthesizer (One 9-bits Cout or 8-bits PWM output).
FIGURE 1 : ROM Map of APExx16 Series
PC[13:0]
14-bit x 2 STACK
16-bit Data Pointer
19-bit Voice Pointer
Reset Vector
00000h
Reserved for Testing
000FEh
000FFh-00400h
00401h
00000h-03FFFh
Program ROM
00000h-0FFFFh
Data ROM for Melody
00000h-7FFFFh
* APE8416 /APE10616 /APE12716 are 64k x 10 bits
Voice ROM for Voice
2
Rev 1.1
2003/9/2
APExx16 Series
3.0 Pin Description
Pad Name
PWM2/Cout
Pin Attr.
PWM1
Vdd1~3
O
Power
PRA0~3
PRC0~3
PRD0~3
I/O
I/O port can be programmed to input/output individually.
Input type with weak pull-low or fix-input-floating capability.
Buffer Output type.
PRB0 / OSC2
I/O
I/O port can be configured to input/output individually or HM OSC pad.
Input type with weak pull-low or fix-input-floating capability.
Buffer Output type.
PRB1 / IR
I/O
I/O port can be configured to input/output individually.
Input type with weak pull-low or fix-input-floating capability.
Buffer Output type.
Mask option selected as an IR Carrier Output with 38k / 56kHz
PRB2
I/O
I/O port can be configured to input/output individually.
Input type with weak pull-low or fix-input-floating capability.
Buffer Output type.
PRB3 / Reset
I/O
I/O port can be configured to input/output individually.
Input type with weak pull-low or fix-input-floating capability.
Buffer Output type.
Mask option selected as an external RESET pin with weak pull-low
capability.
OSC1
GND1~4
I
Power
O
Description
PWM2 output, or Current Output of Audio.
PWM1 output.
Power supply during operation.
RM/HM mode Oscillator input
Ground Potential
4.0 DC Characteristics
Symbol
Vdd
Isb
Iop
Parameter
Operating voltage
Supply
current
Standby
Operating
Iih
Input current
(Internal pull low)
Ioh
Output-high current
Vdd
Min.
2.4
3
4.5
3
4.5
3
4.5
3
4.5
3
4.5
3
4.5
Typ.
3
Max.
5.5
1
1
2
7
3
10
-3
-10
7
19
0.8 ~ 4.8
0.9 ~ 6.5
Unit
V
uA
Condition
depending on Freq.
4MHz, RM,
in HALT Mode
mA
4MHz, RM,
IO Floating
uA
Input ports with weak
pull-low
mA
4MHz, RM
(IO ports)
mA
4MHz, RM
(Full scale)
Iol
Output-low current
Cout
DAC output current
(8-level option)
dF/F
Frequency stability
-5
5
%
Fosc(3v- 2.4v)
Fosc (3v)
dF/F
Fosc lot variation
-10
10
%
Vdd=3V, Rosc=180k,
4MHz
3
Rev 1.1
2003/9/2
APExx16 Series
FIGURE 2 : Frequency vs. Rosc (at 3V)
Resistor (Rosc ohms)
110k
200k
300k
430k
Frequency (MHz)
14.84
8.25
5.54
3.92
R o sc vs F re q.
Freq. (MHz)
20
1 4 .8 4
15
10
8 .25
5 .54
5
3 .92
0
0
100
200
300
400
500
R os c (k o h m )
5.0 Application Circuit
4
Rev 1.1
2003/9/2
APExx16 Series
6.0 Bonding Diagram of APE1016 /APE1516 /APE2016
GND1
25
PRD0
24
PRD1
23
PRD2
22
PRD3
21
PRC0
20
PRC1
19
PRC2
18
PRC3
17
PRB0
16
OSC1
15
GND2
14
ROM
Chip Size : 1432 um x 1650 um
Pad Size : 80 um x 80 um
1
Vdd3
* The IC substrate must be connected to GND.
Y
2
PWM2/Cout
3
Vdd2
PWM1
4
GND3
5
PRA3
PRA2
PRA1
PRA0
6
7
8
9
(0,0)
Pad #
PRB3 PRB2
10
11
PRB1
Vdd1
12
13
X
Pad Name
X
Pad #
Pad Name
647
466
14
15
GND2
OSC1
1261
1261
235
350
58
145
293
182
58
58
16
17
1261
1261
1261
465
580
695
PRA3
PRA2
413
533
87
87
18
19
20
PRB0/OSC2
PRC3
PRC2
PRC1
PRC0
1261
1261
810
925
8
9
PRA1
PRA0
653
773
87
87
21
22
PRD3
PRD2
1261
1261
1040
1155
10
11
PRB3/Reset
PRB2
893
1013
87
87
23
24
PRD1
PRD0
1261
1261
1270
1385
12
13
PRB1/IR
Vdd1
1133
1253
87
87
25
GND1
1261
1500
1
2
Vdd3
PWM2/Cout
56
58
3
4
Vdd2
PWM1
GND3
5
6
7
Y
5
X
Rev 1.1
Y
2003/9/2
APExx16 Series
6.1 Bonding Diagram of APE3116 /APE4116 /APE6316
GND1
25
PRD0
24
PRD1
23
PRD2
22
PRD3
21
PRC0
20
PRC1
19
PRC2
18
PRC3
17
PRB0
16
ROM
Chip Size : 1408 um x 2556 um
Pad Size : 80 um x 80 um
* The IC substrate must be connected to GND.
Y
1
Vdd3
OSC1
15
2
PWM2/Cout
PRB1
14
GND2
13
3
Vdd2
PWM1
4
GND3
5
(0,0)
Pad #
1
2
3
4
5
6
7
8
9
10
11
12
13
Pad Name
Vdd3
PWM2/Cout
Vdd2
PWM1
GND3
PRA3
PRA2
PRA1
PRA0
PRB3/Reset
PRB2
Vdd1
GND2
PRA3
PRA2
PRA1
PRA0
6
7
8
9
PRB3 PRB2
10
11
Vdd1
12
X
X
56
58
58
145
293
430
563
696
829
962
1095
1228
1248
Y
647
466
182
58
58
87
87
87
87
87
87
87
272
Pad #
14
15
16
17
18
19
20
21
22
23
24
25
6
Pad Name
PRB1/IR
OSC1
PRB0/OSC2
PRC3
PRC2
PRC1
PRC0
PRD3
PRD2
PRD1
PRD0
GND1
X
1248
1248
1248
1248
1248
1248
1248
1248
1248
1248
1248
1248
Rev 1.1
Y
405
570
733
896
1056
1218
1379
1540
1700
1861
2022
2310
2003/9/2
APExx16 Series
6.2 Bonding Diagram of APE8416 /APE10616 /APE12716
26
25
24
23
22
21
20
19
Vdd1
PRB3
PRC3
PRC2
PRC1
PRC0
PRD3
PRD2
17
18
PRD0
PRD1
16
GND1
ROM
Chip Size : 2288 um x 2364 um
Pad Size : 80 um x 80 um
Y
* The IC substrate must be connected to GND.
1
GND4
2
GND3
3
PWM1
Vdd3
PWM2/Cout
4
5
GND2 15
Vdd2
OSC1
PRB0
PRB1
PRB2
6
7
8
9
10
(0,0)
PRA0
11
PRA1
12
PRA2
PRA3
13
14
X
Pad #
1
Pad Name
GND4
X
76
Y
Pad Name
404
Pad #
14
X
Y
PRA3
2109
76
GND2
GND1
2128
1927
212
2204
2
3
GND3
PWM1
59
59
294
146
15
16
4
5
Vdd3
PWM2/Cout
183
467
59
59
17
18
PRD0
PRD1
1765
1603
2204
2204
6
7
Vdd2
OSC1
815
976
76
76
19
20
PRD2
PRD3
1441
1279
2204
2204
8
9
PRB0/OSC2
PRB1/IR
PRB2
1140
1304
1465
76
76
76
21
22
PRC0
PRC1
PRC2
1117
955
739
2204
2204
2204
PRA0
PRA1
1626
1787
76
76
PRC3
PRB3/Reset
631
469
2204
2204
PRA2
1948
76
Vdd1
307
2204
10
11
12
13
23
24
25
26
7
Rev 1.1
2003/9/2
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