HSP43881 Data Sheet May 1999 Digital Filter Features The HSP43881 is a video speed Digital Filter (DF) designed to efficiently implement vector operations such as FIR digital filters. It is comprised of eight filter cells cascaded internally and a shift and add output stage, all in a single integrated circuit. Each filter cell contains a 8 x 8-bit multiplier, three decimation registers and a 26-bit accumulator. The output stage contains an additional 26-bit accumulator which can add the contents of any filter cell accumulator to the output stage accumulator shifted right by 8 bits. The HSP43881 has a maximum sample rate of 30MHz. The effective multiply accumulate (mac) rate is 240MHz. • Eight Filter Cells The HSP43881 DF can be configured to process expanded coefficient and word sizes. Multiple DFs can be cascaded for larger filter lengths without degrading the sample rate or a single DF can process larger filter lengths at less than 30MHz with multiple passes. The architecture permits processing filter lengths of over 1000 taps with the guarantee of no overflows. In practice, most filter coefficients are less than 1.0, making even larger filter lengths possible. The DF provides for 8-bit unsigned or two’s complement arithmetic, independently selectable for coefficients and signal data. • 1-D and 2-D FIR Filters File Number 2758.4 • 0MHz to 30MHz Sample Rate • 8-Bit Coefficients and Signal Data • 26-Bit Accumulator Per Stage • Filter Lengths Over 1000 Taps • Expandable Coefficient Size, Data Size and Filter Length • Decimation by 2, 3 or 4 Applications • Radar/Sonar • Adaptive Filters • Echo Cancellation • Complex Multiply-Add • Sample Rate Converters Ordering Information PART NUMBER Each DF filter cell contains three resampling or decimation registers which permit output sample rate reduction at rates of 1/2, 1/3 or 1/4 the input sample rate. These registers also provide the capability to perform 2-D operations such as matrix multiplication and N x N spatial correlations/convolutions for image processing applications. TEMP. RANGE (oC) PACKAGE PKG. NO. HSP43881JC-20 0 to 70 84 Ld PLCC N84.1.15 HSP43881JC-25 0 to 70 84 Ld PLCC N84.1.15 HSP43881JC-30 0 to 70 84 Ld PLCC N84.1.15 HSP43881GC-20 0 to 70 85 Ld PGA G85.A HSP43881GC-25 0 to 70 85 Ld PGA G85.A HSP43881GC-30 0 to 70 85 Ld PGA G85.A Block Diagram VCC DIENB CIENB DCMO - 1 ERASE VSS 8 5 8 TCCI CIN0 - 7 RESET CLK ADR0 - 2 DIN0 - DIN7 TCS DF FILTER CELL 0 8 5 8 8 DF FILTER CELL 1 26 5 26 8 8 8 DF FILTER CELL 2 26 8 8 DF FILTER CELL 3 8 26 DF FILTER CELL 4 26 8 8 DF FILTER CELL 5 26 8 8 8 DF FILTER CELL 6 26 8 DF FILTER CELL 7 26 TCCO 8 COUT0 - 7 COENB 3 MUX RESET CLK SHADD SENBL SENBH 26 ADR0, ADR1, ADR2 2 OUTPUT STAGE 2 26 SUM0 - 25 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 HSP43881 Pinouts 85 PIN GRID ARRAY (PGA) TOP VIEW, PINS DOWN 1 2 3 4 5 6 7 8 9 10 11 DIN0 A VSS COENB VCC RESET DIN7 DIN6 DIN3 TCCI VCC VSS B VCC COUT7 TCCO ERASE TCS DIN1 DIN2 CIENB CIN7 CIN6 CIN4 DIN4 CIN5 CIN3 CIN2 VCC C COUT5 COUT6 ALIGN PIN DIENB DIN5 D COUT3 COUT4 E COUT1 VSS F COUT2 CIN1 CIN0 SENBL COUT0 SHADD SUM0 VCC VSS G ADR2 DCM0 H ADR1 ADR0 J VCC SUM25 K SENBH SUM24 L VSS SUM1 SUM3 SUM2 CLK SUM5 SUM4 SUM20 SUM17 SUM16 VSS VCC SUM19 VSS SUM7 SUM15 SUM12 SUM10 SUM8 SUM6 VSS DCM1 SUM23 SUM22 SUM21 SUM18 SUM14 VCC SUM13 VSS SUM11 SUM9 HSP43881 TOP VIEW, PINS UP 1 2 3 4 5 6 7 8 9 10 11 L DCM1 SUM23 SUM22 SUM21 SUM18 SUM14 VCC SUM13 VSS SUM11 SUM9 SENBH SUM24 SUM19 VSS SUM15 SUM12 SUM10 SUM8 SUM6 VCC SUM25 SUM20 SUM17 SUM16 SUM7 VSS ADR1 ADR0 SUM5 SUM4 ADR2 DCM0 CLK SUM1 SUM3 SUM2 VSS COUT0 SHADD SUM0 VCC VSS COUT1 VSS COUT2 CIN1 CIN0 SENBL CIN2 VCC CIN5 CIN3 K VSS VCC J H G F E D COUT3 COUT4 C COUT5 COUT6 ALIGN PIN VCC COUT7 COUT8 VSS COENB VCC DIENB DIN5 DIN4 ERASE DIN8 DIN1 DIN2 CIENB CIN7 CIN6 CIN4 RESET DIN7 DIN6 DIN3 DIN0 CIN8 VCC VSS B A 2 HSP43881 Pinouts (Continued) COUT5 VCC 1 84 83 82 81 80 79 78 77 76 75 COUT4 2 COUT3 3 COUT2 4 COUT1 ADDR2 5 VSS DCM0 6 COUT0 VSS SHADD ADDR1 7 CLK ADDR0 8 SENBH 9 VCC SUM25 11 10 DCM1 SUM24 VSS 84 LEAD PLCC PACKAGE BOTTOM VIEW SUM23 12 74 COUT6 SUM22 13 73 COUT7 VCC 14 72 VSS SUM21 15 71 TCCO SUM20 16 70 COENB SUM19 17 69 VCC SUM18 18 68 ERASE VSS 19 67 RESET SUM17 20 66 DIENB SUM16 21 65 TCS VCC 22 64 DIN7 SUM15 23 63 DIN6 SUM14 24 62 DIN5 SUM13 25 61 DIN4 SUM12 26 60 DIN3 VSS 27 59 DIN2 SUM11 28 58 DIN1 SUM10 29 57 DIN0 SUM9 30 56 CIENB SUM8 31 55 TCCI SUM7 32 54 VCC NOTE: An overbar on a signal name represents an active LOW signal. 3 CIN7 CIN6 VSS CIN5 CIN4 CIN3 CIN2 VCC CIN1 CIN0 SENBL VSS SUM0 SUM1 SUM2 SUM3 VCC SUM4 SUM5 VSS SUM6 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 HSP43881 Pin Description SYMBOL PIN NUMBER TYPE DESCRIPTION VCC A3, A10, B1, D11, F10, J1, K4, L7 +5V Power Supply Input. VSS A1, A11, E2, F1, E11, H11, K3, K6, L9 Power Supply Ground Input. CLK G3 I The CLK input provides the DF system sample clock. The maximum clock frequency is 30MHz. DIN0-7 A58, B67, C67 I These eight inputs are the data sample input bus. Eight bit data samples are synchronously loaded through these pins to the X register of each filter cell simultaneously. The DIENB signal enables loading, which is synchronous on the rising edge of the clock signal. TCS B5 I The TCS input determines the number system interpretation of the data input samples on pins DIN0-7 as follows: TCS = Low → Unsigned Arithmetic. TCS = High → Two's Complement Arithmetic. The TCS signal is synchronously loaded into the X register in the same way as the DIN0-7 inputs. DIENB C5 I A low on this enables the data sample input bus (DIN0-7) to all the filter cells. A rising edge of the CLK signal occurring while DIENB is low will load the X register of every filter cell with the 8-bit value present on DIN0-7. A high on this input forces all the bits of the data sample input bus to zero; a rising CLK edge when DIENB is high will load the X register of every filter cell with all zeros. This signal is latched inside the DF, delaying its effect by one clock internal to the DF. Therefore, it must be low during the clock cycle immediately preceding presentation of the desired data on the DIN0-7 inputs. Detailed operation is shown in later timing diagrams. CIN0-7 B9-11, C10-11, D10, E9-10 I These eight inputs are used to input the 8-bit coefficients. The coefficients are synchronously loaded into the C register of filter CELL 0 if a rising edge of CLK occurs while CIENB is low. The CIENB signal is delayed by one clock as discussed below. TCCI A9 I The TCCI input determines the number system interpretation of the coefficient inputs on pins CIN07 as follows: TCCI = LOW E Unsigned Arithmetic. TCCI = HIGH E Two's Complement Arithmetic. The TCCI signal is synchronously loaded into the C register in the same way as the CIN0-7 inputs. CIENB B8 I A low on this input enable the C register of every filter cell and the D registers (decimation) of every filter cell according to the state of the DCM0-1 inputs. A rising edge of the CLK signal occurring while CIENB is low will load the C register and appropriate D registers with the coefficient data present at their inputs. This provides the mechanism for shifting the coefficients from cell to cell through the device. A high on this input freezes the contents of the C register and the D registers ignoring the CLK signal. This signal is latched and delayed by one clock internal to the DF. Therefore, it must be low during the clock cycle immediately preceding presentation of the desired coefficient of the CIN07 inputs. Detailed operation is shown in the Timing Diagrams Section. COUT0-7 B2, C1-2, D1-2, E1, E3, F2 O These eight three-state outputs are used to output the 8-bit coefficients from filter cell 7. These outputs are enabled by the COENB signal low. These outputs may be tied to the CIN0-7 inputs of the same DF to recirculate the coefficients, or they may be tied to the CIN0-7 inputs of another DF to cascade DFs for longer filter lengths. TCCO B3 O The TCCO three-state output determines the number system representation of the coefficients output on COUTO-7. It tracks the TCCI signal to this same DF. It should be tied to the TCCI input of the next DF in a cascade of DFs for increased filter lengths. This signal is enabled by COENB low. COENB A2 I A low on the COENB input enables the COUT0-7 and the TCCO output. A high on this input places all these outputs in their high impedance state. 4 HSP43881 Pin Description (Continued) SYMBOL PIN NUMBER DCM0-1 G2, L1 SUM0-25 J2, J5-8, J10, K2, K5-11, L-26, L8, L10-11 O These 26 three-state outputs are used to output the results of the internal filter cell computations. Individual filter cell results or the result of the shift and add output stage can be output. If an individual filter cell result is to be output, the ADR0-2 signals select the filter cell result. The SHADD signal determines whether the selected filter cell result or the output stage adder result is output. The signals SENBH and SENBL enable the most significant and least significant bits of the SUM0-25 result, respectively. Both SENBH and SENBL may be enabled simultaneously if the system has a 26-bit or larger bus. However, individual enables are provided to facilitate use with a 16-bit bus. SENBH K1 I A low on this input enables result bits SUM16-25. A high on this input places these bits in their high impedance state. SENBL E11 I A low on this input enables result bits SUM0-15. A high on this input places these bits in their high impedance state. ADR0-2 G1, H1-2 I These inputs select the one cell whose accumulator will be read through the output bus (SUM0-25) or added to the output stage accumulator. They also determine which accumulator will be cleared when ERASE is low. For selection of which accumulator to read through the output bus (SUM0-25) or which to add to the output stage accumulator, these inputs are latched in the DF and delayed by one clock internal to the device. If the ADR0-2 lines remain at the same address for more than one clock, the output at SUM0-25 will not change to reflect any subsequent accumulator updates in the addressed cell. Only the result available during the first clock, when ADR0-1 selects the cell, will be output. This does not hinder normal operation since the ADR0-1 lines are changed sequentially. This feature facilitates the interface with slow memories where the output is required to be fixed for more than one clock. SHADD F3 I The SHADD input controls the activation of the shift-and-add operation in the output stage. This signal is latched in the DF and delayed by one clock internal to the device. A detailed explanation is given in the DF Output Stage Section. RESET A4 I A low on this input synchronously clears all the internal registers, except the cell accumulators. It can be used with ERASE to also clear all the accumulators simultaneously. This signal is latched in the DF and delayed by one clock internal to the DF. ERASE B4 I A low on this input synchronously clears the cell accumulator selected by the ADR0-1 signals. If RESET is also low simultaneously, all cell accumulators are cleared. ALIGN PIN C3 TYPE DESCRIPTION These two inputs determine the use of the internal decimation registers as follows: DCM1 DCM0 Decimation Function 0 0 Decimation Registers not used. 0 1 One Decimation Register is used. 1 0 Two Decimation Registers are used. 1 1 Three Decimation Registers are used. The coefficients pass from cell to cell at a rate determined by the number of decimation registers used. When no decimation registers are used, coefficients move from cell to cell on each clock. When one decimation register is used, coefficients move from cell to cell on every other clock, etc. These signals are latched and delayed by one clock internal to the DF. Used for aligning chip in socket or printed circuit board. Must be left as a no connect in circuit. Functional Description The Digital Filter Processor (DF) is composed of eight filter cells cascaded together and an output stage for combining or selecting filte5r cell outputs (See Block Diagram). Each filter cell contains a multiplier accumulator and several registers (Figure 1). Each 8-bit coefficient is multiplied by an 8-bit data sample, with the result added to the 26-bit accumulator contents. The coefficient output of each cell is cascaded to the coefficient input of the next cell to its right. DF Filter Cell An 8-bit coefficient (CIN0-7) enters each cell through the C register on the left and exits the cell on the right as signals 5 COUT0-7. With no decimation, the coefficient moves directly from the C register to the output, and is valid on the clock following its entrance. When decimation is selected the coefficient exit is delayed by 1, 2 or 3 clocks by passing through one or more decimation registers (D1, D2 or D3). The combination of D registers through which the coefficient passes is determined by the state of DCM0 and DCM1. The output signals (COUT0-7) are connected to the CIN0-7 inputs of the next cell to its right. The COENB input signal enables the COUT0-7 outputs of the right most cell to the COUT-07 pins of the device. The C and D registers are enabled for loading by CIENB. Loading is synchronous with CLK when CIENB is low. Note that HSP43881 CIENB is latched internally. It enables the register for loading after the next CLK following the onset of CIENB low. Actual loading occurs on the second CLK following the onset of CIENB low. Therefore, CIENB must be low during the clock cycle immediately preceding presentation of the coefficient on the CIN0-7 inputs. In most basic FIR operations, CIENB will be low throughout the process, so this latching and delay sequence is only important during the initialization phase. When CIENB is high, the coefficients are frozen. These registers are cleared synchronously under control of RESET, which is latched and delayed exactly like CIENB. The output of the C register (C0-8) is one input to 8 x 8 multiplier. The other input to the 8 x 8 multiplier comes from the output of the X register. This register is loaded with a data sample from the device input signals DIN0-7 discussed above. The X register is enabled for loading by DIENB. Loading is synchronous with CLK when DIENB is low. Note that DIENB is latched internally. It enables the register for loading after the next CLK following the onset of DIENB low. Actual loading occurs on the second CLK following the onset of DIENB low; therefore, DIENB must be low during the clock cycle immediately preceding presentation of the data sample on the DIN0-7 inputs. In most basic FIR operations, DIENB will be low throughout the process, so this latching and delay sequence is only important during the initialization phase. When DIENB is high, the X register is loaded with all zeros. The multiplier is pipelined and is modeled as a multiplier core followed by two pipeline registers, MREG0 and MREG1 (Figure 1). The multiplier output is sign extended and input as one operand of the 26-bit adder. The other adder operand is the output of the 26-bit accumulator. The adder output is loaded synchronously into both the accumulator and the TREG. The TREG loading is disabled by the cell select signal, CELLn, where n is the cell number. The cell select is decoded from the ADR0-2 signals to generate the TREG load enable. The cell select is inverted and applied as the load enable to the TREG. Operation is such that the TREG is loaded whenever the cell is not selected. Therefore, TREG is loaded every clock except the clock following cell selection. The purpose of the TREG is to hold the result of a sum of products calculation during the clock when the accumulator is cleared to prepare for the next sum of products calculation. This allows continuous accumulation without wasting clocks. The accumulator is loaded with the adder output every clock unless it is cleared. It is cleared synchronously in two ways. When RESET and ERASE are both low, the accumulator is cleared along with all other registers on the device. Since ERASE and RESET are latched and delayed one clock internally, clearing occurs on the second CLK following the onset of both ERASE and RESET low. The second accumulator clearing mechanism clears a single accumulator in a selected cell. The cell select signal, CELLn, 6 decoded from ADR0-2 and the ERASE signal enable clearing of the accumulator on the next CLK. The ERASE and RESET signals clear the DF internal registers and states as follows: ERASE RESET CLEARING EFFECT 1 1 No clearing occurs, internal state remains same. 1 0 RESET only active, all registers except accumulators are cleared, including the internal pipeline registers. 0 1 ERASE only active, the accumulator whose address is given by the ADR0-2 inputs is cleared. 0 0 Both RESET and ERASE active, all accumulators, as well as all other registers are cleared. The DF Output Stage The output stage consists of a 26-bit adder, 26-bit register, feedback multiplexer from the register to the adder, an output multiplexer and a 26-bit three-state driver stage (Figure 2). The 26-bit output adder can add any filter cell accumulator result to the 18 most significant bits of the output buffer. This result is stored back in the output buffer. This operation takes place in one clock period. The eight LSBs of the output buffer are lost. The filter cell accumulator is selected by the ADR0-2 inputs. The 18 MSBs of the output buffer actually pass through the zero mux on their way to the output adder input. The zero mux is controlled by the SHADD input signal and selects either the output buffer 18 MSBs or all zeros for the adder input. A low on the SHADD input selects zero. A high on the SHADD input selects the output buffer MSBs, thus, activating the shift and add operation. The SHADD signal is latched and delayed by one clock internally. HSP43881 DCM1.D DCM0.D RESET.D CIENB.D LD CLR TCCI C.TCCI C REG D1 REG 0-7 7 LD CLR 1 C0-7 CIN0-7 LD CLR LD CLR D2 REG D3 REG THREE-STATE BUFFERS ON CELL 7 ONLY 1 MUX D.TCCI CLK CLK TCCO MUX CLK COUT0-7 D0-7 0 0 C0-8 B RESET.D COENB DIENB.D LD CLR TCS X REG C X0-8 7 MULTIPLIER X CORE DIN0-7 P0-17 CLK MREG0 LATCHES DCM1 DCM1.D DCM0 DCM0.D RESET RESET.D DIENB DIENB.D CIENB CIENB.D ADR0 ADR0.D ADR1 ADR1.D ADR2 ADR2.D ERASE RESET.D CLR CLK MREG1 CLR 0-17 SIGN EXTENSION 18-25 ACC.D0-25 ERASE.D ADDER CLK ACC0-25 ERASE.D ACC CLR CELLn CELL 0 ADR0 CELL 1 ADR1 DECODER CELL 7 ADR2 CELLn D Q T REG LD CLK AOUT0-25 FIGURE 1. FILTER CELL 7 CLK HSP43881 0 1 6 26 26 3 26 7 26 CELL RESULT MUX ADR0.D-ADR2.D 0-18 18 SIGN EXT 18-25 RESET.D 8 26 18 (LSBs) 0-17 + 26 SHADD CLR SHADD.D ZERO MUX Q D 0 OUTPUT BUFFER RESET.D 26 8-25 18 CLK CLK 1 26 0 18 MSBs SHIFTED 8 BITS TO RIGHT (BITS 0 - 17) 1 0 OUTPUT MUX RESET.D 26 CLR D Q SENBL SENBH 2 THREE-STATE BUFFER 26 CLK SUM0-25 FIGURE 2. DF OUTPUT STAGE The 26 least significant bits (LSBs) from either a cell accumulator or the output buffer are output on the SUM0-25 bus. The output mux determines whether the cell accumulator selected by ADR0-2 or the output buffer is output to the bus. This mux is controlled by the SHADD input signal. Control is based on the state of the SHADD during two successive clocks; in other words, the output mux selection contains memory. If SHADD is low during a clock cycle and was low during the previous clock, the output mux selects the contents of the filter cell accumulator addressed by ADR0-2. Otherwise the output mux selects the contents of the output buffer. If the ADR0-2 lines remain at the same address for more than one clock, the output at SUM0-25 will not change to reflect any subsequent accumulator updates in the addressed cell. Only the result available during the first clock when ADR0-2 selects the cell will be output. This does not hinder normal FIR operation since the ADR0-2 lines are changed sequentially. This feature facilitates the interface with slow memories where the output is required to be fixed for more than one clock. 8 The SUM0-25 output bus is controlled by the SENBH and SENBL signals. A low on SENBL enables bits SUM0-15. A low on SENBH enables bits SUM16-25. Thus, all 26 bits can be output simultaneously if the external system has a 26-bit or larger bus. If the external system bus is only 16 bits, the bits can be enabled in two groups of 16 and 10 bits (sign extended). DF Arithmetic Both data samples and coefficients can be represented as either unsigned or two's complement numbers. The TCS and TCCI inputs determine the type of arithmetic representation. Internally all values are represented by a 9-bit two's complement number. The value of the additional ninth bit depends on the arithmetic representation selected. For two's complement arithmetic, the sign is extended into the ninth bit. For unsigned arithmetic, bit-9 is 0. The multiplier output is 18 bits and the accumulator is 26 bits. The accumulator width determines the maximum possible number of terms in the sum of products without HSP43881 overflow. The maximum number of terms depends also on the number system and the distribution of the coefficient and data values. Then maximum numbers of terms in the sum products are: For practical FIR filters, the coefficients are never all near maximum value, so even larger vectors are possible in practice. Basic FIR Operation MAX # OF TERMS NUMBER SYSTEM Two Unsigned Vectors 1032 Two Two's Complement: • Two Positive Vectors 2080 • Negative Vectors 2047 • One Positive and One Negative Vector 2064 One Unsigned and One Two's Complement Vector: • Positive Two's Complement Vector 1036 • Negative Two's Complement Vector 1028 A simple, 30MHz 8-tap filter example serves to illustrate more clearly the operation of the DF. The sequence table (Table 1) shows the results of the multiply accumulate in each cell after each clock. The coefficient sequence, Cn, enters the DF on the left and moves from left to right through the cells. The data sample sequence, Xn, enters the DF from the top, with each cell receiving the same sample simultaneously. Each cell accumulates the sum of products for one output point. Eight sums of products are calculated simultaneously, but staggered in time so that a new output is available every system clock. TABLE 1. 30MHz, 8-TAP FIR FILTER SEQUENCE X15...X9, X8, X7...X1, X0 C0...C6, C7, C0...C6, C7 HSP43881 CLK CELL 0 CELL 1 CELL 2 CELL 3 0 C7 x X0 0 0 0 - 1 +C6 x X1 C7 x X1 0 0 - 2 +C5 x X2 +C6 x X2 C7 x X2 0 - 3 +C4 x X3 +C5 x X3 +C6 x X3 C7 x X3 - 4 +C3 x X4 +C4 x X4 +C5 x X4 +C6 x X4 C7 x X4 5 +C2 x X5 C3 x X5 +C4 x X5 +C5 x X5 +C6 x X5 C7 x X5 6 +C1 x X6 +C2 x X6 +C3 x X6 +C4 x X6 +C5 x X6 +C6 x X6 C7 x X6 7 +C0 x X7 +C1 x X7 +C2 x X7 +C3 x X7 +C4 x X7 +C5 x X7 +C6 x X7 C7 x X7 Cell 0 (Y7) 8 C7 x X8 +C0 x X8 +C1 x X8 +C2 x X8 +C3 x X8 +C4 x X8 +C5 x X8 +C6 x X8 Cell 1 (Y8) 9 +C6 x X9 C7 x X9 +C0 x X9 +C1 x X9 +C2 x X9 +C3 x X9 +C4 x X9 +C5 x X9 Cell 2 (Y9) 10 +C5 x X10 +C6 x X10 C7 x X10 +C0 x X10 +C1 x X10 +C2 x X10 +C3 x X10 +C4 x X10 Cell 3 (Y10) 11 +C4 x X11 +C5 x X11 +C6 x X11 C7 x X11 +C0 x X11 +C1 x X11 +C2 x X11 +C3 x X11 Cell 4 (Y11) 12 +C3 x X12 +C4 x X12 +C5 x X12 +C6 x X12 C7 x X12 +C0 x X12 +C1 x X12 +C2 x X12 Cell 5 (Y12) 13 +C2 x X13 +C3 x X13 +C4 x X13 +C5 x X13 +C6 x X13 C7 x X13 +C0 x X13 +C1 x X13 Cell 6 (Y13) 14 +C1 x X14 +C2 x X14 +C3 x X14 +C4 x X14 +C5 x X14 +C6 x X14 +C7 x X14 +C0 x X14 Cell 7 (Y14) 15 +C0 x X15 +C1 x X15 +C2 x X15 +C3 x X15 +C4 x X15 +C5 x X15 +C6 x X15 C7 x X15 Cell 0 (Y15) 9 CELL 4 Y15...Y14,...Y8, Y7 CELL 5 CELL 6 CELL 7 SUM/CLR - HSP43881 SAMPLE DATA IN (Xn) 3-BIT COUNTER 30MHz CLOCK +5V Y2 Y 1 Y 0 ADR2 ADR1 ADR0 VCC SHADD SENBH SENBL 8 DIN0-7 26 SUM0-25 DIENB SUM OUT (Yn) TCS HSP43881 TCCO CLK A2 A1 A0 TCCI 8 x 8 COEFF. RAM/ROM 8 COUT0-7 8 D0-D7 NC NC CIN0-7 CIENB DCM1 DCM0 RESET ERASE VSS COENB SYSTEM RESET ERASE FIGURE 3. 30MHZ, 8 TAP FIR FILTER APPLICATION SCHEMATIC Detailed operation of the DF to perform a basic 8-tap, 8-bit coefficient, 8-bit data, 30MHz FIR filter is best understood by observing the schematic (Figure 3) and timing diagram (Figure 4). The internal pipeline length of the DF is four (4) clock cycles, corresponding to the register levels CREG (or XREG), MREG0, MREG1, and TREG (Figures 1 and 2). Therefore, the delay from presentation of data and coefficients at the DIN0-7 and CIN0-7 inputs to a sum appearing at the SUM0-25 output is: k + Td Where: k = filter length Td = 4, the internal pipeline delay of DF After the pipeline has filled, a new output sample is available every clock. The delay to last sample output from last sample input is Td. The output sums, Yn, shown in the Timing Diagram are derived from the sum of products equation: Y(n) = C(0) x X(n) + C(1) x X(n1) + C(2) x X(n -2) + C(3) x X(n -3) + C(4) x X(n -4) + C(5) x X(n -5) + C(6) x X(n -6) + C(7) x X(n -7) 10 Extended FIR Filter Length Filter lengths greater that eight taps can be created by either cascading together multiple DF devices or “reusing” a single device. Using multiple devices, an FIR filter of over 1000taps can be constructed to operate at a 30MHz sample rate. Using a single device clocked at 30MHz, a FIR filter of over 1000 taps can be constructed to operate at less than a 30MHz sample rate. Combinations of these two techniques are also possible. HSP43881 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK RESET ERASE DIN0-7 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 C7 C6 C5 C4 C3 C2 C1 C0 C7 C6 C5 C4 C3 C2 C1 C0 C7 C6 C5 0 1 2 3 4 5 6 7 0 Y7 Y8 Y9 DIENB CIN0-7 CIENB ADR0-2 SUM0-24 SHADD SENBL SENBH DCM0-1 0 7 YN = ∑ CK × XN – K K=0 FIGURE 4. 30MHz, 8-TAP FIR FILTER TIMING 11 Y10 Y11 Y12 Y13 Y14 SAMPLE DATA IN (Xn) C Q D Q 30MHz CLOCK 12 +5V ADR1 ADR0 ADR2 VCC SHADD SENBH +5V SENBL ADR1 ADR0 ADR2 VCC SHADD SENBH 25 8 SUM0-24 DIN0-7 Y0 8x16 COEFF. RAM/ROM A0 4-BIT Y1 COUNTER Y2 A1 RESET Y3 A3 A2 D0-D7 DIENB TCS HSP43881 TCS HSP43881 CLK DF0 CLK DF1 TCCI TCCO 8 TCCO TCCI 8 8 CIN0-7 COUT0-7 CIENB DCM1 DCM0 RESET ERASE VSS COENB NC CIN0-7 COUT0-7 NC CIENB DCM1 DCM0 RESET ERASE VSS COENB SUM OUT (Yn) SYSTEM RESET FIGURE 5. 30MHz, 16-TAP FIR FILTER CASCADE APPLICATION SCHEMATIC HSP43881 CLK SUM0-24 DIN0-7 DIENB SENBL 25 8 HSP43881 Cascade Configuration To design a filter length L>8, L/8 DFs are cascaded by connecting the COUT0-7 outputs of the (i)th DF to the CIN07 inputs of the (i+1)th DF. The DIN0-7 inputs and SUM0-25 outputs of all the DFs are also tied together. A specific example of two cascaded DFs illustrates the technique (Figure 5). Timing (Figure 6) is similar to the simple 8-tap FIR, except the ERASE and SENBL/SENBH signals must be enabled independently for the two DFs in order to clear the correct accumulators and enable the SUM0-25 output signals at the proper times. Extended Coefficient and Data Sample Word Size The sample and coefficient word size can be extended by utilizing several DFs in parallel to get the maximum sample rate or a single DF with resulting lower sample rates. The technique is to compute partial products of 8 x 8 and combine these partial products by shifting and adding to obtain the final result. The shifting and adding can be accomplished with external adders (at full speed) or with the DF's shift and add mechanism contained in its output stage (at reduced speed). Single DF Configuration Decimation/Resampling Using a single DF, a filter of length L>8 can be constructed by processing in L/8 passes as illustrated in the following table (Table 2) for a 16-tap FIR. Each pass is composed of Tp = 7 + L cycles and computes eight output samples. In pass i, the sample with indices i*8 to i*8 +(L1) enter the DIN0-7 inputs. The coefficients C0 -CL -1 enter the CIN0-7 inputs, followed by seven zeros. As these zeros are entered, the result samples are output and the accumulators reset. Initial filing of the pipeline is not shown in this sequence table. Filter outputs can be put through a FIFO to even out the sample rate. The HSP43881 DF provides a mechanism for decimating by factors of 2, 3, or 4. From the DF filter cell block diagram (Figure 1), note the three D registers and two multiplexers in the coefficient path through the cell. These allow the coefficients to be delayed by 1, 2, or 3 clocks through the cell. The sequence table (Table 3) for a decimate by two filter illustrates the technique (internal cell pipelining ignored for simplicity). 13 Detailed timing for a 30MHz input sample rate, 15MHz output sample rate (i.e., decimate by two), 16-tap FIR filter, including pipelining, is shown in Figure 7. This filter requires only a single HSP43881 DF. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 25 24 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 CLK RESET DF0 ERASE 14 DF1 ERASE X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 X32 X33 X34 X35 X36 X37 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 X0 DIN0-7 X1 X2 X3 X4 X5 X6 DIENB CIN0-7 C5 C4 C3 C2 C1 C0 C15 C14 C13 C12 C11 C10 C9 C7 C6 5 6 7 C5 C4 C3 C2 C1 2 3 4 C0 C15 C14 C13 C12 C11 C10 CIENB ADR0-2 0 1 2 3 4 0 5 6 7 0 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 DF1 SUM0-25 SHADD DF0 SENBL/H DF1 SENBL/H 0 15 YN = ∑ CK × XN – K K=0 FIGURE 6. 16-TAP 30MHz FIR FILTER TIMING USING TWO CASCADED HSP43881s 1 2 3 Y31 Y32 Y33 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 DF0 SUM0-25 DCM0-1 1 HSP43881 C8 HSP43881 TABLE 2. 16-TAP FIR FILTER SEQUENCE USING A SINGLE DF Data Sequence X30...X9, X8, X22...X1, X0 Input Coefficient Sequence C0...C14, C15, 0...0, C0...C14, C15 Input HSP43881 CLK CELL 0 CELL 1 CELL 2 CELL 3 6 C15 x X0 0 0 0 - 7 +C14 x X1 C15 x X1 0 0 - 8 +C13 x X2 C15 x X2 0 - 9 +C12 x X3 C15 x X3 - 10 +C11 x X4 +C14 x X4 11 +C10 x X5 +C13 x X5 12 +C9 x X6 +C12 x X6 13 +C8 x X7 +C11 x X7 C15 x X7 - 14 +C7 x X8 +C10 x X8 C14 x X8 - 15 +C6 x X9 +C9 x X9 C13 x X9 - 16 +C5 x X10 +C8 x X10 C12 x X10 - 17 +C4 x X11 +C7 x X11 C11 x X11 - 18 +C3 x X12 +C6 x X12 C10 x X12 - 19 +C2 x X13 +C5 x X13 C9 x X13 - 20 +C1 x X14 +C4 x X14 C8 x X14 - 21 +C0 x X15 +C3 x X15 C7 x X15 CELL 0 (Y15) 22 0 +C0 x X16 +C2 x X16 C6 x X16 CELL 1 (Y16) 23 0 0 C0 x X17 +C1 x X17 C5 x X17 CELL 2 (Y17) 24 0 0 0 +C0 x X18 C4 x X18 CELL 3 (Y18) 25 0 0 0 0 C0 x X19 C3 x X19 CELL 4 (Y19) 26 0 0 0 0 0 C0 x X20 C2 x X20 CELL 5 (Y20) 27 0 0 0 0 0 0 C0 x X21 C1 x X21 CELL 6 (Y21) 28 0 0 0 0 0 0 0 C0 x X22 CELL 7 (Y22) 15 CELL 4 ...0, Y30 ...Y23, 0...0, Y22,...Y15, 0...0 CELL 5 CELL 6 CELL 7 C15 x X4 SUM/CLR C15 x X5 C15 x X6 - HSP43881 TABLE 2. 16-TAP FIR FILTER SEQUENCE USING A SINGLE DF (Continued) Data Sequence X30...X9, X8, X22...X1, X0 Input Coefficient Sequence C0...C14, C15, 0...0, C0...C14, C15 Input HSP43881 ...0, Y30 ...Y23, 0...0, Y22,...Y15, 0...0 CLK CELL 0 CELL 1 CELL 2 CELL 3 CELL 4 CELL 5 CELL 6 CELL 7 SUM/CLR 29 C15 x X8 0 0 0 0 0 0 0 - 30 +C14 x X9 C15 x X9 0 0 0 0 0 0 - 31 +C13 x X10 +C15 x X10 0 0 0 0 0 - 32 +C12 x X11 0 0 0 0 - 33 +C11 x X12 C15 x X12 0 0 0 - 34 +C10 x X13 C15 x X13 0 0 - 35 +C9 x X14 C15 x X14 0 - 36 +C8 x X15 C15 x X15 - 37 +C7 x X16 C14 x X16 - 38 +C6 x X17 C13 x X17 - 39 +C5 x X18 C12 x X18 - 40 +C4 x X19 C11 x X19 - 41 +C3 x X20 C10 x X20 - 42 +C2 x X21 C9 x X21 - 43 +C1 x X22 C8 x X22 - 44 +C0 x X23 C7 x X23 CELL 0 (Y23) 45 0 C0 x X24 C6 x X24 CELL 1 (Y24) 46 0 0 C0 x X25 C5 x X25 CELL 2 (Y25) 47 0 0 0 C4 x X26 CELL 3 (Y26) 48 0 0 0 C3 x X27 CELL 4 (Y27) 16 C0 x X26 C0 x X27 HSP43881 TABLE 3. 16-TAP DECIMATE BY TWO FIR FILTER SEQUENCE; 30MHz IN, 15MHz OUT Data Sequence ...X2, X1, X0 Input Coefficient Sequence ...C15, C0, ...C13, C14, C15 Input ...Y19, -, ...Y17, -, Y15 HSP43881 CLK CELL 0 CELL 1 CELL 2 CELL 3 CELL 4 CELL 5 CELL 6 CELL 7 SUM/CLR 6 C15 x X0 0 0 0 0 0 0 0 - 7 +C14 x X1 0 0 0 0 0 0 0 - 8 +C13 x X2 C15 x X2 0 0 0 0 0 0 - 9 +C12 x X3 0 0 0 0 0 0 - 10 +C11 x X4 C15 x X4 0 0 0 0 0 - 11 +C10 x X5 0 0 0 0 0 - 12 +C9 x X6 C15 x X6 0 0 0 0 - 13 +C8 x X7 0 0 0 0 - 14 +C7 x X8 C15 x X8 0 0 0 - 15 +C6 x X9 0 0 0 - 16 +C5 x X10 C15 x X10 0 0 - 17 +C4 x X11 0 0 - 18 +C3 x X12 C15 x X12 0 - 19 +C2 x X13 0 - 20 +C1 x X14 C15 x X14 - 21 +C0 x X15 +C14 x X15 CELL 0 (Y15) 22 C15 x X16 +C13 x X16 - 23 +C14 x X17 +C12 x X17 CELL 1 (Y17) 24 +C13 x X18 +C11 x X18 - 25 +C12 x X19 +C10 x X19 CELL 2 (Y19) 26 +C11 x X20 +C9 x X20 - 27 +C10 x X21 +C8 x X21 CELL 3 (Y21) 28 +C9 x X22 +C7 x X22 - 29 +C8 x X23 +C6 x X23 CELL 4 (Y23) 30 +C7 x X24 +C5 x X24 - 31 +C6 x X25 +C4 x X25 CELL 5 (Y25) 32 +C5 x X26 +C3 x X26 - 33 +C4 x X27 +C2 x X27 CELL 6 (Y27) 34 +C3 x X28 +C1 x X28 - 35 +C2 x X29 +C0 x X29 CELL 7 (Y29) 36 +C1 x X30 C15 x X30 - +C14 x X31 CELL 8 (Y31) 37 +C0 x X31 +C14 x X31 17 +C14 x X31 +C14 x X31 +C14 x X31 +C14 x X31 +C14 x X31 0 1 2 3 4 X0 X1 X2 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 CLK RESET ERASE DIN0-7 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 X32 X33 X34 X35 X36 X37 18 DIENB CIN0-7 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 C15 C14 C13 C12 C11 C10 CIENB ADR0-2 0 Y15 SUM0-25 1 Y17 2 Y19 3 4 Y21 5 Y23 Y25 7 Y27 Y29 0 Y31 1 Y33 HSP43881 SHADD SENBL SENBH DCM0-1 6 1 FIGURE 7. 16-TAP DECIMATE-BY-TWO FIR FILTER TIMING; 30MHz, 15MHz OUT HSP43881 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V Input, Output Voltage . . . . . . . . . . . . . . . . . . . GND -0.5 to VCC 0.5V ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) PLCC Package . . . . . . . . . . . . . . . . . . 34 N/A PGA Package . . . . . . . . . . . . . . . . . . . 36 7 Maximum Junction Temperature PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC PGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (PLCC - Lead Tips Only) Operating Conditions Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±5% Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17,763 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications PARAMETER SYMBOL NOTES Power Supply Current ICCOP Notes 2, 4 Standby Power Supply Current ICCSB Note 4 TEST CONDITIONS MIN MAX UNITS VCC = Max CLK Frequency 20MHz - 140 mA VCC = Max - 500 µA Input Leakage Current II VCC = Max, Input = 0V or VCC -10 10 µA Output Leakage Current IO VCC = Max, Input = 0V or VCC -10 10 µA Logical One Input Voltage VIH VCC = Max 2.0 - V Logical Zero Input Voltage VIL VCC = Min - 0.8 V Logical One Output Voltage VOH IOH = 400µA, VCC = Min 2.6 - V Logical Zero Output Voltage VOL IOL = 2mA, VCC = Min - 0.4 V Clock Input High VIHC VCC = Max 3.0 - V Clock Input Low VILC VCC = Min - 0.8 V Input Capacitance PLCC PGA CIN - 10 15 pF pF Output Capacitance PLCC PGA COUT CLK Frequency 1MHz All measurements referenced to GND TA = 25oC - 10 15 pF pF Note 3 NOTES: 2. Operating supply current is proportional to frequency. Typical rating is 7mA/MHz. 3. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. 4. Output load per test load circuit and CL = 40pF. 19 HSP43881 AC Electrical Specifications VCC = 5V ±5%, TA = 0oC to + 70oC -20 (20MHz) PARAMETER TEST CONDITIONS SYMBOL NOTES -25 (25.6MHz) -30 (30MHz) MIN MAX MIN MAX MIN MAX UNITS Clock Period t CP 50 - 39 - 33 - ns Clock Low t CL 20 - 16 - 13 - ns Clock High t CH 20 - 16 - 13 - ns Input Setup t IS 16 - 14 - 13 - ns Input Hold t IH 0 - 0 - 0 - ns CLK to Coefficient Output Delay t ODC - 24 - 20 - 18 ns Output Enable Delay t OED - 20 - 15 - 15 ns Output Disable Delay t ODD - 20 - 15 - 15 ns CLK to SUM Output Delay t ODS - 27 - 25 - 21 ns Output Rise t OR Note 5 - 6 - 6 - 6 ns Output Fall t OF Note 5 - 6 - 6 - 6 ns Note 5 NOTE: 5. Controlled by design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. Test Load Circuit S1 DUT (NOTE 6) CL IOH ± 1.5V EQUIVALENT CIRCUIT NOTES: 6. Includes stray and jig capacitance. 7. Switch S1 Open for ICCSB and ICCOP Tests. 20 IOL HSP43881 Waveforms 4.0V 2.0V tCP 0.0V CLK tCH t IS tCL 2.0V 2.0V 3.0V INPUT† 0.0V 2.0V CLK † tIH 1.5V 1.5V Input includes: DIN0-7, CIN0-7, DIENB, CIENB, ERASE, RESET,DCM0-1, ADRO-2, TCS, TCCI, SHADD FIGURE 8. CLOCK AC PARAMETERS FIGURE 9. INPUT SETUP AND HOLD 2.0V CLK 2.0V tODC, tODS 0.8V SUM0-25 1.5V COUT0-7 tOR TCCO † SUM-25, COUTO-7, TCCO are assumed not to be in highimpedance state. FIGURE 10. SUM0-25, COUT0-7, TCCO OUTPUT DELAYS SENBL SENBH COENB FIGURE 11. OUTPUT RISE AND FALL TIMES 3.0V 1.5V 1.5V 1.5V INPUT 0.0V tOED SUM0-25 COUT0-7 TCCO tOF HIGH IMPEDANCE DEVICE UNDER TEST 1.5V OUTPUT tODD 1.7V 1.3V HIGH IMPEDANCE FIGURE 12. OUTPUT ENABLE, DISABLE TIMING NOTE: AC Testing: Inputs are driven at 3.0V for Logic and “1” and 0.0V for Logic “0”. Input and output timing measurements are made at 1.5 for both a Logic “1” and “0”. CLK is driven at 4.0 and 0V and measured at 2.0V. FIGURE 13. AC TESTING INPUT, OUTPUT WAVEFORM All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. 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