a FEATURES DC Performance 400 mA max Quiescent Current 10 pA max Bias Current, Warmed Up (AD648C) 300 mV max Offset Voltage (AD648C) 3 mV/8C max Drift (AD648C) 2 mV p-p Noise, 0.1 Hz to 10 Hz AC Performance 1.8 V/ms Slew Rate 1 MHz Unity Gain Bandwidth Available in Plastic Mini-DIP, Cerdip, Plastic SOIC and Hermetic Metal Can Packages MIL-STD-883B Parts Available Surface Mount (SOIC) Package Available in Tape and Reel in Accordance with EIA-481A Standard Single Version: AD548 PRODUCT DESCRIPTION The AD648 is a matched pair of low power, precision monolithic operational amplifiers. It offers both low bias current (10 pA max, warmed up) and low quiescent current (400 µA max) and is fabricated with ion-implanted FET and laser wafer trimming technologies. Input bias current is guaranteed over the AD648’s entire common-mode voltage range. The economical J grade has a maximum guaranteed offset voltage of less than 2 mV and an offset voltage drift of less than 20 µV/°C. The C grade reduces offset voltage to less than 0.30 mV and offset voltage drift to less than 3 µV/°C. This level of dc precision is achieved utilizing Analog’s laser wafer drift trimming process. The combination of low quiescent current and low offset voltage drift minimizes changes in input offset voltage due to self-heating effects. Five additional grades are offered over the commercial, industrial and military temperature ranges. The AD648 is recommended for any dual supply op amp application requiring low power and excellent dc and ac performance. In applications such as battery-powered, precision instrument front ends and CMOS DAC buffers, the AD648’s excellent combination of low input offset voltage and drift, low bias current and low 1/f noise reduces output errors. High common-mode rejection (86 dB, min on the “C” grade) and high open-loop gain ensures better than 12-bit linearity in high impedance, buffer applications. The AD648 is pinned out in a standard dual op amp configuration and is available in seven performance grades. The AD648J and AD648K are rated over the commercial temperature range of 0°C to +70°C. The AD648A, AD648B and AD648C are rated over the industrial temperature range of –40°C to +85°C. Dual Precision, Low Power BiFET Op Amp AD648 CONNECTION DIAGRAMS The AD648S and AD648T are rated over the military temperature range of –55°C to +125°C and are available processed to MIL-STD-883B, Rev. C. The AD648 is available in an 8-pin plastic mini-DIP, cerdip, SOIC, TO-99 metal can, or in chip form. PRODUCT HIGHLIGHTS 1. A combination of low supply current, excellent dc and ac performance and low drift makes the AD648 the ideal op amp for high performance, low power applications. 2. The AD648 is pin compatible with industry standard dual op amps such as the LF442, TL062, and AD642, enabling designers to improve performance while achieving a reduction in power dissipation of up to 85%. 3. Guaranteed low input offset voltage (2 mV max) and drift (20 µV/°C max) for the AD648J are achieved utilizing Analog Devices’ laser drift trimming technology. 4. Analog Devices specifies each device in the warmed-up condition, insuring that the device will meet its published specifications in actual use. 5. Matching characteristics are excellent for all grades. The input offset voltage matching between amplifiers in the AD648J is within 2 mV, for the C grade matching is within 0.4 mV. 6. Crosstalk between amplifiers is less than –120 dB at 1 kHz. 7. The AD648 is available in chip form. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD648–SPECIFICATIONS (@ + 258C and V = 615 V dc, unless otherwise noted) S Model Min INPUT OFFSET VOLTAGE 1 Initial Offset TMIN to TMAX vs. Temperature vs. Supply vs. Supply, T MIN to TMAX Long-Term Offset Stability AD648J/A/S Typ Max 0.75 2.0 3.0/3.0/3.0 20 80 76/76/76 AD648K/B/T Typ Max 0.3 15 5 5 MATCHING CHARACTERISTICS 3 Input Offset Voltage Input Offset Voltage T MIN to T MAX Input Offset Voltage vs. Temperature Input Bias Current Crosstalk 1.0 20 0.45/1.3/20 2 2.0 3.0/3.0/3.0 0.5 10 0.65 pA nA 15 5 0.35 pA pA nA 0.4 0.5 –120 mV mV µV/°C pA dB 1 × 1012i3 3 × 1012i3 ΩipF ΩipF 3 15 5 0.15/0.35/5 2 1.0 1.5/1.5/2.0 0.2 5 10 2.5 5 –120 5 –120 1 × 1012i3 3 × 1012i3 1 × 101 2i3 3 × 1012i3 ± 11 mV mV µV/°C dB dB µV/month 15 10 0.25/0.65/10 ± 20 ± 12 ± 11 76 76/76/76 70 70/70/70 ± 20 ± 12 ± 11 82 82 76 76 Units 0.3 0.5 3.0 86 80 3 30 10 0.25/0.7/10 AD648C Typ Max 0.10 15 8 INPUT IMPEDANCE Differential Common Mode Min 1.0 1.5/1.5/2.0 10 86 80 INPUT BIAS CURRENT Either Input, 2 VCM = 0 Either Input 2 at TMAX, VCM = 0 Max Input Bias Current Over Common-Mode Voltage Range Offset Current, V CM = 0 Offset Current at T MAX INPUT VOLTAGE RANGE Differential 4 Common Mode Common-Mode Rejection VCM = ± 10 V TMIN to TMAX VCM = ± 11 V TMIN to TMAX Min ± 20 ± 12 V V 86 86 76 76 dB dB dB dB INPUT VOLTAGE NOISE Voltage 0.1 Hz to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz 2 80 40 30 30 2 80 40 30 30 2 80 40 30 30 INPUT CURRENT NOISE f = 1 kHz 1.8 1.8 1.8 fA/√Hz 1.0 30 1.8 8 MHz kHz V/µs µs FREQUENCY RESPONSE Unity Gain, Small Signal Full Power Response Slew Rate, Unity Gain Settling Time to ± 0.01% OPEN-LOOP GAIN VO = ± 10 V, RL ≥ 10 kΩ TMIN to TMAX, RL ≥ 10 kΩ VO = ± 10 V, R L ≥ 5 kΩ TMIN to TMAX, RL ≥ 5 kΩ OUTPUT CHARACTERISTICS Voltage @ R L ≥ 10 kΩ, TMIN to TMAX Voltage @ R L ≥ 5 kΩ, TMIN to TMAX Short Circuit Current POWER SUPPLY Rated Performance Operating Range Quiescent Current (Both Amplifiers) TEMPERATURE RANGE Operating, Rated Performance Commercial (0°C to +70°C) Industrial (–40°C to +85°C) Military (–55°C to +125°C) PACKAGE OPTIONS SOIC (R-8) Plastic (N-8) Cerdip (Q-8) Metal Can (H-08A) Tape and Reel Chips Available 0.8 1.0 30 1.8 8 0.8 300 300/300/300 150 150/150/150 1000 700 500 300 ± 12/± 12/± 12 ± 11/± 11/± 11 1.0 ± 4.5 4.0 µV p-p nV/√Hz nV/√Hz nV/√Hz nV/√Hz 1.0 30 1.8 8 0.8 300 300 150 150 1000 700 500 300 300 300 150 150 1000 700 500 300 V/mV V/mV V/mV V/mV ± 13 ± 12 ± 13 ± 12 ± 13 V ± 12 15 ± 11 ± 12 15 ± 11 ± 12 15 V mA ± 15 340 1.0 ± 18 400 ± 4.5 ± 15 340 AD648J AD648A AD648S 1.0 ± 18 400 AD648K AD648B AD648T AD648JR AD648JN AD648AQ, AD648SQ, AD648SQ/883B AD648AH AD648JR-REEL, AD648JR-REEL7 AD648JChips, AD648SChips –2– AD648KR AD648KN AD648BQ, AD648TQ/883B AD648BH, AD648TH/883B AD648KR-REEL, AD648KR-REEL7 ± 4.5 ± 15 340 ± 18 400 V V µA AD648C AD648CQ REV. C AD648 NOTES 1 Input Offset Voltage specifications are guaranteed after 5 minutes of operation at T A = +25°C. 2 Bias Current specifications are guaranteed maximum at either input after 5 minutes of operation at T A = +25°C. For higher temperature, the current doubles every 10°C. 3 Matching is defined as the difference between parameters of the two amplifiers. 4 Defined as voltages between inputs, such that neither exceeds ± 10 V from ground. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS 1 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 500 mW Input Voltage3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite Differential Input Voltage . . . . . . . . . . . . . . . . . . +VS and –VS Storage Temperature Range (Q, H) . . . . . . . . –65°C to +150°C Storage Temperature Range (N, R) . . . . . . . . –65°C to +125°C Operating Temperature Range AD648J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C AD648A/B/C . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C AD648S/T . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C NOTES 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Thermal Characteristics: 8-Pin Plastic Package: θJA = 165°C/Watt 8-Pin Cerdip Package: θJC = 22°C/Watt; θJA = 110°C/Watt 8-Pin Metal Package: θJC = 65°C/Watt; θJA = 150°C/Watt 8-Pin SOIC Package: θJC = 42°C/Wat; θJA = 160°C/Watt 3 For supply voltages less than ± 18 V, the absolute maximum input voltage is equal to the supply voltage. METALIZATION PHOTOGRAPH Contact factory for latest dimensions. Dimensions shown in inches and (mm). CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD648 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. C –3– WARNING! ESD SENSITIVE DEVICE AD648—Typical Characteristics –4– REV. C AD648 REV. C –5– AD648 APPLICATION NOTES The AD648 is a pair of JFET-input op amps with a guaranteed maximum IB of less than 10 pA, and offset and drift lasertrimmed to 0.3 mV and 3 µV/°C, respectively (AD648C). AC specs include 1 MHz bandwidth, 1.8 V/µs typical slew rate and 8 µs settling time for a 20 V step to ± 0.01%—all at a supply current less than 400 µA. To capitalize on the device’s performance, a number of error sources should be considered. The minimal power drain and low offset drift of the AD648 reduce self-heating or “warm-up” effects on input offset voltage, making the AD648 ideal for on/off battery powered applications. The power dissipation due to the AD648’s 400 µA supply current has a negligible effect on input current, but heavy output loading will raise the chip temperature. Since a JFET’s input current doubles for every 10°C rise in chip temperature, this can be a noticeable effect. Figure 22. Board Layout for Guarding Inputs INPUT PROTECTION The AD648 is guaranteed to withstand input voltages equal to the power supply potential. Exceeding the negative supply voltage on either input will forward bias the substrate junction of the chip. The induced current may destroy the amplifier due to excess heat. The amplifier is designed to be functional with power supply voltages as low as ± 4.5 V. It will exhibit a higher input offset voltage than at the rated supply voltage of ± 15 V, due to power supply rejection effects. Common-mode range extends from 3 V more positive than the negative supply to 1 V more negative than the positive supply. Designed to cleanly drive up to 10 kΩ and 100 pF loads, the AD648 will drive a 2 kΩ load with reduced open-loop gain. Input protection is required in applications such as a flame detector in a gas chromatograph, where a very high potential may be applied to the input terminals during a sensor fault condition. Figures 23a and 23b show simple current limiting schemes that can be used. RPROTECT should be chosen such that the maximum overload current is 1.0 mA (for example 100 kΩ for a 100 V overload). Figure 21 shows the recommended crosstalk test circuit. A typical value for crosstalk is –120 dB at 1 kHz. Figure 23a. Input Protection of l-to-V Converter Figure 21. Crosstalk Test Circuit LAYOUT To take full advantage of the AD648’s 10 pA max input current, parasitic leakages must be kept below an acceptable level. The practical limit of the resistance of epoxy or phenolic circuit board material is between 1 × 1012 Ω and 3 × 1012 Ω. This can result in an additional leakage of 5 pA between an input of 0 V and a –15 V supply line. Teflon or a similar low leakage material (with a resistance exceeding 1017 Ω) should be used to isolate high impedance input lines from adjacent lines carrying high voltages. The insulator should be kept clean, since contaminants will degrade the surface resistance. Figure 23b. Voltage Follower Input Protection Method Figure 23b shows the recommended method for protecting a voltage follower from excessive currents due to high voltage breakdown. The protection resistor, RP, limits the input current. A nominal value of 100 kΩ will limit the input current to less than 1 mA with a 100 volt input voltage applied. A metal guard completely surrounding the high impedance nodes and driven by a voltage near the common-mode input potential can also be used to reduce some parasitic leakages. The guarding pattern in Figure 22 will reduce parasitic leakage due to finite board surface resistance; but it will not compensate for a low volume resistivity board. The stray capacitance between the summing junction and ground will produce a high frequency roll-off with a corner frequency equal to: f corner = 1 2 π RP Cstray Accordingly, a 100 kΩ value for RP with a 3 pF Cstray will cause a 3 dB corner frequency to occur at 531 kHz. –6– REV. C AD648 Figure 23c shows a diode clamp protection scheme for an I-to-V converter using low leakage diodes. Because the diodes are connected to the op amp’s summing junction, which is a virtual ground, their leakage contribution is minimal. CMOS DAC’s output current to a voltage and provides the necessary level shifting to achieve a bipolar voltage output. The circuit operates with a 12-bit plus sign input code. The transfer function is shown in Figure 25. The AD7592 is a fully protected dual CMOS SPDT switch with data latches. R4 and R5 should match to within 0.01% to maintain the accuracy of the converter. A mismatch between R4 and R5 introduces a gain error. Overall gain is trimmed by adjusting RIN. The AD648’s low input offset voltage, low drift over temperature, and excellent dynamics make it an attractive low power output buffer. Figure 23c. I-to-V Converter with Diode Input Protection Exceeding the negative common-mode range on either input terminal causes a phase reversal at the output, forcing the amplifier output to the corresponding high or low state. Exceeding the negative common mode on both inputs simultaneously forces the output high. Exceeding the positive common-mode range on a single input doesn’t cause a phase reversal; but if both inputs exceed the limit, the output will be forced high. In all cases, normal amplifier operation is resumed when input voltages are brought back within the common-mode range. D/A CONVERTER BIPOLAR OUTPUT BUFFER The circuit in Figure 24 provides 4 quadrant multiplication with a resolution of 12 bits. The AD648 is used to convert the AD7545 The input offset voltage of the AD648 output amplifier results in an output error voltage. This error voltage equals the input offset voltage of the op amp times the noise gain of the amplifier. That is: R VOS Output = VOS Input 1 + FB RO RFB is the feedback resistor for the op amp, which is internal to the DAC. RO is the DAC’s R-2R ladder output resistance. The value of RO is code dependent. This has the effect of changing the offset error voltage at the amplifier’s output. An output amplifier with a sub millivolt input offset voltage is needed to preserve the linearity of the DAC’s transfer function. Figure 24. 12-Bit Plus Sign Magnitude D/A Converter SIGN BIT BINARY NUMBER IN DAC REGISTER ANALOG OUTPUT 0 0 1 1 1111 0000 0000 1111 1111 0000 0000 1111 +VIN 3 (4095/4096) 0 VOLTS 0 VOLTS –VIN 3 (4095/4096) 1111 0000 0000 1111 NOTE: SIGN BIT AT "0" CONNECTS THE NONINVERTING INPUT OF A2 TO ANALOG COMMON Figure 25. Sign Magnitude Code Table REV. C –7– AD648 DUAL PHOTODIODE PREAMP The AD648 in this configuration provides a 700 kHz small signal bandwidth and 1.8 V/µs typical slew rate. The 33 pF capacitor across the feedback resistor optimizes the circuit’s response. The oscilloscope photos in Figures 26a and 26b show small and large signal outputs of the circuit in Figure 24. Upper traces show the input signal VIN. Lower traces are the resulting output voltage with the DAC’s digital input set to all 1s. The circuit settles to ± 0.01% for a 20 V input step in 14 µs. The performance of the dual photodiode preamp shown in Figure 27 is enhanced by the AD648’s low input current, input voltage offset, and offset voltage drift. Each photodiode sources a current proportional to the incident light power on its surface. RF converts the photodiode current to an output voltage equal to RF × IS. An error budget illustrating the importance of low amplifier input current, voltage offset, and offset voltage drift to minimize output voltage errors can be developed by considering the equivalent circuit for the small (0.2 mm2 area) photodiode shown in Figure 27. The input current results in an error proportional to the feedback resistance used. The amplifier’s offset will produce an error proportional to the preamp’s noise gain (1+RF/RSH), where RSH is the photodiode shunt resistance. The amplifier’s input current will double with every 10°C rise in temperature, and the photodiode’s shunt resistance halves with every 10°C rise. The error budget in Figure 28 assumes a room temperature photodiode RSH of 500 MΩ, and the maximum input current and input offset voltage specs of an AD648C. The capacitance at the amplifier’s negative input (the sum of the photodiode’s shunt capacitance, the op amp’s differential input capacitance, stray capacitance due to wiring, etc.) will cause a rise in the preamp’s noise gain over frequency. This can result in excess noise over the bandwidth of interest. CF reduces the noise gain “peaking” at the expense of signal bandwidth. Figure 26a. Response to ± 20 V p-p Reference Square Wave Figure 26b. Response to ± 100 mV p-p Reference Square Wave Figure 27. A Dual Photodiode Pre-Amp TEMP 8C RSH (MV) VOS (mV) (1 + RF/RSH) VOS IB (pA) IBRF TOTAL –25 0 +25 +50 +75 +85 15,970 2,830 500 88.5 15.6 7.8 150 225 300 375 450 480 151 mV 233 mV 360 mV 800 mV 3.33 mV 6.63 mV 0.30 2.26 10.00 56.6 320 640 30 mV 262 mV 1.0 mV 5.6 mV 32 mV 64 mV 181 mV 495 mV 1.36 mV 6.40 mV 35.3 mV 70.6 mV Figure 28. Photodiode Pre-Amp Errors Over Temperature –8– REV. C AD648 INSTRUMENTATION AMPLIFIER The AD648J’s maximum input current of 20 pA per amplifier makes it an excellent building block for the high input impedance instrumentation amplifier shown in Figure 29. Total current drain for this circuit is under 600 µA. This configuration is optimal for conditioning differential voltages from high impedance sources. The overall gain of the circuit is controlled by RG, resulting in the following transfer function: VOUT (R3 + R4) = 1+ V IN RG Gains of 1 to 100 can be accommodated with gain nonlinearities of less than 0.01%. The maximum input current is 30 pA over the common-mode range, with a common-mode impedance of over 1 × 1012Ω. The capacitors C1, C2, C3 and C4 compensate for peaking in the gain over frequency which is caused by input capacitance. To calibrate this circuit, first adjust trimmer R1 for commonmode rejection with +10 volts dc applied to the input pins. Next, adjust R2 for zero offset at VOUT with both inputs grounded. Trim the circuit a second time for optimal performance. The –3 dB small signal bandwidth for this low power instrumentation amplifier is 700 kHz for a gain of 1 and 10 kHz for a gain of 100. The typical output slew rate is 1.8 V/µs. Figure 29. Low Power Instrumentation Amplifier REV. C –9– AD648 LOG RATIO AMPLIFIER Log ratio amplifiers are useful for a variety of signal conditioning applications, such as linearizing exponential transducer outputs and compressing analog signals having a wide dynamic range. The AD648’s picoamp level input current and low input offset voltage make it a good choice for the front-end amplifier of the log ratio circuit shown in Figure 30. This circuit produces an output voltage equal to the log base 10 of the ratio of the input currents I1 and I2. Resistive inputs R1 and R2 are provided for voltage inputs. Input currents I1 and I2 set the collector currents of Q1 and Q2, a matched pair of logging transistors. Voltages at points A and B are developed according to the following familiar diode equation: VBE = (kT/q) ln (IC/IES) In this equation, k is Boltzmann’s constant, T is absolute temperature, q is an electron charge, and IES is the reverse saturation current of the logging transistors. The difference of these two voltages is taken by the subtractor section and scaled by a factor of approximately 16 by resistors R9, R10 and R8. Temperature compensation is provided by resistors R8 and R15, which have a positive 3500 ppm/°C temperature coefficient. The transfer function for the output voltage is: VOUT = 1 V log10 (I2/I1) Frequency compensation is provided by R11, R12, C1, and C2. Small signal bandwidth is approximately 300 kHz at input currents above 100 µA and will proportionally decrease with lower signal levels. D1, D2, R13, and R14 compensate for the effects of the two logging transistors’ ohmic emitter resistance. To trim this circuit, set the two input currents to 10 µA and adjust VOUT to zero by adjusting the potentiometer on A3. Then set I2 to 1 µA and adjust the scale factor such that the output voltage is 1 V by trimming potentiometer R10. Offset adjustment for A1 and A2 is provided to increase the accuracy of the voltage inputs. This circuit ensures a 1% log conformance error over an input current range of 300 pA to l mA, with low level accuracy limited by the AD648’s input current. The low level input voltage accuracy of this circuit is limited by the input offset voltage and drift of the AD648. Figure 30. Precision Log Ratio Amplifier –10– REV. C AD648 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). REV. C –11– –12– PRINTED IN U.S.A. C1023–5–10/88