MC100EP809 3.3V1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable The MC100EP809 is a low skew 1–to–9 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low voltage applications which require a large number of outputs to drive precisely aligned low skew signals to their destination. The two clock inputs are differential HSTL or PECL and they are selected by the CLK_SEL pin which is LVTTL. To avoid generation of a runt clock pulse when the device is enabled/disabled, the Output Enable (OE), which is LVTTL, is synchronous ensuring the outputs will only be enabled/disabled when they are already in LOW state (See Figure 8). The MC100EP809 guarantees low output–to–output skew. The optimal design, layout, and processing minimize skew within a device and from lot to lot. The MC100EP809 output structure uses open emitter architecture and will be terminated with 50 to ground instead of a standard HSTL configuration (See Figure 6). To ensure the tight skew specification is realized, both sides of the differential output need to be terminated identically into 50 even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew. Designers can take advantage of the EP809’s performance to distribute low skew clocks across the backplane of the board. HSTL clock inputs may be driven single–end by biasing the non–driven pin in an input pair (see Figure 7). • 100 ps Typical Device–to–Device Skew • 15 ps Typical Within Device Skew • HSTL Compatible Outputs Drive 50 to Ground with no Offset Voltage Maximum Frequency > 750 MHz 850 ps Typical Propagation Delay • • • Fully Compatible with Micrel SY89809L • PECL and HSTL Mode Operating Range: VCCI = 3 V to 3.6 V http://onsemi.com MARKING DIAGRAM* MC100 EP809 32–LEAD LQFP FA SUFFIX CASE 873A AWLYYWW 32 1 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week *For additional information, see Application Note AND8002/D ORDERING INFORMATION Device Package Shipping MC100EP809FA LQFP–32 250 Units/Tray MC100EP809FAR2 LQFP–32 2000/Tape & Reel with GND = 0 V, VCCO = 1.6 V to 2.0 V • Open Input Default State Semiconductor Components Industries, LLC, 2002 August, 2002 – Rev. 5 1 Publication Order Number: MC100EP809/D VCCO Q3 Q3 Q4 Q4 Q5 Q5 VCCO MC100EP809 24 23 22 21 20 19 18 17 VCCO 25 16 VCCO Q2 26 15 Q6 Q2 27 14 Q6 Q1 28 13 Q7 Q1 29 12 Q7 Q0 30 11 Q8 Q0 31 10 Q8 VCCO 32 MC100EP809 4 5 6 HSTL_CLK HSTL_CLK CLK_SEL LVPECL_CLK LVPECL_CLK 7 8 OE 3 GND 2 VCCI 9 1 VCCO All VCCI, VCCO, and GND pins must be externally connected to appropriate Power Supply to guarantee proper operation (VCCI VCCO). Figure 1. 32–Lead LQFP Pinout (Top View) PIN DESCRIPTION FUNCTION TABLE PIN FUNCTION HSTL_CLK*, HSTL_CLK** LVPECL_CLK*, LVPECL_CLK** CLK_SEL** OE** Q0–Q8, Q0–Q8 VCCI VCCO HSTL or LVDS Differential Inputs LVPECL Differential Inputs LVCMOS/LVTTL Input CLK Select LVCMOS/LVTTL Output Enable HSTL Differential Outputs Positive Supply_Core (3.0 V – 3.6 V) Positive Supply_HSTL Outputs (1.6 V – 2.0 V) Ground GND OE* CLK_SEL Q0–Q8 Q0–Q8 L L H H L H L H L L HSTL_CLK LVPECL_CLK H H HSTL_CLK LVPECL_CLK * The OE (Output Enable) signal is synchronized with the rising edge of the HSTL_CLK and LVPECL_CLK signal. * Pins will default LOW when left open. ** Pins will default HIGH when left open. CLK_SEL HSTL_CLK 0 9 HSTL_CLK 9 LVPECL_CLK VCCI GND Q0–Q8 (HSTL) Q0–Q8 (HSTL) 1 LVPECL_CLK Q D OE Figure 2. Logic Diagram http://onsemi.com 2 VCCO MC100EP809 ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor 37.5 k ESD Protection Human Body Model Machine Model Charged Device Model > 2 kV > 200 V > 2 kV Moisture Sensitivity (Note 1) Level 2 Flammability Rating Oxygen Index: 28 to 34 UL 94 V–0 @ 0.125 in Transistor Count 478 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, refer to Application Note AND8003/D. MAXIMUM RATINGS (Note 2) Parameter Symbol Condition 1 Condition 2 Rating Units VCCI Core Power Supply GND= 0 V VCCO= 1.8 V 4 V VCCO HSTL Output Power Supply GND= 0 V VCCI = 3.3 V 4 V VI PECL Mode Input Voltage GND = 0 V VI ≤ VCCI 6 V Iout Output Current Continuous Surge 50 100 mA mA TA Operating Temperature Range 0 to +85 °C Tstg Storage Temperature Range –65 to +150 °C JA Thermal Resistance (Junction–to–Ambient) 0 LFPM 500 LFPM 32 LQFP 32 LQFP 80 55 °C/W °C/W JC Thermal Resistance (Junction–to–Case) std bd 32 LQFP 12 to 17 °C/W Tsol Wave Solder < 2 to 3 sec @ 248°C 265 °C 2. Maximum Ratings are those values beyond which device damage may occur. LVPECL DC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V 0°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 75 95 115 75 95 115 75 95 115 mA ICC Core Power Supply Current VIH Input HIGH Voltage (Single–Ended) VCCI– 1.165 VCCI –0.88 VCCI– 1.165 VCCI –0.88 VCCI– 1.165 VCCI –0.88 V VIL Input LOW Voltage (Single–Ended) VCCI– 1.945 VCCI –1.6 VCCI– 1.945 VCCI –1.6 VCCI– 1.945 VCCI –1.6 V 1.2 VCCI 1.2 VCCI 1.2 VCCI V VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 3) (Figure 4) LVPECL_CLK/LVPECL_CLK IIH Input HIGH Current –150 150 –150 150 –150 150 A IIL Input LOW Current –150 150 –150 150 –150 150 A NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 3. VIHCMR max varies 1:1 with VCCI. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 3 MC100EP809 LVTTL/LVCMOS DC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V 0°C Symbol Characteristic Min Typ 25°C Max Min Max VIH Input HIGH Voltage VIL Input LOW Voltage IIH Input HIGH Current –150 150 –150 150 IIL Input LOW Current –300 300 –300 300 NOTE: 2.0 Typ 85°C 2.0 Min Typ Max 2.0 0.8 Unit V 0.8 0.8 V –150 150 A –300 300 A 100EP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. HSTL DC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V 0°C Symbol Characteristic Min 25°C Typ Max Min Typ 85°C Max Min Typ Max Unit VOH Output HIGH Voltage (Note 4) 1.0 1.2 1.0 1.2 1.0 1.2 V VOL Output LOW Voltage (Note 4) 0.1 0.4 0.1 0.4 0.1 0.4 V VIH Input HIGH Voltage (Figure 5) VX+0.1 – 1.6 VX+0.1 – 1.6 VX+0.1 – 1.6 V VIL Input LOW Voltage (Figure 5) –0.3 – VX–0.1 –0.3 – VX–0.1 –0.3 – VX–0.1 V VX HSTL Input Crossover Voltage 0.68 – 0.9 0.68 – 0.9 0.68 – 0.9 V IIH Input HIGH Current –150 150 –150 150 –150 150 A IIL Input LOW Current –300 300 –300 300 –300 300 A 0.6 VCCI –1.2 0.6 VCCI –1.2 0.6 VCCI –1.2 V V VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 5) HSTL_CLK/HSTL_CLK NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 4. All outputs loaded with 50 to GND (See Figure 6). 5. VIHCMR max varies 1:1 with VCCI. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 MC100EP809 AC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V (Note 6) 0°C 25°C Min Typ fout < 100 MHz fout < 500 MHz fout < 750 MHz 600 600 450 850 750 575 tPLH tPHL Propagation Delay (Differential) LVPECL_CLK to Q HSTL_CLK to Q 680 690 800 830 930 990 tskew Within–Device Skew (Note 7) Device–to–Device Skew (Note 8) 15 100 Random Clock Jitter (Figure 3) (RMS) 1.4 Symbol VOpp Differential Output Voltage (Figure 3) tJITTER VPP Characteristic Max 85°C Min Typ Max Min Typ 600 600 450 850 750 575 700 700 820 850 950 1000 50 200 15 100 3.0 1.4 Max 600 600 450 850 750 575 780 790 920 950 1070 1110 ps ps 50 200 15 100 50 200 ps ps 3.0 1.4 3.0 ps Unit mV mV Input Swing (Differential Mode) (Note 10) (Figure 4) LVPECL HSTL 200 200 200 200 200 200 mV mV tS OE Set Up Time (Note 9) 0.5 0.5 0.5 ns tH OE Hold Time 0.5 0.5 0.5 ns tr/tf Output Rise/Fall Time (20%–80%) 350 600 350 450 600 350 600 ps 6. Measured with 750 mV (LVPECL) source or 1 V (HSTL) source, 50% duty cycle clock source. All outputs loaded with 50 to Ground (See Figure 6). 7. Skew is measured between outputs under identical transitions and conditions on any one device. 8. Device–to–Device skew for identical transitions and conditions. 9. OE Set Up Time is defined with respect to the rising edge of the clock. OE High–to–Low transition ensures outputs remain disabled during the next clock cycle. OE Low–to–High transition enables normal operation of the next input clock (See Figure 8). 10. VPP is the Differential Input Voltage swing required to maintain AC characteristics listed herein. 900 9 800 8 VOPP 7 600 6 500 5 400 4 300 3 tJITTER ps (RMS) VOPP (mV) 700 RMS JITTER 200 2 100 1 0 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz) Figure 3. Output Frequency (FOUT) versus Output Voltage (VOPP) and Random Clock Jitter (tJITTER) http://onsemi.com 5 MC100EP809 VCCI VCCO(HSTL) VCCI(LVPECL) VIH(DIFF) VX VIH(DIFF) VIHCMR VPP VIL(DIFF) VIL(DIFF) VPP GND Figure 4. LVPECL Differential Input Levels GND Figure 5. HSTL Differential Input Levels Z = 50 Q HSTL OUTPUT Q 50 50 GROUND Figure 6. HSTL Output Termination and AC Test Reference CLK/CLK D.C. Bias* *Must fall within 680 to 900 mV (Preferably (VIH + VIL)/2). Figure 7. HSTL Single–Ended Input Configuration CLK CLK OE Q Q Figure 8. Output Enable (OE) Timing Diagram Resource Reference of Application Notes AN1405 – ECL Clock Distribution Techniques AN1406 – Designing with PECL (ECL at +5.0 V) AND8002 – Marking and Date Codes AND8009 – ECLinPS Plus Spice I/O Model Kit AND8020 – Termination of ECL Logic Devices For an updated list of Application Notes, please see our website at http://onsemi.com. http://onsemi.com 6 MC100EP809 PACKAGE DIMENSIONS A 32 –T–, –U–, –Z– LQFP FA SUFFIX 32–LEAD PLASTIC PACKAGE CASE 873A–02 ISSUE A 4X A1 0.20 (0.008) AB T-U Z 25 1 AE –U– –T– B P V AE B1 DETAIL Y 9 4X –Z– 9 DETAIL Y V1 17 8 0.20 (0.008) AC T-U Z S1 S 0.10 (0.004) AC ÉÉ ÉÉ ÉÉ N F D J 8X SECTION AE–AE M R K X DETAIL AD Q GAUGE PLANE W 0.250 (0.010) C E H M BASE METAL –AC– 0.20 (0.008) –AB– SEATING PLANE AC T-U Z DETAIL AD G http://onsemi.com 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12 REF 0.090 0.160 0.400 BSC 1 5 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12 REF 0.004 0.006 0.016 BSC 1 5 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF MC100EP809 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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