NXP HEF4043BT Quad r/s latch with 3-state output Datasheet

HEF4043B
Quad R/S latch with 3-state outputs
Rev. 06 — 11 November 2008
Product data sheet
1. General description
The HEF4043B is a quad R/S latch with 3-state outputs with a common output enable
input (OE). Each latch has an active HIGH set input (1S to 4S), an active HIGH reset input
(1R to 4R) and an active HIGH 3-state output (1Q to 4Q).
When OE is HIGH, the latch output (nQ) is determined by the nR and nS inputs as shown
in Table 3. When OE is LOW, the latch outputs are in the high impedance OFF-state. OE
does not affect the state of the latch. The high impedance off-state feature allows common
bussing of the outputs.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is
also suitable for use over the industrial (−40 °C to +85 °C) temperature range.
2. Features
n
n
n
n
n
n
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Operates across the full industrial temperature range −40 °C to +85 °C
Complies with JEDEC standard JESD 13-B
ESD protection:
u HBM JESD22-A114E exceeds 2000 V
u MM JESD22-A115-A exceeds 200 V
3. Applications
n Four-bit storage with output enable
4. Ordering information
Table 1.
Ordering information
All types operate from −40 °C to +85 °C.
Type number
Package
Name
Description
Version
HEF4043BP
DIP16
plastic dual in-line package; 16-leads (300 mil)
SOT38-4
HEF4043BT
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
HEF4043B
NXP Semiconductors
Quad R/S latch with 3-state outputs
5. Functional diagram
4 1S
1Q 2
3 1R
6 2S
2Q 9
7 2R
12 3S
3-STATE
OUTPUTS
nS
nQ
3Q 10
11 3R
nR
14 4S
4Q 1
15 4R
nOE
5 OE
to other latches
001aae616
Fig 1.
001aae618
Functional diagram
Fig 2.
Logic diagram for one latch
6. Pinning information
6.1 Pinning
HEF4043B
4Q
1
16 VDD
1Q
2
15 4R
1R
3
14 4S
1S
4
13 n.c.
OE
5
12 3S
2S
6
11 3R
2R
7
10 3Q
VSS
8
9
2Q
001aae617
Fig 3.
Pin configuration
HEF4043B_6
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 06 — 11 November 2008
2 of 13
HEF4043B
NXP Semiconductors
Quad R/S latch with 3-state outputs
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1Q to 4Q
2, 9, 10, 1
3-state buffered latch output
1R to 4R
3, 7, 11, 15
reset input (active HIGH)
1S to 4S
4, 6, 12, 14
set input (active HIGH)
OE
5
common output enable input
VSS
8
ground supply voltage
n.c.
13
not connected
VDD
16
supply voltage
7. Functional description
Table 3.
Function table[1]
Inputs
Output
OE
nS
nR
nQ
L
X
X
Z
H
L
H
L
H
H
X
H
H
L
L
latched
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high impedance state.
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
supply voltage
Conditions
Min
Max
Unit
−0.5
+18
V
VI
input voltage
−0.5
VDD + 0.5
V
IIK
input clamping current
VI < 0.5 V or VI > VDD + 0.5 V
-
±10
mA
IOK
output clamping current
VO < 0.5 V or VO > VDD + 0.5 V
-
±10
mA
II/O
input/output current
-
±10
mA
Tstg
storage temperature
−65
+150
°C
Tamb
ambient temperature
−40
+85
°C
Ptot
total power dissipation
P
power dissipation
Tamb −40 °C to +85 °C
DIP16 package
[1]
-
750
mW
SO16 package
[2]
-
500
mW
-
100
mW
per output
[1]
For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C.
[2]
For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.
HEF4043B_6
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 06 — 11 November 2008
3 of 13
HEF4043B
NXP Semiconductors
Quad R/S latch with 3-state outputs
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
VDD
Conditions
Min
Typ
Max
Unit
supply voltage
3
-
15
V
VI
input voltage
0
-
VDD
V
Tamb
ambient temperature
in free air
−40
-
+85
°C
∆t/∆V
input transition rise and fall rate
VDD = 5 V
-
-
3.75
ns/V
VDD = 10 V
-
-
0.5
ns/V
VDD = 15 V
-
-
0.08
ns/V
10. Static characteristics
Table 6.
Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter
VIH
VIL
VOH
VOL
IOH
IOL
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
HIGH-level output current
LOW-level output current
Conditions
|IO| < 1 µA
|IO| < 1 µA
|IO| < 1 µA
input leakage current
IOZ
OFF-state output current
Tamb = −40 °C Tamb = 25 °C
Max
Min
Max
Min
Max
5V
3.5
-
3.5
-
3.5
-
V
10 V
7.0
-
7.0
-
7.0
-
V
15 V
11.0
-
11.0
-
11.0
-
V
5V
-
1.5
-
1.5
-
1.5
V
10 V
-
3.0
-
3.0
-
3.0
V
15 V
-
4.0
-
4.0
-
4.0
V
5V
4.95
-
4.95
-
4.95
-
V
9.95
-
9.95
-
9.95
-
V
15 V
14.95
-
14.95
-
14.95
-
V
5V
-
0.05
-
0.05
-
0.05
V
10 V
-
0.05
-
0.05
-
0.05
V
15 V
-
0.05
-
0.05
-
0.05
V
VO = 2.5 V
5V
−1.7
-
−1.4
-
−1.1
-
mA
VO = 4.6 V
5V
−0.52
-
−0.44
-
−0.36
-
mA
VO = 9.5 V
10 V
−1.3
-
−1.1
-
−0.9
-
mA
VO = 13.5 V
15 V
−3.6
-
−3.0
-
−2.4
-
mA
VO = 0.4 V
5V
0.52
-
0.44
-
0.36
-
mA
VO = 0.5 V
10 V
1.3
-
1.1
-
0.9
-
mA
|IO| < 1 µA
15 V
3.6
-
3.0
-
2.4
-
mA
15 V
-
±0.3
-
±0.3
-
±1.0
µA
nQ output HIGH;
returned to VDD
15 V
-
1.6
-
1.6
-
12.0
µA
nQ output LOW;
returned to VSS
15 V
-
1.6
-
1.6
-
12.0
µA
HEF4043B_6
Product data sheet
Tamb = 85 °C Unit
Min
10 V
VO = 1.5 V
II
VDD
© NXP B.V. 2008. All rights reserved.
Rev. 06 — 11 November 2008
4 of 13
HEF4043B
NXP Semiconductors
Quad R/S latch with 3-state outputs
Table 6.
Static characteristics …continued
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter
IDD
supply current
Conditions
IO = 0 A
VDD
Tamb = 85 °C Unit
Min
Max
Min
Max
Min
Max
5V
-
20
-
20
-
150
µA
10 V
-
40
-
40
-
300
µA
15 V
-
80
-
80
-
600
µA
-
-
-
7.5
-
-
pF
input capacitance
CI
Tamb = −40 °C Tamb = 25 °C
11. Dynamic characteristics
Table 7.
Dynamic characteristics
VSS = 0 V; Tamb = 25 °C; For waveforms and test circuit see Section 12; unless otherwise specified.
Symbol
tPHL
Parameter
Conditions
HIGH to LOW
propagation delay
nR → nQ;
see Figure 4
VDD
Typ
Max
Unit
-
90
180
ns
-
35
70
ns
17 ns + (0.16 ns/pF)CL
-
25
50
ns
38 ns + (0.55 ns/pF)CL
-
65
135
ns
10 V
14 ns + (0.23 ns/pF)CL
-
25
50
ns
15 V
7 ns + (0.16 ns/pF)CL
-
15
35
ns
10 ns + (1.00 ns/pF)CL
-
60
120
ns
10 V
9 ns + (0.42 ns/pF)CL
-
30
60
ns
15 V
6 ns + (0.28 ns/pF)CL
5V
[1]
10 V
15 V
LOW to HIGH
propagation delay
tPLH
transition time
tt
HIGH to OFF-state
propagation delay
tPHZ
LOW to OFF-state
propagation delay
tPLZ
tPZH
tPZL
OFF-state to HIGH
propagation delay
nS → nQ;
see Figure 4
nQ output;
see Figure 4
OE → nQ;
see Figure 5
OE → nQ;
see Figure 5
OE → nQ;
see Figure 5
5V
5V
[1]
[1] [2]
Extrapolation formula
Min
63 ns + (0.55 ns/pF)CL
24 ns + (0.23 ns/pF)CL
-
20
40
ns
5V
-
45
90
ns
10 V
-
20
35
ns
15 V
-
10
25
ns
5V
-
50
100
ns
10 V
-
20
40
ns
15 V
-
10
25
ns
5V
-
25
50
ns
10 V
-
15
30
ns
15 V
-
10
25
ns
5V
-
40
80
ns
10 V
-
20
45
ns
OFF-state to LOW
propagation delay
OE → nQ;
see Figure 5
-
15
pulse width
nS input HIGH;
5V
minimum width; 10 V
see Figure 4
15 V
30
15
-
ns
20
10
-
ns
16
8
-
ns
nR input HIGH; 5 V
minimum width; 10 V
see Figure 4
15 V
30
15
-
ns
20
10
-
ns
16
8
-
ns
15 V
tW
35
ns
[1]
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
[2]
tt is the same as tTHL and tTLH.
HEF4043B_6
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 06 — 11 November 2008
5 of 13
HEF4043B
NXP Semiconductors
Quad R/S latch with 3-state outputs
Table 8.
Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.
Symbol
PD
Parameter
dynamic power
dissipation
VDD
5V
Typical formula for PD (µW)
where:
PD = 1100 × fi + Σ(fo × CL) ×
fi = input frequency in MHz;
VDD2
10 V
PD = 4400 × fi + Σ(fo × CL) × VDD2
15 V
PD = 11400 × fi + Σ(fo × CL) × VDD
fo = output frequency in MHz;
CL = output load capacitance in pF;
2
VDD = supply voltage in V;
Σ(CL × fo) = sum of the outputs.
12. Waveforms
tr
VI
tf
90 %
input nS
VM
0V
10 %
tW
VI
input nR
VM
0V
tW
tPLH
VOH
tPHL
90 %
VM
output nQ
VOL
10 %
tTLH
tTHL
001aai286
tr and tf are the input rise and fall times
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Transition times: transition time (tt) = HIGH LOW (tTHL) or LOW HIGH (tTLH) transition times.
Measurement points are given in Table 9 and test data is given in Table 10.
Fig 4.
Input minimum set (nS) and reset (nR) pulse widths, inputs nS or nR to latch output (nQ) propagation
delay and nQ transition time
HEF4043B_6
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 06 — 11 November 2008
6 of 13
HEF4043B
NXP Semiconductors
Quad R/S latch with 3-state outputs
VDD
VM
OE input
VSS
tPLZ
output
LOW-to-OFF
OFF-to-LOW
tPZL
VDD
VY
VX
VSS
tPHZ
VDD
tPZH
VY
output
HIGH-to-OFF
OFF-to-HIGH
VX
VSS
outputs on
outputs off
outputs on
001aag355
Measurement points are given in Table 9.
Fig 5.
Output enable (OE) to latch output (nQ) enable time (tPZL and tPZH) and disable time (tPLZ and tPHZ)
Table 9.
Measurement points
Supply voltage
Input
Output
VDD
VI
VM
VM
VX
VY
5 V to 15 V
VDD or 0 V
0.5VDD
0.5VDD
0.1VDD
0.9VDD
HEF4043B_6
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 06 — 11 November 2008
7 of 13
HEF4043B
NXP Semiconductors
Quad R/S latch with 3-state outputs
VI
tW
90 %
negative
pulse
VM
0V
tf
tr
tr
tf
VI
90 %
positive
pulse
0V
VM
10 %
VM
VM
10 %
tW
VEXT
VDD
VI
RL
VO
G
DUT
RT
CL
RL
001aai546
Test and measurement data is given in Table 10.
Definitions test circuit:
DUT = Device Under Test.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
Fig 6.
Test circuit for measuring switching times
Table 10.
Test data
Supply voltage
5 V to 15 V
Input
Load
VEXT
VI
tr, tf
CL
RL
tPLH, tPHL
tPLZ, tPZL
tPHZ, tPZH
VDD
≤ 20 ns
50 pF
1 kΩ
open
2VDD
GND
HEF4043B_6
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 06 — 11 November 2008
8 of 13
HEF4043B
NXP Semiconductors
Quad R/S latch with 3-state outputs
13. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
ME
seating plane
D
A2
A
A1
L
c
e
Z
w M
b1
(e 1)
b
b2
MH
9
16
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
b2
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
4.2
0.51
3.2
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
2.54
7.62
3.60
3.05
8.25
7.80
10.0
8.3
0.254
0.76
inches
0.17
0.02
0.13
0.068
0.051
0.021
0.015
0.049
0.033
0.014
0.009
0.77
0.73
0.26
0.24
0.1
0.3
0.14
0.12
0.32
0.31
0.39
0.33
0.01
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
ISSUE DATE
95-01-14
03-02-13
SOT38-4
Fig 7.
EUROPEAN
PROJECTION
Package outline SOT38-4 (DIP16)
HEF4043B_6
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 06 — 11 November 2008
9 of 13
HEF4043B
NXP Semiconductors
Quad R/S latch with 3-state outputs
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.039
0.016
0.028
0.020
inches
0.010 0.057
0.069
0.004 0.049
0.16
0.15
0.05
0.244
0.041
0.228
0.01
0.01
0.028
0.004
0.012
θ
o
8
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
Fig 8.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Package outline SOT109-1 (SO16)
HEF4043B_6
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 06 — 11 November 2008
10 of 13
HEF4043B
NXP Semiconductors
Quad R/S latch with 3-state outputs
14. Abbreviations
Table 11.
Abbreviations
Acronym
Description
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
15. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
HEF4043B_6
20081111
Product data sheet
-
HEF4043B_5
Modifications:
•
•
•
Maximum Tamb changed to 85 °C and Tamb = 125 °C parameter data removed throughout.
Section 1 “General description” temperature range statement modified.
Table 6 “Static characteristics” IOH, IOL, IOZ and IDD values updated.
HEF4043B_5
20080729
Product data sheet
-
HEF4043B_4
HEF4043B_4
20080710
Product data sheet
-
HEF4043B_CNV_3
HEF4043B_CNV_3
19950101
Product specification
-
HEF4043B_CNV_2
HEF4043B_CNV_2
19950101
Product specification
-
-
HEF4043B_6
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 06 — 11 November 2008
11 of 13
HEF4043B
NXP Semiconductors
Quad R/S latch with 3-state outputs
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
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or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
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Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
HEF4043B_6
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 06 — 11 November 2008
12 of 13
HEF4043B
NXP Semiconductors
Quad R/S latch with 3-state outputs
18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11
Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Contact information. . . . . . . . . . . . . . . . . . . . . 12
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 11 November 2008
Document identifier: HEF4043B_6
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