K7A163631B K7A161831B 512Kx36 & 1Mx18 Synchronous SRAM 18Mb B-die Sync. SRAM Specification 100TQFP with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. -1- July 2005 Rev 1.0 K7A163631B K7A161831B 512Kx36 & 1Mx18 Synchronous SRAM Document Title 512Kx36 & 1Mx18-Bit Synchronous Pipelined Burst SRAM Revision History History Draft Date Remark 0.0 1. Initial draft Mar. 23. 2004 Advance 0.1 1. Update the DC current spec(ICC, ISB) May. 21, 2004 Preliminary 0.2 1. Change the ISB,ISB1,ISB2 - ISB ; from 120mA to 170mA - ISB1 ; from 80mA to 150mA - ISB2 ; from 80mA to 130mA Sep. 21. 2004 Preliminary 0.3 1. Remove the 1.8V Vdd voltage level Oct. 18, 2004 Preliminary 0.4 1. Remove the -16 speed bin Jan. 04, 2005 Preliminary 1.0 1. Finalize the datasheet July 18, 2005 Final Rev. No. -2- July 2005 Rev 1.0 K7A163631B K7A161831B 512Kx36 & 1Mx18 Synchronous SRAM 18Mb SB/SPB Synchronous SRAM Ordering Information Org. Mode VDD Speed SB ; Access Time(ns) SPB ; Cycle Time(MHz) SB 3.3/2.5 7.5ns K7A161830B-Q(P)C(I)25/16 SPB(2E1D) 3.3/2.5 250/167MHz K7A161831B-Q(P)C(I)20 SPB(2E2D) 3.3/2.5 200MHz K7B163635B-Q(P)C(I)75 SB 3.3/2.5 7.5ns SPB(2E1D) 3.3/2.5 250/167MHz SPB(2E2D) 3.3/2.5 200MHz Part Number K7B161835B-Q(P)C(I)75 1Mx18 512Kx36 K7A163630B-Q(P)C(I)25/16 K7A163631B-Q(P)C(I)20 -3- PKG Temp C ; Commercial Q : 100TQFP Temp.Range P : Lead free 100TQFP I ; Industrial Temp.Range July 2005 Rev 1.0 K7A163631B K7A161831B 512Kx36 & 1Mx18 Synchronous SRAM 512Kx36 & 1Mx18-Bit Synchronous Pipelined Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. • 2 Stage Pipelined operation with 4 Burst. • On-Chip Address Counter. • Self-Timed Write Cycle. • On-Chip Address and Control Registers. • VDD= 2.5 or 3.3V +/- 5% Power Supply. • 5V Tolerant Inputs Except I/O Pins. • Byte Writable Function. • Global Write Enable Controls a full bus-width write. • Power Down State via ZZ Signal. • LBO Pin allows a choice of either a interleaved burst or a linear burst. • Three Chip Enables for simple depth expansion with No Data Contention ; 2cycle Enable, 2cycle Disable. • Asynchronous Output Enable Control. • ADSP, ADSC, ADV Burst Control Pins. • TTL-Level Three-State Output. • 100-TQFP-1420A Package (Lead and Lead free package) • Operating in commeical and industrial temperature range. The K7A163631B and K7A161831B are 18,874,368-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 512K(1M) words of 36(18) bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for high performance cache RAM applications; GW, BW, LBO, ZZ. Write cycles are internally selftimed and synchronous. Full bus-width write is done by GW, and each byte write is performed by the combination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control signals. Burst cycle can be initiated with either the address status processor(ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in the system′s burst sequence and are controlled by the burst address advance(ADV) input. LBO pin is DC operated and determines burst sequence(linear or interleaved). ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK. The K7A163631B and K7A161831B are fabricated using SAMSUNG′s high performance CMOS technology and is available in a 100pin TQFP package. Multiple power and ground pins are utilized to minimize ground bounce. FAST ACCESS TIMES PARAMETER Symbol -20 Unit tCYC 5.0 ns Clock Access Time tCD 3.1 ns Output Enable Access Time tOE 3.1 ns Cycle Time LOGIC BLOCK DIAGRAM CLK LBO BURST CONTROL LOGIC CONTROL REGISTER ADV ADSC A0~A18 or A0~A19 A′0~A′1 ADDRESS REGISTER A2~A18 or A2~A19 DATA-IN REGISTER CONTROL REGISTER BW WEx (x=a,b,c,d or a,b) 512Kx36, 1Mx18 MEMORY ARRAY A0~A1 ADSP CS1 CS2 CS2 GW BURST ADDRESS COUNTER OUTPUT REGISTER CONTROL LOGIC BUFFER OE ZZ DQa0 ~ DQd7 or DQa0 ~ DQb7 DQPa,DQPb DQPa ~ DQPd -4- July 2005 Rev 1.0 K7A163631B K7A161831B 512Kx36 & 1Mx18 Synchronous SRAM ADV A8 A9 82 81 49 50 A15 A16 ADSP 83 48 A14 ADSC 84 47 A13 OE 85 46 86 A12 BW 87 45 GW 88 A11 CLK 89 44 VSS 90 A10 VDD 91 43 CS2 92 A17 WEa 93 42 WEb 94 A18 WEd CS2 WEc CS1 97 95 A7 98 96 A6 99 100 Pin TQFP (20mm x 14mm) 37 38 39 40 41 N.C. VSS VDD 35 A2 A0 34 A3 N.C. 33 A4 36 32 A1 31 K7A163631B(512Kx36) A5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LBO NC/DQPc DQc0 DQc1 VDDQ VSSQ DQc2 DQc3 DQc4 DQc5 VSSQ VDDQ DQc6 DQc7 N.C. VDD N.C. VSS DQd0 DQd1 VDDQ VSSQ DQd2 DQd3 DQd4 DQd5 VSSQ VDDQ DQd6 DQd7 NC/DQPd 100 PIN CONFIGURATION(TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPb/NC DQb7 DQb6 VDDQ VSSQ DQb5 DQb4 DQb3 DQb2 VSSQ VDDQ DQb1 DQb0 VSS N.C. VDD ZZ DQa7 DQa6 VDDQ VSSQ DQa5 DQa4 DQa3 DQa2 VSSQ VDDQ DQa1 DQa0 DQPa/NC PIN NAME SYMBOL A0 - A18 PIN NAME TQFP PIN NO. Address Inputs 32,33,34,35,36,37,42 43,44,45,46,47,48,49 50,81,82,99,100 ADV Burst Address Advance 83 ADSP Address Status Processor 84 ADSC Address Status Controller 85 CLK Clock 89 CS1 Chip Select 98 CS2 Chip Select 97 CS2 Chip Select 92 WEx(x=a,b,c,d) Byte Write Inputs 93,94,95,96 OE Output Enable 86 GW Global Write Enable 88 BW Byte Write Enable 87 ZZ Power Down Input 64 LBO Burst Mode Control 31 SYMBOL PIN NAME TQFP PIN NO. VDD VSS Power Supply(+3.3V) Ground 15,41,65,91 17,40,67,90 N.C. No Connect 14,16,38,39,66 DQa0~a7 DQb0~b7 DQc0~c7 DQd0~d7 DQPa~Pd or N.C Data Inputs/Outputs 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 VDDQ Output Power Supply (3.3V or 2.5V) Output Ground 4,11,20,27,54,61,70,77 VSSQ 5,10,21,26,55,60,71,76 Note : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. -5- July 2005 Rev 1.0 K7A163631B K7A161831B 512Kx36 & 1Mx18 Synchronous SRAM ADSP ADV A8 A9 83 82 81 48 49 50 A15 A16 A17 ADSC 84 47 A14 OE 85 46 A13 BW 86 45 A12 GW 87 44 A11 CLK 88 43 A18 VSS 89 WEa 90 WEb 93 42 N.C. 94 A19 N.C. 95 CS2 CS2 96 VDD CS1 97 91 A7 98 92 A6 99 100 Pin TQFP (20mm x 14mm) 31 32 33 34 35 36 37 38 39 40 41 A4 A3 A2 A1 A0 N.C. N.C. VSS VDD K7A161831B(1Mx18) A5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LBO N.C. N.C. N.C. VDDQ VSSQ N.C. N.C. DQb0 DQb1 VSSQ VDDQ DQb2 DQb3 N.C. VDD N.C. VSS DQb4 DQb5 VDDQ VSSQ DQb6 DQb7 DQPb N.C. VSSQ VDDQ N.C. N.C. N.C. 100 PIN CONFIGURATION(TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A10 N.C. N.C. VDDQ VSSQ N.C. DQPa DQa7 DQa6 VSSQ VDDQ DQa5 DQa4 VSS N.C. VDD ZZ DQa3 DQa2 VDDQ VSSQ DQa1 DQa0 N.C. N.C. VSSQ VDDQ N.C. N.C. N.C. PIN NAME SYMBOL PIN NAME A0 - A19 Address Inputs ADV ADSP ADSC CLK CS1 CS2 CS2 WEx(x=a,b) OE GW BW ZZ LBO Burst Address Advance Address Status Processor Address Status Controller Clock Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Global Write Enable Byte Write Enable Power Down Input Burst Mode Control TQFP PIN NO. SYMBOL 32,33,34,35,36,37,42 43,44,45,46,47,48,49 50 80,81,82,99,100 83 84 85 89 98 97 92 93,94 86 88 87 64 31 PIN NAME TQFP PIN NO. VDD VSS Power Supply(+3.3V) Ground 15,41,65,91 17,40,67,90 N.C. No Connect 1,2,3,6,7,14,16,25,28,29 30,38,39,51,52,53,56,57 66,75,78,79,95,96 DQa0 ~ a7 DQb0 ~ b7 DQPa, Pb Data Inputs/Outputs 58,59,62,63,68,69,72,73 8,9,12,13,18,19,22,23 74,24 VDDQ Output Power Supply (3.3V or 2.5V) Output Ground 4,11,20,27,54,61,70,77 VSSQ 5,10,21,26,55,60,71,76 Note : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. -6- July 2005 Rev 1.0 K7A163631B K7A161831B 512Kx36 & 1Mx18 Synchronous SRAM FUNCTION DESCRIPTION The K7A163631B and K7A161831B are synchronous SRAM designed to support the burst address accessing sequence of the Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins. The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with ADV. When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally. Read cycles are initiated with ADSP(regardless of WEx and ADSC)using the new external address clocked into the on-chip address register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read operation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are carried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to control signals by disabling CS1. All byte write is done by GW(regaedless of BW and WEx.), and each byte write is performed by the combination of BW and WEx when GW is high. Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that samples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled Low(regaedless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa control DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7 and DQPb, WEc controls DQc0 ~ DQc7 and DQPc, and WEd control DQd0 ~ DQd7 and DQPd. Read or write cycle may also be initiated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows; ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC. WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high). Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is selected. BURST SEQUENCE TABLE LBO PIN (Interleaved Burst) Case 1 HIGH A1 0 0 1 1 First Address Fourth Address Case 2 A0 0 1 0 1 A1 0 0 1 1 Case 3 A0 1 0 1 0 A1 1 1 0 0 Case 4 A0 0 1 0 1 A1 1 1 0 0 BQ TABLE LBO PIN A0 1 0 1 0 (Linear Burst) Case 1 LOW A1 0 0 1 1 First Address Fourth Address Case 2 A0 0 1 0 1 A1 0 1 1 0 Case 3 A0 1 0 1 0 A1 1 1 0 0 Case 4 A0 0 1 0 1 A1 1 0 0 1 A0 1 0 1 0 Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed. ASYNCHRONOUS TRUTH TABLE OPERATION ZZ OE I/O Status Sleep Mode H X High-Z L L DQ Read L H High-Z Write L X Din, High-Z Deselected L X High-Z Notes 1. X means "Don′t Care". 2. ZZ pin is pulled down internally 3. For write cycles that following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 4. Sleep Mode means power down state of which stand-by current does not depend on cycle time. 5. Deselected means power down state of which stand-by current depends on cycle time. -7- July 2005 Rev 1.0 K7A163631B K7A161831B 512Kx36 & 1Mx18 Synchronous SRAM TRUTH TABLES SYNCHRONOUS TRUTH TABLE CS1 CS2 CS2 ADV WRITE CLK ADDRESS ACCESSED Operation H X X ADSP ADSC X L X X ↑ N/A Not Selected L L X L X X X ↑ N/A Not Selected L X H L X X X ↑ N/A Not Selected L L X X L X X ↑ N/A Not Selected L X H X L X X ↑ N/A Not Selected L H L L X X X ↑ External Address Begin Burst Read Cycle L H L H L X L ↑ External Address Begin Burst Write Cycle L H L H L X H ↑ External Address Begin Burst Read Cycle X X X H H L H ↑ Next Address Continue Burst Read Cycle H X X X H L H ↑ Next Address Continue Burst Read Cycle X X X H H L L ↑ Next Address Continue Burst Write Cycle H X X X H L L ↑ Next Address Continue Burst Write Cycle X X X H H H H ↑ Current Address Suspend Burst Read Cycle H X X X H H H ↑ Current Address Suspend Burst Read Cycle X X X H H H L ↑ Current Address Suspend Burst Write Cycle H X X X H H L ↑ Current Address Suspend Burst Write Cycle Notes : 1. X means "Don′t Care". 2. The rising edge of clock is symbolized by ↑. 3. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. 4. Operation finally depends on status of asynchronous input pins(ZZ and OE). WRITE TRUTH TABLE(x36) GW BW WEa WEb WEc WEd OPERATION H H X X X X READ H L H H H H READ H L L H H H WRITE BYTE a H L H L H H WRITE BYTE b H L H H L L WRITE BYTE c and d H L L L L L WRITE ALL BYTEs L X X X X X WRITE ALL BYTEs Notes : 1. X means "Don′t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑). WRITE TRUTH TABLE(x18) GW BW WEa WEb OPERATION H H X X READ H L H H READ H L L H WRITE BYTE a H L H L WRITE BYTE b H L L L WRITE ALL BYTEs L X X X WRITE ALL BYTEs Notes : 1. X means "Don′t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑). -8- July 2005 Rev 1.0 K7A163631B K7A161831B 512Kx36 & 1Mx18 Synchronous SRAM ABSOLUTE MAXIMUM RATINGS* SYMBOL RATING UNIT Voltage on VDD Supply Relative to VSS PARAMETER VDD -0.3 to 4.6 V Voltage on VDDQ Supply Relative to VSS VDDQ VDD V Voltage on Input Pin Relative to VSS VIN -0.3 to VDD+0.3 V Voltage on I/O Pin Relative to VSS VIO -0.3 to VDDQ+0.3 V Power Dissipation PD 1.6 W TSTG -65 to 150 °C Commercial TOPR 0 to 70 °C Industrial TOPR -40 to 85 °C TBIAS -10 to 85 °C Storage Temperature Operating Temperature Storage Temperature Range Under Bias *Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING CONDITIONS (0°C ≤ TA ≤ 70°C) PARAMETER SYMBOL MIN Typ. MAX UNIT Supply Voltage Ground VDD1 2.375 2.5 2.625 V VDDQ1 2.375 2.5 2.625 V VDD2 3.135 3.3 3.465 V VDDQ2 3.135 3.3 3.465 V VSS 0 0 0 V Notes: 1. The above parameters are also guaranteed at industrial temperature range. 2. It should be VDDQ ≤ VDD CAPACITANCE*(TA=25°C, f=1MHz) PARAMETER SYMBOL Input Capacitance Output Capacitance TEST CONDITION Min Max Unit CIN VIN=0V - 5 pF COUT VOUT=0V - 6 pF *Note : Sampled not 100% tested. VIH VSS VSS-1.0V 20% tCYC(MIN) -9- July 2005 Rev 1.0 K7A163631B K7A161831B 512Kx36 & 1Mx18 Synchronous SRAM DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL MIN MAX UNIT Input Leakage Current(except ZZ) IIL VDD = Max ; VIN=VSS to VDD -2 +2 µA Output Leakage Current IOL Output Disabled, VOUT=VSS to VDDQ -2 +2 µA ICC Device Selected, IOUT=0mA, ZZ≤VIL , Cycle Time ≥ tCYC Min -20 - 340 mA -20 - 170 mA Operating Current TEST CONDITIONS NOTES 1,2 Device deselected, IOUT=0mA, ISB ZZ≤VIL, f=Max, All Inputs≤0.2V or ≥ VDD-0.2V ISB1 Device deselected, IOUT=0mA, ZZ≤0.2V, f = 0, All Inputs=fixed (VDD-0.2V or 0.2V) - 150 mA ISB2 Device deselected, IOUT=0mA, ZZ≥VDD-0.2V, f=Max, All Inputs≤VIL or ≥VIH - 130 mA Output Low Voltage(3.3V I/O) VOL IOL=8.0mA - 0.4 V Output High Voltage(3.3V I/O) VOH IOH=-4.0mA 2.4 - V Output Low Voltage(2.5V I/O) VOL IOL=1.0mA - 0.4 V Output High Voltage(2.5V I/O) VOH IOH=-1.0mA Input Low Voltage(3.3V I/O) VIL Standby Current 2.0 - V -0.3* 0.8 V nput High Voltage(3.3V I/O) VIH 2.0 VDD+0.3** V Input Low Voltage(2.5V I/O) VIL -0.3* 0.7 V Input High Voltage(2.5V I/O) VIH 1.7 VDD+0.3** V 3 3 Notes : 1. The above parameters are also guaranteed at industrial temperature range. 2. Reference AC Operating Conditions and Characteristics for input and timing. 3. Data states are all zero. 4. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V. TEST CONDITIONS PARAMETER Input Pulse Level(for 3.3V I/O) Input Pulse Level(for 2.5V I/O) Input Rise and Fall Time(Measured at 20% to 80% for 3.3/2.5V I/O) Input and Output Timing Reference Levels for 3.3V I/O Input and Output Timing Reference Levels for 2.5V I/O Output Load VALUE 0 to 3.0V 0 to 2.5V 1.0V/ns 1.5V VDDQ/2 See Fig. 1 * The above parameters are also guaranteed at industrial temperature range. - 10 - July 2005 Rev 1.0 K7A163631B K7A161831B 512Kx36 & 1Mx18 Synchronous SRAM Output Load(A) Output Load(B), (for tLZC, tLZOE, tHZOE & tHZC) +3.3V for 3.3V I/O /+2.5V for 2.5V I/O RL=50Ω Dout VL=1.5V for 3.3V I/O VDDQ/2 for 2.5V I/O Zo=50Ω 319Ω / 1667Ω Dout 353Ω / 1538Ω 5pF* * Including Scope and Jig Capacitance Fig. 1 AC TIMING CHARACTERISTICS Parameter -20 Symbol MIN MAX Unit Cycle Time tCYC 5.0 - ns Clock Access Time tCD - 3.1 ns Output Enable to Data Valid tOE - 3.1 ns Clock High to Output Low-Z tLZC 0 - ns Output Hold from Clock High tOH 1.5 - ns Output Enable Low to Output Low-Z tLZOE 0 - ns Output Enable High to Output High-Z tHZOE - 3.0 ns Clock High to Output High-Z tHZC 1.5 3.0 ns Clock High Pulse Width tCH 2.0 - ns Clock Low Pulse Width tCL 2.0 - ns Address Setup to Clock High tAS 1.4 - ns Address Status Setup to Clock High tSS 1.4 - ns Data Setup to Clock High tDS 1.4 - ns tWS 1.4 - ns Address Advance Setup to Clock High tADVS 1.4 - ns Chip Select Setup to Clock High tCSS 1.4 - ns Address Hold from Clock High tAH 0.4 - ns Address Status Hold from Clock High tSH 0.4 - ns Data Hold from Clock High tDH 0.4 - ns Write Setup to Clock High (GW, BW, WEX) Write Hold from Clock High (GW, BW, WEX) tWH 0.4 - ns Address Advance Hold from Clock High tADVH 0.4 - ns Chip Select Hold from Clock High tCSH 0.4 - ns ZZ High to Power Down tPDS 2 - cycle ZZ Low to Power Up tPUS 2 - cycle Notes : 1. The above parameters are also guaranteed at industrial temperature range. 2. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 3. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled. 4. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state. - 11 - July 2005 Rev 1.0 tCH K7A163631B K7A161831B TIMING WAVEFORM OF READ CYCLE tCL CLOCK tSS tCYC tSH ADSP tSS tSH ADSC tAS BURST CONTINUED WITH NEW BASE ADDRESS tAH A2 A1 ADDRESS tWS A3 tWH tCSS tCSH CS tADVS tADVH ADV (ADV INSERTS WAIT STATE) OE tOE tHZOE tLZOE Data Out Q1-1 tCD tOH Q2-1 tHZC Q2-2 Q2-3 July 2005 Rev 1.0 NOTES : WRITE = L means GW = L, or GW = H, BW = L, WEx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L Q2-4 Q3-1 Q3-2 Q3-3 Q3-4 Don′t Care Undefined 512Kx36 & 1Mx18 Synchronous SRAM - 12 - WRITE tCH K7A163631B K7A161831B TIMING WAVEFORM OF WRTE CYCLE tCL CLOCK tCYC tSH tSS ADSP tSS tSH tWS tWH ADSC tAS (ADSC EXTENDED BURST) tAH A1 ADDRESS A2 A3 tCSS tCSH CS (ADV SUSPENDS BURST) tADVS tADVH ADV OE tDH tDS D1-1 Data In D2-1 D2-2 D2-2 D2-3 D2-4 D3-1 D3-2 D3-3 D3-4 tHZOE July 2005 Rev 1.0 Data Out Q0-3 Q0-4 Don′t Care Undefined 512Kx36 & 1Mx18 Synchronous SRAM - 13 - WRITE K7A163631B K7A161831B TIMING WAVEFORM OF COMBINATION READ/WRTE CYCLE(ADSP CONTROLLED , ADSC=HIGH) tCL tCH CLOCK tSS tCYC tSH ADSP tAS A2 A1 ADDRESS tAH A3 tWH tWS WRITE tADVS tADVH tDS tDH ADV OE Data In D2-1 tHZC Data Out tCD tLZC tHZOE Q1-1 tLZOE tOH Q3-1 Q3-2 Q3-3 Q3-4 July 2005 Rev 1.0 Don′t Care Undefined 512Kx36 & 1Mx18 Synchronous SRAM - 14 - CS K7A163631B K7A161831B TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSC CONTROLLED , ADSP=HIGH) tCH tCL CLOCK tSS tCYC tSH ADSC tWS ADDRESS A1 A2 A3 A4 A5 A6 A7 tWH A8 A9 tWH tWS WRITE tCSH - 15 - CS ADV OE tOE tLZOE tHZOE tOH tLZOE Data Out Q1-1 Q2-1 Q3-1 Q8-1 Q4-1 tDS Data In D5-1 Q9-1 tDH D6-1 D7-1 July 2005 Rev 1.0 Don′t Care Undefined 512Kx36 & 1Mx18 Synchronous SRAM tCSS tCH K7A163631B K7A161831B TIMING WAVEFORM OF POWER DOWN CYCLE tCL CLOCK tSS tSH tAS tAH tCYC ADSP ADSC ADDRESS A1 A2 tWS tWH WRITE tCSH CS ADV OE tOE tLZOE D2-1 Data In tHZOE tHZC Data Out Q1-1 tPUS tPDS ZZ Recovery Cycle July 2005 Rev 1.0 ZZ D2-2 Normal Operation Mode ZZ Setup Cycle Sleep State Don′t Care Undefined 512Kx36 & 1Mx18 Synchronous SRAM - 16 - tCSS K7A163631B K7A161831B 512Kx36 & 1Mx18 Synchronous SRAM APPLICATION INFORMATION DEPTH EXPANSION The Samsung 512Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 512K depth to 1M depth without extra logic. I/O[0:71] Data Address A[0:19] A[19] A[0:18] A[19] A[0:18] Address Data Address Data CLK CS2 CS2 CS2 CS2 CLK Microprocessor Address ADSC CLK WEx OE Cache Controller 512Kx36 SPB SRAM ADSC WEx (Bank 0) 512Kx36 SPB SRAM (Bank 1) OE CS1 CS1 ADV CLK ADV ADSP ADSP ADS INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing) (ADSP CONTROLLED , ADSC=HIGH) Clock tSS tSH ADSP tAS ADDRESS [0:n*] A1 tAH A2 tWS tWH WRITE tCSS tCSH CS1 Bank 0 is selected by CS2, and Bank 1 deselected by CS2 An+1* tADVS Bank 0 is deselected by CS2, and Bank 1 selected by CS2 tADVH ADV OE tOE Data Out (Bank 0) tLZOE tHZC Q1-1 Q1-2 Q1-3 Q1-4 tCD tLZC Data Out (Bank 1) *Notes : n = 14 32K depth , 16 128K depth , 18 512K depth , 15 64K depth 17 256K depth 19 1M depth - 17 - Q2-1 Q2-2 Q2-3 Q2-4 Don′t Care Undefined July 2005 Rev 1.0 K7A163631B K7A161831B 512Kx36 & 1Mx18 Synchronous SRAM APPLICATION INFORMATION DEPTH EXPANSION The Samsung 1Mx18 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 1M depth to 2M depth without extra logic. I/O[0:71] Data Address A[20] A[0:19] A[20] A[0:19] A[0:20] Address Data Address Data CLK Microprocessor CS2 CS2 CS2 CS2 CLK Address ADSC CLK WEx OE Cache Controller 1Mx18 SPB SRAM CLK 1Mx18 SPB SRAM ADSC WEx (Bank 0) CS1 CS1 ADV (Bank 1) OE ADV ADSP ADSP ADS INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing) (ADSP CONTROLLED , ADSC=HIGH) Clock tSS tSH ADSP tAS ADDRESS [0:n*] A1 tAH A2 tWS tWH WRITE tCSS tCSH CS1 Bank 0 is selected by CS2, and Bank 1 deselected by CS2 An+1* tADVS Bank 0 is deselected by CS2, and Bank 1 selected by CS2 tADVH ADV OE tOE Data Out (Bank 0) Data Out (Bank 1) tLZOE tHZC Q1-1 Q1-2 Q1-3 Q1-4 tCD tLZC *Notes : n = 14 16 18 20 32K depth , 128K depth , 512K depth , 2M depth 15 64K depth 17 256K depth 19 1M depth - 18 - Q2-1 Q2-2 Q2-3 Q2-4 Don′t Care Undefined July 2005 Rev 1.0 K7A163631B K7A161831B 512Kx36 & 1Mx18 Synchronous SRAM PACKAGE DIMENSIONS 100-TQFP-1420A (Lead and Lead free package) Units ; millimeters/Inches 0~8° 22.00 ±0.30 0.10 0.127 +- 0.05 20.00 ±0.20 16.00 ±0.30 14.00 ±0.20 0.10 MAX (0.83) 0.50 ±0.10 #1 0.65 (0.58) 0.30 ±0.10 0.10 MAX 1.40 ±0.10 1.60 MAX 0.50 ±0.10 - 19 - 0.05 MIN July 2005 Rev 1.0