Cypress CY7C276-35HMB 16k x 16 reprogrammable prom Datasheet

1CY 7C27 6
CY7C276
16K x 16 Reprogrammable PROM
Features
Functional Description
• 0.8-micron CMOS for optimum speed/power
The CY7C276 is a high-performance 16K-word by 16-bit
CMOS PROM. It is available in a 44-pin PLCC/CLCC and a
44-pin LCC packages, and is 100% reprogrammable in windowed packages. The memory cells utilize proven EPROM
floating gate technology and word-wide programming algorithms.
• High speed (for commercial and military)
— 25-ns access time
• 16-bit-wide words
• Three programmable chip selects
• Programmable output enable
• 44-pin PLCC and 44-pin LCC packages
• 100% reprogrammable in windowed packages
• TTL-compatible I/O
• Capable of withstanding greater than 2001V static dis-
charge
The CY7C276 allows the user to independently program the
polarity of each chip select (CS2−CS0). This provides on-chip
decoding of up to eight banks of PROM. The polarity of the
asynchronous output enable pin (OE) is also programmable.
In order to read the CY7C276, all three chip selects must be
active and OE must be asserted. The contents of the memory
location addressed by the address lines (A13−A0) will become
available on the output lines (D15−D 0). The data will remain on
the outputs until the address changes or the outputs are disabled.
Logic Block Diagram
A13
A12
A11
A10
A9
Pin Configuration
LCC/PLCC/CLCC
Top View
D15
D14
16K x 16
PROGRAMMABLE
ARRAY
D13
A8
A7
A6
A5
A4
A3
A2
D12
D12
D11
D10
D9
D8
VSS
VCC
D7
D6
D5
D4
D11
D10
D9
D8
A1
A0
D7
D6
7
8
9
10
11
12
13
14
15
16
17
6 5 4 3 2 1 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
18 19 20 21 22 23 24 25 26 27 28
A13
A12
A11
A10
A9
VSS
VSS
A8
A7
A6
A5
D5
D4
D3
CS0
CS1
CS2
C276–2
D2
CS
DECODE
D1
D0
OE
Cypress Semiconductor Corporation
C276–1
•
3901 North First Street
•
San Jose •
CA 95134 •
408-943-2600
March 1991 – Revised December 1993
CY7C276
Selection Guide
CY7C276-25
CY7C276-30
CY7C276-35
25
30
35
Commercial
175
175
175
Military
200
200
200
Maximum Access Time (ns)
Maximum Operating
Current (mA)
Maximum Ratings
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Latch-Up Current ..................................................... >200 mA
Storage Temperature ................................. –65°C to+150°C
Operating Range
Ambient Temperature with
Power Applied............................................. –55°C to+125°C
Supply Voltage to Ground Potential ................ –0.5V to+7.0V
DC Voltage Applied to Outputs
in High Z State ................................................ –0.5V to+7.0V
DC Input Voltage............................................ –3.0V to +7.0V
Range
Ambient
Temperature
VCC
Commercial
0°C to +70°C
5V ±10%
Industrial[1]
–40°C to +85°C
5V ±10%
Military[2]
–55°C to +125°C
5V ±10%
DC Program Voltage .....................................................13.0V
UV Erasure ...................................................7258 Wsec/cm2
Electrical Characteristics[3, 4]
CY7C276-25
CY7C276-30
CY7C276-35
Parameter
Description
Test Conditions
Min.
Max.
2.4
Unit
VOH
Output HIGH Voltage
VCC = Min., IOH = –2.0 mA
V
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA (6.0 mA Mil)
VIH
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for All Inputs
VIL
Input LOW Level
IIX
Input Leakage Current
VCD
Input Clamp Diode Voltage
IOZ
Output Leakage Current
VCC = Max., VOL < VOUT < VOH,
Output Disabled
–40
+40
µA
IOS
Output Short Circuit Current
VCC = Max., VOUT = 0.0V[5]
–20
–90
mA
ICC
Power Supply Current
VCC = Max., IOUT = 0.0 mA
Com’l
175
mA
Military
200
mA
0.4
V
2.0
VCC
V
Guaranteed Input Logical LOW Voltage for All Inputs
–3.0
0.8
V
GND < VIN < VCC
–10
+10
µA
µA
Note 3
Capacitance[3]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
10
pF
10
pF
Notes:
1. Contact a Cypress representative for industrial temperature range specifications.
2. TA is the “instant on” case temperature
3. See Introduction to CMOS PROMs in this Data Book for general information on testing.
4. See the last page of this specification for Group A subgroup testing information.
5. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
2
CY7C276
AC Test Loads and Waveforms
R1 500Ω
(658Ω MIL)
5V
R1 500Ω
(658Ω MIL)
5V
OUTPUT
OUTPUT
50 pF
INCLUDING
JIG AND
SCOPE
R2
333Ω
(403Ω
MIL)
(a) Normal Load
90%
R2
333Ω
(403Ω
MIL)
5 pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
3.0V
90%
10%
GND
10%
< 3 ns
< 3 ns
C276–3
(b) High Z Load
C276–4
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
200Ω (250ΩMIL)
2.0V (1.9V Mil)
C276–5
Switching Characteristics Over the Operating Range[3,4]
CY7C276-25
Parameter
Description
Min.
Max.
CY7C276-30
Min.
Max.
CY7C276-35
Min.
Max.
Unit
tAA
Address to Output Data Valid
25
30
35
ns
tCSOV
CS Active to Output Valid
13
15
18
ns
tCSOZ
CS Inactive to High Z Output
13
15
18
ns
tOEV
OE Active to Output Valid
11
12
15
ns
tOEZ
OE Inactive to High Z Output
11
12
15
ns
age may result if the EPROM is exposed to high-intensity UV
light for an extended period of time. 7258 Wsec/cm2 is the
recommended maximum dosage.
Erasure Characteristics
The recommended dose of ultraviolet light for erasure is a
wavelength of 2537 Angstroms for a minimum dose (UV intensity multiplied by exposure time) of 25 Wsec/cm2. For an ultraviolet lamp with a 12 mW/cm2 power rating the exposure
time would be approximately 35 minutes. The 7C276 needs to
be within 1 inch of the lamp during erasure. Permanent dam-
Wavelengths of light less than 4000 Angstroms begin to erase
the 7C276 in the windowed package. For this reason, an
opaque label should be placed over the window if the EPROM
is exposed to sunlight or fluorescent lighting for extended periods of time.
3
CY7C276
Switching Waveforms
Read Operation Timing Diagram [6]
ADDR A
A13 − A0
ADDR B
tAA
tAA
D15 − D0
DATA A
DATA B
C276–6
Chip Select and Output Enable Timing Diagrams
A13 − A0
CS2 − CS0
INACTIVE
ACTIVE
INACTIVE
OE
ACTIVE HIGH
tCSOV
D15 − D0
tOEV
tOEZ
VALID
tCSOZ
VALID
HIGH Z
C276–7
Notes:
6. CS2 – CS0, OE assumed active.
Architecture Configuration Bits
Programming Information
The CY7C276 has four user-programmable options in addition
to the reprogrammable data array. For detailed programming
information contact your local Cypress representative.
Programming support is available from Cypress as well as
from a number of third-party software vendors. For detailed
programming information, including a listing of software packages, please see the PROM Programming Information located
at the end of this section. Programming algorithms can be obtained from any Cypress representative.
The programmable options determine the active polarity for
the three chip selects (CS2 - CS0) and OE. When these control bits are programmed with a 0 the inputs are active LOW.
When these control bits are programmed with a 1 the inputs
are active HIGH.
4
CY7C276
Table 1. Control Word for Architecture Configuration
Control Word
Control Option
Bit
Programmed Level
Function
OE
D0
0=Default
1=Programmed
OE Active LOW
OE Active HIGH
CS0
D12
0=Default
1=Programmed
CS0 Active LOW
CS0 Active HIGH
CS1
D13
0=Default
1=Programmed
CS1 Active LOW
CS1 Active HIGH
CS2
D14
0=Default
1=Programmed
CS2 Active LOW
CS2 Active HIGH
Control Word (4000H)
D15
D0
X CS2 CS1 CS0 X X X X X X X X 1 X X OE
Bit Map
Programmer Address (Hex)
0000
RAM Data
Table 2. Program Mode Table
Data
.
.
.
VPP
PGM
VFY
D0 − D15
Program Inhibit
VPP
VIHP
VIHP
High Z
Program Enable
VPP
VILP
VIHP
Data
Program Verify
VPP
VIHP
VILP
Data
Mode
.
.
.
3FFF
Data
4000
Control Word
Table 3. Configuration Mode Table
VPP
PGM
VFY
A2
D0 − D15
Program Inhibit
VPP
VIHP
VIHP
VPP
High Z
Program Control Word
VPP
VILP
VIHP
VPP
Control Word
Verify Control Word
VPP
VIHP
VILP
VPP
Control Word
Mode
D12
D11
D10
D9
D8
VSS
VCC
D7
D6
D5
D4
7
8
9
10
11
12
13
14
15
16
17
6 5 4 3 2 1 44 43 42 41 40
39
38
37
CY7C276
36
35
34
33
32
31
30
29
18 19 20 21 22 23 24 25 26 27 28
A13
A12
A11
A10
A9
VSS
VSS
A8
A7
A6
A5
C276–8
Figure 1. Programming Pinout
5
CY7C276
Typical DC and AC Characteristics
NORMALIZED I CC vs.
tCKA CYCLE
NORMALIZED t CKA
vs. TEMPERATURE
NORMALIZED ICC vs. OUTPUT
VOLTAGE
1.2
1.4
1.4
VCC=4.5V
1.1
TA =25°C
VCC=5.5V
1.0
TA =25°C
f=f MAX
1.2
1.2
0.9
1.0
1.0
0.8
0.8
0.8
0.7
0.6
0.5
0.6
0
100
200
300
400
500
4
4.5
5
5.5
OUTPUT VOLTAGE (V)
ACCESS TIME (ns)
0.6
−55
6
AMBIENT TEMPERATURE (°C)
tCKA CHANGE
vs. OUTPUT LOADING
NORMALIZED t CKA
vs. SUPPLY VOLTAGE
1.2
25
1.1
20
125
25
NORMALIZED I CC vs.
AMBIENT TEMPERATURE
1.1
TA =25°C
VCC=4.5V
VCC=5.6V
1.05
15
1.0
10
0.95
5
0.90
1.0
0.9
TA =90°C
0.9
4.0
4.5
5.0
5.5
6.0
0
0
200
SUPPLYVOLTAGE(V)
400
600
0.85
−55
800 1000
25
125
AMBIENT TEMPERATURE (°C)
OUTPUT LOAD (pF)
NORMALIZED t OEV vs.
TEMPERATURE
tOEV CHANGE vs. OUTPUT
LOADING
1.2
35
30
1.1
25
20
1.0
15
VCC =4.5V
10
0.9
VCC =4.5V
TA =25°C
5
0
−55
0
25
125
0
TEMPERATURE(°C)
200
400
600
800 1000
OUTPUT LOAD (pF)
6
C276–9
CY7C276
Ordering Information[7]
Speed
(ns)
25
30
35
Ordering Code
Package
Name
Operating
Range
Package Type
CY7C276-25HC
H67
44-Pin Windowed Leaded Chip Carrier
CY7C276-25JC
J67
44-Lead Plastic Leaded Chip Carrier
CY7C276-25HMB
H67
44-Pin Windowed Leaded Chip Carrier
CY7C276-25QMB
Q67
44-Pin Windowed Leadless Chip Carrier
CY7C276-30HC
H67
44-Pin Windowed Leaded Chip Carrier
CY7C276-30JC
J67
44-Lead Plastic Leaded Chip Carrier
CY7C276-30HMB
H67
44-Pin Windowed Leaded Chip Carrier
CY7C276-30QMB
Q67
44-Pin Windowed Leadless Chip Carrier
CY7C276-35HC
H67
44-Pin Windowed Leaded Chip Carrier
CY7C276-35JC
J67
44-Lead Plastic Leaded Chip Carrier
CY7C276-35HMB
H67
44-Pin Windowed Leaded Chip Carrier
CY7C276-35QMB
Q67
44-Pin Windowed Leadless Chip Carrier
Commercial
Military
Commercial
Military
Commercial
Military
Notes:
7. Most of the above products are available in industrial temperature range. Contact a Cypress representative for specifications and
product availability.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
Parameter
Subgroups
VOH
1, 2, 3
tAA
7, 8, 9, 10, 11
VOL
1, 2, 3
tCSOV
7, 8, 9, 10, 11
VIH
1, 2, 3
tOEV
7, 8, 9, 10, 11
VIL
1, 2, 3
IIX
1, 2, 3
IOZ
1, 2, 3
ICC
1, 2, 3
Document #: 38-00183-D
7
CY7C276
Package Diagrams
44-Pin Windowed Leaded Chip Carrier H67
8
CY7C276
Package Diagrams (continued)
44-Lead Plastic Leaded Chip Carrier J67
44-Square Leadless Chip Carrier L67
MIL-STD-1835 C-5
44-Pin Windowed Leadless Chip Carrier Q67
MIL-STD-1835 C-5
© Cypress Semiconductor Corporation, 1993. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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